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authorBen Skeggs <bskeggs@redhat.com>2011-11-09 05:22:25 -0500
committerBen Skeggs <bskeggs@redhat.com>2011-12-21 04:01:44 -0500
commitc8b9641a9146b13d34824f99c3d22c8c0c3a06bd (patch)
tree3b4280f3757ab9f9e82a4feaaec0336b38040a03
parenteeb7a50bddb281d7beecb0ad73c9f1233e9932c2 (diff)
drm/nouveau/hwsq: remove some magic, give proper opcode names
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hwsq.h21
-rw-r--r--drivers/gpu/drm/nouveau/nv50_pm.c8
2 files changed, 23 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_hwsq.h b/drivers/gpu/drm/nouveau/nouveau_hwsq.h
index d59a3b3ff644..697687593a81 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hwsq.h
+++ b/drivers/gpu/drm/nouveau/nouveau_hwsq.h
@@ -57,9 +57,26 @@ hwsq_fini(struct hwsq_ucode *hwsq)
57} 57}
58 58
59static inline void 59static inline void
60hwsq_unkn(struct hwsq_ucode *hwsq, u8 v0) 60hwsq_usec(struct hwsq_ucode *hwsq, u8 usec)
61{ 61{
62 *hwsq->ptr.u08++ = v0; 62 u32 shift = 0;
63 while (usec & ~3) {
64 usec >>= 2;
65 shift++;
66 }
67
68 *hwsq->ptr.u08++ = (shift << 2) | usec;
69}
70
71static inline void
72hwsq_setf(struct hwsq_ucode *hwsq, u8 flag, int val)
73{
74 flag += 0x80;
75 if (val >= 0)
76 flag += 0x20;
77 if (val >= 1)
78 flag += 0x20;
79 *hwsq->ptr.u08++ = flag;
63} 80}
64 81
65static inline void 82static inline void
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
index 22789db48969..fce1214c3db1 100644
--- a/drivers/gpu/drm/nouveau/nv50_pm.c
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -459,7 +459,7 @@ calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq)
459 } 459 }
460 if (dev_priv->chipset >= 0x92) 460 if (dev_priv->chipset >= 0x92)
461 hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */ 461 hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */
462 hwsq_unkn(hwsq, 0xb0); /* disable bus access */ 462 hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
463 hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */ 463 hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */
464 464
465 /* prepare memory controller */ 465 /* prepare memory controller */
@@ -478,10 +478,10 @@ calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq)
478 hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */ 478 hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */
479 hwsq_wr32(hwsq, 0x1002dc, 0x00000000); /* stop self refresh mode */ 479 hwsq_wr32(hwsq, 0x1002dc, 0x00000000); /* stop self refresh mode */
480 hwsq_wr32(hwsq, 0x100210, 0x80000000); /* restart automatic refresh */ 480 hwsq_wr32(hwsq, 0x100210, 0x80000000); /* restart automatic refresh */
481 hwsq_unkn(hwsq, 0x07); /* wait for the PLL to stabilize (12us) */ 481 hwsq_usec(hwsq, 12); /* wait for the PLL to stabilize */
482 482
483 hwsq_unkn(hwsq, 0x0b); /* may be unnecessary: causes flickering */ 483 hwsq_usec(hwsq, 48); /* may be unnecessary: causes flickering */
484 hwsq_unkn(hwsq, 0xd0); /* enable bus access again */ 484 hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
485 hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */ 485 hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
486 if (dev_priv->chipset >= 0x92) 486 if (dev_priv->chipset >= 0x92)
487 hwsq_wr32(hwsq, 0x611200, 0x00003330); /* enable scanout */ 487 hwsq_wr32(hwsq, 0x611200, 0x00003330); /* enable scanout */