diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-01-16 12:59:03 -0500 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-01-17 16:23:48 -0500 |
| commit | c70af1e4b60a1853feeaae2bf6e2aa98de68acd9 (patch) | |
| tree | 1d5a0105f51176deb4c5cb161802d230c4b06ac7 | |
| parent | eef90ccb8a4d50b219a95cc53878ebb007315b32 (diff) | |
drm/i915: Fix SPRITE0_FLIP_DONE_INT_EN_VLV and SPRITE0_FLIPDONE_INT_STATUS_VLV
Fix up some copypaste errors in the PIPESTAT register for VLV.
SPRITE0_FLIP_DONE_INT_EN_VLV is bit 22, not bit 26.
SPRITE0_FLIPDONE_INT_STATUS_VLV is bit 14, not bit 15.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3b039f4268e3..4c33bd2bd4e6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -2672,7 +2672,7 @@ | |||
| 2672 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | 2672 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
| 2673 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | 2673 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
| 2674 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | 2674 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
| 2675 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) | 2675 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) |
| 2676 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | 2676 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
| 2677 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | 2677 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
| 2678 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | 2678 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
| @@ -2682,7 +2682,7 @@ | |||
| 2682 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) | 2682 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
| 2683 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) | 2683 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
| 2684 | #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) | 2684 | #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) |
| 2685 | #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) | 2685 | #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14) |
| 2686 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | 2686 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
| 2687 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | 2687 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
| 2688 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) | 2688 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |