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authorBen Skeggs <bskeggs@redhat.com>2011-05-24 01:44:37 -0400
committerBen Skeggs <bskeggs@redhat.com>2011-06-23 01:57:20 -0400
commitb53a2d06496d9de109620e4fe136b654bb0ce249 (patch)
treed3ea2b23081652a8e526014a4ed1668a2dd2612c
parente1b89b1ca59f558d4f7ec18e0b6a8eb34437c8d9 (diff)
drm/nvc0/gr: enable 0xc8/0xce support, no idea if it works or not..
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.h3
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grctx.c10
2 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.h b/drivers/gpu/drm/nouveau/nvc0_graph.h
index 2b667d4e88ca..f067ed232f97 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.h
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.h
@@ -82,13 +82,14 @@ nvc0_graph_class(struct drm_device *dev)
82 case 0xc0: 82 case 0xc0:
83 case 0xc3: 83 case 0xc3:
84 case 0xc4: 84 case 0xc4:
85 case 0xce: /* guess, mmio trace shows only 0x9097 state */
85 return 0x9097; 86 return 0x9097;
86#if 0 87#if 0
87 case 0xc1: 88 case 0xc1:
88 return 0x9197; 89 return 0x9197;
90#endif
89 case 0xc8: 91 case 0xc8:
90 return 0x9297; 92 return 0x9297;
91#endif
92 default: 93 default:
93 return 0; 94 return 0;
94 } 95 }
diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c
index 3ac376235d29..562a0cd950ee 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grctx.c
+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c
@@ -1642,8 +1642,8 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
1642 nv_wr32(dev, 0x419a14, 0x00000200); 1642 nv_wr32(dev, 0x419a14, 0x00000200);
1643 nv_wr32(dev, 0x419a1c, 0x00000000); 1643 nv_wr32(dev, 0x419a1c, 0x00000000);
1644 nv_wr32(dev, 0x419a20, 0x00000800); 1644 nv_wr32(dev, 0x419a20, 0x00000800);
1645 if (dev_priv->chipset != 0xc0) 1645 if (dev_priv->chipset != 0xc0 && dev_priv->chipset != 0xc8)
1646 nv_wr32(dev, 0x00419ac4, 0x0007f440); /* 0xc3 */ 1646 nv_wr32(dev, 0x00419ac4, 0x0007f440);
1647 nv_wr32(dev, 0x419b00, 0x0a418820); 1647 nv_wr32(dev, 0x419b00, 0x0a418820);
1648 nv_wr32(dev, 0x419b04, 0x062080e6); 1648 nv_wr32(dev, 0x419b04, 0x062080e6);
1649 nv_wr32(dev, 0x419b08, 0x020398a4); 1649 nv_wr32(dev, 0x419b08, 0x020398a4);
@@ -1657,7 +1657,7 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
1657 nv_wr32(dev, 0x419c04, 0x00000006); 1657 nv_wr32(dev, 0x419c04, 0x00000006);
1658 nv_wr32(dev, 0x419c08, 0x00000002); 1658 nv_wr32(dev, 0x419c08, 0x00000002);
1659 nv_wr32(dev, 0x419c20, 0x00000000); 1659 nv_wr32(dev, 0x419c20, 0x00000000);
1660 nv_wr32(dev, 0x419cb0, 0x00060048); 1660 nv_wr32(dev, 0x419cb0, 0x00060048); //XXX: 0xce 0x00020048
1661 nv_wr32(dev, 0x419ce8, 0x00000000); 1661 nv_wr32(dev, 0x419ce8, 0x00000000);
1662 nv_wr32(dev, 0x419cf4, 0x00000183); 1662 nv_wr32(dev, 0x419cf4, 0x00000183);
1663 nv_wr32(dev, 0x419d20, 0x02180000); 1663 nv_wr32(dev, 0x419d20, 0x02180000);
@@ -1687,11 +1687,11 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
1687 nv_wr32(dev, 0x419e8c, 0x00000000); 1687 nv_wr32(dev, 0x419e8c, 0x00000000);
1688 nv_wr32(dev, 0x419e90, 0x00000000); 1688 nv_wr32(dev, 0x419e90, 0x00000000);
1689 nv_wr32(dev, 0x419e98, 0x00000000); 1689 nv_wr32(dev, 0x419e98, 0x00000000);
1690 if (dev_priv->chipset != 0xc0) 1690 if (dev_priv->chipset != 0xc0 && dev_priv->chipset != 0xc8)
1691 nv_wr32(dev, 0x419ee0, 0x00011110); 1691 nv_wr32(dev, 0x419ee0, 0x00011110);
1692 nv_wr32(dev, 0x419f50, 0x00000000); 1692 nv_wr32(dev, 0x419f50, 0x00000000);
1693 nv_wr32(dev, 0x419f54, 0x00000000); 1693 nv_wr32(dev, 0x419f54, 0x00000000);
1694 if (dev_priv->chipset != 0xc0) 1694 if (dev_priv->chipset != 0xc0 && dev_priv->chipset != 0xc8)
1695 nv_wr32(dev, 0x419f58, 0x00000000); 1695 nv_wr32(dev, 0x419f58, 0x00000000);
1696} 1696}
1697 1697