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authorSenthil Balasubramanian <senthilkumar@atheros.com>2010-11-10 08:03:07 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-11-16 16:37:05 -0500
commitb3dd6bc1f052ef3a754fa866743e4fda38522811 (patch)
tree52b6a010a51f0e46b069ed781bf48c793d08ed17
parenta9d85fbd3e5f7a0679e6276953cd23ac7bb72789 (diff)
ath9k_hw: Add new member into the eeprom structure.
Add eeprom base extension structures which are needed for AR938x caliberation changes and gain calculation. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c21
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h18
2 files changed, 32 insertions, 7 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index a88fe0d6142f..bc3f49c5c5b4 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -147,10 +147,13 @@ static const struct ar9300_eeprom ar9300_default = {
147 .papdRateMaskHt20 = LE32(0x80c080), 147 .papdRateMaskHt20 = LE32(0x80c080),
148 .papdRateMaskHt40 = LE32(0x80c080), 148 .papdRateMaskHt40 = LE32(0x80c080),
149 .futureModal = { 149 .futureModal = {
150 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 150 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
151 0, 0, 0, 0, 0, 0, 0, 0
152 }, 151 },
153 }, 152 },
153 .base_ext1 = {
154 .ant_div_control = 0,
155 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
156 },
154 .calFreqPier2G = { 157 .calFreqPier2G = {
155 FREQ2FBIN(2412, 1), 158 FREQ2FBIN(2412, 1),
156 FREQ2FBIN(2437, 1), 159 FREQ2FBIN(2437, 1),
@@ -285,8 +288,7 @@ static const struct ar9300_eeprom ar9300_default = {
285 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 288 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
286 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 289 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
287 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 290 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
288 /* Data[11].ctlEdges[3].bChannel */ 291 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
289 FREQ2FBIN(2462, 1),
290 } 292 }
291 }, 293 },
292 .ctlPowerData_2G = { 294 .ctlPowerData_2G = {
@@ -346,10 +348,17 @@ static const struct ar9300_eeprom ar9300_default = {
346 .papdRateMaskHt20 = LE32(0xf0e0e0), 348 .papdRateMaskHt20 = LE32(0xf0e0e0),
347 .papdRateMaskHt40 = LE32(0xf0e0e0), 349 .papdRateMaskHt40 = LE32(0xf0e0e0),
348 .futureModal = { 350 .futureModal = {
349 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 351 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
350 0, 0, 0, 0, 0, 0, 0, 0
351 }, 352 },
352 }, 353 },
354 .base_ext2 = {
355 .tempSlopeLow = 0,
356 .tempSlopeHigh = 0,
357 .xatten1DBLow = {0, 0, 0},
358 .xatten1MarginLow = {0, 0, 0},
359 .xatten1DBHigh = {0, 0, 0},
360 .xatten1MarginHigh = {0, 0, 0}
361 },
353 .calFreqPier5G = { 362 .calFreqPier5G = {
354 FREQ2FBIN(5180, 0), 363 FREQ2FBIN(5180, 0),
355 FREQ2FBIN(5220, 0), 364 FREQ2FBIN(5220, 0),
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 3c533bb983c7..5301df3e9ec0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -236,7 +236,7 @@ struct ar9300_modal_eep_header {
236 u8 thresh62; 236 u8 thresh62;
237 __le32 papdRateMaskHt20; 237 __le32 papdRateMaskHt20;
238 __le32 papdRateMaskHt40; 238 __le32 papdRateMaskHt40;
239 u8 futureModal[24]; 239 u8 futureModal[10];
240} __packed; 240} __packed;
241 241
242struct ar9300_cal_data_per_freq_op_loop { 242struct ar9300_cal_data_per_freq_op_loop {
@@ -274,6 +274,20 @@ struct cal_ctl_data_5g {
274 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G]; 274 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
275} __packed; 275} __packed;
276 276
277struct ar9300_BaseExtension_1 {
278 u8 ant_div_control;
279 u8 future[13];
280} __packed;
281
282struct ar9300_BaseExtension_2 {
283 int8_t tempSlopeLow;
284 int8_t tempSlopeHigh;
285 u8 xatten1DBLow[AR9300_MAX_CHAINS];
286 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
287 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
288 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
289} __packed;
290
277struct ar9300_eeprom { 291struct ar9300_eeprom {
278 u8 eepromVersion; 292 u8 eepromVersion;
279 u8 templateVersion; 293 u8 templateVersion;
@@ -283,6 +297,7 @@ struct ar9300_eeprom {
283 struct ar9300_base_eep_hdr baseEepHeader; 297 struct ar9300_base_eep_hdr baseEepHeader;
284 298
285 struct ar9300_modal_eep_header modalHeader2G; 299 struct ar9300_modal_eep_header modalHeader2G;
300 struct ar9300_BaseExtension_1 base_ext1;
286 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; 301 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
287 struct ar9300_cal_data_per_freq_op_loop 302 struct ar9300_cal_data_per_freq_op_loop
288 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; 303 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
@@ -302,6 +317,7 @@ struct ar9300_eeprom {
302 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]; 317 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
303 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]; 318 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
304 struct ar9300_modal_eep_header modalHeader5G; 319 struct ar9300_modal_eep_header modalHeader5G;
320 struct ar9300_BaseExtension_2 base_ext2;
305 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; 321 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
306 struct ar9300_cal_data_per_freq_op_loop 322 struct ar9300_cal_data_per_freq_op_loop
307 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; 323 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];