diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-11-09 17:46:36 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-11-09 17:46:36 -0500 |
commit | b1f368b58b3c8095de4cff9eeb69babffab4e3d3 (patch) | |
tree | efd28998e71ad2a5433ca79e858a2cfc71f30a2d | |
parent | a3157809772c4a5256ef68a4d5b21ea4ecc80ad4 (diff) | |
parent | 92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c (diff) |
Merge tag 'armsoc-for-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Another quiet week:
- a fix to silence edma probe error on non-supported platforms from
Arnd
- a fix to enable the PL clock for Parallella, to make mainline
usable with the SDK.
- a somewhat verbose fix for the PLL clock tree on VF610
- enabling of SD/MMC on one of the VF610-based boards (for testing)
- a fix for i.MX where CONFIG_SPI used to be implicitly enabled and
now needs to be added to the defconfig instead
- another maintainer added for bcm2835: Lee Jones"
* tag 'armsoc-for-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: zynq: Enable PL clocks for Parallella
dma: edma: move device registration to platform code
ARM: dts: vf610: add SD node to cosmic dts
MAINTAINERS: update bcm2835 entry
ARM: imx: Fix the removal of CONFIG_SPI option
ARM: imx: clk-vf610: define PLL's clock tree
-rw-r--r-- | MAINTAINERS | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/vf610-cosmic.dts | 19 | ||||
-rw-r--r-- | arch/arm/boot/dts/zynq-parallella.dts | 4 | ||||
-rw-r--r-- | arch/arm/common/edma.c | 9 | ||||
-rw-r--r-- | arch/arm/configs/imx_v4_v5_defconfig | 1 | ||||
-rw-r--r-- | arch/arm/configs/imx_v6_v7_defconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-imx/clk-vf610.c | 134 | ||||
-rw-r--r-- | drivers/dma/edma.c | 40 | ||||
-rw-r--r-- | include/dt-bindings/clock/vf610-clock.h | 39 |
9 files changed, 160 insertions, 90 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index a0d386e234ed..ea4d0058fd1b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
@@ -2072,8 +2072,9 @@ F: drivers/clocksource/bcm_kona_timer.c | |||
2072 | 2072 | ||
2073 | BROADCOM BCM2835 ARM ARCHITECTURE | 2073 | BROADCOM BCM2835 ARM ARCHITECTURE |
2074 | M: Stephen Warren <swarren@wwwdotorg.org> | 2074 | M: Stephen Warren <swarren@wwwdotorg.org> |
2075 | M: Lee Jones <lee@kernel.org> | ||
2075 | L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) | 2076 | L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers) |
2076 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git | 2077 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi.git |
2077 | S: Maintained | 2078 | S: Maintained |
2078 | N: bcm2835 | 2079 | N: bcm2835 |
2079 | 2080 | ||
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts index 3fd1b74e1216..de1b453c2932 100644 --- a/arch/arm/boot/dts/vf610-cosmic.dts +++ b/arch/arm/boot/dts/vf610-cosmic.dts | |||
@@ -33,6 +33,13 @@ | |||
33 | 33 | ||
34 | }; | 34 | }; |
35 | 35 | ||
36 | &esdhc1 { | ||
37 | pinctrl-names = "default"; | ||
38 | pinctrl-0 = <&pinctrl_esdhc1>; | ||
39 | bus-width = <4>; | ||
40 | status = "okay"; | ||
41 | }; | ||
42 | |||
36 | &fec1 { | 43 | &fec1 { |
37 | phy-mode = "rmii"; | 44 | phy-mode = "rmii"; |
38 | pinctrl-names = "default"; | 45 | pinctrl-names = "default"; |
@@ -42,6 +49,18 @@ | |||
42 | 49 | ||
43 | &iomuxc { | 50 | &iomuxc { |
44 | vf610-cosmic { | 51 | vf610-cosmic { |
52 | pinctrl_esdhc1: esdhc1grp { | ||
53 | fsl,pins = < | ||
54 | VF610_PAD_PTA24__ESDHC1_CLK 0x31ef | ||
55 | VF610_PAD_PTA25__ESDHC1_CMD 0x31ef | ||
56 | VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef | ||
57 | VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef | ||
58 | VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef | ||
59 | VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef | ||
60 | VF610_PAD_PTB28__GPIO_98 0x219d | ||
61 | >; | ||
62 | }; | ||
63 | |||
45 | pinctrl_fec1: fec1grp { | 64 | pinctrl_fec1: fec1grp { |
46 | fsl,pins = < | 65 | fsl,pins = < |
47 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 | 66 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 |
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index e1f51ca127fe..0429bbd89fba 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts | |||
@@ -34,6 +34,10 @@ | |||
34 | }; | 34 | }; |
35 | }; | 35 | }; |
36 | 36 | ||
37 | &clkc { | ||
38 | fclk-enable = <0xf>; | ||
39 | }; | ||
40 | |||
37 | &gem0 { | 41 | &gem0 { |
38 | status = "okay"; | 42 | status = "okay"; |
39 | phy-mode = "rgmii-id"; | 43 | phy-mode = "rgmii-id"; |
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index d86771abbf57..72041f002b7e 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
28 | #include <linux/edma.h> | 28 | #include <linux/edma.h> |
29 | #include <linux/dma-mapping.h> | ||
29 | #include <linux/of_address.h> | 30 | #include <linux/of_address.h> |
30 | #include <linux/of_device.h> | 31 | #include <linux/of_device.h> |
31 | #include <linux/of_dma.h> | 32 | #include <linux/of_dma.h> |
@@ -1623,6 +1624,11 @@ static int edma_probe(struct platform_device *pdev) | |||
1623 | struct device_node *node = pdev->dev.of_node; | 1624 | struct device_node *node = pdev->dev.of_node; |
1624 | struct device *dev = &pdev->dev; | 1625 | struct device *dev = &pdev->dev; |
1625 | int ret; | 1626 | int ret; |
1627 | struct platform_device_info edma_dev_info = { | ||
1628 | .name = "edma-dma-engine", | ||
1629 | .dma_mask = DMA_BIT_MASK(32), | ||
1630 | .parent = &pdev->dev, | ||
1631 | }; | ||
1626 | 1632 | ||
1627 | if (node) { | 1633 | if (node) { |
1628 | /* Check if this is a second instance registered */ | 1634 | /* Check if this is a second instance registered */ |
@@ -1793,6 +1799,9 @@ static int edma_probe(struct platform_device *pdev) | |||
1793 | edma_write_array(j, EDMA_QRAE, i, 0x0); | 1799 | edma_write_array(j, EDMA_QRAE, i, 0x0); |
1794 | } | 1800 | } |
1795 | arch_num_cc++; | 1801 | arch_num_cc++; |
1802 | |||
1803 | edma_dev_info.id = j; | ||
1804 | platform_device_register_full(&edma_dev_info); | ||
1796 | } | 1805 | } |
1797 | 1806 | ||
1798 | return 0; | 1807 | return 0; |
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index e688741c89aa..e6b0007355f8 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig | |||
@@ -97,6 +97,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y | |||
97 | # CONFIG_HW_RANDOM is not set | 97 | # CONFIG_HW_RANDOM is not set |
98 | CONFIG_I2C_CHARDEV=y | 98 | CONFIG_I2C_CHARDEV=y |
99 | CONFIG_I2C_IMX=y | 99 | CONFIG_I2C_IMX=y |
100 | CONFIG_SPI=y | ||
100 | CONFIG_SPI_IMX=y | 101 | CONFIG_SPI_IMX=y |
101 | CONFIG_SPI_SPIDEV=y | 102 | CONFIG_SPI_SPIDEV=y |
102 | CONFIG_GPIO_SYSFS=y | 103 | CONFIG_GPIO_SYSFS=y |
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 8fca6e276b69..6790f1b3f3a1 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig | |||
@@ -158,6 +158,7 @@ CONFIG_I2C_CHARDEV=y | |||
158 | CONFIG_I2C_ALGOPCF=m | 158 | CONFIG_I2C_ALGOPCF=m |
159 | CONFIG_I2C_ALGOPCA=m | 159 | CONFIG_I2C_ALGOPCA=m |
160 | CONFIG_I2C_IMX=y | 160 | CONFIG_I2C_IMX=y |
161 | CONFIG_SPI=y | ||
161 | CONFIG_SPI_IMX=y | 162 | CONFIG_SPI_IMX=y |
162 | CONFIG_GPIO_SYSFS=y | 163 | CONFIG_GPIO_SYSFS=y |
163 | CONFIG_GPIO_MC9S08DZ60=y | 164 | CONFIG_GPIO_MC9S08DZ60=y |
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index a17818475050..409637254594 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c | |||
@@ -58,8 +58,14 @@ | |||
58 | #define PFD_PLL1_BASE (anatop_base + 0x2b0) | 58 | #define PFD_PLL1_BASE (anatop_base + 0x2b0) |
59 | #define PFD_PLL2_BASE (anatop_base + 0x100) | 59 | #define PFD_PLL2_BASE (anatop_base + 0x100) |
60 | #define PFD_PLL3_BASE (anatop_base + 0xf0) | 60 | #define PFD_PLL3_BASE (anatop_base + 0xf0) |
61 | #define PLL1_CTRL (anatop_base + 0x270) | ||
62 | #define PLL2_CTRL (anatop_base + 0x30) | ||
61 | #define PLL3_CTRL (anatop_base + 0x10) | 63 | #define PLL3_CTRL (anatop_base + 0x10) |
64 | #define PLL4_CTRL (anatop_base + 0x70) | ||
65 | #define PLL5_CTRL (anatop_base + 0xe0) | ||
66 | #define PLL6_CTRL (anatop_base + 0xa0) | ||
62 | #define PLL7_CTRL (anatop_base + 0x20) | 67 | #define PLL7_CTRL (anatop_base + 0x20) |
68 | #define ANA_MISC1 (anatop_base + 0x160) | ||
63 | 69 | ||
64 | static void __iomem *anatop_base; | 70 | static void __iomem *anatop_base; |
65 | static void __iomem *ccm_base; | 71 | static void __iomem *ccm_base; |
@@ -67,25 +73,34 @@ static void __iomem *ccm_base; | |||
67 | /* sources for multiplexer clocks, this is used multiple times */ | 73 | /* sources for multiplexer clocks, this is used multiple times */ |
68 | static const char *fast_sels[] = { "firc", "fxosc", }; | 74 | static const char *fast_sels[] = { "firc", "fxosc", }; |
69 | static const char *slow_sels[] = { "sirc_32k", "sxosc", }; | 75 | static const char *slow_sels[] = { "sirc_32k", "sxosc", }; |
70 | static const char *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; | 76 | static const char *pll1_sels[] = { "pll1_sys", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; |
71 | static const char *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; | 77 | static const char *pll2_sels[] = { "pll2_bus", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; |
72 | static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; | 78 | static const char *pll_bypass_src_sels[] = { "fast_clk_sel", "lvds1_in", }; |
79 | static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; | ||
80 | static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; | ||
81 | static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; | ||
82 | static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; | ||
83 | static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; | ||
84 | static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; | ||
85 | static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; | ||
86 | static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_bus", "pll1_pfd_sel", "pll3_usb_otg", }; | ||
73 | static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; | 87 | static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; |
74 | static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; | 88 | static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; |
75 | static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; | 89 | static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; |
76 | static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; | 90 | static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", }; |
77 | static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; | 91 | static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_audio_div", }; |
78 | static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; | 92 | static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; |
79 | static const char *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; | 93 | static const char *qspi_sels[] = { "pll3_usb_otg", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; |
80 | static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; | 94 | static const char *esdhc_sels[] = { "pll3_usb_otg", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; |
81 | static const char *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; | 95 | static const char *dcu_sels[] = { "pll1_pfd2", "pll3_usb_otg", }; |
82 | static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; | 96 | static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; |
83 | static const char *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; | 97 | static const char *vadc_sels[] = { "pll6_video_div", "pll3_usb_otg_div", "pll3_usb_otg", }; |
84 | /* FTM counter clock source, not module clock */ | 98 | /* FTM counter clock source, not module clock */ |
85 | static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; | 99 | static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; |
86 | static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; | 100 | static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; |
87 | 101 | ||
88 | static struct clk_div_table pll4_main_div_table[] = { | 102 | |
103 | static struct clk_div_table pll4_audio_div_table[] = { | ||
89 | { .val = 0, .div = 1 }, | 104 | { .val = 0, .div = 1 }, |
90 | { .val = 1, .div = 2 }, | 105 | { .val = 1, .div = 2 }, |
91 | { .val = 2, .div = 6 }, | 106 | { .val = 2, .div = 6 }, |
@@ -120,6 +135,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) | |||
120 | clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0); | 135 | clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0); |
121 | clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0); | 136 | clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0); |
122 | 137 | ||
138 | /* Clock source from external clock via LVDs PAD */ | ||
139 | clk[VF610_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); | ||
140 | |||
123 | clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); | 141 | clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); |
124 | 142 | ||
125 | np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); | 143 | np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); |
@@ -133,31 +151,63 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) | |||
133 | clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); | 151 | clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); |
134 | clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); | 152 | clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); |
135 | 153 | ||
136 | clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1); | 154 | clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
137 | clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0); | 155 | clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
138 | clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1); | 156 | clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
139 | clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2); | 157 | clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
140 | clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3); | 158 | clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
141 | 159 | clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
142 | clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1); | 160 | clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
143 | clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0); | 161 | |
144 | clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1); | 162 | clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); |
145 | clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2); | 163 | clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); |
146 | clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3); | 164 | clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1); |
147 | 165 | clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); | |
148 | clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1); | 166 | clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); |
149 | clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0); | 167 | clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); |
150 | clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1); | 168 | clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1); |
151 | clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2); | 169 | |
152 | clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3); | 170 | clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); |
153 | 171 | clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); | |
154 | clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1); | 172 | clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); |
155 | /* Enet pll: fixed 50Mhz */ | 173 | clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); |
156 | clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); | 174 | clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); |
157 | /* pll6: default 960Mhz */ | 175 | clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); |
158 | clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); | 176 | clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); |
159 | /* pll7: USB1 PLL at 480MHz */ | 177 | |
160 | clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2); | 178 | /* Do not bypass PLLs initially */ |
179 | clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); | ||
180 | clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); | ||
181 | clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); | ||
182 | clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); | ||
183 | clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); | ||
184 | clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); | ||
185 | clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); | ||
186 | |||
187 | clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", PLL1_CTRL, 13); | ||
188 | clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", PLL2_CTRL, 13); | ||
189 | clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", PLL3_CTRL, 13); | ||
190 | clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", PLL4_CTRL, 13); | ||
191 | clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13); | ||
192 | clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video", "pll6_bypass", PLL6_CTRL, 13); | ||
193 | clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13); | ||
194 | |||
195 | clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10)); | ||
196 | |||
197 | clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0); | ||
198 | clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1); | ||
199 | clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2); | ||
200 | clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3); | ||
201 | |||
202 | clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0); | ||
203 | clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1); | ||
204 | clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2); | ||
205 | clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3); | ||
206 | |||
207 | clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0); | ||
208 | clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1); | ||
209 | clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2); | ||
210 | clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3); | ||
161 | 211 | ||
162 | clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); | 212 | clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); |
163 | clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); | 213 | clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); |
@@ -167,12 +217,12 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) | |||
167 | clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); | 217 | clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); |
168 | clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); | 218 | clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); |
169 | 219 | ||
170 | clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); | 220 | clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1); |
171 | clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); | 221 | clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); |
172 | clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); | 222 | clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1); |
173 | 223 | ||
174 | clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6); | 224 | clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6); |
175 | clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6); | 225 | clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6); |
176 | 226 | ||
177 | clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); | 227 | clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); |
178 | clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); | 228 | clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); |
@@ -191,8 +241,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) | |||
191 | clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); | 241 | clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); |
192 | clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); | 242 | clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); |
193 | 243 | ||
194 | clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); | 244 | clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10); |
195 | clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); | 245 | clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20); |
196 | clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); | 246 | clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); |
197 | clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); | 247 | clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); |
198 | clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); | 248 | clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); |
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 123f578d6dd3..4cfaaa5a49be 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c | |||
@@ -1107,52 +1107,14 @@ bool edma_filter_fn(struct dma_chan *chan, void *param) | |||
1107 | } | 1107 | } |
1108 | EXPORT_SYMBOL(edma_filter_fn); | 1108 | EXPORT_SYMBOL(edma_filter_fn); |
1109 | 1109 | ||
1110 | static struct platform_device *pdev0, *pdev1; | ||
1111 | |||
1112 | static const struct platform_device_info edma_dev_info0 = { | ||
1113 | .name = "edma-dma-engine", | ||
1114 | .id = 0, | ||
1115 | .dma_mask = DMA_BIT_MASK(32), | ||
1116 | }; | ||
1117 | |||
1118 | static const struct platform_device_info edma_dev_info1 = { | ||
1119 | .name = "edma-dma-engine", | ||
1120 | .id = 1, | ||
1121 | .dma_mask = DMA_BIT_MASK(32), | ||
1122 | }; | ||
1123 | |||
1124 | static int edma_init(void) | 1110 | static int edma_init(void) |
1125 | { | 1111 | { |
1126 | int ret = platform_driver_register(&edma_driver); | 1112 | return platform_driver_register(&edma_driver); |
1127 | |||
1128 | if (ret == 0) { | ||
1129 | pdev0 = platform_device_register_full(&edma_dev_info0); | ||
1130 | if (IS_ERR(pdev0)) { | ||
1131 | platform_driver_unregister(&edma_driver); | ||
1132 | ret = PTR_ERR(pdev0); | ||
1133 | goto out; | ||
1134 | } | ||
1135 | } | ||
1136 | |||
1137 | if (!of_have_populated_dt() && EDMA_CTLRS == 2) { | ||
1138 | pdev1 = platform_device_register_full(&edma_dev_info1); | ||
1139 | if (IS_ERR(pdev1)) { | ||
1140 | platform_driver_unregister(&edma_driver); | ||
1141 | platform_device_unregister(pdev0); | ||
1142 | ret = PTR_ERR(pdev1); | ||
1143 | } | ||
1144 | } | ||
1145 | |||
1146 | out: | ||
1147 | return ret; | ||
1148 | } | 1113 | } |
1149 | subsys_initcall(edma_init); | 1114 | subsys_initcall(edma_init); |
1150 | 1115 | ||
1151 | static void __exit edma_exit(void) | 1116 | static void __exit edma_exit(void) |
1152 | { | 1117 | { |
1153 | platform_device_unregister(pdev0); | ||
1154 | if (pdev1) | ||
1155 | platform_device_unregister(pdev1); | ||
1156 | platform_driver_unregister(&edma_driver); | 1118 | platform_driver_unregister(&edma_driver); |
1157 | } | 1119 | } |
1158 | module_exit(edma_exit); | 1120 | module_exit(edma_exit); |
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index d6b56b21539b..801c0ac50c47 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h | |||
@@ -21,24 +21,24 @@ | |||
21 | #define VF610_CLK_FASK_CLK_SEL 8 | 21 | #define VF610_CLK_FASK_CLK_SEL 8 |
22 | #define VF610_CLK_AUDIO_EXT 9 | 22 | #define VF610_CLK_AUDIO_EXT 9 |
23 | #define VF610_CLK_ENET_EXT 10 | 23 | #define VF610_CLK_ENET_EXT 10 |
24 | #define VF610_CLK_PLL1_MAIN 11 | 24 | #define VF610_CLK_PLL1_SYS 11 |
25 | #define VF610_CLK_PLL1_PFD1 12 | 25 | #define VF610_CLK_PLL1_PFD1 12 |
26 | #define VF610_CLK_PLL1_PFD2 13 | 26 | #define VF610_CLK_PLL1_PFD2 13 |
27 | #define VF610_CLK_PLL1_PFD3 14 | 27 | #define VF610_CLK_PLL1_PFD3 14 |
28 | #define VF610_CLK_PLL1_PFD4 15 | 28 | #define VF610_CLK_PLL1_PFD4 15 |
29 | #define VF610_CLK_PLL2_MAIN 16 | 29 | #define VF610_CLK_PLL2_BUS 16 |
30 | #define VF610_CLK_PLL2_PFD1 17 | 30 | #define VF610_CLK_PLL2_PFD1 17 |
31 | #define VF610_CLK_PLL2_PFD2 18 | 31 | #define VF610_CLK_PLL2_PFD2 18 |
32 | #define VF610_CLK_PLL2_PFD3 19 | 32 | #define VF610_CLK_PLL2_PFD3 19 |
33 | #define VF610_CLK_PLL2_PFD4 20 | 33 | #define VF610_CLK_PLL2_PFD4 20 |
34 | #define VF610_CLK_PLL3_MAIN 21 | 34 | #define VF610_CLK_PLL3_USB_OTG 21 |
35 | #define VF610_CLK_PLL3_PFD1 22 | 35 | #define VF610_CLK_PLL3_PFD1 22 |
36 | #define VF610_CLK_PLL3_PFD2 23 | 36 | #define VF610_CLK_PLL3_PFD2 23 |
37 | #define VF610_CLK_PLL3_PFD3 24 | 37 | #define VF610_CLK_PLL3_PFD3 24 |
38 | #define VF610_CLK_PLL3_PFD4 25 | 38 | #define VF610_CLK_PLL3_PFD4 25 |
39 | #define VF610_CLK_PLL4_MAIN 26 | 39 | #define VF610_CLK_PLL4_AUDIO 26 |
40 | #define VF610_CLK_PLL5_MAIN 27 | 40 | #define VF610_CLK_PLL5_ENET 27 |
41 | #define VF610_CLK_PLL6_MAIN 28 | 41 | #define VF610_CLK_PLL6_VIDEO 28 |
42 | #define VF610_CLK_PLL3_MAIN_DIV 29 | 42 | #define VF610_CLK_PLL3_MAIN_DIV 29 |
43 | #define VF610_CLK_PLL4_MAIN_DIV 30 | 43 | #define VF610_CLK_PLL4_MAIN_DIV 30 |
44 | #define VF610_CLK_PLL6_MAIN_DIV 31 | 44 | #define VF610_CLK_PLL6_MAIN_DIV 31 |
@@ -166,9 +166,32 @@ | |||
166 | #define VF610_CLK_DMAMUX3 153 | 166 | #define VF610_CLK_DMAMUX3 153 |
167 | #define VF610_CLK_FLEXCAN0_EN 154 | 167 | #define VF610_CLK_FLEXCAN0_EN 154 |
168 | #define VF610_CLK_FLEXCAN1_EN 155 | 168 | #define VF610_CLK_FLEXCAN1_EN 155 |
169 | #define VF610_CLK_PLL7_MAIN 156 | 169 | #define VF610_CLK_PLL7_USB_HOST 156 |
170 | #define VF610_CLK_USBPHY0 157 | 170 | #define VF610_CLK_USBPHY0 157 |
171 | #define VF610_CLK_USBPHY1 158 | 171 | #define VF610_CLK_USBPHY1 158 |
172 | #define VF610_CLK_END 159 | 172 | #define VF610_CLK_LVDS1_IN 159 |
173 | #define VF610_CLK_ANACLK1 160 | ||
174 | #define VF610_CLK_PLL1_BYPASS_SRC 161 | ||
175 | #define VF610_CLK_PLL2_BYPASS_SRC 162 | ||
176 | #define VF610_CLK_PLL3_BYPASS_SRC 163 | ||
177 | #define VF610_CLK_PLL4_BYPASS_SRC 164 | ||
178 | #define VF610_CLK_PLL5_BYPASS_SRC 165 | ||
179 | #define VF610_CLK_PLL6_BYPASS_SRC 166 | ||
180 | #define VF610_CLK_PLL7_BYPASS_SRC 167 | ||
181 | #define VF610_CLK_PLL1 168 | ||
182 | #define VF610_CLK_PLL2 169 | ||
183 | #define VF610_CLK_PLL3 170 | ||
184 | #define VF610_CLK_PLL4 171 | ||
185 | #define VF610_CLK_PLL5 172 | ||
186 | #define VF610_CLK_PLL6 173 | ||
187 | #define VF610_CLK_PLL7 174 | ||
188 | #define VF610_PLL1_BYPASS 175 | ||
189 | #define VF610_PLL2_BYPASS 176 | ||
190 | #define VF610_PLL3_BYPASS 177 | ||
191 | #define VF610_PLL4_BYPASS 178 | ||
192 | #define VF610_PLL5_BYPASS 179 | ||
193 | #define VF610_PLL6_BYPASS 180 | ||
194 | #define VF610_PLL7_BYPASS 181 | ||
195 | #define VF610_CLK_END 182 | ||
173 | 196 | ||
174 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ | 197 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ |