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authorPatil, Rachna <rachna@ti.com>2013-07-20 12:27:00 -0400
committerJonathan Cameron <jic23@kernel.org>2013-07-21 13:27:35 -0400
commitb1451e546899bc8f450773b2af02e0cd000cf1fa (patch)
treeb4147d4c31a3572c0c6c427fcd1ae8dfc7401c6c
parenta1a8e1dc111d6f05e7164e851e58219d428359e1 (diff)
iio: ti_am335x_adc: Fix wrong samples received on 1st read
Previously we tried to read data form ADC even before ADC sequencer finished sampling. This led to wrong samples. We now wait on ADC status register idle bit to be set. Signed-off-by: Patil, Rachna <rachna@ti.com> Signed-off-by: Zubair Lutfullah <zubair.lutfullah@gmail.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
-rw-r--r--drivers/iio/adc/ti_am335x_adc.c30
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h16
2 files changed, 38 insertions, 8 deletions
diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c
index 0ad208a69c29..3ceac3e91dde 100644
--- a/drivers/iio/adc/ti_am335x_adc.c
+++ b/drivers/iio/adc/ti_am335x_adc.c
@@ -60,7 +60,6 @@ static void tiadc_step_config(struct tiadc_device *adc_dev)
60{ 60{
61 unsigned int stepconfig; 61 unsigned int stepconfig;
62 int i, steps; 62 int i, steps;
63 u32 step_en;
64 63
65 /* 64 /*
66 * There are 16 configurable steps and 8 analog input 65 * There are 16 configurable steps and 8 analog input
@@ -86,8 +85,7 @@ static void tiadc_step_config(struct tiadc_device *adc_dev)
86 adc_dev->channel_step[i] = steps; 85 adc_dev->channel_step[i] = steps;
87 steps++; 86 steps++;
88 } 87 }
89 step_en = get_adc_step_mask(adc_dev); 88
90 am335x_tsc_se_set(adc_dev->mfd_tscadc, step_en);
91} 89}
92 90
93static const char * const chan_name_ain[] = { 91static const char * const chan_name_ain[] = {
@@ -142,10 +140,22 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
142 int *val, int *val2, long mask) 140 int *val, int *val2, long mask)
143{ 141{
144 struct tiadc_device *adc_dev = iio_priv(indio_dev); 142 struct tiadc_device *adc_dev = iio_priv(indio_dev);
145 int i; 143 int i, map_val;
146 unsigned int fifo1count, read; 144 unsigned int fifo1count, read, stepid;
147 u32 step = UINT_MAX; 145 u32 step = UINT_MAX;
148 bool found = false; 146 bool found = false;
147 u32 step_en;
148 unsigned long timeout = jiffies + usecs_to_jiffies
149 (IDLE_TIMEOUT * adc_dev->channels);
150 step_en = get_adc_step_mask(adc_dev);
151 am335x_tsc_se_set(adc_dev->mfd_tscadc, step_en);
152
153 /* Wait for ADC sequencer to complete sampling */
154 while (tiadc_readl(adc_dev, REG_ADCFSM) & SEQ_STATUS) {
155 if (time_after(jiffies, timeout))
156 return -EAGAIN;
157 }
158 map_val = chan->channel + TOTAL_CHANNELS;
149 159
150 /* 160 /*
151 * When the sub-system is first enabled, 161 * When the sub-system is first enabled,
@@ -170,12 +180,16 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
170 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); 180 fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
171 for (i = 0; i < fifo1count; i++) { 181 for (i = 0; i < fifo1count; i++) {
172 read = tiadc_readl(adc_dev, REG_FIFO1); 182 read = tiadc_readl(adc_dev, REG_FIFO1);
173 if (read >> 16 == step) { 183 stepid = read & FIFOREAD_CHNLID_MASK;
174 *val = read & 0xfff; 184 stepid = stepid >> 0x10;
185
186 if (stepid == map_val) {
187 read = read & FIFOREAD_DATA_MASK;
175 found = true; 188 found = true;
189 *val = read;
176 } 190 }
177 } 191 }
178 am335x_tsc_se_update(adc_dev->mfd_tscadc); 192
179 if (found == false) 193 if (found == false)
180 return -EBUSY; 194 return -EBUSY;
181 return IIO_VAL_INT; 195 return IIO_VAL_INT;
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index 8d73fe29796a..db1791bb997a 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -113,11 +113,27 @@
113#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) 113#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
114#define CNTRLREG_TSCENB BIT(7) 114#define CNTRLREG_TSCENB BIT(7)
115 115
116/* FIFO READ Register */
117#define FIFOREAD_DATA_MASK (0xfff << 0)
118#define FIFOREAD_CHNLID_MASK (0xf << 16)
119
120/* Sequencer Status */
121#define SEQ_STATUS BIT(5)
122
116#define ADC_CLK 3000000 123#define ADC_CLK 3000000
117#define MAX_CLK_DIV 7 124#define MAX_CLK_DIV 7
118#define TOTAL_STEPS 16 125#define TOTAL_STEPS 16
119#define TOTAL_CHANNELS 8 126#define TOTAL_CHANNELS 8
120 127
128/*
129* ADC runs at 3MHz, and it takes
130* 15 cycles to latch one data output.
131* Hence the idle time for ADC to
132* process one sample data would be
133* around 5 micro seconds.
134*/
135#define IDLE_TIMEOUT 5 /* microsec */
136
121#define TSCADC_CELLS 2 137#define TSCADC_CELLS 2
122 138
123struct ti_tscadc_dev { 139struct ti_tscadc_dev {