Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
 "A collection of fixes pretty much across the MIPS code.  Even the
  change to include/linux/signal.h by David Howells' 2a1486981c13 ("Fix
  breakage in MIPS siginfo handling") should be considered MIPS-specific
  as it touches an ifdefed segment that is only relevant to MIPS and
  which unfortunately can't be made to go away entirely."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  Fix breakage in MIPS siginfo handling
  Revert "MIPS: BCM63XX: Call board_register_device from device_initcall()"
  MIPS: BCM63XX: Make nvram checksum failure non fatal
  MIPS: Fix code generation for non-DSP capable CPUs
  MIPS: Fix inconsistent formatting inside /proc/cpuinfo
  MIPS: SEAD3: Enable LL/SC.
  MIPS: Get rid of CONFIG_CPU_HAS_LLSC again
  MIPS: Add dependencies for HAVE_ARCH_TRANSPARENT_HUGEPAGE
  MIPS: VR4133: Fix probe for LL/SC.
  MIPS: Fix logic errors in bitops.c
  MIPS: Use CONFIG_CPU_MIPSR2 in csum_partial.S
  MIPS: compat: Return same error ENOSYS as native for invalid operation.

16 files changed, 224 insertions, 76 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cd2e21ff562a..a6fdd1643903 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -18,7 +18,7 @@ config MIPS
         select HAVE_KRETPROBES
         select HAVE_DEBUG_KMEMLEAK
         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
-        select HAVE_ARCH_TRANSPARENT_HUGEPAGE
+        select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -1493,7 +1493,6 @@ config CPU_XLP
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
-        select CPU_HAS_LLSC
         select WEAK_ORDERING
         select WEAK_REORDERING_BEYOND_LLSC
         select CPU_HAS_PREFETCH
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index ed1949c29508..9aa7d44898ed 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -745,10 +745,7 @@ void __init board_prom_init(void)
                 strcpy(cfe_version, "unknown");
         printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
 
-        if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) {
-                printk(KERN_ERR PFX "invalid nvram checksum\n");
-                return;
-        }
+        bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
 
         board_name = bcm63xx_nvram_get_name();
         /* find board by name */
diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c
index 620611680839..a4b8864f9307 100644
--- a/arch/mips/bcm63xx/nvram.c
+++ b/arch/mips/bcm63xx/nvram.c
@@ -38,7 +38,7 @@ struct bcm963xx_nvram {
 static struct bcm963xx_nvram nvram;
 static int mac_addr_used;
 
-int __init bcm63xx_nvram_init(void *addr)
+void __init bcm63xx_nvram_init(void *addr)
 {
         unsigned int check_len;
         u32 crc, expected_crc;
@@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr)
         crc = crc32_le(~0, (u8 *)&nvram, check_len);
 
         if (crc != expected_crc)
-                return -EINVAL;
-
-        return 0;
+                pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
+                        expected_crc, crc);
 }
 
 u8 *bcm63xx_nvram_get_name(void)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 314231be788c..35e18e98beb9 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void)
         return board_register_devices();
 }
 
-device_initcall(bcm63xx_register_devices);
+arch_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
index 62d6a3b4d3b7..4e0b6bc1165e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -9,10 +9,8 @@
  *
  * Initialized the local nvram copy from the target address and checks
  * its checksum.
- *
- * Returns 0 on success.
  */
-int __init bcm63xx_nvram_init(void *nvram);
+void bcm63xx_nvram_init(void *nvram);
 
 /**
  * bcm63xx_nvram_get_name() - returns the board name according to nvram
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index d9c828419037..193c0912d38e 100644
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -28,11 +28,7 @@
 /* #define cpu_has_prefetch     ? */
 #define cpu_has_mcheck          1
 /* #define cpu_has_ejtag        ? */
-#ifdef CONFIG_CPU_HAS_LLSC
 #define cpu_has_llsc            1
-#else
-#define cpu_has_llsc            0
-#endif
 /* #define cpu_has_vtag_icache  ? */
 /* #define cpu_has_dc_aliases   ? */
 /* #define cpu_has_ic_fills_f_dc ? */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 12b70c25906a..0da44d422f5b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1166,7 +1166,10 @@ do {									\
         unsigned int __dspctl;                                          \
                                                                         \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
         "       rddsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
         : "=r" (__dspctl)                                               \
         : "i" (mask));                                                  \
         __dspctl;                                                       \
@@ -1175,30 +1178,198 @@ do {									\
 #define wrdsp(val, mask)                                                \
 do {                                                                    \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
         "       wrdsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
         :                                                               \
         : "r" (val), "i" (mask));                                       \
 } while (0)
 
-#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
-#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
-#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
-#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
-
-#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
-#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
-#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
-#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
-
-#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
-#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
-#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
-#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
-
-#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
-#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
-#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
-#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
+#define mflo0()                                                         \
+({                                                                      \
+        long mflo0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo0));                                                \
+        mflo0;                                                          \
+})
+
+#define mflo1()                                                         \
+({                                                                      \
+        long mflo1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo1));                                                \
+        mflo1;                                                          \
+})
+
+#define mflo2()                                                         \
+({                                                                      \
+        long mflo2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo2));                                                \
+        mflo2;                                                          \
+})
+
+#define mflo3()                                                         \
+({                                                                      \
+        long mflo3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo3));                                                \
+        mflo3;                                                          \
+})
+
+#define mfhi0()                                                         \
+({                                                                      \
+        long mfhi0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi0));                                                \
+        mfhi0;                                                          \
+})
+
+#define mfhi1()                                                         \
+({                                                                      \
+        long mfhi1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi1));                                                \
+        mfhi1;                                                          \
+})
+
+#define mfhi2()                                                         \
+({                                                                      \
+        long mfhi2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi2));                                                \
+        mfhi2;                                                          \
+})
+
+#define mfhi3()                                                         \
+({                                                                      \
+        long mfhi3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi3));                                                \
+        mfhi3;                                                          \
+})
+
+
+#define mtlo0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
 
 #else
 
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index 197f6367c201..8efe5a9e2c3e 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -21,6 +21,6 @@
 #include <asm/sigcontext.h>
 #include <asm/siginfo.h>
 
-#define __ARCH_HAS_ODD_SIGACTION
+#define __ARCH_HAS_IRIX_SIGACTION
 
 #endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index f81d98f6184c..de75fb50562b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_mipsxx.o
 obj-$(CONFIG_JUMP_LABEL)        += jump_label.o
 
 #
-# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
-# to enable DSP assembler support here even if the MIPS Release 2 CPU we
-# are targetting does not support DSP because all code-paths making use of
-# it properly check that the running CPU *actually does* support these
-# instructions.
+# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
+# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
+# here because the compiler may use DSP ASE instructions (such as lwx) in
+# code paths where we cannot check that the CPU we are running on supports it.
+# Proper abstraction using HAVE_AS_DSP and macros is done in
+# arch/mips/include/asm/mipsregs.h.
 #
 ifeq ($(CONFIG_CPU_MIPSR2), y)
 CFLAGS_DSP                      = -DHAVE_AS_DSP
 
-#
-# Check if assembler supports DSP ASE
-#
-ifeq ($(call cc-option-yn,-mdsp), y)
-CFLAGS_DSP                      += -mdsp
-endif
-
-#
-# Check if assembler supports DSP ASE Rev2
-#
-ifeq ($(call cc-option-yn,-mdspr2), y)
-CFLAGS_DSP                      += -mdspr2
-endif
-
 CFLAGS_signal.o                 = $(CFLAGS_DSP)
 CFLAGS_signal32.o               = $(CFLAGS_DSP)
 CFLAGS_process.o                = $(CFLAGS_DSP)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6bfccc227a95..d069a19112e8 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                 c->tlbsize = 48;
                 break;
         case PRID_IMP_VR41XX:
+                set_isa(c, MIPS_CPU_ISA_III);
+                c->options = R4K_OPTS;
+                c->tlbsize = 32;
                 switch (c->processor_id & 0xf0) {
                 case PRID_REV_VR4111:
                         c->cputype = CPU_VR4111;
@@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                                 __cpu_name[cpu] = "NEC VR4131";
                         } else {
                                 c->cputype = CPU_VR4133;
+                                c->options |= MIPS_CPU_LLSC;
                                 __cpu_name[cpu] = "NEC VR4133";
                         }
                         break;
@@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                         __cpu_name[cpu] = "NEC Vr41xx";
                         break;
                 }
-                set_isa(c, MIPS_CPU_ISA_III);
-                c->options = R4K_OPTS;
-                c->tlbsize = 32;
                 break;
         case PRID_IMP_R4300:
                 c->cputype = CPU_R4300;
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 8eeee1c860c0..db9655f08892 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
                 err = compat_sys_shmctl(first, second, compat_ptr(ptr));
                 break;
         default:
-                err = -EINVAL;
+                err = -ENOSYS;
                 break;
         }
 
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 135c4aadccbe..7a54f74b7818 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         if (cpu_has_mips_r) {
                 seq_printf(m, "isa\t\t\t:");
                 if (cpu_has_mips_1)
-                        seq_printf(m, "%s", "mips1");
+                        seq_printf(m, "%s", " mips1");
                 if (cpu_has_mips_2)
                         seq_printf(m, "%s", " mips2");
                 if (cpu_has_mips_3)
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
index 81f1dcfdcab8..a64daee740ee 100644
--- a/arch/mips/lib/bitops.c
+++ b/arch/mips/lib/bitops.c
@@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr,
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a |= mask;
         raw_local_irq_restore(flags);
         return res;
@@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr,
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a |= mask;
         raw_local_irq_restore(flags);
         return res;
@@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a &= ~mask;
         raw_local_irq_restore(flags);
         return res;
@@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a ^= mask;
         raw_local_irq_restore(flags);
         return res;
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 507147aebd41..a6adffbb4e5f 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -270,7 +270,7 @@ LEAF(csum_partial)
 #endif
 
         /* odd buffer alignment? */
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
         wsbh    v1, sum
         movn    sum, v1, t7
 #else
@@ -670,7 +670,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
         addu    sum, v1
 #endif
 
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
         wsbh    v1, sum
         movn    sum, v1, odd
 #else
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 76a87fb57ac2..377cd8c3395e 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -141,11 +141,11 @@ typedef struct {
 } compat_sigset_t;
 
 struct compat_sigaction {
-#ifndef __ARCH_HAS_ODD_SIGACTION
+#ifndef __ARCH_HAS_IRIX_SIGACTION
         compat_uptr_t                   sa_handler;
         compat_ulong_t                  sa_flags;
 #else
-        compat_ulong_t                  sa_flags;
+        compat_uint_t                   sa_flags;
         compat_uptr_t                   sa_handler;
 #endif
 #ifdef __ARCH_HAS_SA_RESTORER
diff --git a/include/linux/signal.h b/include/linux/signal.h
index a2dcb94ea49d..9475c5cb28bc 100644
--- a/include/linux/signal.h
+++ b/include/linux/signal.h
@@ -250,11 +250,11 @@ extern int show_unhandled_signals;
 extern int sigsuspend(sigset_t *);
 
 struct sigaction {
-#ifndef __ARCH_HAS_ODD_SIGACTION
+#ifndef __ARCH_HAS_IRIX_SIGACTION
         __sighandler_t  sa_handler;
         unsigned long   sa_flags;
 #else
-        unsigned long   sa_flags;
+        unsigned int    sa_flags;
         __sighandler_t  sa_handler;
 #endif
 #ifdef __ARCH_HAS_SA_RESTORER