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authorSujith <Sujith.Manoharan@atheros.com>2009-03-12 23:26:04 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-03-27 20:12:49 -0400
commita83615d74d9b952f24c904baad58610ed9d76838 (patch)
tree29589bcca77d3dc44b90b3f1c5518501a749ceac
parent355363fcf7daded4a48308b54d6b86bea4f8bb6d (diff)
ath9k: Introduce a helper function for setting board gain values
This improves readability. Handle both 4K/non-4K EEPROM in this patch. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c219
1 files changed, 99 insertions, 120 deletions
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index 49dee238c683..c3bb1968bb5e 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -1193,57 +1193,63 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1193 } 1193 }
1194} 1194}
1195 1195
1196static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, 1196static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
1197 struct ath9k_channel *chan) 1197 struct modal_eep_4k_header *pModal,
1198 struct ar5416_eeprom_4k *eep,
1199 u8 txRxAttenLocal, int regChainOffset)
1198{ 1200{
1199 struct modal_eep_4k_header *pModal;
1200 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1201 int regChainOffset;
1202 u8 txRxAttenLocal;
1203 u8 ob[5], db1[5], db2[5];
1204 u8 ant_div_control1, ant_div_control2;
1205 u32 regVal;
1206
1207
1208 pModal = &eep->modalHeader;
1209
1210 txRxAttenLocal = 23;
1211
1212 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1213 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1214
1215 regChainOffset = 0;
1216 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, 1201 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1217 pModal->antCtrlChain[0]); 1202 pModal->antCtrlChain[0]);
1218 1203
1219 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 1204 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1220 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & 1205 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1221 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 1206 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1222 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1207 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1223 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1208 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1224 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1209 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1225 1210
1226 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1211 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1227 AR5416_EEP_MINOR_VER_3) { 1212 AR5416_EEP_MINOR_VER_3) {
1228 txRxAttenLocal = pModal->txRxAttenCh[0]; 1213 txRxAttenLocal = pModal->txRxAttenCh[0];
1214
1229 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1215 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1230 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 1216 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1231 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1217 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1232 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 1218 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1233 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1219 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1234 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 1220 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1235 pModal->xatten2Margin[0]); 1221 pModal->xatten2Margin[0]);
1236 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1222 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1237 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 1223 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1238 } 1224 }
1239 1225
1240 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 1226 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1241 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1227 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1242 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 1228 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1243 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 1229 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1244 1230
1245 if (AR_SREV_9285_11(ah)) 1231 if (AR_SREV_9285_11(ah))
1246 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 1232 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1233}
1234
1235static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1236 struct ath9k_channel *chan)
1237{
1238 struct modal_eep_4k_header *pModal;
1239 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1240 u8 txRxAttenLocal;
1241 u8 ob[5], db1[5], db2[5];
1242 u8 ant_div_control1, ant_div_control2;
1243 u32 regVal;
1244
1245 pModal = &eep->modalHeader;
1246 txRxAttenLocal = 23;
1247
1248 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1249 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1250
1251 /* Single chain for 4K EEPROM*/
1252 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal, 0);
1247 1253
1248 /* Initialize Ant Diversity settings from EEPROM */ 1254 /* Initialize Ant Diversity settings from EEPROM */
1249 if (pModal->version == 3) { 1255 if (pModal->version == 3) {
@@ -1656,7 +1662,62 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1656 } 1662 }
1657} 1663}
1658 1664
1659/* XXX: Clean me up, make me more legible */ 1665static void ath9k_hw_def_set_gain(struct ath_hw *ah,
1666 struct modal_eep_header *pModal,
1667 struct ar5416_eeprom_def *eep,
1668 u8 txRxAttenLocal, int regChainOffset, int i)
1669{
1670 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1671 txRxAttenLocal = pModal->txRxAttenCh[i];
1672
1673 if (AR_SREV_9280_10_OR_LATER(ah)) {
1674 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1675 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1676 pModal->bswMargin[i]);
1677 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1678 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1679 pModal->bswAtten[i]);
1680 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1681 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1682 pModal->xatten2Margin[i]);
1683 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1684 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1685 pModal->xatten2Db[i]);
1686 } else {
1687 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1688 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1689 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1690 | SM(pModal-> bswMargin[i],
1691 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1692 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1693 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1694 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1695 | SM(pModal->bswAtten[i],
1696 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1697 }
1698 }
1699
1700 if (AR_SREV_9280_10_OR_LATER(ah)) {
1701 REG_RMW_FIELD(ah,
1702 AR_PHY_RXGAIN + regChainOffset,
1703 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1704 REG_RMW_FIELD(ah,
1705 AR_PHY_RXGAIN + regChainOffset,
1706 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
1707 } else {
1708 REG_WRITE(ah,
1709 AR_PHY_RXGAIN + regChainOffset,
1710 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
1711 ~AR_PHY_RXGAIN_TXRX_ATTEN)
1712 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
1713 REG_WRITE(ah,
1714 AR_PHY_GAIN_2GHZ + regChainOffset,
1715 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1716 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1717 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1718 }
1719}
1720
1660static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, 1721static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1661 struct ath9k_channel *chan) 1722 struct ath9k_channel *chan)
1662{ 1723{
@@ -1666,7 +1727,6 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1666 u8 txRxAttenLocal; 1727 u8 txRxAttenLocal;
1667 1728
1668 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 1729 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1669
1670 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; 1730 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1671 1731
1672 REG_WRITE(ah, AR_PHY_SWITCH_COM, 1732 REG_WRITE(ah, AR_PHY_SWITCH_COM,
@@ -1679,8 +1739,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1679 } 1739 }
1680 1740
1681 if (AR_SREV_5416_20_OR_LATER(ah) && 1741 if (AR_SREV_5416_20_OR_LATER(ah) &&
1682 (ah->rxchainmask == 5 || ah->txchainmask == 5) 1742 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
1683 && (i != 0))
1684 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1743 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1685 else 1744 else
1686 regChainOffset = i * 0x1000; 1745 regChainOffset = i * 0x1000;
@@ -1689,9 +1748,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1689 pModal->antCtrlChain[i]); 1748 pModal->antCtrlChain[i]);
1690 1749
1691 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 1750 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1692 (REG_READ(ah, 1751 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1693 AR_PHY_TIMING_CTRL4(0) +
1694 regChainOffset) &
1695 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 1752 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1696 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1753 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1697 SM(pModal->iqCalICh[i], 1754 SM(pModal->iqCalICh[i],
@@ -1699,87 +1756,9 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1699 SM(pModal->iqCalQCh[i], 1756 SM(pModal->iqCalQCh[i],
1700 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1757 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1701 1758
1702 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 1759 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
1703 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { 1760 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
1704 txRxAttenLocal = pModal->txRxAttenCh[i]; 1761 regChainOffset, i);
1705 if (AR_SREV_9280_10_OR_LATER(ah)) {
1706 REG_RMW_FIELD(ah,
1707 AR_PHY_GAIN_2GHZ +
1708 regChainOffset,
1709 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1710 pModal->
1711 bswMargin[i]);
1712 REG_RMW_FIELD(ah,
1713 AR_PHY_GAIN_2GHZ +
1714 regChainOffset,
1715 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1716 pModal->
1717 bswAtten[i]);
1718 REG_RMW_FIELD(ah,
1719 AR_PHY_GAIN_2GHZ +
1720 regChainOffset,
1721 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1722 pModal->
1723 xatten2Margin[i]);
1724 REG_RMW_FIELD(ah,
1725 AR_PHY_GAIN_2GHZ +
1726 regChainOffset,
1727 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1728 pModal->
1729 xatten2Db[i]);
1730 } else {
1731 REG_WRITE(ah,
1732 AR_PHY_GAIN_2GHZ +
1733 regChainOffset,
1734 (REG_READ(ah,
1735 AR_PHY_GAIN_2GHZ +
1736 regChainOffset) &
1737 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1738 | SM(pModal->
1739 bswMargin[i],
1740 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1741 REG_WRITE(ah,
1742 AR_PHY_GAIN_2GHZ +
1743 regChainOffset,
1744 (REG_READ(ah,
1745 AR_PHY_GAIN_2GHZ +
1746 regChainOffset) &
1747 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1748 | SM(pModal->bswAtten[i],
1749 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1750 }
1751 }
1752 if (AR_SREV_9280_10_OR_LATER(ah)) {
1753 REG_RMW_FIELD(ah,
1754 AR_PHY_RXGAIN +
1755 regChainOffset,
1756 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1757 txRxAttenLocal);
1758 REG_RMW_FIELD(ah,
1759 AR_PHY_RXGAIN +
1760 regChainOffset,
1761 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1762 pModal->rxTxMarginCh[i]);
1763 } else {
1764 REG_WRITE(ah,
1765 AR_PHY_RXGAIN + regChainOffset,
1766 (REG_READ(ah,
1767 AR_PHY_RXGAIN +
1768 regChainOffset) &
1769 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1770 SM(txRxAttenLocal,
1771 AR_PHY_RXGAIN_TXRX_ATTEN));
1772 REG_WRITE(ah,
1773 AR_PHY_GAIN_2GHZ +
1774 regChainOffset,
1775 (REG_READ(ah,
1776 AR_PHY_GAIN_2GHZ +
1777 regChainOffset) &
1778 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1779 SM(pModal->rxTxMarginCh[i],
1780 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1781 }
1782 }
1783 } 1762 }
1784 1763
1785 if (AR_SREV_9280_10_OR_LATER(ah)) { 1764 if (AR_SREV_9280_10_OR_LATER(ah)) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-31 18:55:13 -0500