ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DL

i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 86567d980b07..82a85cea7ce0 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -554,7 +554,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
         clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
 
-        if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
+        if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
                 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
                 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
         }