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authorBaruch Siach <baruch@tkos.co.il>2013-11-28 11:00:04 -0500
committerMax Filippov <jcmvbkbc@gmail.com>2014-01-14 15:27:03 -0500
commita6f3eefad8d1c9abd98fa03ba2b3abeb708e3b95 (patch)
treebad16557f26b29175252d299bfe4ba0b93845d19
parent6cb971114f633a0bf240c20b681d989b45e3ec56 (diff)
xtensa: enable HAVE_PERF_EVENTS
This allows the perf tool to monitor kernel tracepoint events. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
-rw-r--r--arch/xtensa/Kconfig1
-rw-r--r--arch/xtensa/include/asm/perf_event.h4
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 49d2e843552b..c3ccf379289a 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -19,6 +19,7 @@ config XTENSA
19 select HAVE_OPROFILE 19 select HAVE_OPROFILE
20 select HAVE_FUNCTION_TRACER 20 select HAVE_FUNCTION_TRACER
21 select HAVE_IRQ_TIME_ACCOUNTING 21 select HAVE_IRQ_TIME_ACCOUNTING
22 select HAVE_PERF_EVENTS
22 help 23 help
23 Xtensa processors are 32-bit RISC machines designed by Tensilica 24 Xtensa processors are 32-bit RISC machines designed by Tensilica
24 primarily for embedded systems. These processors are both 25 primarily for embedded systems. These processors are both
diff --git a/arch/xtensa/include/asm/perf_event.h b/arch/xtensa/include/asm/perf_event.h
new file mode 100644
index 000000000000..5aa4590acaae
--- /dev/null
+++ b/arch/xtensa/include/asm/perf_event.h
@@ -0,0 +1,4 @@
1#ifndef __ASM_XTENSA_PERF_EVENT_H
2#define __ASM_XTENSA_PERF_EVENT_H
3
4#endif /* __ASM_XTENSA_PERF_EVENT_H */