diff options
author | Mythri P K <mythripk@ti.com> | 2012-01-06 07:22:08 -0500 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-01-25 06:48:33 -0500 |
commit | a05ce78f308fa22b6254995c25ff79e82a27de75 (patch) | |
tree | ca08f86355cb6b6be93e7821d936f633bdf20b8d | |
parent | aeec1a6ccbe28c2cea5f19803394f99859566552 (diff) |
OMAPDSS: HDMI: update static timing table
Add the vsync polarity, hsync polarity, interlace to hdmi_video_timings.
Remove the now duplicate structure hdmi_timings.
update the static table structure in HDMI with CEA/VESA code and mode.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
-rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 96 | ||||
-rw-r--r-- | drivers/video/omap2/dss/ti_hdmi.h | 14 | ||||
-rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 20 |
3 files changed, 63 insertions, 67 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index b4c270edb915..266af264eb9b 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c | |||
@@ -88,42 +88,42 @@ static struct { | |||
88 | * map it to corresponding CEA or VESA index. | 88 | * map it to corresponding CEA or VESA index. |
89 | */ | 89 | */ |
90 | 90 | ||
91 | static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { | 91 | static const struct hdmi_config cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { |
92 | { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0}, | 92 | { {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} }, |
93 | { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1}, | 93 | { {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} }, |
94 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}, | 94 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} }, |
95 | { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0}, | 95 | { {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} }, |
96 | { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0}, | 96 | { {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} }, |
97 | { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0}, | 97 | { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} }, |
98 | { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0}, | 98 | { {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} }, |
99 | { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1}, | 99 | { {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} }, |
100 | { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1}, | 100 | { {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} }, |
101 | { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1}, | 101 | { {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} }, |
102 | { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0}, | 102 | { {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} }, |
103 | { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0}, | 103 | { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} }, |
104 | { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1}, | 104 | { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} }, |
105 | { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0}, | 105 | { {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} }, |
106 | { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1}, | 106 | { {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} }, |
107 | /* VESA From Here */ | 107 | /* VESA From Here */ |
108 | { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0}, | 108 | { {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} }, |
109 | { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1}, | 109 | { {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} }, |
110 | { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1}, | 110 | { {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} }, |
111 | { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0}, | 111 | { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} }, |
112 | { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0}, | 112 | { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} }, |
113 | { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1}, | 113 | { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} }, |
114 | { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1}, | 114 | { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} }, |
115 | { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1}, | 115 | { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} }, |
116 | { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0}, | 116 | { {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} }, |
117 | { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0}, | 117 | { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} }, |
118 | { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0}, | 118 | { {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} }, |
119 | { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0}, | 119 | { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} }, |
120 | { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1}, | 120 | { {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} }, |
121 | { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1}, | 121 | { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} }, |
122 | { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1}, | 122 | { {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} }, |
123 | { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1}, | 123 | { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} }, |
124 | { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1}, | 124 | { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} }, |
125 | { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1}, | 125 | { {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} }, |
126 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1} | 126 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} } |
127 | }; | 127 | }; |
128 | 128 | ||
129 | /* | 129 | /* |
@@ -253,23 +253,23 @@ static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | |||
253 | static void update_hdmi_timings(struct hdmi_config *cfg, | 253 | static void update_hdmi_timings(struct hdmi_config *cfg, |
254 | struct omap_video_timings *timings, int code) | 254 | struct omap_video_timings *timings, int code) |
255 | { | 255 | { |
256 | cfg->timings.timings.x_res = timings->x_res; | 256 | cfg->timings.x_res = timings->x_res; |
257 | cfg->timings.timings.y_res = timings->y_res; | 257 | cfg->timings.y_res = timings->y_res; |
258 | cfg->timings.timings.hbp = timings->hbp; | 258 | cfg->timings.hbp = timings->hbp; |
259 | cfg->timings.timings.hfp = timings->hfp; | 259 | cfg->timings.hfp = timings->hfp; |
260 | cfg->timings.timings.hsw = timings->hsw; | 260 | cfg->timings.hsw = timings->hsw; |
261 | cfg->timings.timings.vbp = timings->vbp; | 261 | cfg->timings.vbp = timings->vbp; |
262 | cfg->timings.timings.vfp = timings->vfp; | 262 | cfg->timings.vfp = timings->vfp; |
263 | cfg->timings.timings.vsw = timings->vsw; | 263 | cfg->timings.vsw = timings->vsw; |
264 | cfg->timings.timings.pixel_clock = timings->pixel_clock; | 264 | cfg->timings.pixel_clock = timings->pixel_clock; |
265 | cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol; | 265 | cfg->timings.vsync_pol = cea_vesa_timings[code].timings.vsync_pol; |
266 | cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; | 266 | cfg->timings.hsync_pol = cea_vesa_timings[code].timings.hsync_pol; |
267 | } | 267 | } |
268 | 268 | ||
269 | unsigned long hdmi_get_pixel_clock(void) | 269 | unsigned long hdmi_get_pixel_clock(void) |
270 | { | 270 | { |
271 | /* HDMI Pixel Clock in Mhz */ | 271 | /* HDMI Pixel Clock in Mhz */ |
272 | return hdmi.ip_data.cfg.timings.timings.pixel_clock * 1000; | 272 | return hdmi.ip_data.cfg.timings.pixel_clock * 1000; |
273 | } | 273 | } |
274 | 274 | ||
275 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, | 275 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h index 7503f7f619a7..26ec6d1162ff 100644 --- a/drivers/video/omap2/dss/ti_hdmi.h +++ b/drivers/video/omap2/dss/ti_hdmi.h | |||
@@ -42,6 +42,7 @@ enum hdmi_clk_refsel { | |||
42 | HDMI_REFSEL_SYSCLK = 3 | 42 | HDMI_REFSEL_SYSCLK = 3 |
43 | }; | 43 | }; |
44 | 44 | ||
45 | /* HDMI timing structure */ | ||
45 | struct hdmi_video_timings { | 46 | struct hdmi_video_timings { |
46 | u16 x_res; | 47 | u16 x_res; |
47 | u16 y_res; | 48 | u16 y_res; |
@@ -53,13 +54,9 @@ struct hdmi_video_timings { | |||
53 | u16 vsw; | 54 | u16 vsw; |
54 | u16 vfp; | 55 | u16 vfp; |
55 | u16 vbp; | 56 | u16 vbp; |
56 | }; | 57 | bool vsync_pol; |
57 | 58 | bool hsync_pol; | |
58 | /* HDMI timing structure */ | 59 | bool interlace; |
59 | struct hdmi_timings { | ||
60 | struct hdmi_video_timings timings; | ||
61 | int vsync_pol; | ||
62 | int hsync_pol; | ||
63 | }; | 60 | }; |
64 | 61 | ||
65 | struct hdmi_cm { | 62 | struct hdmi_cm { |
@@ -68,8 +65,7 @@ struct hdmi_cm { | |||
68 | }; | 65 | }; |
69 | 66 | ||
70 | struct hdmi_config { | 67 | struct hdmi_config { |
71 | struct hdmi_timings timings; | 68 | struct hdmi_video_timings timings; |
72 | u16 interlace; | ||
73 | struct hdmi_cm cm; | 69 | struct hdmi_cm cm; |
74 | }; | 70 | }; |
75 | 71 | ||
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c index bafbd9fad4b5..a229ae71be79 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | |||
@@ -656,15 +656,15 @@ static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, | |||
656 | { | 656 | { |
657 | pr_debug("Enter hdmi_wp_video_init_format\n"); | 657 | pr_debug("Enter hdmi_wp_video_init_format\n"); |
658 | 658 | ||
659 | video_fmt->y_res = param->timings.timings.y_res; | 659 | video_fmt->y_res = param->timings.y_res; |
660 | video_fmt->x_res = param->timings.timings.x_res; | 660 | video_fmt->x_res = param->timings.x_res; |
661 | 661 | ||
662 | timings->hbp = param->timings.timings.hbp; | 662 | timings->hbp = param->timings.hbp; |
663 | timings->hfp = param->timings.timings.hfp; | 663 | timings->hfp = param->timings.hfp; |
664 | timings->hsw = param->timings.timings.hsw; | 664 | timings->hsw = param->timings.hsw; |
665 | timings->vbp = param->timings.timings.vbp; | 665 | timings->vbp = param->timings.vbp; |
666 | timings->vfp = param->timings.timings.vfp; | 666 | timings->vfp = param->timings.vfp; |
667 | timings->vsw = param->timings.timings.vsw; | 667 | timings->vsw = param->timings.vsw; |
668 | } | 668 | } |
669 | 669 | ||
670 | static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, | 670 | static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, |
@@ -688,7 +688,7 @@ static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data) | |||
688 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); | 688 | r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); |
689 | r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7); | 689 | r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7); |
690 | r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6); | 690 | r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6); |
691 | r = FLD_MOD(r, ip_data->cfg.interlace, 3, 3); | 691 | r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3); |
692 | r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ | 692 | r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ |
693 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); | 693 | hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); |
694 | } | 694 | } |