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authorJesse Barnes <jbarnes@virtuousgeek.org>2011-02-07 15:26:52 -0500
committerChris Wilson <chris@chris-wilson.co.uk>2011-02-07 16:17:15 -0500
commit9db4a9c7b2a3bd5b4952846bc0c2f58daa80ddd7 (patch)
tree3d0d27e1115a5fae8984fbf2069d8720e5e6ee8e
parent8d7e3de1e019238211fa06e109437a13cae62004 (diff)
drm/i915: cleanup per-pipe reg usage
We had some conversions over to the _PIPE macros, but didn't get everything. So hide the per-pipe regs with an _ (still used in a few places for legacy) and add a few _PIPE based macros, then make sure everyone uses them. [update: remove usage of non-existent no-op macro] [update 2: keep modesetting suspend/resume code, update to new reg names] Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: stylistic cleanups for checkpatch and taste] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c20
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c7
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h12
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c149
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h432
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c429
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c33
-rw-r--r--drivers/gpu/drm/i915/intel_display.c141
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c45
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c2
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c5
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c2
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c10
13 files changed, 640 insertions, 647 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 786c3ba8886c..d659f36419af 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -326,21 +326,21 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
326 struct intel_crtc *crtc; 326 struct intel_crtc *crtc;
327 327
328 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 328 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
329 const char *pipe = crtc->pipe ? "B" : "A"; 329 const char pipe = pipe_name(crtc->pipe);
330 const char *plane = crtc->plane ? "B" : "A"; 330 const char plane = plane_name(crtc->plane);
331 struct intel_unpin_work *work; 331 struct intel_unpin_work *work;
332 332
333 spin_lock_irqsave(&dev->event_lock, flags); 333 spin_lock_irqsave(&dev->event_lock, flags);
334 work = crtc->unpin_work; 334 work = crtc->unpin_work;
335 if (work == NULL) { 335 if (work == NULL) {
336 seq_printf(m, "No flip due on pipe %s (plane %s)\n", 336 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
337 pipe, plane); 337 pipe, plane);
338 } else { 338 } else {
339 if (!work->pending) { 339 if (!work->pending) {
340 seq_printf(m, "Flip queued on pipe %s (plane %s)\n", 340 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
341 pipe, plane); 341 pipe, plane);
342 } else { 342 } else {
343 seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n", 343 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
344 pipe, plane); 344 pipe, plane);
345 } 345 }
346 if (work->enable_stall_check) 346 if (work->enable_stall_check)
@@ -458,7 +458,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
458 struct drm_info_node *node = (struct drm_info_node *) m->private; 458 struct drm_info_node *node = (struct drm_info_node *) m->private;
459 struct drm_device *dev = node->minor->dev; 459 struct drm_device *dev = node->minor->dev;
460 drm_i915_private_t *dev_priv = dev->dev_private; 460 drm_i915_private_t *dev_priv = dev->dev_private;
461 int ret, i; 461 int ret, i, pipe;
462 462
463 ret = mutex_lock_interruptible(&dev->struct_mutex); 463 ret = mutex_lock_interruptible(&dev->struct_mutex);
464 if (ret) 464 if (ret)
@@ -471,10 +471,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
471 I915_READ(IIR)); 471 I915_READ(IIR));
472 seq_printf(m, "Interrupt mask: %08x\n", 472 seq_printf(m, "Interrupt mask: %08x\n",
473 I915_READ(IMR)); 473 I915_READ(IMR));
474 seq_printf(m, "Pipe A stat: %08x\n", 474 for_each_pipe(pipe)
475 I915_READ(PIPEASTAT)); 475 seq_printf(m, "Pipe %c stat: %08x\n",
476 seq_printf(m, "Pipe B stat: %08x\n", 476 pipe_name(pipe),
477 I915_READ(PIPEBSTAT)); 477 I915_READ(PIPESTAT(pipe)));
478 } else { 478 } else {
479 seq_printf(m, "North Display Interrupt enable: %08x\n", 479 seq_printf(m, "North Display Interrupt enable: %08x\n",
480 I915_READ(DEIER)); 480 I915_READ(DEIER));
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index c79efbc15c5e..ffa2196eb3b9 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2005,7 +2005,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2005 spin_lock_init(&dev_priv->irq_lock); 2005 spin_lock_init(&dev_priv->irq_lock);
2006 spin_lock_init(&dev_priv->error_lock); 2006 spin_lock_init(&dev_priv->error_lock);
2007 2007
2008 ret = drm_vblank_init(dev, I915_NUM_PIPE); 2008 if (IS_MOBILE(dev) || !IS_GEN2(dev))
2009 dev_priv->num_pipe = 2;
2010 else
2011 dev_priv->num_pipe = 1;
2012
2013 ret = drm_vblank_init(dev, dev_priv->num_pipe);
2009 if (ret) 2014 if (ret)
2010 goto out_gem_unload; 2015 goto out_gem_unload;
2011 2016
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bdfda0b8c604..f9e9f9840dea 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -50,17 +50,22 @@
50enum pipe { 50enum pipe {
51 PIPE_A = 0, 51 PIPE_A = 0,
52 PIPE_B, 52 PIPE_B,
53 PIPE_C,
54 I915_MAX_PIPES
53}; 55};
56#define pipe_name(p) ((p) + 'A')
54 57
55enum plane { 58enum plane {
56 PLANE_A = 0, 59 PLANE_A = 0,
57 PLANE_B, 60 PLANE_B,
61 PLANE_C,
58}; 62};
59 63#define plane_name(p) ((p) + 'A')
60#define I915_NUM_PIPE 2
61 64
62#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 65#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
63 66
67#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
68
64/* Interface history: 69/* Interface history:
65 * 70 *
66 * 1.1: Original. 71 * 1.1: Original.
@@ -143,8 +148,7 @@ struct intel_display_error_state;
143struct drm_i915_error_state { 148struct drm_i915_error_state {
144 u32 eir; 149 u32 eir;
145 u32 pgtbl_er; 150 u32 pgtbl_er;
146 u32 pipeastat; 151 u32 pipestat[I915_MAX_PIPES];
147 u32 pipebstat;
148 u32 ipeir; 152 u32 ipeir;
149 u32 ipehr; 153 u32 ipehr;
150 u32 instdone; 154 u32 instdone;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 15d6269027e7..da3edf891c21 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -85,21 +85,11 @@ ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85 } 85 }
86} 86}
87 87
88static inline u32
89i915_pipestat(int pipe)
90{
91 if (pipe == 0)
92 return PIPEASTAT;
93 if (pipe == 1)
94 return PIPEBSTAT;
95 BUG();
96}
97
98void 88void
99i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 89i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
100{ 90{
101 if ((dev_priv->pipestat[pipe] & mask) != mask) { 91 if ((dev_priv->pipestat[pipe] & mask) != mask) {
102 u32 reg = i915_pipestat(pipe); 92 u32 reg = PIPESTAT(pipe);
103 93
104 dev_priv->pipestat[pipe] |= mask; 94 dev_priv->pipestat[pipe] |= mask;
105 /* Enable the interrupt, clear any pending status */ 95 /* Enable the interrupt, clear any pending status */
@@ -112,7 +102,7 @@ void
112i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 102i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
113{ 103{
114 if ((dev_priv->pipestat[pipe] & mask) != 0) { 104 if ((dev_priv->pipestat[pipe] & mask) != 0) {
115 u32 reg = i915_pipestat(pipe); 105 u32 reg = PIPESTAT(pipe);
116 106
117 dev_priv->pipestat[pipe] &= ~mask; 107 dev_priv->pipestat[pipe] &= ~mask;
118 I915_WRITE(reg, dev_priv->pipestat[pipe]); 108 I915_WRITE(reg, dev_priv->pipestat[pipe]);
@@ -171,12 +161,12 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
171 161
172 if (!i915_pipe_enabled(dev, pipe)) { 162 if (!i915_pipe_enabled(dev, pipe)) {
173 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
174 "pipe %d\n", pipe); 164 "pipe %c\n", pipe_name(pipe));
175 return 0; 165 return 0;
176 } 166 }
177 167
178 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; 168 high_frame = PIPEFRAME(pipe);
179 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; 169 low_frame = PIPEFRAMEPIXEL(pipe);
180 170
181 /* 171 /*
182 * High & low register fields aren't synchronized, so make sure 172 * High & low register fields aren't synchronized, so make sure
@@ -197,11 +187,11 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
197u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 187u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
198{ 188{
199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; 190 int reg = PIPE_FRMCOUNT_GM45(pipe);
201 191
202 if (!i915_pipe_enabled(dev, pipe)) { 192 if (!i915_pipe_enabled(dev, pipe)) {
203 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
204 "pipe %d\n", pipe); 194 "pipe %c\n", pipe_name(pipe));
205 return 0; 195 return 0;
206 } 196 }
207 197
@@ -219,7 +209,7 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
219 209
220 if (!i915_pipe_enabled(dev, pipe)) { 210 if (!i915_pipe_enabled(dev, pipe)) {
221 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
222 "pipe %d\n", pipe); 212 "pipe %c\n", pipe_name(pipe));
223 return 0; 213 return 0;
224 } 214 }
225 215
@@ -417,6 +407,7 @@ static void pch_irq_handler(struct drm_device *dev)
417{ 407{
418 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 408 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
419 u32 pch_iir; 409 u32 pch_iir;
410 int pipe;
420 411
421 pch_iir = I915_READ(SDEIIR); 412 pch_iir = I915_READ(SDEIIR);
422 413
@@ -437,13 +428,11 @@ static void pch_irq_handler(struct drm_device *dev)
437 if (pch_iir & SDE_POISON) 428 if (pch_iir & SDE_POISON)
438 DRM_ERROR("PCH poison interrupt\n"); 429 DRM_ERROR("PCH poison interrupt\n");
439 430
440 if (pch_iir & SDE_FDI_MASK) { 431 if (pch_iir & SDE_FDI_MASK)
441 u32 fdia, fdib; 432 for_each_pipe(pipe)
442 433 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
443 fdia = I915_READ(FDI_RXA_IIR); 434 pipe_name(pipe),
444 fdib = I915_READ(FDI_RXB_IIR); 435 I915_READ(FDI_RX_IIR(pipe)));
445 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
446 }
447 436
448 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 437 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
449 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 438 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
@@ -770,7 +759,7 @@ static void i915_capture_error_state(struct drm_device *dev)
770 struct drm_i915_gem_object *obj; 759 struct drm_i915_gem_object *obj;
771 struct drm_i915_error_state *error; 760 struct drm_i915_error_state *error;
772 unsigned long flags; 761 unsigned long flags;
773 int i; 762 int i, pipe;
774 763
775 spin_lock_irqsave(&dev_priv->error_lock, flags); 764 spin_lock_irqsave(&dev_priv->error_lock, flags);
776 error = dev_priv->first_error; 765 error = dev_priv->first_error;
@@ -778,6 +767,7 @@ static void i915_capture_error_state(struct drm_device *dev)
778 if (error) 767 if (error)
779 return; 768 return;
780 769
770 /* Account for pipe specific data like PIPE*STAT */
781 error = kmalloc(sizeof(*error), GFP_ATOMIC); 771 error = kmalloc(sizeof(*error), GFP_ATOMIC);
782 if (!error) { 772 if (!error) {
783 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 773 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
@@ -790,8 +780,8 @@ static void i915_capture_error_state(struct drm_device *dev)
790 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); 780 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
791 error->eir = I915_READ(EIR); 781 error->eir = I915_READ(EIR);
792 error->pgtbl_er = I915_READ(PGTBL_ER); 782 error->pgtbl_er = I915_READ(PGTBL_ER);
793 error->pipeastat = I915_READ(PIPEASTAT); 783 for_each_pipe(pipe)
794 error->pipebstat = I915_READ(PIPEBSTAT); 784 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
795 error->instpm = I915_READ(INSTPM); 785 error->instpm = I915_READ(INSTPM);
796 error->error = 0; 786 error->error = 0;
797 if (INTEL_INFO(dev)->gen >= 6) { 787 if (INTEL_INFO(dev)->gen >= 6) {
@@ -912,6 +902,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
912{ 902{
913 struct drm_i915_private *dev_priv = dev->dev_private; 903 struct drm_i915_private *dev_priv = dev->dev_private;
914 u32 eir = I915_READ(EIR); 904 u32 eir = I915_READ(EIR);
905 int pipe;
915 906
916 if (!eir) 907 if (!eir)
917 return; 908 return;
@@ -960,14 +951,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
960 } 951 }
961 952
962 if (eir & I915_ERROR_MEMORY_REFRESH) { 953 if (eir & I915_ERROR_MEMORY_REFRESH) {
963 u32 pipea_stats = I915_READ(PIPEASTAT); 954 printk(KERN_ERR "memory refresh error:\n");
964 u32 pipeb_stats = I915_READ(PIPEBSTAT); 955 for_each_pipe(pipe)
965 956 printk(KERN_ERR "pipe %c stat: 0x%08x\n",
966 printk(KERN_ERR "memory refresh error\n"); 957 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
967 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
968 pipea_stats);
969 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
970 pipeb_stats);
971 /* pipestat has already been acked */ 958 /* pipestat has already been acked */
972 } 959 }
973 if (eir & I915_ERROR_INSTRUCTION) { 960 if (eir & I915_ERROR_INSTRUCTION) {
@@ -1081,10 +1068,10 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1081 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1068 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1082 obj = work->pending_flip_obj; 1069 obj = work->pending_flip_obj;
1083 if (INTEL_INFO(dev)->gen >= 4) { 1070 if (INTEL_INFO(dev)->gen >= 4) {
1084 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; 1071 int dspsurf = DSPSURF(intel_crtc->plane);
1085 stall_detected = I915_READ(dspsurf) == obj->gtt_offset; 1072 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1086 } else { 1073 } else {
1087 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; 1074 int dspaddr = DSPADDR(intel_crtc->plane);
1088 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1075 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1089 crtc->y * crtc->fb->pitch + 1076 crtc->y * crtc->fb->pitch +
1090 crtc->x * crtc->fb->bits_per_pixel/8); 1077 crtc->x * crtc->fb->bits_per_pixel/8);
@@ -1104,12 +1091,13 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1104 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1091 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1105 struct drm_i915_master_private *master_priv; 1092 struct drm_i915_master_private *master_priv;
1106 u32 iir, new_iir; 1093 u32 iir, new_iir;
1107 u32 pipea_stats, pipeb_stats; 1094 u32 pipe_stats[I915_MAX_PIPES];
1108 u32 vblank_status; 1095 u32 vblank_status;
1109 int vblank = 0; 1096 int vblank = 0;
1110 unsigned long irqflags; 1097 unsigned long irqflags;
1111 int irq_received; 1098 int irq_received;
1112 int ret = IRQ_NONE; 1099 int ret = IRQ_NONE, pipe;
1100 bool blc_event = false;
1113 1101
1114 atomic_inc(&dev_priv->irq_received); 1102 atomic_inc(&dev_priv->irq_received);
1115 1103
@@ -1132,27 +1120,23 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1132 * interrupts (for non-MSI). 1120 * interrupts (for non-MSI).
1133 */ 1121 */
1134 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1122 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1135 pipea_stats = I915_READ(PIPEASTAT);
1136 pipeb_stats = I915_READ(PIPEBSTAT);
1137
1138 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 1123 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1139 i915_handle_error(dev, false); 1124 i915_handle_error(dev, false);
1140 1125
1141 /* 1126 for_each_pipe(pipe) {
1142 * Clear the PIPE(A|B)STAT regs before the IIR 1127 int reg = PIPESTAT(pipe);
1143 */ 1128 pipe_stats[pipe] = I915_READ(reg);
1144 if (pipea_stats & 0x8000ffff) { 1129
1145 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) 1130 /*
1146 DRM_DEBUG_DRIVER("pipe a underrun\n"); 1131 * Clear the PIPE*STAT regs before the IIR
1147 I915_WRITE(PIPEASTAT, pipea_stats); 1132 */
1148 irq_received = 1; 1133 if (pipe_stats[pipe] & 0x8000ffff) {
1149 } 1134 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1150 1135 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1151 if (pipeb_stats & 0x8000ffff) { 1136 pipe_name(pipe));
1152 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) 1137 I915_WRITE(reg, pipe_stats[pipe]);
1153 DRM_DEBUG_DRIVER("pipe b underrun\n"); 1138 irq_received = 1;
1154 I915_WRITE(PIPEBSTAT, pipeb_stats); 1139 }
1155 irq_received = 1;
1156 } 1140 }
1157 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1141 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1158 1142
@@ -1203,27 +1187,22 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1203 intel_finish_page_flip_plane(dev, 1); 1187 intel_finish_page_flip_plane(dev, 1);
1204 } 1188 }
1205 1189
1206 if (pipea_stats & vblank_status && 1190 for_each_pipe(pipe) {
1207 drm_handle_vblank(dev, 0)) { 1191 if (pipe_stats[pipe] & vblank_status &&
1208 vblank++; 1192 drm_handle_vblank(dev, pipe)) {
1209 if (!dev_priv->flip_pending_is_done) { 1193 vblank++;
1210 i915_pageflip_stall_check(dev, 0); 1194 if (!dev_priv->flip_pending_is_done) {
1211 intel_finish_page_flip(dev, 0); 1195 i915_pageflip_stall_check(dev, pipe);
1196 intel_finish_page_flip(dev, pipe);
1197 }
1212 } 1198 }
1213 }
1214 1199
1215 if (pipeb_stats & vblank_status && 1200 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1216 drm_handle_vblank(dev, 1)) { 1201 blc_event = true;
1217 vblank++;
1218 if (!dev_priv->flip_pending_is_done) {
1219 i915_pageflip_stall_check(dev, 1);
1220 intel_finish_page_flip(dev, 1);
1221 }
1222 } 1202 }
1223 1203
1224 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || 1204
1225 (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || 1205 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1226 (iir & I915_ASLE_INTERRUPT))
1227 intel_opregion_asle_intr(dev); 1206 intel_opregion_asle_intr(dev);
1228 1207
1229 /* With MSI, interrupts are only generated when iir 1208 /* With MSI, interrupts are only generated when iir
@@ -1634,6 +1613,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1634 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1613 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1635 u32 render_irqs; 1614 u32 render_irqs;
1636 u32 hotplug_mask; 1615 u32 hotplug_mask;
1616 int pipe;
1637 1617
1638 dev_priv->irq_mask = ~display_mask; 1618 dev_priv->irq_mask = ~display_mask;
1639 1619
@@ -1668,8 +1648,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1668 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | 1648 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1669 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; 1649 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1670 hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK; 1650 hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
1671 I915_WRITE(FDI_RXA_IMR, 0); 1651 for_each_pipe(pipe)
1672 I915_WRITE(FDI_RXB_IMR, 0); 1652 I915_WRITE(FDI_RX_IMR(pipe), 0);
1673 } 1653 }
1674 1654
1675 dev_priv->pch_irq_mask = ~hotplug_mask; 1655 dev_priv->pch_irq_mask = ~hotplug_mask;
@@ -1692,6 +1672,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1692void i915_driver_irq_preinstall(struct drm_device * dev) 1672void i915_driver_irq_preinstall(struct drm_device * dev)
1693{ 1673{
1694 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1674 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1675 int pipe;
1695 1676
1696 atomic_set(&dev_priv->irq_received, 0); 1677 atomic_set(&dev_priv->irq_received, 0);
1697 atomic_set(&dev_priv->vblank_enabled, 0); 1678 atomic_set(&dev_priv->vblank_enabled, 0);
@@ -1711,8 +1692,8 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1711 } 1692 }
1712 1693
1713 I915_WRITE(HWSTAM, 0xeffe); 1694 I915_WRITE(HWSTAM, 0xeffe);
1714 I915_WRITE(PIPEASTAT, 0); 1695 for_each_pipe(pipe)
1715 I915_WRITE(PIPEBSTAT, 0); 1696 I915_WRITE(PIPESTAT(pipe), 0);
1716 I915_WRITE(IMR, 0xffffffff); 1697 I915_WRITE(IMR, 0xffffffff);
1717 I915_WRITE(IER, 0x0); 1698 I915_WRITE(IER, 0x0);
1718 POSTING_READ(IER); 1699 POSTING_READ(IER);
@@ -1824,6 +1805,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
1824void i915_driver_irq_uninstall(struct drm_device * dev) 1805void i915_driver_irq_uninstall(struct drm_device * dev)
1825{ 1806{
1826 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1807 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1808 int pipe;
1827 1809
1828 if (!dev_priv) 1810 if (!dev_priv)
1829 return; 1811 return;
@@ -1841,12 +1823,13 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
1841 } 1823 }
1842 1824
1843 I915_WRITE(HWSTAM, 0xffffffff); 1825 I915_WRITE(HWSTAM, 0xffffffff);
1844 I915_WRITE(PIPEASTAT, 0); 1826 for_each_pipe(pipe)
1845 I915_WRITE(PIPEBSTAT, 0); 1827 I915_WRITE(PIPESTAT(pipe), 0);
1846 I915_WRITE(IMR, 0xffffffff); 1828 I915_WRITE(IMR, 0xffffffff);
1847 I915_WRITE(IER, 0x0); 1829 I915_WRITE(IER, 0x0);
1848 1830
1849 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 1831 for_each_pipe(pipe)
1850 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 1832 I915_WRITE(PIPESTAT(pipe),
1833 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
1851 I915_WRITE(IIR, I915_READ(IIR)); 1834 I915_WRITE(IIR, I915_READ(IIR));
1852} 1835}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3297cf1a14ed..6bd9659861e5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -704,9 +704,9 @@
704#define VGA1_PD_P1_DIV_2 (1 << 13) 704#define VGA1_PD_P1_DIV_2 (1 << 13)
705#define VGA1_PD_P1_SHIFT 8 705#define VGA1_PD_P1_SHIFT 8
706#define VGA1_PD_P1_MASK (0x1f << 8) 706#define VGA1_PD_P1_MASK (0x1f << 8)
707#define DPLL_A 0x06014 707#define _DPLL_A 0x06014
708#define DPLL_B 0x06018 708#define _DPLL_B 0x06018
709#define DPLL(pipe) _PIPE(pipe, DPLL_A, DPLL_B) 709#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
710#define DPLL_VCO_ENABLE (1 << 31) 710#define DPLL_VCO_ENABLE (1 << 31)
711#define DPLL_DVO_HIGH_SPEED (1 << 30) 711#define DPLL_DVO_HIGH_SPEED (1 << 30)
712#define DPLL_SYNCLOCK_ENABLE (1 << 29) 712#define DPLL_SYNCLOCK_ENABLE (1 << 29)
@@ -777,7 +777,7 @@
777#define SDVO_MULTIPLIER_MASK 0x000000ff 777#define SDVO_MULTIPLIER_MASK 0x000000ff
778#define SDVO_MULTIPLIER_SHIFT_HIRES 4 778#define SDVO_MULTIPLIER_SHIFT_HIRES 4
779#define SDVO_MULTIPLIER_SHIFT_VGA 0 779#define SDVO_MULTIPLIER_SHIFT_VGA 0
780#define DPLL_A_MD 0x0601c /* 965+ only */ 780#define _DPLL_A_MD 0x0601c /* 965+ only */
781/* 781/*
782 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 782 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
783 * 783 *
@@ -814,14 +814,14 @@
814 */ 814 */
815#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 815#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
816#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 816#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
817#define DPLL_B_MD 0x06020 /* 965+ only */ 817#define _DPLL_B_MD 0x06020 /* 965+ only */
818#define DPLL_MD(pipe) _PIPE(pipe, DPLL_A_MD, DPLL_B_MD) 818#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
819#define FPA0 0x06040 819#define _FPA0 0x06040
820#define FPA1 0x06044 820#define _FPA1 0x06044
821#define FPB0 0x06048 821#define _FPB0 0x06048
822#define FPB1 0x0604c 822#define _FPB1 0x0604c
823#define FP0(pipe) _PIPE(pipe, FPA0, FPB0) 823#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
824#define FP1(pipe) _PIPE(pipe, FPA1, FPB1) 824#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
825#define FP_N_DIV_MASK 0x003f0000 825#define FP_N_DIV_MASK 0x003f0000
826#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 826#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
827#define FP_N_DIV_SHIFT 16 827#define FP_N_DIV_SHIFT 16
@@ -960,8 +960,9 @@
960 * Palette regs 960 * Palette regs
961 */ 961 */
962 962
963#define PALETTE_A 0x0a000 963#define _PALETTE_A 0x0a000
964#define PALETTE_B 0x0a800 964#define _PALETTE_B 0x0a800
965#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
965 966
966/* MCH MMIO space */ 967/* MCH MMIO space */
967 968
@@ -1265,32 +1266,32 @@
1265 */ 1266 */
1266 1267
1267/* Pipe A timing regs */ 1268/* Pipe A timing regs */
1268#define HTOTAL_A 0x60000 1269#define _HTOTAL_A 0x60000
1269#define HBLANK_A 0x60004 1270#define _HBLANK_A 0x60004
1270#define HSYNC_A 0x60008 1271#define _HSYNC_A 0x60008
1271#define VTOTAL_A 0x6000c 1272#define _VTOTAL_A 0x6000c
1272#define VBLANK_A 0x60010 1273#define _VBLANK_A 0x60010
1273#define VSYNC_A 0x60014 1274#define _VSYNC_A 0x60014
1274#define PIPEASRC 0x6001c 1275#define _PIPEASRC 0x6001c
1275#define BCLRPAT_A 0x60020 1276#define _BCLRPAT_A 0x60020
1276 1277
1277/* Pipe B timing regs */ 1278/* Pipe B timing regs */
1278#define HTOTAL_B 0x61000 1279#define _HTOTAL_B 0x61000
1279#define HBLANK_B 0x61004 1280#define _HBLANK_B 0x61004
1280#define HSYNC_B 0x61008 1281#define _HSYNC_B 0x61008
1281#define VTOTAL_B 0x6100c 1282#define _VTOTAL_B 0x6100c
1282#define VBLANK_B 0x61010 1283#define _VBLANK_B 0x61010
1283#define VSYNC_B 0x61014 1284#define _VSYNC_B 0x61014
1284#define PIPEBSRC 0x6101c 1285#define _PIPEBSRC 0x6101c
1285#define BCLRPAT_B 0x61020 1286#define _BCLRPAT_B 0x61020
1286 1287
1287#define HTOTAL(pipe) _PIPE(pipe, HTOTAL_A, HTOTAL_B) 1288#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1288#define HBLANK(pipe) _PIPE(pipe, HBLANK_A, HBLANK_B) 1289#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1289#define HSYNC(pipe) _PIPE(pipe, HSYNC_A, HSYNC_B) 1290#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1290#define VTOTAL(pipe) _PIPE(pipe, VTOTAL_A, VTOTAL_B) 1291#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1291#define VBLANK(pipe) _PIPE(pipe, VBLANK_A, VBLANK_B) 1292#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1292#define VSYNC(pipe) _PIPE(pipe, VSYNC_A, VSYNC_B) 1293#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1293#define BCLRPAT(pipe) _PIPE(pipe, BCLRPAT_A, BCLRPAT_B) 1294#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1294 1295
1295/* VGA port control */ 1296/* VGA port control */
1296#define ADPA 0x61100 1297#define ADPA 0x61100
@@ -2208,8 +2209,8 @@
2208 * which is after the LUTs, so we want the bytes for our color format. 2209 * which is after the LUTs, so we want the bytes for our color format.
2209 * For our current usage, this is always 3, one byte for R, G and B. 2210 * For our current usage, this is always 3, one byte for R, G and B.
2210 */ 2211 */
2211#define PIPEA_GMCH_DATA_M 0x70050 2212#define _PIPEA_GMCH_DATA_M 0x70050
2212#define PIPEB_GMCH_DATA_M 0x71050 2213#define _PIPEB_GMCH_DATA_M 0x71050
2213 2214
2214/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2215/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2215#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2216#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
@@ -2217,8 +2218,8 @@
2217 2218
2218#define PIPE_GMCH_DATA_M_MASK (0xffffff) 2219#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2219 2220
2220#define PIPEA_GMCH_DATA_N 0x70054 2221#define _PIPEA_GMCH_DATA_N 0x70054
2221#define PIPEB_GMCH_DATA_N 0x71054 2222#define _PIPEB_GMCH_DATA_N 0x71054
2222#define PIPE_GMCH_DATA_N_MASK (0xffffff) 2223#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2223 2224
2224/* 2225/*
@@ -2232,20 +2233,25 @@
2232 * Attributes and VB-ID. 2233 * Attributes and VB-ID.
2233 */ 2234 */
2234 2235
2235#define PIPEA_DP_LINK_M 0x70060 2236#define _PIPEA_DP_LINK_M 0x70060
2236#define PIPEB_DP_LINK_M 0x71060 2237#define _PIPEB_DP_LINK_M 0x71060
2237#define PIPEA_DP_LINK_M_MASK (0xffffff) 2238#define PIPEA_DP_LINK_M_MASK (0xffffff)
2238 2239
2239#define PIPEA_DP_LINK_N 0x70064 2240#define _PIPEA_DP_LINK_N 0x70064
2240#define PIPEB_DP_LINK_N 0x71064 2241#define _PIPEB_DP_LINK_N 0x71064
2241#define PIPEA_DP_LINK_N_MASK (0xffffff) 2242#define PIPEA_DP_LINK_N_MASK (0xffffff)
2242 2243
2244#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2245#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2246#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2247#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2248
2243/* Display & cursor control */ 2249/* Display & cursor control */
2244 2250
2245/* Pipe A */ 2251/* Pipe A */
2246#define PIPEADSL 0x70000 2252#define _PIPEADSL 0x70000
2247#define DSL_LINEMASK 0x00000fff 2253#define DSL_LINEMASK 0x00000fff
2248#define PIPEACONF 0x70008 2254#define _PIPEACONF 0x70008
2249#define PIPECONF_ENABLE (1<<31) 2255#define PIPECONF_ENABLE (1<<31)
2250#define PIPECONF_DISABLE 0 2256#define PIPECONF_DISABLE 0
2251#define PIPECONF_DOUBLE_WIDE (1<<30) 2257#define PIPECONF_DOUBLE_WIDE (1<<30)
@@ -2271,7 +2277,7 @@
2271#define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2277#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2272#define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2278#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2273#define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2279#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2274#define PIPEASTAT 0x70024 2280#define _PIPEASTAT 0x70024
2275#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2281#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2276#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2282#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2277#define PIPE_CRC_DONE_ENABLE (1UL<<28) 2283#define PIPE_CRC_DONE_ENABLE (1UL<<28)
@@ -2307,10 +2313,12 @@
2307#define PIPE_6BPC (2 << 5) 2313#define PIPE_6BPC (2 << 5)
2308#define PIPE_12BPC (3 << 5) 2314#define PIPE_12BPC (3 << 5)
2309 2315
2310#define PIPESRC(pipe) _PIPE(pipe, PIPEASRC, PIPEBSRC) 2316#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2311#define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF) 2317#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2312#define PIPEDSL(pipe) _PIPE(pipe, PIPEADSL, PIPEBDSL) 2318#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2313#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, PIPEAFRAMEPIXEL, PIPEBFRAMEPIXEL) 2319#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2320#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2321#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2314 2322
2315#define DSPARB 0x70030 2323#define DSPARB 0x70030
2316#define DSPARB_CSTART_MASK (0x7f << 7) 2324#define DSPARB_CSTART_MASK (0x7f << 7)
@@ -2472,20 +2480,21 @@
2472 * } while (high1 != high2); 2480 * } while (high1 != high2);
2473 * frame = (high1 << 8) | low1; 2481 * frame = (high1 << 8) | low1;
2474 */ 2482 */
2475#define PIPEAFRAMEHIGH 0x70040 2483#define _PIPEAFRAMEHIGH 0x70040
2476#define PIPE_FRAME_HIGH_MASK 0x0000ffff 2484#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2477#define PIPE_FRAME_HIGH_SHIFT 0 2485#define PIPE_FRAME_HIGH_SHIFT 0
2478#define PIPEAFRAMEPIXEL 0x70044 2486#define _PIPEAFRAMEPIXEL 0x70044
2479#define PIPE_FRAME_LOW_MASK 0xff000000 2487#define PIPE_FRAME_LOW_MASK 0xff000000
2480#define PIPE_FRAME_LOW_SHIFT 24 2488#define PIPE_FRAME_LOW_SHIFT 24
2481#define PIPE_PIXEL_MASK 0x00ffffff 2489#define PIPE_PIXEL_MASK 0x00ffffff
2482#define PIPE_PIXEL_SHIFT 0 2490#define PIPE_PIXEL_SHIFT 0
2483/* GM45+ just has to be different */ 2491/* GM45+ just has to be different */
2484#define PIPEA_FRMCOUNT_GM45 0x70040 2492#define _PIPEA_FRMCOUNT_GM45 0x70040
2485#define PIPEA_FLIPCOUNT_GM45 0x70044 2493#define _PIPEA_FLIPCOUNT_GM45 0x70044
2494#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2486 2495
2487/* Cursor A & B regs */ 2496/* Cursor A & B regs */
2488#define CURACNTR 0x70080 2497#define _CURACNTR 0x70080
2489/* Old style CUR*CNTR flags (desktop 8xx) */ 2498/* Old style CUR*CNTR flags (desktop 8xx) */
2490#define CURSOR_ENABLE 0x80000000 2499#define CURSOR_ENABLE 0x80000000
2491#define CURSOR_GAMMA_ENABLE 0x40000000 2500#define CURSOR_GAMMA_ENABLE 0x40000000
@@ -2506,23 +2515,23 @@
2506#define MCURSOR_PIPE_A 0x00 2515#define MCURSOR_PIPE_A 0x00
2507#define MCURSOR_PIPE_B (1 << 28) 2516#define MCURSOR_PIPE_B (1 << 28)
2508#define MCURSOR_GAMMA_ENABLE (1 << 26) 2517#define MCURSOR_GAMMA_ENABLE (1 << 26)
2509#define CURABASE 0x70084 2518#define _CURABASE 0x70084
2510#define CURAPOS 0x70088 2519#define _CURAPOS 0x70088
2511#define CURSOR_POS_MASK 0x007FF 2520#define CURSOR_POS_MASK 0x007FF
2512#define CURSOR_POS_SIGN 0x8000 2521#define CURSOR_POS_SIGN 0x8000
2513#define CURSOR_X_SHIFT 0 2522#define CURSOR_X_SHIFT 0
2514#define CURSOR_Y_SHIFT 16 2523#define CURSOR_Y_SHIFT 16
2515#define CURSIZE 0x700a0 2524#define CURSIZE 0x700a0
2516#define CURBCNTR 0x700c0 2525#define _CURBCNTR 0x700c0
2517#define CURBBASE 0x700c4 2526#define _CURBBASE 0x700c4
2518#define CURBPOS 0x700c8 2527#define _CURBPOS 0x700c8
2519 2528
2520#define CURCNTR(pipe) _PIPE(pipe, CURACNTR, CURBCNTR) 2529#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2521#define CURBASE(pipe) _PIPE(pipe, CURABASE, CURBBASE) 2530#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2522#define CURPOS(pipe) _PIPE(pipe, CURAPOS, CURBPOS) 2531#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2523 2532
2524/* Display A control */ 2533/* Display A control */
2525#define DSPACNTR 0x70180 2534#define _DSPACNTR 0x70180
2526#define DISPLAY_PLANE_ENABLE (1<<31) 2535#define DISPLAY_PLANE_ENABLE (1<<31)
2527#define DISPLAY_PLANE_DISABLE 0 2536#define DISPLAY_PLANE_DISABLE 0
2528#define DISPPLANE_GAMMA_ENABLE (1<<30) 2537#define DISPPLANE_GAMMA_ENABLE (1<<30)
@@ -2548,20 +2557,20 @@
2548#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2557#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2549#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2558#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2550#define DISPPLANE_TILED (1<<10) 2559#define DISPPLANE_TILED (1<<10)
2551#define DSPAADDR 0x70184 2560#define _DSPAADDR 0x70184
2552#define DSPASTRIDE 0x70188 2561#define _DSPASTRIDE 0x70188
2553#define DSPAPOS 0x7018C /* reserved */ 2562#define _DSPAPOS 0x7018C /* reserved */
2554#define DSPASIZE 0x70190 2563#define _DSPASIZE 0x70190
2555#define DSPASURF 0x7019C /* 965+ only */ 2564#define _DSPASURF 0x7019C /* 965+ only */
2556#define DSPATILEOFF 0x701A4 /* 965+ only */ 2565#define _DSPATILEOFF 0x701A4 /* 965+ only */
2557 2566
2558#define DSPCNTR(plane) _PIPE(plane, DSPACNTR, DSPBCNTR) 2567#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2559#define DSPADDR(plane) _PIPE(plane, DSPAADDR, DSPBADDR) 2568#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2560#define DSPSTRIDE(plane) _PIPE(plane, DSPASTRIDE, DSPBSTRIDE) 2569#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2561#define DSPPOS(plane) _PIPE(plane, DSPAPOS, DSPBPOS) 2570#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2562#define DSPSIZE(plane) _PIPE(plane, DSPASIZE, DSPBSIZE) 2571#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2563#define DSPSURF(plane) _PIPE(plane, DSPASURF, DSPBSURF) 2572#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2564#define DSPTILEOFF(plane) _PIPE(plane, DSPATILEOFF, DSPBTILEOFF) 2573#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2565 2574
2566/* VBIOS flags */ 2575/* VBIOS flags */
2567#define SWF00 0x71410 2576#define SWF00 0x71410
@@ -2579,27 +2588,27 @@
2579#define SWF32 0x7241c 2588#define SWF32 0x7241c
2580 2589
2581/* Pipe B */ 2590/* Pipe B */
2582#define PIPEBDSL 0x71000 2591#define _PIPEBDSL 0x71000
2583#define PIPEBCONF 0x71008 2592#define _PIPEBCONF 0x71008
2584#define PIPEBSTAT 0x71024 2593#define _PIPEBSTAT 0x71024
2585#define PIPEBFRAMEHIGH 0x71040 2594#define _PIPEBFRAMEHIGH 0x71040
2586#define PIPEBFRAMEPIXEL 0x71044 2595#define _PIPEBFRAMEPIXEL 0x71044
2587#define PIPEB_FRMCOUNT_GM45 0x71040 2596#define _PIPEB_FRMCOUNT_GM45 0x71040
2588#define PIPEB_FLIPCOUNT_GM45 0x71044 2597#define _PIPEB_FLIPCOUNT_GM45 0x71044
2589 2598
2590 2599
2591/* Display B control */ 2600/* Display B control */
2592#define DSPBCNTR 0x71180 2601#define _DSPBCNTR 0x71180
2593#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2602#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2594#define DISPPLANE_ALPHA_TRANS_DISABLE 0 2603#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2595#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2604#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2596#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2605#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2597#define DSPBADDR 0x71184 2606#define _DSPBADDR 0x71184
2598#define DSPBSTRIDE 0x71188 2607#define _DSPBSTRIDE 0x71188
2599#define DSPBPOS 0x7118C 2608#define _DSPBPOS 0x7118C
2600#define DSPBSIZE 0x71190 2609#define _DSPBSIZE 0x71190
2601#define DSPBSURF 0x7119C 2610#define _DSPBSURF 0x7119C
2602#define DSPBTILEOFF 0x711A4 2611#define _DSPBTILEOFF 0x711A4
2603 2612
2604/* VBIOS regs */ 2613/* VBIOS regs */
2605#define VGACNTRL 0x71400 2614#define VGACNTRL 0x71400
@@ -2653,68 +2662,80 @@
2653#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2662#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2654 2663
2655 2664
2656#define PIPEA_DATA_M1 0x60030 2665#define _PIPEA_DATA_M1 0x60030
2657#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2666#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2658#define TU_SIZE_MASK 0x7e000000 2667#define TU_SIZE_MASK 0x7e000000
2659#define PIPE_DATA_M1_OFFSET 0 2668#define PIPE_DATA_M1_OFFSET 0
2660#define PIPEA_DATA_N1 0x60034 2669#define _PIPEA_DATA_N1 0x60034
2661#define PIPE_DATA_N1_OFFSET 0 2670#define PIPE_DATA_N1_OFFSET 0
2662 2671
2663#define PIPEA_DATA_M2 0x60038 2672#define _PIPEA_DATA_M2 0x60038
2664#define PIPE_DATA_M2_OFFSET 0 2673#define PIPE_DATA_M2_OFFSET 0
2665#define PIPEA_DATA_N2 0x6003c 2674#define _PIPEA_DATA_N2 0x6003c
2666#define PIPE_DATA_N2_OFFSET 0 2675#define PIPE_DATA_N2_OFFSET 0
2667 2676
2668#define PIPEA_LINK_M1 0x60040 2677#define _PIPEA_LINK_M1 0x60040
2669#define PIPE_LINK_M1_OFFSET 0 2678#define PIPE_LINK_M1_OFFSET 0
2670#define PIPEA_LINK_N1 0x60044 2679#define _PIPEA_LINK_N1 0x60044
2671#define PIPE_LINK_N1_OFFSET 0 2680#define PIPE_LINK_N1_OFFSET 0
2672 2681
2673#define PIPEA_LINK_M2 0x60048 2682#define _PIPEA_LINK_M2 0x60048
2674#define PIPE_LINK_M2_OFFSET 0 2683#define PIPE_LINK_M2_OFFSET 0
2675#define PIPEA_LINK_N2 0x6004c 2684#define _PIPEA_LINK_N2 0x6004c
2676#define PIPE_LINK_N2_OFFSET 0 2685#define PIPE_LINK_N2_OFFSET 0
2677 2686
2678/* PIPEB timing regs are same start from 0x61000 */ 2687/* PIPEB timing regs are same start from 0x61000 */
2679 2688
2680#define PIPEB_DATA_M1 0x61030 2689#define _PIPEB_DATA_M1 0x61030
2681#define PIPEB_DATA_N1 0x61034 2690#define _PIPEB_DATA_N1 0x61034
2682 2691
2683#define PIPEB_DATA_M2 0x61038 2692#define _PIPEB_DATA_M2 0x61038
2684#define PIPEB_DATA_N2 0x6103c 2693#define _PIPEB_DATA_N2 0x6103c
2685 2694
2686#define PIPEB_LINK_M1 0x61040 2695#define _PIPEB_LINK_M1 0x61040
2687#define PIPEB_LINK_N1 0x61044 2696#define _PIPEB_LINK_N1 0x61044
2688 2697
2689#define PIPEB_LINK_M2 0x61048 2698#define _PIPEB_LINK_M2 0x61048
2690#define PIPEB_LINK_N2 0x6104c 2699#define _PIPEB_LINK_N2 0x6104c
2691 2700
2692#define PIPE_DATA_M1(pipe) _PIPE(pipe, PIPEA_DATA_M1, PIPEB_DATA_M1) 2701#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2693#define PIPE_DATA_N1(pipe) _PIPE(pipe, PIPEA_DATA_N1, PIPEB_DATA_N1) 2702#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2694#define PIPE_DATA_M2(pipe) _PIPE(pipe, PIPEA_DATA_M2, PIPEB_DATA_M2) 2703#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2695#define PIPE_DATA_N2(pipe) _PIPE(pipe, PIPEA_DATA_N2, PIPEB_DATA_N2) 2704#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2696#define PIPE_LINK_M1(pipe) _PIPE(pipe, PIPEA_LINK_M1, PIPEB_LINK_M1) 2705#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2697#define PIPE_LINK_N1(pipe) _PIPE(pipe, PIPEA_LINK_N1, PIPEB_LINK_N1) 2706#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2698#define PIPE_LINK_M2(pipe) _PIPE(pipe, PIPEA_LINK_M2, PIPEB_LINK_M2) 2707#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2699#define PIPE_LINK_N2(pipe) _PIPE(pipe, PIPEA_LINK_N2, PIPEB_LINK_N2) 2708#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2700 2709
2701/* CPU panel fitter */ 2710/* CPU panel fitter */
2702#define PFA_CTL_1 0x68080 2711/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2703#define PFB_CTL_1 0x68880 2712#define _PFA_CTL_1 0x68080
2713#define _PFB_CTL_1 0x68880
2704#define PF_ENABLE (1<<31) 2714#define PF_ENABLE (1<<31)
2705#define PF_FILTER_MASK (3<<23) 2715#define PF_FILTER_MASK (3<<23)
2706#define PF_FILTER_PROGRAMMED (0<<23) 2716#define PF_FILTER_PROGRAMMED (0<<23)
2707#define PF_FILTER_MED_3x3 (1<<23) 2717#define PF_FILTER_MED_3x3 (1<<23)
2708#define PF_FILTER_EDGE_ENHANCE (2<<23) 2718#define PF_FILTER_EDGE_ENHANCE (2<<23)
2709#define PF_FILTER_EDGE_SOFTEN (3<<23) 2719#define PF_FILTER_EDGE_SOFTEN (3<<23)
2710#define PFA_WIN_SZ 0x68074 2720#define _PFA_WIN_SZ 0x68074
2711#define PFB_WIN_SZ 0x68874 2721#define _PFB_WIN_SZ 0x68874
2712#define PFA_WIN_POS 0x68070 2722#define _PFA_WIN_POS 0x68070
2713#define PFB_WIN_POS 0x68870 2723#define _PFB_WIN_POS 0x68870
2724#define _PFA_VSCALE 0x68084
2725#define _PFB_VSCALE 0x68884
2726#define _PFA_HSCALE 0x68090
2727#define _PFB_HSCALE 0x68890
2728
2729#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2730#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2731#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2732#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2733#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2714 2734
2715/* legacy palette */ 2735/* legacy palette */
2716#define LGC_PALETTE_A 0x4a000 2736#define _LGC_PALETTE_A 0x4a000
2717#define LGC_PALETTE_B 0x4a800 2737#define _LGC_PALETTE_B 0x4a800
2738#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2718 2739
2719/* interrupts */ 2740/* interrupts */
2720#define DE_MASTER_IRQ_CONTROL (1 << 31) 2741#define DE_MASTER_IRQ_CONTROL (1 << 31)
@@ -2880,17 +2901,17 @@
2880#define PCH_GMBUS4 0xc5110 2901#define PCH_GMBUS4 0xc5110
2881#define PCH_GMBUS5 0xc5120 2902#define PCH_GMBUS5 0xc5120
2882 2903
2883#define PCH_DPLL_A 0xc6014 2904#define _PCH_DPLL_A 0xc6014
2884#define PCH_DPLL_B 0xc6018 2905#define _PCH_DPLL_B 0xc6018
2885#define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B) 2906#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2886 2907
2887#define PCH_FPA0 0xc6040 2908#define _PCH_FPA0 0xc6040
2888#define FP_CB_TUNE (0x3<<22) 2909#define FP_CB_TUNE (0x3<<22)
2889#define PCH_FPA1 0xc6044 2910#define _PCH_FPA1 0xc6044
2890#define PCH_FPB0 0xc6048 2911#define _PCH_FPB0 0xc6048
2891#define PCH_FPB1 0xc604c 2912#define _PCH_FPB1 0xc604c
2892#define PCH_FP0(pipe) _PIPE(pipe, PCH_FPA0, PCH_FPB0) 2913#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2893#define PCH_FP1(pipe) _PIPE(pipe, PCH_FPA1, PCH_FPB1) 2914#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2894 2915
2895#define PCH_DPLL_TEST 0xc606c 2916#define PCH_DPLL_TEST 0xc606c
2896 2917
@@ -2942,60 +2963,69 @@
2942 2963
2943/* transcoder */ 2964/* transcoder */
2944 2965
2945#define TRANS_HTOTAL_A 0xe0000 2966#define _TRANS_HTOTAL_A 0xe0000
2946#define TRANS_HTOTAL_SHIFT 16 2967#define TRANS_HTOTAL_SHIFT 16
2947#define TRANS_HACTIVE_SHIFT 0 2968#define TRANS_HACTIVE_SHIFT 0
2948#define TRANS_HBLANK_A 0xe0004 2969#define _TRANS_HBLANK_A 0xe0004
2949#define TRANS_HBLANK_END_SHIFT 16 2970#define TRANS_HBLANK_END_SHIFT 16
2950#define TRANS_HBLANK_START_SHIFT 0 2971#define TRANS_HBLANK_START_SHIFT 0
2951#define TRANS_HSYNC_A 0xe0008 2972#define _TRANS_HSYNC_A 0xe0008
2952#define TRANS_HSYNC_END_SHIFT 16 2973#define TRANS_HSYNC_END_SHIFT 16
2953#define TRANS_HSYNC_START_SHIFT 0 2974#define TRANS_HSYNC_START_SHIFT 0
2954#define TRANS_VTOTAL_A 0xe000c 2975#define _TRANS_VTOTAL_A 0xe000c
2955#define TRANS_VTOTAL_SHIFT 16 2976#define TRANS_VTOTAL_SHIFT 16
2956#define TRANS_VACTIVE_SHIFT 0 2977#define TRANS_VACTIVE_SHIFT 0
2957#define TRANS_VBLANK_A 0xe0010 2978#define _TRANS_VBLANK_A 0xe0010
2958#define TRANS_VBLANK_END_SHIFT 16 2979#define TRANS_VBLANK_END_SHIFT 16
2959#define TRANS_VBLANK_START_SHIFT 0 2980#define TRANS_VBLANK_START_SHIFT 0
2960#define TRANS_VSYNC_A 0xe0014 2981#define _TRANS_VSYNC_A 0xe0014
2961#define TRANS_VSYNC_END_SHIFT 16 2982#define TRANS_VSYNC_END_SHIFT 16
2962#define TRANS_VSYNC_START_SHIFT 0 2983#define TRANS_VSYNC_START_SHIFT 0
2963 2984
2964#define TRANSA_DATA_M1 0xe0030 2985#define _TRANSA_DATA_M1 0xe0030
2965#define TRANSA_DATA_N1 0xe0034 2986#define _TRANSA_DATA_N1 0xe0034
2966#define TRANSA_DATA_M2 0xe0038 2987#define _TRANSA_DATA_M2 0xe0038
2967#define TRANSA_DATA_N2 0xe003c 2988#define _TRANSA_DATA_N2 0xe003c
2968#define TRANSA_DP_LINK_M1 0xe0040 2989#define _TRANSA_DP_LINK_M1 0xe0040
2969#define TRANSA_DP_LINK_N1 0xe0044 2990#define _TRANSA_DP_LINK_N1 0xe0044
2970#define TRANSA_DP_LINK_M2 0xe0048 2991#define _TRANSA_DP_LINK_M2 0xe0048
2971#define TRANSA_DP_LINK_N2 0xe004c 2992#define _TRANSA_DP_LINK_N2 0xe004c
2972 2993
2973#define TRANS_HTOTAL_B 0xe1000 2994#define _TRANS_HTOTAL_B 0xe1000
2974#define TRANS_HBLANK_B 0xe1004 2995#define _TRANS_HBLANK_B 0xe1004
2975#define TRANS_HSYNC_B 0xe1008 2996#define _TRANS_HSYNC_B 0xe1008
2976#define TRANS_VTOTAL_B 0xe100c 2997#define _TRANS_VTOTAL_B 0xe100c
2977#define TRANS_VBLANK_B 0xe1010 2998#define _TRANS_VBLANK_B 0xe1010
2978#define TRANS_VSYNC_B 0xe1014 2999#define _TRANS_VSYNC_B 0xe1014
2979 3000
2980#define TRANS_HTOTAL(pipe) _PIPE(pipe, TRANS_HTOTAL_A, TRANS_HTOTAL_B) 3001#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
2981#define TRANS_HBLANK(pipe) _PIPE(pipe, TRANS_HBLANK_A, TRANS_HBLANK_B) 3002#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
2982#define TRANS_HSYNC(pipe) _PIPE(pipe, TRANS_HSYNC_A, TRANS_HSYNC_B) 3003#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
2983#define TRANS_VTOTAL(pipe) _PIPE(pipe, TRANS_VTOTAL_A, TRANS_VTOTAL_B) 3004#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
2984#define TRANS_VBLANK(pipe) _PIPE(pipe, TRANS_VBLANK_A, TRANS_VBLANK_B) 3005#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
2985#define TRANS_VSYNC(pipe) _PIPE(pipe, TRANS_VSYNC_A, TRANS_VSYNC_B) 3006#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
2986 3007
2987#define TRANSB_DATA_M1 0xe1030 3008#define _TRANSB_DATA_M1 0xe1030
2988#define TRANSB_DATA_N1 0xe1034 3009#define _TRANSB_DATA_N1 0xe1034
2989#define TRANSB_DATA_M2 0xe1038 3010#define _TRANSB_DATA_M2 0xe1038
2990#define TRANSB_DATA_N2 0xe103c 3011#define _TRANSB_DATA_N2 0xe103c
2991#define TRANSB_DP_LINK_M1 0xe1040 3012#define _TRANSB_DP_LINK_M1 0xe1040
2992#define TRANSB_DP_LINK_N1 0xe1044 3013#define _TRANSB_DP_LINK_N1 0xe1044
2993#define TRANSB_DP_LINK_M2 0xe1048 3014#define _TRANSB_DP_LINK_M2 0xe1048
2994#define TRANSB_DP_LINK_N2 0xe104c 3015#define _TRANSB_DP_LINK_N2 0xe104c
2995 3016
2996#define TRANSACONF 0xf0008 3017#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
2997#define TRANSBCONF 0xf1008 3018#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
2998#define TRANSCONF(plane) _PIPE(plane, TRANSACONF, TRANSBCONF) 3019#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3020#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3021#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3022#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3023#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3024#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3025
3026#define _TRANSACONF 0xf0008
3027#define _TRANSBCONF 0xf1008
3028#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
2999#define TRANS_DISABLE (0<<31) 3029#define TRANS_DISABLE (0<<31)
3000#define TRANS_ENABLE (1<<31) 3030#define TRANS_ENABLE (1<<31)
3001#define TRANS_STATE_MASK (1<<30) 3031#define TRANS_STATE_MASK (1<<30)
@@ -3013,19 +3043,19 @@
3013#define TRANS_6BPC (2<<5) 3043#define TRANS_6BPC (2<<5)
3014#define TRANS_12BPC (3<<5) 3044#define TRANS_12BPC (3<<5)
3015 3045
3016#define FDI_RXA_CHICKEN 0xc200c 3046#define _FDI_RXA_CHICKEN 0xc200c
3017#define FDI_RXB_CHICKEN 0xc2010 3047#define _FDI_RXB_CHICKEN 0xc2010
3018#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 3048#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3019#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 3049#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3020#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN) 3050#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3021 3051
3022#define SOUTH_DSPCLK_GATE_D 0xc2020 3052#define SOUTH_DSPCLK_GATE_D 0xc2020
3023#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3053#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3024 3054
3025/* CPU: FDI_TX */ 3055/* CPU: FDI_TX */
3026#define FDI_TXA_CTL 0x60100 3056#define _FDI_TXA_CTL 0x60100
3027#define FDI_TXB_CTL 0x61100 3057#define _FDI_TXB_CTL 0x61100
3028#define FDI_TX_CTL(pipe) _PIPE(pipe, FDI_TXA_CTL, FDI_TXB_CTL) 3058#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3029#define FDI_TX_DISABLE (0<<31) 3059#define FDI_TX_DISABLE (0<<31)
3030#define FDI_TX_ENABLE (1<<31) 3060#define FDI_TX_ENABLE (1<<31)
3031#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3061#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
@@ -3065,9 +3095,9 @@
3065#define FDI_SCRAMBLING_DISABLE (1<<7) 3095#define FDI_SCRAMBLING_DISABLE (1<<7)
3066 3096
3067/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3097/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3068#define FDI_RXA_CTL 0xf000c 3098#define _FDI_RXA_CTL 0xf000c
3069#define FDI_RXB_CTL 0xf100c 3099#define _FDI_RXB_CTL 0xf100c
3070#define FDI_RX_CTL(pipe) _PIPE(pipe, FDI_RXA_CTL, FDI_RXB_CTL) 3100#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3071#define FDI_RX_ENABLE (1<<31) 3101#define FDI_RX_ENABLE (1<<31)
3072/* train, dp width same as FDI_TX */ 3102/* train, dp width same as FDI_TX */
3073#define FDI_DP_PORT_WIDTH_X8 (7<<19) 3103#define FDI_DP_PORT_WIDTH_X8 (7<<19)
@@ -3092,15 +3122,15 @@
3092#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3122#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3093#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3123#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3094 3124
3095#define FDI_RXA_MISC 0xf0010 3125#define _FDI_RXA_MISC 0xf0010
3096#define FDI_RXB_MISC 0xf1010 3126#define _FDI_RXB_MISC 0xf1010
3097#define FDI_RXA_TUSIZE1 0xf0030 3127#define _FDI_RXA_TUSIZE1 0xf0030
3098#define FDI_RXA_TUSIZE2 0xf0038 3128#define _FDI_RXA_TUSIZE2 0xf0038
3099#define FDI_RXB_TUSIZE1 0xf1030 3129#define _FDI_RXB_TUSIZE1 0xf1030
3100#define FDI_RXB_TUSIZE2 0xf1038 3130#define _FDI_RXB_TUSIZE2 0xf1038
3101#define FDI_RX_MISC(pipe) _PIPE(pipe, FDI_RXA_MISC, FDI_RXB_MISC) 3131#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3102#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, FDI_RXA_TUSIZE1, FDI_RXB_TUSIZE1) 3132#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3103#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, FDI_RXA_TUSIZE2, FDI_RXB_TUSIZE2) 3133#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3104 3134
3105/* FDI_RX interrupt register format */ 3135/* FDI_RX interrupt register format */
3106#define FDI_RX_INTER_LANE_ALIGN (1<<10) 3136#define FDI_RX_INTER_LANE_ALIGN (1<<10)
@@ -3115,12 +3145,12 @@
3115#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3145#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3116#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3146#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3117 3147
3118#define FDI_RXA_IIR 0xf0014 3148#define _FDI_RXA_IIR 0xf0014
3119#define FDI_RXA_IMR 0xf0018 3149#define _FDI_RXA_IMR 0xf0018
3120#define FDI_RXB_IIR 0xf1014 3150#define _FDI_RXB_IIR 0xf1014
3121#define FDI_RXB_IMR 0xf1018 3151#define _FDI_RXB_IMR 0xf1018
3122#define FDI_RX_IIR(pipe) _PIPE(pipe, FDI_RXA_IIR, FDI_RXB_IIR) 3152#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3123#define FDI_RX_IMR(pipe) _PIPE(pipe, FDI_RXA_IMR, FDI_RXB_IMR) 3153#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3124 3154
3125#define FDI_PLL_CTL_1 0xfe000 3155#define FDI_PLL_CTL_1 0xfe000
3126#define FDI_PLL_CTL_2 0xfe004 3156#define FDI_PLL_CTL_2 0xfe004
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 0521ecf26017..da474153a0a2 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -34,11 +34,10 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 35 u32 dpll_reg;
36 36
37 if (HAS_PCH_SPLIT(dev)) { 37 if (HAS_PCH_SPLIT(dev))
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 38 dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B;
39 } else { 39 else
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; 40 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
41 }
42 41
43 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); 42 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
44} 43}
@@ -46,7 +45,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
46static void i915_save_palette(struct drm_device *dev, enum pipe pipe) 45static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
47{ 46{
48 struct drm_i915_private *dev_priv = dev->dev_private; 47 struct drm_i915_private *dev_priv = dev->dev_private;
49 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 48 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
50 u32 *array; 49 u32 *array;
51 int i; 50 int i;
52 51
@@ -54,7 +53,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
54 return; 53 return;
55 54
56 if (HAS_PCH_SPLIT(dev)) 55 if (HAS_PCH_SPLIT(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 56 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
58 57
59 if (pipe == PIPE_A) 58 if (pipe == PIPE_A)
60 array = dev_priv->save_palette_a; 59 array = dev_priv->save_palette_a;
@@ -68,7 +67,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
68static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) 67static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
69{ 68{
70 struct drm_i915_private *dev_priv = dev->dev_private; 69 struct drm_i915_private *dev_priv = dev->dev_private;
71 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 70 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
72 u32 *array; 71 u32 *array;
73 int i; 72 int i;
74 73
@@ -76,7 +75,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
76 return; 75 return;
77 76
78 if (HAS_PCH_SPLIT(dev)) 77 if (HAS_PCH_SPLIT(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 78 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
80 79
81 if (pipe == PIPE_A) 80 if (pipe == PIPE_A)
82 array = dev_priv->save_palette_a; 81 array = dev_priv->save_palette_a;
@@ -241,12 +240,12 @@ static void i915_save_modeset_reg(struct drm_device *dev)
241 return; 240 return;
242 241
243 /* Cursor state */ 242 /* Cursor state */
244 dev_priv->saveCURACNTR = I915_READ(CURACNTR); 243 dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
245 dev_priv->saveCURAPOS = I915_READ(CURAPOS); 244 dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
246 dev_priv->saveCURABASE = I915_READ(CURABASE); 245 dev_priv->saveCURABASE = I915_READ(_CURABASE);
247 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR); 246 dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
248 dev_priv->saveCURBPOS = I915_READ(CURBPOS); 247 dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
249 dev_priv->saveCURBBASE = I915_READ(CURBBASE); 248 dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
250 if (IS_GEN2(dev)) 249 if (IS_GEN2(dev))
251 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 250 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
252 251
@@ -256,118 +255,118 @@ static void i915_save_modeset_reg(struct drm_device *dev)
256 } 255 }
257 256
258 /* Pipe & plane A info */ 257 /* Pipe & plane A info */
259 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 258 dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
260 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 259 dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
261 if (HAS_PCH_SPLIT(dev)) { 260 if (HAS_PCH_SPLIT(dev)) {
262 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 261 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
263 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 262 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
264 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); 263 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
265 } else { 264 } else {
266 dev_priv->saveFPA0 = I915_READ(FPA0); 265 dev_priv->saveFPA0 = I915_READ(_FPA0);
267 dev_priv->saveFPA1 = I915_READ(FPA1); 266 dev_priv->saveFPA1 = I915_READ(_FPA1);
268 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 267 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
269 } 268 }
270 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 269 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
271 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 270 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
272 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 271 dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
273 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 272 dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
274 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); 273 dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
275 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 274 dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
276 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 275 dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
277 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 276 dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
278 if (!HAS_PCH_SPLIT(dev)) 277 if (!HAS_PCH_SPLIT(dev))
279 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 278 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
280 279
281 if (HAS_PCH_SPLIT(dev)) { 280 if (HAS_PCH_SPLIT(dev)) {
282 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1); 281 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
283 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1); 282 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
284 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1); 283 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
285 dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1); 284 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
286 285
287 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL); 286 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
288 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL); 287 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
289 288
290 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1); 289 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
291 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ); 290 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
292 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS); 291 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
293 292
294 dev_priv->saveTRANSACONF = I915_READ(TRANSACONF); 293 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
295 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A); 294 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
296 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A); 295 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
297 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A); 296 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
298 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A); 297 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
299 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A); 298 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
300 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A); 299 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
301 } 300 }
302 301
303 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); 302 dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
304 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 303 dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
305 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); 304 dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
306 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); 305 dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
307 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); 306 dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
308 if (INTEL_INFO(dev)->gen >= 4) { 307 if (INTEL_INFO(dev)->gen >= 4) {
309 dev_priv->saveDSPASURF = I915_READ(DSPASURF); 308 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
310 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 309 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
311 } 310 }
312 i915_save_palette(dev, PIPE_A); 311 i915_save_palette(dev, PIPE_A);
313 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); 312 dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
314 313
315 /* Pipe & plane B info */ 314 /* Pipe & plane B info */
316 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 315 dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
317 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 316 dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
318 if (HAS_PCH_SPLIT(dev)) { 317 if (HAS_PCH_SPLIT(dev)) {
319 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 318 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
320 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 319 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
321 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); 320 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
322 } else { 321 } else {
323 dev_priv->saveFPB0 = I915_READ(FPB0); 322 dev_priv->saveFPB0 = I915_READ(_FPB0);
324 dev_priv->saveFPB1 = I915_READ(FPB1); 323 dev_priv->saveFPB1 = I915_READ(_FPB1);
325 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 324 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
326 } 325 }
327 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 326 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
328 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 327 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
329 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 328 dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
330 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 329 dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
331 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); 330 dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
332 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 331 dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
333 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 332 dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
334 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 333 dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
335 if (!HAS_PCH_SPLIT(dev)) 334 if (!HAS_PCH_SPLIT(dev))
336 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 335 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
337 336
338 if (HAS_PCH_SPLIT(dev)) { 337 if (HAS_PCH_SPLIT(dev)) {
339 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1); 338 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
340 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1); 339 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
341 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1); 340 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
342 dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1); 341 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
343 342
344 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL); 343 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
345 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL); 344 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
346 345
347 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1); 346 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
348 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ); 347 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
349 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS); 348 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
350 349
351 dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF); 350 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
352 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B); 351 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
353 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B); 352 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
354 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B); 353 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
355 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B); 354 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
356 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B); 355 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
357 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B); 356 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
358 } 357 }
359 358
360 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); 359 dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
361 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 360 dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
362 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); 361 dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
363 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); 362 dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
364 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); 363 dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
365 if (INTEL_INFO(dev)->gen >= 4) { 364 if (INTEL_INFO(dev)->gen >= 4) {
366 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); 365 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
367 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 366 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
368 } 367 }
369 i915_save_palette(dev, PIPE_B); 368 i915_save_palette(dev, PIPE_B);
370 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); 369 dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
371 370
372 /* Fences */ 371 /* Fences */
373 switch (INTEL_INFO(dev)->gen) { 372 switch (INTEL_INFO(dev)->gen) {
@@ -426,19 +425,19 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
426 425
427 426
428 if (HAS_PCH_SPLIT(dev)) { 427 if (HAS_PCH_SPLIT(dev)) {
429 dpll_a_reg = PCH_DPLL_A; 428 dpll_a_reg = _PCH_DPLL_A;
430 dpll_b_reg = PCH_DPLL_B; 429 dpll_b_reg = _PCH_DPLL_B;
431 fpa0_reg = PCH_FPA0; 430 fpa0_reg = _PCH_FPA0;
432 fpb0_reg = PCH_FPB0; 431 fpb0_reg = _PCH_FPB0;
433 fpa1_reg = PCH_FPA1; 432 fpa1_reg = _PCH_FPA1;
434 fpb1_reg = PCH_FPB1; 433 fpb1_reg = _PCH_FPB1;
435 } else { 434 } else {
436 dpll_a_reg = DPLL_A; 435 dpll_a_reg = _DPLL_A;
437 dpll_b_reg = DPLL_B; 436 dpll_b_reg = _DPLL_B;
438 fpa0_reg = FPA0; 437 fpa0_reg = _FPA0;
439 fpb0_reg = FPB0; 438 fpb0_reg = _FPB0;
440 fpa1_reg = FPA1; 439 fpa1_reg = _FPA1;
441 fpb1_reg = FPB1; 440 fpb1_reg = _FPB1;
442 } 441 }
443 442
444 if (HAS_PCH_SPLIT(dev)) { 443 if (HAS_PCH_SPLIT(dev)) {
@@ -461,60 +460,60 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
461 POSTING_READ(dpll_a_reg); 460 POSTING_READ(dpll_a_reg);
462 udelay(150); 461 udelay(150);
463 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { 462 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
464 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 463 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
465 POSTING_READ(DPLL_A_MD); 464 POSTING_READ(_DPLL_A_MD);
466 } 465 }
467 udelay(150); 466 udelay(150);
468 467
469 /* Restore mode */ 468 /* Restore mode */
470 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); 469 I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
471 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); 470 I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
472 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); 471 I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
473 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 472 I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
474 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 473 I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
475 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 474 I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
476 if (!HAS_PCH_SPLIT(dev)) 475 if (!HAS_PCH_SPLIT(dev))
477 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 476 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
478 477
479 if (HAS_PCH_SPLIT(dev)) { 478 if (HAS_PCH_SPLIT(dev)) {
480 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); 479 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
481 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); 480 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
482 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); 481 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
483 I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1); 482 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
484 483
485 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); 484 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
486 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); 485 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
487 486
488 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1); 487 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
489 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ); 488 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
490 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS); 489 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
491 490
492 I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF); 491 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
493 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A); 492 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
494 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A); 493 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
495 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A); 494 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
496 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A); 495 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
497 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A); 496 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
498 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A); 497 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
499 } 498 }
500 499
501 /* Restore plane info */ 500 /* Restore plane info */
502 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 501 I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
503 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); 502 I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
504 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); 503 I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
505 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); 504 I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
506 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); 505 I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
507 if (INTEL_INFO(dev)->gen >= 4) { 506 if (INTEL_INFO(dev)->gen >= 4) {
508 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); 507 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
509 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); 508 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
510 } 509 }
511 510
512 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); 511 I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
513 512
514 i915_restore_palette(dev, PIPE_A); 513 i915_restore_palette(dev, PIPE_A);
515 /* Enable the plane */ 514 /* Enable the plane */
516 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); 515 I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
517 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); 516 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
518 517
519 /* Pipe & plane B info */ 518 /* Pipe & plane B info */
520 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 519 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
@@ -530,68 +529,68 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
530 POSTING_READ(dpll_b_reg); 529 POSTING_READ(dpll_b_reg);
531 udelay(150); 530 udelay(150);
532 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { 531 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
533 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 532 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
534 POSTING_READ(DPLL_B_MD); 533 POSTING_READ(_DPLL_B_MD);
535 } 534 }
536 udelay(150); 535 udelay(150);
537 536
538 /* Restore mode */ 537 /* Restore mode */
539 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); 538 I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
540 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); 539 I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
541 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); 540 I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
542 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 541 I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
543 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 542 I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
544 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 543 I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
545 if (!HAS_PCH_SPLIT(dev)) 544 if (!HAS_PCH_SPLIT(dev))
546 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 545 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
547 546
548 if (HAS_PCH_SPLIT(dev)) { 547 if (HAS_PCH_SPLIT(dev)) {
549 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); 548 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
550 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); 549 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
551 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); 550 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
552 I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1); 551 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
553 552
554 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); 553 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
555 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); 554 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
556 555
557 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1); 556 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
558 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ); 557 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
559 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS); 558 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
560 559
561 I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF); 560 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
562 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B); 561 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
563 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B); 562 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
564 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B); 563 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
565 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B); 564 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
566 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B); 565 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
567 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B); 566 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
568 } 567 }
569 568
570 /* Restore plane info */ 569 /* Restore plane info */
571 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 570 I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
572 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); 571 I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
573 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); 572 I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
574 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); 573 I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
575 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 574 I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
576 if (INTEL_INFO(dev)->gen >= 4) { 575 if (INTEL_INFO(dev)->gen >= 4) {
577 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); 576 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
578 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); 577 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
579 } 578 }
580 579
581 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); 580 I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
582 581
583 i915_restore_palette(dev, PIPE_B); 582 i915_restore_palette(dev, PIPE_B);
584 /* Enable the plane */ 583 /* Enable the plane */
585 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 584 I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
586 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 585 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
587 586
588 /* Cursor state */ 587 /* Cursor state */
589 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS); 588 I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
590 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR); 589 I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
591 I915_WRITE(CURABASE, dev_priv->saveCURABASE); 590 I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
592 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS); 591 I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
593 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR); 592 I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
594 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE); 593 I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
595 if (IS_GEN2(dev)) 594 if (IS_GEN2(dev))
596 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 595 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
597 596
@@ -653,14 +652,14 @@ void i915_save_display(struct drm_device *dev)
653 dev_priv->saveDP_B = I915_READ(DP_B); 652 dev_priv->saveDP_B = I915_READ(DP_B);
654 dev_priv->saveDP_C = I915_READ(DP_C); 653 dev_priv->saveDP_C = I915_READ(DP_C);
655 dev_priv->saveDP_D = I915_READ(DP_D); 654 dev_priv->saveDP_D = I915_READ(DP_D);
656 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M); 655 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
657 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M); 656 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
658 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N); 657 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
659 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N); 658 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
660 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M); 659 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
661 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M); 660 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
662 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N); 661 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
663 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N); 662 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
664 } 663 }
665 /* FIXME: save TV & SDVO state */ 664 /* FIXME: save TV & SDVO state */
666 665
@@ -699,14 +698,14 @@ void i915_restore_display(struct drm_device *dev)
699 698
700 /* Display port ratios (must be done before clock is set) */ 699 /* Display port ratios (must be done before clock is set) */
701 if (SUPPORTS_INTEGRATED_DP(dev)) { 700 if (SUPPORTS_INTEGRATED_DP(dev)) {
702 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M); 701 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
703 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M); 702 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
704 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N); 703 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
705 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N); 704 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
706 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M); 705 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
707 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M); 706 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
708 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N); 707 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
709 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N); 708 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
710 } 709 }
711 710
712 /* This is only meaningful in non-KMS mode */ 711 /* This is only meaningful in non-KMS mode */
@@ -808,8 +807,8 @@ int i915_save_state(struct drm_device *dev)
808 dev_priv->saveDEIMR = I915_READ(DEIMR); 807 dev_priv->saveDEIMR = I915_READ(DEIMR);
809 dev_priv->saveGTIER = I915_READ(GTIER); 808 dev_priv->saveGTIER = I915_READ(GTIER);
810 dev_priv->saveGTIMR = I915_READ(GTIMR); 809 dev_priv->saveGTIMR = I915_READ(GTIMR);
811 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR); 810 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
812 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR); 811 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
813 dev_priv->saveMCHBAR_RENDER_STANDBY = 812 dev_priv->saveMCHBAR_RENDER_STANDBY =
814 I915_READ(RSTDBYCTL); 813 I915_READ(RSTDBYCTL);
815 } else { 814 } else {
@@ -857,11 +856,11 @@ int i915_restore_state(struct drm_device *dev)
857 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 856 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
858 I915_WRITE(GTIER, dev_priv->saveGTIER); 857 I915_WRITE(GTIER, dev_priv->saveGTIER);
859 I915_WRITE(GTIMR, dev_priv->saveGTIMR); 858 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
860 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); 859 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
861 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); 860 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
862 } else { 861 } else {
863 I915_WRITE (IER, dev_priv->saveIER); 862 I915_WRITE(IER, dev_priv->saveIER);
864 I915_WRITE (IMR, dev_priv->saveIMR); 863 I915_WRITE(IMR, dev_priv->saveIMR);
865 } 864 }
866 865
867 /* Clock gating state */ 866 /* Clock gating state */
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 8a77ff4a7237..8342259f3160 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -129,10 +129,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
129 u32 adpa, dpll_md; 129 u32 adpa, dpll_md;
130 u32 adpa_reg; 130 u32 adpa_reg;
131 131
132 if (intel_crtc->pipe == 0) 132 dpll_md_reg = DPLL_MD(intel_crtc->pipe);
133 dpll_md_reg = DPLL_A_MD;
134 else
135 dpll_md_reg = DPLL_B_MD;
136 133
137 if (HAS_PCH_SPLIT(dev)) 134 if (HAS_PCH_SPLIT(dev))
138 adpa_reg = PCH_ADPA; 135 adpa_reg = PCH_ADPA;
@@ -160,17 +157,16 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
160 adpa |= PORT_TRANS_A_SEL_CPT; 157 adpa |= PORT_TRANS_A_SEL_CPT;
161 else 158 else
162 adpa |= ADPA_PIPE_A_SELECT; 159 adpa |= ADPA_PIPE_A_SELECT;
163 if (!HAS_PCH_SPLIT(dev))
164 I915_WRITE(BCLRPAT_A, 0);
165 } else { 160 } else {
166 if (HAS_PCH_CPT(dev)) 161 if (HAS_PCH_CPT(dev))
167 adpa |= PORT_TRANS_B_SEL_CPT; 162 adpa |= PORT_TRANS_B_SEL_CPT;
168 else 163 else
169 adpa |= ADPA_PIPE_B_SELECT; 164 adpa |= ADPA_PIPE_B_SELECT;
170 if (!HAS_PCH_SPLIT(dev))
171 I915_WRITE(BCLRPAT_B, 0);
172 } 165 }
173 166
167 if (!HAS_PCH_SPLIT(dev))
168 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
169
174 I915_WRITE(adpa_reg, adpa); 170 I915_WRITE(adpa_reg, adpa);
175} 171}
176 172
@@ -353,21 +349,12 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt)
353 349
354 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 350 DRM_DEBUG_KMS("starting load-detect on CRT\n");
355 351
356 if (pipe == 0) { 352 bclrpat_reg = BCLRPAT(pipe);
357 bclrpat_reg = BCLRPAT_A; 353 vtotal_reg = VTOTAL(pipe);
358 vtotal_reg = VTOTAL_A; 354 vblank_reg = VBLANK(pipe);
359 vblank_reg = VBLANK_A; 355 vsync_reg = VSYNC(pipe);
360 vsync_reg = VSYNC_A; 356 pipeconf_reg = PIPECONF(pipe);
361 pipeconf_reg = PIPEACONF; 357 pipe_dsl_reg = PIPEDSL(pipe);
362 pipe_dsl_reg = PIPEADSL;
363 } else {
364 bclrpat_reg = BCLRPAT_B;
365 vtotal_reg = VTOTAL_B;
366 vblank_reg = VBLANK_B;
367 vsync_reg = VSYNC_B;
368 pipeconf_reg = PIPEBCONF;
369 pipe_dsl_reg = PIPEBDSL;
370 }
371 358
372 save_bclrpat = I915_READ(bclrpat_reg); 359 save_bclrpat = I915_READ(bclrpat_reg);
373 save_vtotal = I915_READ(vtotal_reg); 360 save_vtotal = I915_READ(vtotal_reg);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cc431f4581c3..37765e01d7f1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -989,7 +989,7 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
989void intel_wait_for_vblank(struct drm_device *dev, int pipe) 989void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990{ 990{
991 struct drm_i915_private *dev_priv = dev->dev_private; 991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); 992 int pipestat_reg = PIPESTAT(pipe);
993 993
994 /* Clear existing vblank status. Note this will clear any other 994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well. 995 * sticky status fields as well.
@@ -1185,7 +1185,7 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1185 1185
1186 WARN(panel_pipe == pipe && locked, 1186 WARN(panel_pipe == pipe && locked,
1187 "panel assertion failure, pipe %c regs locked\n", 1187 "panel assertion failure, pipe %c regs locked\n",
1188 pipe ? 'B' : 'A'); 1188 pipe_name(pipe));
1189} 1189}
1190 1190
1191static void assert_pipe(struct drm_i915_private *dev_priv, 1191static void assert_pipe(struct drm_i915_private *dev_priv,
@@ -1200,7 +1200,7 @@ static void assert_pipe(struct drm_i915_private *dev_priv,
1200 cur_state = !!(val & PIPECONF_ENABLE); 1200 cur_state = !!(val & PIPECONF_ENABLE);
1201 WARN(cur_state != state, 1201 WARN(cur_state != state,
1202 "pipe %c assertion failure (expected %s, current %s)\n", 1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe ? 'B' : 'A', state_string(state), state_string(cur_state)); 1203 pipe_name(pipe), state_string(state), state_string(cur_state));
1204} 1204}
1205#define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 1205#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206#define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 1206#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
@@ -1215,7 +1215,7 @@ static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1215 val = I915_READ(reg); 1215 val = I915_READ(reg);
1216 WARN(!(val & DISPLAY_PLANE_ENABLE), 1216 WARN(!(val & DISPLAY_PLANE_ENABLE),
1217 "plane %c assertion failure, should be active but is disabled\n", 1217 "plane %c assertion failure, should be active but is disabled\n",
1218 plane ? 'B' : 'A'); 1218 plane_name(plane));
1219} 1219}
1220 1220
1221static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1221static void assert_planes_disabled(struct drm_i915_private *dev_priv,
@@ -1236,8 +1236,8 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1236 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1236 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237 DISPPLANE_SEL_PIPE_SHIFT; 1237 DISPPLANE_SEL_PIPE_SHIFT;
1238 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, 1238 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1239 "plane %d assertion failure, should be off on pipe %c but is still active\n", 1239 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240 i, pipe ? 'B' : 'A'); 1240 plane_name(i), pipe_name(pipe));
1241 } 1241 }
1242} 1242}
1243 1243
@@ -1262,7 +1262,9 @@ static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1262 reg = TRANSCONF(pipe); 1262 reg = TRANSCONF(pipe);
1263 val = I915_READ(reg); 1263 val = I915_READ(reg);
1264 enabled = !!(val & TRANS_ENABLE); 1264 enabled = !!(val & TRANS_ENABLE);
1265 WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", pipe ? 'B' :'A'); 1265 WARN(enabled,
1266 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1267 pipe_name(pipe));
1266} 1268}
1267 1269
1268static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1270static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
@@ -1275,7 +1277,7 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1275 sel_pipe = (val & DP_PIPEB_SELECT) >> 30; 1277 sel_pipe = (val & DP_PIPEB_SELECT) >> 30;
1276 WARN((val & DP_PORT_EN) && sel_pipe == pipe, 1278 WARN((val & DP_PORT_EN) && sel_pipe == pipe,
1277 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1279 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1278 reg, pipe ? 'B' : 'A'); 1280 reg, pipe_name(pipe));
1279} 1281}
1280 1282
1281static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1283static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
@@ -1288,7 +1290,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1288 sel_pipe = (val & TRANSCODER_B) >> 30; 1290 sel_pipe = (val & TRANSCODER_B) >> 30;
1289 WARN((val & PORT_ENABLE) && sel_pipe == pipe, 1291 WARN((val & PORT_ENABLE) && sel_pipe == pipe,
1290 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1292 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1291 reg, pipe ? 'B' : 'A'); 1293 reg, pipe_name(pipe));
1292} 1294}
1293 1295
1294static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1296static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
@@ -1307,14 +1309,14 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1307 sel_pipe = (val & ADPA_TRANS_B_SELECT) >> 30; 1309 sel_pipe = (val & ADPA_TRANS_B_SELECT) >> 30;
1308 WARN(sel_pipe == pipe && (val & ADPA_DAC_ENABLE), 1310 WARN(sel_pipe == pipe && (val & ADPA_DAC_ENABLE),
1309 "PCH VGA enabled on transcoder %c, should be disabled\n", 1311 "PCH VGA enabled on transcoder %c, should be disabled\n",
1310 pipe ? 'B' : 'A'); 1312 pipe_name(pipe));
1311 1313
1312 reg = PCH_LVDS; 1314 reg = PCH_LVDS;
1313 val = I915_READ(reg); 1315 val = I915_READ(reg);
1314 sel_pipe = (val & LVDS_PIPEB_SELECT) >> 30; 1316 sel_pipe = (val & LVDS_PIPEB_SELECT) >> 30;
1315 WARN(sel_pipe == pipe && (val & LVDS_PORT_EN), 1317 WARN(sel_pipe == pipe && (val & LVDS_PORT_EN),
1316 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1317 pipe ? 'B' : 'A'); 1319 pipe_name(pipe));
1318 1320
1319 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); 1321 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1320 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); 1322 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
@@ -2816,12 +2818,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2816 * as some pre-programmed values are broken, 2818 * as some pre-programmed values are broken,
2817 * e.g. x201. 2819 * e.g. x201.
2818 */ 2820 */
2819 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 2821 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2820 PF_ENABLE | PF_FILTER_MED_3x3); 2822 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2821 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, 2823 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2822 dev_priv->pch_pf_pos);
2823 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2824 dev_priv->pch_pf_size);
2825 } 2824 }
2826 2825
2827 intel_enable_pipe(dev_priv, pipe, is_pch_port); 2826 intel_enable_pipe(dev_priv, pipe, is_pch_port);
@@ -2860,8 +2859,8 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
2860 intel_disable_pipe(dev_priv, pipe); 2859 intel_disable_pipe(dev_priv, pipe);
2861 2860
2862 /* Disable PF */ 2861 /* Disable PF */
2863 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); 2862 I915_WRITE(PF_CTL(pipe), 0);
2864 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); 2863 I915_WRITE(PF_WIN_SZ(pipe), 0);
2865 2864
2866 ironlake_fdi_disable(crtc); 2865 ironlake_fdi_disable(crtc);
2867 2866
@@ -2886,10 +2885,20 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
2886 2885
2887 /* disable DPLL_SEL */ 2886 /* disable DPLL_SEL */
2888 temp = I915_READ(PCH_DPLL_SEL); 2887 temp = I915_READ(PCH_DPLL_SEL);
2889 if (pipe == 0) 2888 switch (pipe) {
2890 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 2889 case 0:
2891 else 2890 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2891 break;
2892 case 1:
2892 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2893 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2894 break;
2895 case 2:
2896 /* FIXME: manage transcoder PLLs? */
2897 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2898 break;
2899 default:
2900 BUG(); /* wtf */
2901 }
2893 I915_WRITE(PCH_DPLL_SEL, temp); 2902 I915_WRITE(PCH_DPLL_SEL, temp);
2894 } 2903 }
2895 2904
@@ -3074,7 +3083,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3074 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; 3083 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3075 break; 3084 break;
3076 default: 3085 default:
3077 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); 3086 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3078 break; 3087 break;
3079 } 3088 }
3080} 3089}
@@ -4923,10 +4932,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4923 /* enable transcoder DPLL */ 4932 /* enable transcoder DPLL */
4924 if (HAS_PCH_CPT(dev)) { 4933 if (HAS_PCH_CPT(dev)) {
4925 temp = I915_READ(PCH_DPLL_SEL); 4934 temp = I915_READ(PCH_DPLL_SEL);
4926 if (pipe == 0) 4935 switch (pipe) {
4936 case 0:
4927 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; 4937 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4928 else 4938 break;
4939 case 1:
4929 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; 4940 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4941 break;
4942 case 2:
4943 /* FIXME: manage transcoder PLLs? */
4944 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4945 break;
4946 default:
4947 BUG();
4948 }
4930 I915_WRITE(PCH_DPLL_SEL, temp); 4949 I915_WRITE(PCH_DPLL_SEL, temp);
4931 4950
4932 POSTING_READ(PCH_DPLL_SEL); 4951 POSTING_READ(PCH_DPLL_SEL);
@@ -5009,17 +5028,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
5009 intel_dp_set_m_n(crtc, mode, adjusted_mode); 5028 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5010 } else if (HAS_PCH_SPLIT(dev)) { 5029 } else if (HAS_PCH_SPLIT(dev)) {
5011 /* For non-DP output, clear any trans DP clock recovery setting.*/ 5030 /* For non-DP output, clear any trans DP clock recovery setting.*/
5012 if (pipe == 0) { 5031 I915_WRITE(TRANSDATA_M1(pipe), 0);
5013 I915_WRITE(TRANSA_DATA_M1, 0); 5032 I915_WRITE(TRANSDATA_N1(pipe), 0);
5014 I915_WRITE(TRANSA_DATA_N1, 0); 5033 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5015 I915_WRITE(TRANSA_DP_LINK_M1, 0); 5034 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5016 I915_WRITE(TRANSA_DP_LINK_N1, 0);
5017 } else {
5018 I915_WRITE(TRANSB_DATA_M1, 0);
5019 I915_WRITE(TRANSB_DATA_N1, 0);
5020 I915_WRITE(TRANSB_DP_LINK_M1, 0);
5021 I915_WRITE(TRANSB_DP_LINK_N1, 0);
5022 }
5023 } 5035 }
5024 5036
5025 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 5037 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
@@ -5153,7 +5165,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
5153 struct drm_device *dev = crtc->dev; 5165 struct drm_device *dev = crtc->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private; 5166 struct drm_i915_private *dev_priv = dev->dev_private;
5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5156 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; 5168 int palreg = PALETTE(intel_crtc->pipe);
5157 int i; 5169 int i;
5158 5170
5159 /* The clocks have to be on to load the palette. */ 5171 /* The clocks have to be on to load the palette. */
@@ -5162,8 +5174,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
5162 5174
5163 /* use legacy palette for Ironlake */ 5175 /* use legacy palette for Ironlake */
5164 if (HAS_PCH_SPLIT(dev)) 5176 if (HAS_PCH_SPLIT(dev))
5165 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : 5177 palreg = LGC_PALETTE(intel_crtc->pipe);
5166 LGC_PALETTE_B;
5167 5178
5168 for (i = 0; i < 256; i++) { 5179 for (i = 0; i < 256; i++) {
5169 I915_WRITE(palreg + 4 * i, 5180 I915_WRITE(palreg + 4 * i,
@@ -5184,12 +5195,12 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5184 if (intel_crtc->cursor_visible == visible) 5195 if (intel_crtc->cursor_visible == visible)
5185 return; 5196 return;
5186 5197
5187 cntl = I915_READ(CURACNTR); 5198 cntl = I915_READ(_CURACNTR);
5188 if (visible) { 5199 if (visible) {
5189 /* On these chipsets we can only modify the base whilst 5200 /* On these chipsets we can only modify the base whilst
5190 * the cursor is disabled. 5201 * the cursor is disabled.
5191 */ 5202 */
5192 I915_WRITE(CURABASE, base); 5203 I915_WRITE(_CURABASE, base);
5193 5204
5194 cntl &= ~(CURSOR_FORMAT_MASK); 5205 cntl &= ~(CURSOR_FORMAT_MASK);
5195 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 5206 /* XXX width must be 64, stride 256 => 0x00 << 28 */
@@ -5198,7 +5209,7 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5198 CURSOR_FORMAT_ARGB; 5209 CURSOR_FORMAT_ARGB;
5199 } else 5210 } else
5200 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 5211 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5201 I915_WRITE(CURACNTR, cntl); 5212 I915_WRITE(_CURACNTR, cntl);
5202 5213
5203 intel_crtc->cursor_visible = visible; 5214 intel_crtc->cursor_visible = visible;
5204} 5215}
@@ -5212,7 +5223,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5212 bool visible = base != 0; 5223 bool visible = base != 0;
5213 5224
5214 if (intel_crtc->cursor_visible != visible) { 5225 if (intel_crtc->cursor_visible != visible) {
5215 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); 5226 uint32_t cntl = CURCNTR(pipe);
5216 if (base) { 5227 if (base) {
5217 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 5228 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5218 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 5229 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
@@ -5221,12 +5232,12 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5221 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 5232 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5222 cntl |= CURSOR_MODE_DISABLE; 5233 cntl |= CURSOR_MODE_DISABLE;
5223 } 5234 }
5224 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); 5235 I915_WRITE(CURCNTR(pipe), cntl);
5225 5236
5226 intel_crtc->cursor_visible = visible; 5237 intel_crtc->cursor_visible = visible;
5227 } 5238 }
5228 /* and commit changes on next vblank */ 5239 /* and commit changes on next vblank */
5229 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); 5240 I915_WRITE(CURBASE(pipe), base);
5230} 5241}
5231 5242
5232/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 5243/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
@@ -5276,7 +5287,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5276 if (!visible && !intel_crtc->cursor_visible) 5287 if (!visible && !intel_crtc->cursor_visible)
5277 return; 5288 return;
5278 5289
5279 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); 5290 I915_WRITE(CURPOS(pipe), pos);
5280 if (IS_845G(dev) || IS_I865G(dev)) 5291 if (IS_845G(dev) || IS_I865G(dev))
5281 i845_update_cursor(crtc, base); 5292 i845_update_cursor(crtc, base);
5282 else 5293 else
@@ -5582,14 +5593,14 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5582 struct drm_i915_private *dev_priv = dev->dev_private; 5593 struct drm_i915_private *dev_priv = dev->dev_private;
5583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5584 int pipe = intel_crtc->pipe; 5595 int pipe = intel_crtc->pipe;
5585 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); 5596 u32 dpll = DPLL(pipe);
5586 u32 fp; 5597 u32 fp;
5587 intel_clock_t clock; 5598 intel_clock_t clock;
5588 5599
5589 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 5600 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5590 fp = I915_READ((pipe == 0) ? FPA0 : FPB0); 5601 fp = FP0(pipe);
5591 else 5602 else
5592 fp = I915_READ((pipe == 0) ? FPA1 : FPB1); 5603 fp = FP1(pipe);
5593 5604
5594 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 5605 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5595 if (IS_PINEVIEW(dev)) { 5606 if (IS_PINEVIEW(dev)) {
@@ -5667,14 +5678,13 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5667struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 5678struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5668 struct drm_crtc *crtc) 5679 struct drm_crtc *crtc)
5669{ 5680{
5670 struct drm_i915_private *dev_priv = dev->dev_private;
5671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5672 int pipe = intel_crtc->pipe; 5682 int pipe = intel_crtc->pipe;
5673 struct drm_display_mode *mode; 5683 struct drm_display_mode *mode;
5674 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); 5684 int htot = HTOTAL(pipe);
5675 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); 5685 int hsync = HSYNC(pipe);
5676 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); 5686 int vtot = VTOTAL(pipe);
5677 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); 5687 int vsync = VSYNC(pipe);
5678 5688
5679 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 5689 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5680 if (!mode) 5690 if (!mode)
@@ -5783,7 +5793,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
5783 drm_i915_private_t *dev_priv = dev->dev_private; 5793 drm_i915_private_t *dev_priv = dev->dev_private;
5784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5785 int pipe = intel_crtc->pipe; 5795 int pipe = intel_crtc->pipe;
5786 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 5796 int dpll_reg = DPLL(pipe);
5787 int dpll = I915_READ(dpll_reg); 5797 int dpll = I915_READ(dpll_reg);
5788 5798
5789 if (HAS_PCH_SPLIT(dev)) 5799 if (HAS_PCH_SPLIT(dev))
@@ -6164,7 +6174,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6164 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 6174 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6165 */ 6175 */
6166 pf = 0; 6176 pf = 0;
6167 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; 6177 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6168 OUT_RING(pf | pipesrc); 6178 OUT_RING(pf | pipesrc);
6169 break; 6179 break;
6170 6180
@@ -6174,8 +6184,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6174 OUT_RING(fb->pitch | obj->tiling_mode); 6184 OUT_RING(fb->pitch | obj->tiling_mode);
6175 OUT_RING(obj->gtt_offset); 6185 OUT_RING(obj->gtt_offset);
6176 6186
6177 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 6187 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6178 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; 6188 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6179 OUT_RING(pf | pipesrc); 6189 OUT_RING(pf | pipesrc);
6180 break; 6190 break;
6181 } 6191 }
@@ -6945,6 +6955,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6945void intel_enable_clock_gating(struct drm_device *dev) 6955void intel_enable_clock_gating(struct drm_device *dev)
6946{ 6956{
6947 struct drm_i915_private *dev_priv = dev->dev_private; 6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958 int pipe;
6948 6959
6949 /* 6960 /*
6950 * Disable clock gating reported to work incorrectly according to the 6961 * Disable clock gating reported to work incorrectly according to the
@@ -7054,12 +7065,10 @@ void intel_enable_clock_gating(struct drm_device *dev)
7054 ILK_DPARB_CLK_GATE | 7065 ILK_DPARB_CLK_GATE |
7055 ILK_DPFD_CLK_GATE); 7066 ILK_DPFD_CLK_GATE);
7056 7067
7057 I915_WRITE(DSPACNTR, 7068 for_each_pipe(pipe)
7058 I915_READ(DSPACNTR) | 7069 I915_WRITE(DSPCNTR(pipe),
7059 DISPPLANE_TRICKLE_FEED_DISABLE); 7070 I915_READ(DSPCNTR(pipe)) |
7060 I915_WRITE(DSPBCNTR, 7071 DISPPLANE_TRICKLE_FEED_DISABLE);
7061 I915_READ(DSPBCNTR) |
7062 DISPPLANE_TRICKLE_FEED_DISABLE);
7063 } 7072 }
7064 } else if (IS_G4X(dev)) { 7073 } else if (IS_G4X(dev)) {
7065 uint32_t dspclk_gate; 7074 uint32_t dspclk_gate;
@@ -7394,10 +7403,6 @@ void intel_modeset_init(struct drm_device *dev)
7394 } 7403 }
7395 dev->mode_config.fb_base = dev->agp->base; 7404 dev->mode_config.fb_base = dev->agp->base;
7396 7405
7397 if (IS_MOBILE(dev) || !IS_GEN2(dev))
7398 dev_priv->num_pipe = 2;
7399 else
7400 dev_priv->num_pipe = 1;
7401 DRM_DEBUG_KMS("%d display pipe%s available.\n", 7406 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7402 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); 7407 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7403 7408
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ac261155b2f7..e478f6a94535 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -685,6 +685,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
686 int lane_count = 4, bpp = 24; 686 int lane_count = 4, bpp = 24;
687 struct intel_dp_m_n m_n; 687 struct intel_dp_m_n m_n;
688 int pipe = intel_crtc->pipe;
688 689
689 /* 690 /*
690 * Find the lane count in the intel_encoder private 691 * Find the lane count in the intel_encoder private
@@ -715,39 +716,19 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
715 mode->clock, adjusted_mode->clock, &m_n); 716 mode->clock, adjusted_mode->clock, &m_n);
716 717
717 if (HAS_PCH_SPLIT(dev)) { 718 if (HAS_PCH_SPLIT(dev)) {
718 if (intel_crtc->pipe == 0) { 719 I915_WRITE(TRANSDATA_M1(pipe),
719 I915_WRITE(TRANSA_DATA_M1, 720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 721 m_n.gmch_m);
721 m_n.gmch_m); 722 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
722 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); 723 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
723 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); 724 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
724 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
725 } else {
726 I915_WRITE(TRANSB_DATA_M1,
727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
728 m_n.gmch_m);
729 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
730 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
731 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
732 }
733 } else { 725 } else {
734 if (intel_crtc->pipe == 0) { 726 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
735 I915_WRITE(PIPEA_GMCH_DATA_M, 727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
736 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 728 m_n.gmch_m);
737 m_n.gmch_m); 729 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
738 I915_WRITE(PIPEA_GMCH_DATA_N, 730 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
739 m_n.gmch_n); 731 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
740 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
741 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
742 } else {
743 I915_WRITE(PIPEB_GMCH_DATA_M,
744 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
745 m_n.gmch_m);
746 I915_WRITE(PIPEB_GMCH_DATA_N,
747 m_n.gmch_n);
748 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
749 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
750 }
751 } 732 }
752} 733}
753 734
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index ea373283c93b..6eda1b51c636 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -178,7 +178,7 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
178 int pipe = intel_crtc->pipe; 178 int pipe = intel_crtc->pipe;
179 u32 dvo_val; 179 u32 dvo_val;
180 u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; 180 u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
181 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 181 int dpll_reg = DPLL(pipe);
182 182
183 switch (dvo_reg) { 183 switch (dvo_reg) {
184 case DVOA: 184 case DVOA:
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 3eec52a0b8e6..cd089607eb89 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -231,6 +231,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
231 struct intel_lvds *intel_lvds = to_intel_lvds(encoder); 231 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
232 struct drm_encoder *tmp_encoder; 232 struct drm_encoder *tmp_encoder;
233 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 233 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
234 int pipe;
234 235
235 /* Should never happen!! */ 236 /* Should never happen!! */
236 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { 237 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
@@ -283,8 +284,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
283 * to register description and PRM. 284 * to register description and PRM.
284 * Change the value here to see the borders for debugging 285 * Change the value here to see the borders for debugging
285 */ 286 */
286 I915_WRITE(BCLRPAT_A, 0); 287 for_each_pipe(pipe)
287 I915_WRITE(BCLRPAT_B, 0); 288 I915_WRITE(BCLRPAT(pipe), 0);
288 289
289 switch (intel_lvds->fitting_mode) { 290 switch (intel_lvds->fitting_mode) {
290 case DRM_MODE_SCALE_CENTER: 291 case DRM_MODE_SCALE_CENTER:
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index d2fdfd589c85..29fb2174eaaa 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -255,7 +255,7 @@ i830_activate_pipe_a(struct drm_device *dev)
255 return 0; 255 return 0;
256 256
257 /* most i8xx have pipe a forced on, so don't trust dpms mode */ 257 /* most i8xx have pipe a forced on, so don't trust dpms mode */
258 if (I915_READ(PIPEACONF) & PIPECONF_ENABLE) 258 if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
259 return 0; 259 return 0;
260 260
261 crtc_funcs = crtc->base.helper_private; 261 crtc_funcs = crtc->base.helper_private;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 93206e4eaa6f..5455287cacea 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1006,6 +1006,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1006 const struct video_levels *video_levels; 1006 const struct video_levels *video_levels;
1007 const struct color_conversion *color_conversion; 1007 const struct color_conversion *color_conversion;
1008 bool burst_ena; 1008 bool burst_ena;
1009 int pipe = intel_crtc->pipe;
1009 1010
1010 if (!tv_mode) 1011 if (!tv_mode)
1011 return; /* can't happen (mode_prepare prevents this) */ 1012 return; /* can't happen (mode_prepare prevents this) */
@@ -1149,14 +1150,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1149 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | 1150 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1150 (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); 1151 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1151 { 1152 {
1152 int pipeconf_reg = (intel_crtc->pipe == 0) ? 1153 int pipeconf_reg = PIPECONF(pipe);
1153 PIPEACONF : PIPEBCONF; 1154 int dspcntr_reg = DSPCNTR(pipe);
1154 int dspcntr_reg = (intel_crtc->plane == 0) ?
1155 DSPACNTR : DSPBCNTR;
1156 int pipeconf = I915_READ(pipeconf_reg); 1155 int pipeconf = I915_READ(pipeconf_reg);
1157 int dspcntr = I915_READ(dspcntr_reg); 1156 int dspcntr = I915_READ(dspcntr_reg);
1158 int dspbase_reg = (intel_crtc->plane == 0) ? 1157 int dspbase_reg = DSPADDR(pipe);
1159 DSPAADDR : DSPBADDR;
1160 int xpos = 0x0, ypos = 0x0; 1158 int xpos = 0x0, ypos = 0x0;
1161 unsigned int xsize, ysize; 1159 unsigned int xsize, ysize;
1162 /* Pipe must be off here */ 1160 /* Pipe must be off here */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 02:58:15 -0500