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authorChris Wilson <chris@chris-wilson.co.uk>2013-10-30 05:28:22 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-30 05:37:58 -0400
commit94e39e282ecd299b095f37cd0f521d83bd799b14 (patch)
tree1c5588c1eb250b4d6eafd0da40365a744f0a2f7e
parentf4adcd247766e5b914f861ed143ff328f869bf80 (diff)
drm/i915: Capture batchbuffer state upon GPU hang
The bbstate contains useful bits of debugging information such as whether the batch is being read from GTT or PPGTT, or whether it is allowed to execute privileged instructions. v2: Only record BB_STATE for gen4+ Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_gpu_error.c4
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
3 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57715c8e59c6..8bc0b3b42183 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -299,6 +299,7 @@ struct drm_i915_error_state {
299 u32 cpu_ring_tail[I915_NUM_RINGS]; 299 u32 cpu_ring_tail[I915_NUM_RINGS];
300 u32 error; /* gen6+ */ 300 u32 error; /* gen6+ */
301 u32 err_int; /* gen7 */ 301 u32 err_int; /* gen7 */
302 u32 bbstate[I915_NUM_RINGS];
302 u32 instpm[I915_NUM_RINGS]; 303 u32 instpm[I915_NUM_RINGS];
303 u32 instps[I915_NUM_RINGS]; 304 u32 instps[I915_NUM_RINGS];
304 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 305 u32 extra_instdone[I915_NUM_INSTDONE_REG];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5dde81026471..a8bb213da79f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -249,7 +249,8 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); 249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
250 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) 250 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr); 251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
252 252 if (INTEL_INFO(dev)->gen >= 4)
253 err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]);
253 if (INTEL_INFO(dev)->gen >= 4) 254 if (INTEL_INFO(dev)->gen >= 4)
254 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); 255 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
255 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); 256 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
@@ -725,6 +726,7 @@ static void i915_record_ring_state(struct drm_device *dev,
725 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 726 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
726 if (ring->id == RCS) 727 if (ring->id == RCS)
727 error->bbaddr = I915_READ64(BB_ADDR); 728 error->bbaddr = I915_READ64(BB_ADDR);
729 error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
728 } else { 730 } else {
729 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); 731 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
730 error->ipeir[ring->id] = I915_READ(IPEIR); 732 error->ipeir[ring->id] = I915_READ(IPEIR);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47de41f1d4b4..9785f7d031a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -718,6 +718,7 @@
718#define NOPID 0x02094 718#define NOPID 0x02094
719#define HWSTAM 0x02098 719#define HWSTAM 0x02098
720#define DMA_FADD_I8XX 0x020d0 720#define DMA_FADD_I8XX 0x020d0
721#define RING_BBSTATE(base) ((base)+0x110)
721 722
722#define ERROR_GEN6 0x040a0 723#define ERROR_GEN6 0x040a0
723#define GEN7_ERR_INT 0x44040 724#define GEN7_ERR_INT 0x44040