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authorSteven J. Hill <Steven.Hill@imgtec.com>2013-11-07 07:48:29 -0500
committerRalf Baechle <ralf@linux-mips.org>2014-01-13 17:40:55 -0500
commit9355e59c332858f0e52c62659bb41a7c2bca0a1b (patch)
tree3ce0718e4202d493a87a0b121a32760372af7af4
parent1ac944007bede6d6f934831959b0e2b65c82d291 (diff)
MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulator
This patch adds support for microMIPS encodings of the mfhc1 & mthc1 instructions introduced in release 2 of the mips32 & mips64 architectures, converting them to their mips32 equivalents for the FPU emulator. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/uapi/asm/inst.h2
-rw-r--r--arch/mips/math-emu/cp1emu.c8
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 0ee96563e6f0..b39ba25b41cc 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -398,8 +398,10 @@ enum mm_32f_73_minor_op {
398 mm_movt1_op = 0xa5, 398 mm_movt1_op = 0xa5,
399 mm_ftruncw_op = 0xac, 399 mm_ftruncw_op = 0xac,
400 mm_fneg1_op = 0xad, 400 mm_fneg1_op = 0xad,
401 mm_mfhc1_op = 0xc0,
401 mm_froundl_op = 0xcc, 402 mm_froundl_op = 0xcc,
402 mm_fcvtd1_op = 0xcd, 403 mm_fcvtd1_op = 0xcd,
404 mm_mthc1_op = 0xe0,
403 mm_froundw_op = 0xec, 405 mm_froundw_op = 0xec,
404 mm_fcvts1_op = 0xed, 406 mm_fcvts1_op = 0xed,
405}; 407};
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index aaf7c92f4629..0e47ae2aa96b 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -417,14 +417,20 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
417 case mm_mtc1_op: 417 case mm_mtc1_op:
418 case mm_cfc1_op: 418 case mm_cfc1_op:
419 case mm_ctc1_op: 419 case mm_ctc1_op:
420 case mm_mfhc1_op:
421 case mm_mthc1_op:
420 if (insn.mm_fp1_format.op == mm_mfc1_op) 422 if (insn.mm_fp1_format.op == mm_mfc1_op)
421 op = mfc_op; 423 op = mfc_op;
422 else if (insn.mm_fp1_format.op == mm_mtc1_op) 424 else if (insn.mm_fp1_format.op == mm_mtc1_op)
423 op = mtc_op; 425 op = mtc_op;
424 else if (insn.mm_fp1_format.op == mm_cfc1_op) 426 else if (insn.mm_fp1_format.op == mm_cfc1_op)
425 op = cfc_op; 427 op = cfc_op;
426 else 428 else if (insn.mm_fp1_format.op == mm_ctc1_op)
427 op = ctc_op; 429 op = ctc_op;
430 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
431 op = mfhc_op;
432 else
433 op = mthc_op;
428 mips32_insn.fp1_format.opcode = cop1_op; 434 mips32_insn.fp1_format.opcode = cop1_op;
429 mips32_insn.fp1_format.op = op; 435 mips32_insn.fp1_format.op = op;
430 mips32_insn.fp1_format.rt = 436 mips32_insn.fp1_format.rt =