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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-04-12 01:37:20 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-06-04 08:04:02 -0400
commit87f8c988636db0d477bb63fddfaefb5be9b1c386 (patch)
treec7dc0ee693df73b3b50a65a0600c2732fa347e13
parented3e26049e238d066841f858509b764df37c3776 (diff)
sh-pfc: Add r8a7778 pinmux support
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms@verge.net.au>
Diffstat
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c3
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c2369
5 files changed, 2379 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index a0b6bd0b1993..32161c4fbb1d 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -30,6 +30,11 @@ config PINCTRL_PFC_R8A7740
30 depends on ARCH_R8A7740 30 depends on ARCH_R8A7740
31 select PINCTRL_SH_PFC 31 select PINCTRL_SH_PFC
32 32
33config PINCTRL_PFC_R8A7778
34 def_bool y
35 depends on ARCH_R8A7778
36 select PINCTRL_SH_PFC
37
33config PINCTRL_PFC_R8A7779 38config PINCTRL_PFC_R8A7779
34 def_bool y 39 def_bool y
35 depends on ARCH_R8A7779 40 depends on ARCH_R8A7779
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 1cbf5b180617..5e0c222c12d7 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -5,6 +5,7 @@ endif
5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o 5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o 6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o 7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o 9obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
9obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o 10obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
10obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 11obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index db0d6f7adc9f..4540ce384ee5 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -424,6 +424,9 @@ static const struct platform_device_id sh_pfc_id_table[] = {
424#ifdef CONFIG_PINCTRL_PFC_R8A7740 424#ifdef CONFIG_PINCTRL_PFC_R8A7740
425 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, 425 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
426#endif 426#endif
427#ifdef CONFIG_PINCTRL_PFC_R8A7778
428 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
429#endif
427#ifdef CONFIG_PINCTRL_PFC_R8A7779 430#ifdef CONFIG_PINCTRL_PFC_R8A7779
428 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, 431 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
429#endif 432#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 6ec746f0339b..e847afbe1f98 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -57,6 +57,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
57 57
58extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; 58extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
59extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 59extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
60extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
60extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 61extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
61extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 62extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
62extern const struct sh_pfc_soc_info sh7203_pinmux_info; 63extern const struct sh_pfc_soc_info sh7203_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
new file mode 100644
index 000000000000..ddbd27b73782
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -0,0 +1,2369 @@
1/*
2 * r8a7778 processor support - PFC hardware block
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 * Copyright (C) 2011 Magnus Damm
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/platform_data/gpio-rcar.h>
22#include <linux/kernel.h>
23#include "sh_pfc.h"
24
25#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
26
27#define PORT_GP_32(bank, fn, sfx) \
28 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
29 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
30 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
31 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
32 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
33 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
34 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
35 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
36 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
37 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
38 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
39 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
40 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
41 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
42 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
43 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
44
45#define PORT_GP_27(bank, fn, sfx) \
46 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
47 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
48 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
49 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
50 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
51 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
52 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
53 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
54 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
55 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
56 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
57 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
58 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
59 PORT_GP_1(bank, 26, fn, sfx)
60
61#define CPU_ALL_PORT(fn, sfx) \
62 PORT_GP_32(0, fn, sfx), \
63 PORT_GP_32(1, fn, sfx), \
64 PORT_GP_32(2, fn, sfx), \
65 PORT_GP_32(3, fn, sfx), \
66 PORT_GP_27(4, fn, sfx)
67
68#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
69
70#define _GP_GPIO(bank, pin, _name, sfx) \
71 [RCAR_GP_PIN(bank, pin)] = { \
72 .name = __stringify(_name), \
73 .enum_id = _name##_DATA, \
74 }
75
76#define _GP_DATA(bank, pin, name, sfx) \
77 PINMUX_DATA(name##_DATA, name##_FN)
78
79#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
80#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
81#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
82
83#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn)
84#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
85#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
86#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
87
88enum {
89 PINMUX_RESERVED = 0,
90
91 PINMUX_DATA_BEGIN,
92 GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
93 PINMUX_DATA_END,
94
95 PINMUX_FUNCTION_BEGIN,
96 GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
97
98 /* GPSR0 */
99 FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2,
100 FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1,
101 FN_A2, FN_A3, FN_IP0_15, FN_IP0_16,
102 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20,
103 FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24,
104 FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28,
105 FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1,
106 FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11,
107
108 /* GPSR1 */
109 FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25,
110 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6,
111 FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17,
112 FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2,
113 FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13,
114 FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24,
115 FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30,
116 FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4,
117
118 /* GPSR2 */
119 FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11,
120 FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21,
121 FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0,
122 FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7,
123 FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13,
124 FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
125 FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29,
126 FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7,
127
128 /* GPSR3 */
129 FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10,
130 FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16,
131 FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22,
132 FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30,
133 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6,
134 FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
135 FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29,
136 FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9,
137
138 /* GPSR4 */
139 FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19,
140 FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0,
141 FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12,
142 FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24,
143 FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6,
144 FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19,
145 FN_IP10_24_22, FN_AVS1, FN_AVS2,
146
147 /* IPSR0 */
148 FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0,
149 FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B,
150 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C,
151 FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A,
152 FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A,
153 FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0,
154 FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5,
155 FN_A6, FN_A7, FN_A8, FN_A9,
156 FN_A10, FN_A11, FN_A12, FN_A13,
157 FN_A14, FN_A15, FN_A16, FN_A17,
158 FN_A18, FN_A19,
159
160 /* IPSR1 */
161 FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B,
162 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
163 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
164 FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24,
165 FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A,
166 FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A,
167 FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT,
168 FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B,
169 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
170 FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR,
171 FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0,
172 FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1,
173 FN_MMC_D4,
174
175 /* IPSR2 */
176 FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2,
177 FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3,
178 FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4,
179 FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A,
180 FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A,
181 FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0,
182 FN_PWM0_C, FN_D0, FN_D1, FN_D2,
183 FN_D3, FN_D4, FN_D5, FN_D6,
184 FN_D7, FN_D8, FN_D9, FN_D10,
185 FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK,
186 FN_IRQ1_A,
187
188 /* IPSR3 */
189 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
190 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
191 FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B,
192 FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A,
193 FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A,
194 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
195 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B,
196 FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0,
197 FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2,
198 FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4,
199 FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3,
200 FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
201 FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3,
202 FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5,
203 FN_DU0_DR6, FN_LCDOUT6,
204
205 /* IPSR4 */
206 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
207 FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D,
208 FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9,
209 FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D,
210 FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10,
211 FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12,
212 FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B,
213 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7,
214 FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B,
215 FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6,
216 FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B,
217 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
218 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A,
219 FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2,
220 FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19,
221 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20,
222
223 /* IPSR5 */
224 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B,
225 FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B,
226 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN,
227 FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK,
228 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A,
229 FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
230 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
231 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
232 FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP,
233 FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK,
234 FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB,
235 FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D,
236 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
237 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
238 FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B,
239 FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B,
240 FN_RX2_A, FN_CAN0_RX_B,
241
242 /* IPSR6 */
243 FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B,
244 FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B,
245 FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5,
246 FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5,
247 FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8,
248 FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9,
249 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
250 FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
251 FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12,
252 FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13,
253 FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
254 FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0,
255 FN_ARM_TRACEDATA_15,
256 FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST,
257 FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK,
258 FN_SD0_DAT2, FN_SUB_TDI,
259
260 /* IPSR7 */
261 FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A,
262 FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A,
263 FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A,
264 FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A,
265 FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC,
266 FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C,
267 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C,
268 FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A,
269 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
270 FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B,
271 FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A,
272 FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2,
273 FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B,
274
275 /* IPSR8 */
276 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
277 FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0,
278 FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1,
279 FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2,
280 FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3,
281 FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4,
282 FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5,
283 FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B,
284 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A,
285 FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
286 FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4,
287 FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B,
288 FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B,
289
290 /* IPSR9 */
291 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
292 FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7,
293 FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK,
294 FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A,
295 FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2,
296 FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7,
297 FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV,
298 FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN,
299 FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER,
300 FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A,
301 FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C,
302 FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A,
303 FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C,
304 FN_RX2_D, FN_SCL2_C,
305
306 /* IPSR10 */
307 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1,
308 FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A,
309 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1,
310 FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP,
311 FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A,
312 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
313 FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A,
314 FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B,
315 FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B,
316 FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A,
317 FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B,
318 FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B,
319 FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C,
320
321 /* SEL */
322 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
323 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
324 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
325 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
326 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
327 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
328 FN_SEL_SSI2_A, FN_SEL_SSI2_B,
329 FN_SEL_SSI1_A, FN_SEL_SSI1_B,
330 FN_SEL_VI1_A, FN_SEL_VI1_B,
331 FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D,
332 FN_SEL_SD2_A, FN_SEL_SD2_B,
333 FN_SEL_SD1_A, FN_SEL_SD1_B,
334 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
335 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C,
336 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
337 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
338 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
339 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
340 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
341 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
342 FN_SEL_CAN1_A, FN_SEL_CAN1_B,
343 FN_SEL_CAN0_A, FN_SEL_CAN0_B,
344 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
345 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
346 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
347 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
348 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C,
349 FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D,
350 FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C,
351 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
352 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
353 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
354 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
355 FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C,
356 FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C,
357 FN_SEL_I2C1_A, FN_SEL_I2C1_B,
358 PINMUX_FUNCTION_END,
359
360 PINMUX_MARK_BEGIN,
361
362 /* GPSR0 */
363 PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK,
364
365 /* GPSR1 */
366 WE0_MARK,
367
368 /* GPSR2 */
369 AUDIO_CLKA_MARK,
370 AUDIO_CLKB_MARK,
371
372 /* GPSR3 */
373 SSI_SCK34_MARK,
374
375 /* GPSR4 */
376 AVS1_MARK,
377 AVS2_MARK,
378
379 VI0_R0_C_MARK, /* see GPIO_FN_VI0_R0_A */
380 VI0_R1_C_MARK, /* see GPIO_FN_VI0_R1_A */
381 VI0_R2_C_MARK, /* see GPIO_FN_VI0_R2_A */
382 /* VI0_R3_C_MARK, see GPIO_FN_VI0_R3_A */
383 VI0_R4_C_MARK, /* see GPIO_FN_VI0_R4_A */
384 VI0_R5_C_MARK, /* see GPIO_FN_VI0_R5_A */
385
386 VI0_R0_D_MARK, /* see GPIO_FN_VI0_R0_B */
387 VI0_R1_D_MARK, /* see GPIO_FN_VI0_R1_B */
388 VI0_R2_D_MARK, /* see GPIO_FN_VI0_R2_B */
389 VI0_R3_D_MARK, /* see GPIO_FN_VI0_R3_B */
390 VI0_R4_D_MARK, /* see GPIO_FN_VI0_R4_B */
391 VI0_R5_D_MARK, /* see GPIO_FN_VI0_R5_B */
392
393 /* IPSR0 */
394 PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK,
395 ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK,
396 TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK,
397 GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK,
398 SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK,
399 ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK,
400 MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK,
401 A4_MARK, A5_MARK, A6_MARK, A7_MARK,
402 A8_MARK, A9_MARK, A10_MARK, A11_MARK,
403 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
404 A16_MARK, A17_MARK, A18_MARK, A19_MARK,
405
406 /* IPSR1 */
407 A20_MARK, HSPI_CS1_B_MARK, A21_MARK,
408 HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK,
409 RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK,
410 TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK,
411 SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK,
412 HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK,
413 MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK,
414 RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK,
415 HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK,
416 HSPI_RX1_B_MARK, SSI_SCK1_B_MARK,
417 ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK,
418 MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK,
419 ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK,
420 TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK,
421
422 /* IPSR2 */
423 SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK,
424 SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK,
425 SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK,
426 EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK,
427 MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK,
428 DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK,
429 DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK,
430 D1_MARK, D2_MARK, D3_MARK, D4_MARK,
431 D5_MARK, D6_MARK, D7_MARK, D8_MARK,
432 D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK,
433 IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK,
434
435 /* IPSR3 */
436 MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK,
437 MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK,
438 SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK,
439 CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK,
440 TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK,
441 RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK,
442 SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK,
443 HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK,
444 HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK,
445 DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK,
446 SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK,
447 SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK,
448 ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK,
449 TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
450 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
451 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
452
453 /* IPSR4 */
454 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
455 AUDATA4_MARK, ARM_TRACEDATA_4_MARK,
456 TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK,
457 LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK,
458 RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK,
459 LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK,
460 LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK,
461 TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK,
462 DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK,
463 VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK,
464 ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK,
465 ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK,
466 VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK,
467 ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK,
468 TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
469 VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK,
470 DU0_DB4_MARK, LCDOUT20_MARK,
471
472 /* IPSR5 */
473 VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK,
474 DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK,
475 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK,
476 QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
477 QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK,
478 AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK,
479 DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
480 DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
481 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
482 QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK,
483 DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK,
484 BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK,
485 AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK,
486 SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK,
487 TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK,
488 RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK,
489 SSI_SCK2_A_MARK, HSPI_CS0_B_MARK,
490 TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK,
491 HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK,
492
493 /* IPSR6 */
494 SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK,
495 CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK,
496 BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK,
497 HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK,
498 RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK,
499 RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK,
500 SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
501 SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK,
502 SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK,
503 TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
504 SSI_SDATA2_MARK, HSPI_CS2_A_MARK,
505 ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK,
506 ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK,
507 SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK,
508 SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK,
509 SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK,
510 SD0_DAT2_MARK, SUB_TDI_MARK,
511
512 /* IPSR7 */
513 SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK,
514 SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK,
515 HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK,
516 HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK,
517 HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK,
518 VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK,
519 TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK,
520 IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK,
521 CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK,
522 VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK,
523 RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK,
524 VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK,
525 TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK,
526 DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK,
527
528 /* IPSR8 */
529 VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK,
530 HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK,
531 DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK,
532 DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK,
533 DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK,
534 DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK,
535 DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK,
536 DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK,
537 VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK,
538 PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK,
539 RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK,
540 DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK,
541 VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK,
542
543 /* IPSR9 */
544 VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK,
545 DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK,
546 VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK,
547 VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK,
548 VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK,
549 PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK,
550 DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK,
551 ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK,
552 VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK,
553 TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK,
554 IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK,
555 DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK,
556 BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK,
557 DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK,
558 RX2_D_MARK, SCL2_C_MARK,
559
560 /* IPSR10 */
561 SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK,
562 ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK,
563 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK,
564 ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK,
565 DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK,
566 CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK,
567 ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK,
568 PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK,
569 DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK,
570 GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK,
571 DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK,
572 GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK,
573 EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK,
574 REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK,
575 EX_WAIT2_B_MARK, DACK0_B_MARK,
576 HSPI_TX2_B_MARK, CAN_CLK_C_MARK,
577
578 PINMUX_MARK_END,
579};
580
581static const pinmux_enum_t pinmux_data[] = {
582 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
583
584 PINMUX_DATA(PENC0_MARK, FN_PENC0),
585 PINMUX_DATA(PENC1_MARK, FN_PENC1),
586 PINMUX_DATA(A1_MARK, FN_A1),
587 PINMUX_DATA(A2_MARK, FN_A2),
588 PINMUX_DATA(A3_MARK, FN_A3),
589 PINMUX_DATA(WE0_MARK, FN_WE0),
590 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
591 PINMUX_DATA(AUDIO_CLKB_MARK, FN_AUDIO_CLKB),
592 PINMUX_DATA(SSI_SCK34_MARK, FN_SSI_SCK34),
593 PINMUX_DATA(AVS1_MARK, FN_AVS1),
594 PINMUX_DATA(AVS2_MARK, FN_AVS2),
595
596 /* IPSR0 */
597 PINMUX_IPSR_DATA(IP0_1_0, PRESETOUT),
598 PINMUX_IPSR_DATA(IP0_1_0, PWM1),
599
600 PINMUX_IPSR_DATA(IP0_4_2, AUDATA0),
601 PINMUX_IPSR_DATA(IP0_4_2, ARM_TRACEDATA_0),
602 PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C),
603 PINMUX_IPSR_DATA(IP0_4_2, USB_OVC0),
604 PINMUX_IPSR_DATA(IP0_4_2, TX2_E),
605 PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B),
606
607 PINMUX_IPSR_DATA(IP0_7_5, AUDATA1),
608 PINMUX_IPSR_DATA(IP0_7_5, ARM_TRACEDATA_1),
609 PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C),
610 PINMUX_IPSR_DATA(IP0_7_5, USB_OVC1),
611 PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E),
612 PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B),
613
614 PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A),
615 PINMUX_IPSR_DATA(IP0_11_8, MMC_D2),
616 PINMUX_IPSR_DATA(IP0_11_8, BS),
617 PINMUX_IPSR_DATA(IP0_11_8, ATADIR0_A),
618 PINMUX_IPSR_DATA(IP0_11_8, SDSELF_A),
619 PINMUX_IPSR_DATA(IP0_11_8, PWM4_B),
620
621 PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A),
622 PINMUX_IPSR_DATA(IP0_14_12, MMC_D3),
623 PINMUX_IPSR_DATA(IP0_14_12, A0),
624 PINMUX_IPSR_DATA(IP0_14_12, ATAG0_A),
625 PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B),
626
627 PINMUX_IPSR_DATA(IP0_15, A4),
628 PINMUX_IPSR_DATA(IP0_16, A5),
629 PINMUX_IPSR_DATA(IP0_17, A6),
630 PINMUX_IPSR_DATA(IP0_18, A7),
631 PINMUX_IPSR_DATA(IP0_19, A8),
632 PINMUX_IPSR_DATA(IP0_20, A9),
633 PINMUX_IPSR_DATA(IP0_21, A10),
634 PINMUX_IPSR_DATA(IP0_22, A11),
635 PINMUX_IPSR_DATA(IP0_23, A12),
636 PINMUX_IPSR_DATA(IP0_24, A13),
637 PINMUX_IPSR_DATA(IP0_25, A14),
638 PINMUX_IPSR_DATA(IP0_26, A15),
639 PINMUX_IPSR_DATA(IP0_27, A16),
640 PINMUX_IPSR_DATA(IP0_28, A17),
641 PINMUX_IPSR_DATA(IP0_29, A18),
642 PINMUX_IPSR_DATA(IP0_30, A19),
643
644 /* IPSR1 */
645 PINMUX_IPSR_DATA(IP1_0, A20),
646 PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B),
647
648 PINMUX_IPSR_DATA(IP1_1, A21),
649 PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B),
650
651 PINMUX_IPSR_DATA(IP1_4_2, A22),
652 PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B),
653 PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B),
654 PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A),
655
656 PINMUX_IPSR_DATA(IP1_7_5, A23),
657 PINMUX_IPSR_DATA(IP1_7_5, HTX0_B),
658 PINMUX_IPSR_DATA(IP1_7_5, TX2_B),
659 PINMUX_IPSR_DATA(IP1_7_5, DACK2_A),
660 PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A),
661
662 PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A),
663 PINMUX_IPSR_DATA(IP1_10_8, MMC_D6),
664 PINMUX_IPSR_DATA(IP1_10_8, A24),
665 PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A),
666 PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B),
667 PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A),
668
669 PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A),
670 PINMUX_IPSR_DATA(IP1_14_11, MMC_D7),
671 PINMUX_IPSR_DATA(IP1_14_11, A25),
672 PINMUX_IPSR_DATA(IP1_14_11, DACK1_A),
673 PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B),
674 PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C),
675 PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A),
676
677 PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT),
678 PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B),
679 PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B),
680
681 PINMUX_IPSR_NOGP(IP1_17, CS0),
682 PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B),
683
684 PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B),
685 PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B),
686 PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26),
687 PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A),
688 PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B),
689
690 PINMUX_IPSR_DATA(IP1_23_21, MMC_D5),
691 PINMUX_IPSR_DATA(IP1_23_21, ATADIR0_B),
692 PINMUX_IPSR_DATA(IP1_23_21, RD_WR),
693
694 PINMUX_IPSR_DATA(IP1_24, WE1),
695 PINMUX_IPSR_DATA(IP1_24, ATAWR0_B),
696
697 PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B),
698 PINMUX_IPSR_DATA(IP1_27_25, EX_CS0),
699 PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A),
700 PINMUX_IPSR_DATA(IP1_27_25, TX3_C),
701 PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A),
702
703 PINMUX_IPSR_DATA(IP1_29_28, EX_CS1),
704 PINMUX_IPSR_DATA(IP1_29_28, MMC_D4),
705
706 /* IPSR2 */
707 PINMUX_IPSR_DATA(IP2_2_0, SD1_CLK_A),
708 PINMUX_IPSR_DATA(IP2_2_0, MMC_CLK),
709 PINMUX_IPSR_DATA(IP2_2_0, ATACS00),
710 PINMUX_IPSR_DATA(IP2_2_0, EX_CS2),
711
712 PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A),
713 PINMUX_IPSR_DATA(IP2_5_3, MMC_CMD),
714 PINMUX_IPSR_DATA(IP2_5_3, ATACS10),
715 PINMUX_IPSR_DATA(IP2_5_3, EX_CS3),
716
717 PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A),
718 PINMUX_IPSR_DATA(IP2_8_6, MMC_D0),
719 PINMUX_IPSR_DATA(IP2_8_6, ATARD0),
720 PINMUX_IPSR_DATA(IP2_8_6, EX_CS4),
721 PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A),
722
723 PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A),
724 PINMUX_IPSR_DATA(IP2_11_9, MMC_D1),
725 PINMUX_IPSR_DATA(IP2_11_9, ATAWR0_A),
726 PINMUX_IPSR_DATA(IP2_11_9, EX_CS5),
727 PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A),
728
729 PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A),
730 PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A),
731
732 PINMUX_IPSR_DATA(IP2_16_14, DACK0),
733 PINMUX_IPSR_DATA(IP2_16_14, TX3_A),
734 PINMUX_IPSR_DATA(IP2_16_14, DRACK0),
735
736 PINMUX_IPSR_DATA(IP2_17, EX_WAIT0),
737 PINMUX_IPSR_DATA(IP2_17, PWM0_C),
738
739 PINMUX_IPSR_NOGP(IP2_18, D0),
740 PINMUX_IPSR_NOGP(IP2_19, D1),
741 PINMUX_IPSR_NOGP(IP2_20, D2),
742 PINMUX_IPSR_NOGP(IP2_21, D3),
743 PINMUX_IPSR_NOGP(IP2_22, D4),
744 PINMUX_IPSR_NOGP(IP2_23, D5),
745 PINMUX_IPSR_NOGP(IP2_24, D6),
746 PINMUX_IPSR_NOGP(IP2_25, D7),
747 PINMUX_IPSR_NOGP(IP2_26, D8),
748 PINMUX_IPSR_NOGP(IP2_27, D9),
749 PINMUX_IPSR_NOGP(IP2_28, D10),
750 PINMUX_IPSR_NOGP(IP2_29, D11),
751
752 PINMUX_IPSR_DATA(IP2_30, RD_WR_B),
753 PINMUX_IPSR_DATA(IP2_30, IRQ0),
754
755 PINMUX_IPSR_DATA(IP2_31, MLB_CLK),
756 PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A),
757
758 /* IPSR3 */
759 PINMUX_IPSR_DATA(IP3_1_0, MLB_SIG),
760 PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B),
761 PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A),
762 PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A),
763
764 PINMUX_IPSR_DATA(IP3_4_2, MLB_DAT),
765 PINMUX_IPSR_DATA(IP3_4_2, TX5_B),
766 PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A),
767 PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A),
768 PINMUX_IPSR_DATA(IP3_4_2, SDSELF_B),
769
770 PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B),
771 PINMUX_IPSR_DATA(IP3_7_5, SCIF_CLK),
772 PINMUX_IPSR_DATA(IP3_7_5, AUDIO_CLKOUT_B),
773 PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B),
774 PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B),
775
776 PINMUX_IPSR_DATA(IP3_9_8, SD1_CLK_B),
777 PINMUX_IPSR_DATA(IP3_9_8, HTX0_A),
778 PINMUX_IPSR_DATA(IP3_9_8, TX0_A),
779
780 PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B),
781 PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A),
782 PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A),
783
784 PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B),
785 PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A),
786 PINMUX_IPSR_DATA(IP3_15_13, SCK0),
787 PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B),
788
789 PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B),
790 PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A),
791 PINMUX_IPSR_DATA(IP3_18_16, CTS0),
792
793 PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B),
794 PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A),
795 PINMUX_IPSR_DATA(IP3_20_19, RTS0),
796
797 PINMUX_IPSR_DATA(IP3_23_21, SSI_SCK4),
798 PINMUX_IPSR_DATA(IP3_23_21, DU0_DR0),
799 PINMUX_IPSR_DATA(IP3_23_21, LCDOUT0),
800 PINMUX_IPSR_DATA(IP3_23_21, AUDATA2),
801 PINMUX_IPSR_DATA(IP3_23_21, ARM_TRACEDATA_2),
802 PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C),
803 PINMUX_IPSR_DATA(IP3_23_21, ADICHS1),
804 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B),
805
806 PINMUX_IPSR_DATA(IP3_26_24, SSI_WS4),
807 PINMUX_IPSR_DATA(IP3_26_24, DU0_DR1),
808 PINMUX_IPSR_DATA(IP3_26_24, LCDOUT1),
809 PINMUX_IPSR_DATA(IP3_26_24, AUDATA3),
810 PINMUX_IPSR_DATA(IP3_26_24, ARM_TRACEDATA_3),
811 PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C),
812 PINMUX_IPSR_DATA(IP3_26_24, ADICHS2),
813 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B),
814
815 PINMUX_IPSR_DATA(IP3_27, DU0_DR2),
816 PINMUX_IPSR_DATA(IP3_27, LCDOUT2),
817
818 PINMUX_IPSR_DATA(IP3_28, DU0_DR3),
819 PINMUX_IPSR_DATA(IP3_28, LCDOUT3),
820
821 PINMUX_IPSR_DATA(IP3_29, DU0_DR4),
822 PINMUX_IPSR_DATA(IP3_29, LCDOUT4),
823
824 PINMUX_IPSR_DATA(IP3_30, DU0_DR5),
825 PINMUX_IPSR_DATA(IP3_30, LCDOUT5),
826
827 PINMUX_IPSR_DATA(IP3_31, DU0_DR6),
828 PINMUX_IPSR_DATA(IP3_31, LCDOUT6),
829
830 /* IPSR4 */
831 PINMUX_IPSR_DATA(IP4_0, DU0_DR7),
832 PINMUX_IPSR_DATA(IP4_0, LCDOUT7),
833
834 PINMUX_IPSR_DATA(IP4_3_1, DU0_DG0),
835 PINMUX_IPSR_DATA(IP4_3_1, LCDOUT8),
836 PINMUX_IPSR_DATA(IP4_3_1, AUDATA4),
837 PINMUX_IPSR_DATA(IP4_3_1, ARM_TRACEDATA_4),
838 PINMUX_IPSR_DATA(IP4_3_1, TX1_D),
839 PINMUX_IPSR_DATA(IP4_3_1, CAN0_TX_A),
840 PINMUX_IPSR_DATA(IP4_3_1, ADICHS0),
841
842 PINMUX_IPSR_DATA(IP4_6_4, DU0_DG1),
843 PINMUX_IPSR_DATA(IP4_6_4, LCDOUT9),
844 PINMUX_IPSR_DATA(IP4_6_4, AUDATA5),
845 PINMUX_IPSR_DATA(IP4_6_4, ARM_TRACEDATA_5),
846 PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D),
847 PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A),
848 PINMUX_IPSR_DATA(IP4_6_4, ADIDATA),
849
850 PINMUX_IPSR_DATA(IP4_7, DU0_DG2),
851 PINMUX_IPSR_DATA(IP4_7, LCDOUT10),
852
853 PINMUX_IPSR_DATA(IP4_8, DU0_DG3),
854 PINMUX_IPSR_DATA(IP4_8, LCDOUT11),
855
856 PINMUX_IPSR_DATA(IP4_10_9, DU0_DG4),
857 PINMUX_IPSR_DATA(IP4_10_9, LCDOUT12),
858 PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B),
859
860 PINMUX_IPSR_DATA(IP4_12_11, DU0_DG5),
861 PINMUX_IPSR_DATA(IP4_12_11, LCDOUT13),
862 PINMUX_IPSR_DATA(IP4_12_11, TX0_B),
863
864 PINMUX_IPSR_DATA(IP4_14_13, DU0_DG6),
865 PINMUX_IPSR_DATA(IP4_14_13, LCDOUT14),
866 PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A),
867
868 PINMUX_IPSR_DATA(IP4_16_15, DU0_DG7),
869 PINMUX_IPSR_DATA(IP4_16_15, LCDOUT15),
870 PINMUX_IPSR_DATA(IP4_16_15, TX4_A),
871
872 PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B),
873 PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */
874 PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */
875 PINMUX_IPSR_DATA(IP4_20_17, DU0_DB0),
876 PINMUX_IPSR_DATA(IP4_20_17, LCDOUT16),
877 PINMUX_IPSR_DATA(IP4_20_17, AUDATA6),
878 PINMUX_IPSR_DATA(IP4_20_17, ARM_TRACEDATA_6),
879 PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A),
880 PINMUX_IPSR_DATA(IP4_20_17, PWM0_A),
881 PINMUX_IPSR_DATA(IP4_20_17, ADICLK),
882 PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B),
883
884 PINMUX_IPSR_DATA(IP4_24_21, AUDIO_CLKC),
885 PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */
886 PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */
887 PINMUX_IPSR_DATA(IP4_24_21, DU0_DB1),
888 PINMUX_IPSR_DATA(IP4_24_21, LCDOUT17),
889 PINMUX_IPSR_DATA(IP4_24_21, AUDATA7),
890 PINMUX_IPSR_DATA(IP4_24_21, ARM_TRACEDATA_7),
891 PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A),
892 PINMUX_IPSR_DATA(IP4_24_21, ADICS_SAMP),
893 PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B),
894
895 PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */
896 PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */
897 PINMUX_IPSR_DATA(IP4_26_25, DU0_DB2),
898 PINMUX_IPSR_DATA(IP4_26_25, LCDOUT18),
899
900 PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B),
901 PINMUX_IPSR_DATA(IP4_28_27, DU0_DB3),
902 PINMUX_IPSR_DATA(IP4_28_27, LCDOUT19),
903
904 PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */
905 PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */
906 PINMUX_IPSR_DATA(IP4_30_29, DU0_DB4),
907 PINMUX_IPSR_DATA(IP4_30_29, LCDOUT20),
908
909 /* IPSR5 */
910 PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */
911 PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */
912 PINMUX_IPSR_DATA(IP5_1_0, DU0_DB5),
913 PINMUX_IPSR_DATA(IP5_1_0, LCDOUT21),
914
915 PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B),
916 PINMUX_IPSR_DATA(IP5_3_2, DU0_DB6),
917 PINMUX_IPSR_DATA(IP5_3_2, LCDOUT22),
918
919 PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B),
920 PINMUX_IPSR_DATA(IP5_5_4, DU0_DB7),
921 PINMUX_IPSR_DATA(IP5_5_4, LCDOUT23),
922
923 PINMUX_IPSR_DATA(IP5_6, DU0_DOTCLKIN),
924 PINMUX_IPSR_DATA(IP5_6, QSTVA_QVS),
925
926 PINMUX_IPSR_DATA(IP5_7, DU0_DOTCLKO_UT0),
927 PINMUX_IPSR_DATA(IP5_7, QCLK),
928
929 PINMUX_IPSR_DATA(IP5_9_8, DU0_DOTCLKO_UT1),
930 PINMUX_IPSR_DATA(IP5_9_8, QSTVB_QVE),
931 PINMUX_IPSR_DATA(IP5_9_8, AUDIO_CLKOUT_A),
932 PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C),
933
934 PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B),
935 PINMUX_IPSR_DATA(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC),
936 PINMUX_IPSR_DATA(IP5_11_10, QSTH_QHS),
937
938 PINMUX_IPSR_DATA(IP5_12, DU0_EXVSYNC_DU0_VSYNC),
939 PINMUX_IPSR_DATA(IP5_12, QSTB_QHE),
940
941 PINMUX_IPSR_DATA(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE),
942 PINMUX_IPSR_DATA(IP5_14_13, QCPV_QDE),
943 PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D),
944
945 PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A),
946 PINMUX_IPSR_DATA(IP5_17_15, DU0_DISP),
947 PINMUX_IPSR_DATA(IP5_17_15, QPOLA),
948 PINMUX_IPSR_DATA(IP5_17_15, AUDCK),
949 PINMUX_IPSR_DATA(IP5_17_15, ARM_TRACECLK),
950 PINMUX_IPSR_DATA(IP5_17_15, BPFCLK_D),
951
952 PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A),
953 PINMUX_IPSR_DATA(IP5_20_18, DU0_CDE),
954 PINMUX_IPSR_DATA(IP5_20_18, QPOLB),
955 PINMUX_IPSR_DATA(IP5_20_18, AUDSYNC),
956 PINMUX_IPSR_DATA(IP5_20_18, ARM_TRACECTL),
957 PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D),
958
959 PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B),
960 PINMUX_IPSR_DATA(IP5_22_21, SSI_SCK78),
961 PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B),
962 PINMUX_IPSR_DATA(IP5_22_21, TX1_B),
963
964 PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B),
965 PINMUX_IPSR_DATA(IP5_25_23, SSI_WS78),
966 PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B),
967 PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B),
968 PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D),
969
970 PINMUX_IPSR_DATA(IP5_28_26, SSI_SDATA8),
971 PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A),
972 PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B),
973 PINMUX_IPSR_DATA(IP5_28_26, TX2_A),
974 PINMUX_IPSR_DATA(IP5_28_26, CAN0_TX_B),
975
976 PINMUX_IPSR_DATA(IP5_30_29, SSI_SDATA7),
977 PINMUX_IPSR_DATA(IP5_30_29, HSPI_TX0_B),
978 PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A),
979 PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B),
980
981 /* IPSR6 */
982 PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK6),
983 PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A),
984 PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B),
985 PINMUX_IPSR_DATA(IP6_1_0, CAN1_TX_B),
986
987 PINMUX_IPSR_DATA(IP6_4_2, SSI_WS6),
988 PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A),
989 PINMUX_IPSR_DATA(IP6_4_2, BPFCLK_B),
990 PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B),
991
992 PINMUX_IPSR_DATA(IP6_6_5, SSI_SDATA6),
993 PINMUX_IPSR_DATA(IP6_6_5, HSPI_TX2_A),
994 PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B),
995
996 PINMUX_IPSR_DATA(IP6_7, SSI_SCK5),
997 PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C),
998
999 PINMUX_IPSR_DATA(IP6_8, SSI_WS5),
1000 PINMUX_IPSR_DATA(IP6_8, TX4_C),
1001
1002 PINMUX_IPSR_DATA(IP6_9, SSI_SDATA5),
1003 PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D),
1004
1005 PINMUX_IPSR_DATA(IP6_10, SSI_WS34),
1006 PINMUX_IPSR_DATA(IP6_10, ARM_TRACEDATA_8),
1007
1008 PINMUX_IPSR_DATA(IP6_12_11, SSI_SDATA4),
1009 PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A),
1010 PINMUX_IPSR_DATA(IP6_12_11, ARM_TRACEDATA_9),
1011
1012 PINMUX_IPSR_DATA(IP6_13, SSI_SDATA3),
1013 PINMUX_IPSR_DATA(IP6_13, ARM_TRACEDATA_10),
1014
1015 PINMUX_IPSR_DATA(IP6_15_14, SSI_SCK012),
1016 PINMUX_IPSR_DATA(IP6_15_14, ARM_TRACEDATA_11),
1017 PINMUX_IPSR_DATA(IP6_15_14, TX0_D),
1018
1019 PINMUX_IPSR_DATA(IP6_16, SSI_WS012),
1020 PINMUX_IPSR_DATA(IP6_16, ARM_TRACEDATA_12),
1021
1022 PINMUX_IPSR_DATA(IP6_18_17, SSI_SDATA2),
1023 PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A),
1024 PINMUX_IPSR_DATA(IP6_18_17, ARM_TRACEDATA_13),
1025 PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A),
1026
1027 PINMUX_IPSR_DATA(IP6_20_19, SSI_SDATA1),
1028 PINMUX_IPSR_DATA(IP6_20_19, ARM_TRACEDATA_14),
1029 PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A),
1030 PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A),
1031
1032 PINMUX_IPSR_DATA(IP6_21, SSI_SDATA0),
1033 PINMUX_IPSR_DATA(IP6_21, ARM_TRACEDATA_15),
1034
1035 PINMUX_IPSR_DATA(IP6_23_22, SD0_CLK),
1036 PINMUX_IPSR_DATA(IP6_23_22, SUB_TDO),
1037
1038 PINMUX_IPSR_DATA(IP6_25_24, SD0_CMD),
1039 PINMUX_IPSR_DATA(IP6_25_24, SUB_TRST),
1040
1041 PINMUX_IPSR_DATA(IP6_27_26, SD0_DAT0),
1042 PINMUX_IPSR_DATA(IP6_27_26, SUB_TMS),
1043
1044 PINMUX_IPSR_DATA(IP6_29_28, SD0_DAT1),
1045 PINMUX_IPSR_DATA(IP6_29_28, SUB_TCK),
1046
1047 PINMUX_IPSR_DATA(IP6_31_30, SD0_DAT2),
1048 PINMUX_IPSR_DATA(IP6_31_30, SUB_TDI),
1049
1050 /* IPSR7 */
1051 PINMUX_IPSR_DATA(IP7_1_0, SD0_DAT3),
1052 PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B),
1053
1054 PINMUX_IPSR_DATA(IP7_3_2, SD0_CD),
1055 PINMUX_IPSR_DATA(IP7_3_2, TX5_A),
1056
1057 PINMUX_IPSR_DATA(IP7_5_4, SD0_WP),
1058 PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A),
1059
1060 PINMUX_IPSR_DATA(IP7_8_6, VI1_CLKENB),
1061 PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A),
1062 PINMUX_IPSR_DATA(IP7_8_6, HTX1_A),
1063 PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C),
1064
1065 PINMUX_IPSR_DATA(IP7_11_9, VI1_FIELD),
1066 PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A),
1067 PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A),
1068 PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C),
1069
1070 PINMUX_IPSR_DATA(IP7_14_12, VI1_HSYNC),
1071 PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A),
1072 PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A),
1073 PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A),
1074 PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C),
1075
1076 PINMUX_IPSR_DATA(IP7_17_15, VI1_VSYNC),
1077 PINMUX_IPSR_DATA(IP7_17_15, HSPI_TX0),
1078 PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A),
1079 PINMUX_IPSR_DATA(IP7_17_15, BPFCLK_A),
1080 PINMUX_IPSR_DATA(IP7_17_15, TX1_C),
1081
1082 PINMUX_IPSR_DATA(IP7_20_18, TCLK0),
1083 PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A),
1084 PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A),
1085 PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C),
1086 PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C),
1087 PINMUX_IPSR_DATA(IP7_20_18, SPEEDIN),
1088
1089 PINMUX_IPSR_DATA(IP7_21, VI0_CLK),
1090 PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A),
1091
1092 PINMUX_IPSR_DATA(IP7_24_22, VI0_CLKENB),
1093 PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B),
1094 PINMUX_IPSR_DATA(IP7_24_22, VI1_DATA0),
1095 PINMUX_IPSR_DATA(IP7_24_22, DU1_DG6),
1096 PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A),
1097 PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B),
1098
1099 PINMUX_IPSR_DATA(IP7_28_25, VI0_FIELD),
1100 PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B),
1101 PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */
1102 PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */
1103 PINMUX_IPSR_DATA(IP7_28_25, VI1_DATA1),
1104 PINMUX_IPSR_DATA(IP7_28_25, DU1_DG7),
1105 PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A),
1106 PINMUX_IPSR_DATA(IP7_28_25, TX4_B),
1107
1108 PINMUX_IPSR_DATA(IP7_31_29, VI0_HSYNC),
1109 PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B),
1110 PINMUX_IPSR_DATA(IP7_31_29, VI1_DATA2),
1111 PINMUX_IPSR_DATA(IP7_31_29, DU1_DR2),
1112 PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A),
1113 PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B),
1114
1115 /* IPSR8 */
1116 PINMUX_IPSR_DATA(IP8_2_0, VI0_VSYNC),
1117 PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B),
1118 PINMUX_IPSR_DATA(IP8_2_0, VI1_DATA3),
1119 PINMUX_IPSR_DATA(IP8_2_0, DU1_DR3),
1120 PINMUX_IPSR_DATA(IP8_2_0, HSPI_TX1_A),
1121 PINMUX_IPSR_DATA(IP8_2_0, TX3_B),
1122
1123 PINMUX_IPSR_DATA(IP8_5_3, VI0_DATA0_VI0_B0),
1124 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG2),
1125 PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B),
1126 PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D),
1127
1128 PINMUX_IPSR_DATA(IP8_8_6, VI0_DATA1_VI0_B1),
1129 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG3),
1130 PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B),
1131 PINMUX_IPSR_DATA(IP8_8_6, TX3_D),
1132
1133 PINMUX_IPSR_DATA(IP8_10_9, VI0_DATA2_VI0_B2),
1134 PINMUX_IPSR_DATA(IP8_10_9, DU1_DG4),
1135 PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C),
1136
1137 PINMUX_IPSR_DATA(IP8_13_11, VI0_DATA3_VI0_B3),
1138 PINMUX_IPSR_DATA(IP8_13_11, DU1_DG5),
1139 PINMUX_IPSR_DATA(IP8_13_11, TX1_A),
1140 PINMUX_IPSR_DATA(IP8_13_11, TX0_C),
1141
1142 PINMUX_IPSR_DATA(IP8_15_14, VI0_DATA4_VI0_B4),
1143 PINMUX_IPSR_DATA(IP8_15_14, DU1_DB2),
1144 PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A),
1145
1146 PINMUX_IPSR_DATA(IP8_18_16, VI0_DATA5_VI0_B5),
1147 PINMUX_IPSR_DATA(IP8_18_16, DU1_DB3),
1148 PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A),
1149 PINMUX_IPSR_DATA(IP8_18_16, PWM4),
1150 PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B),
1151
1152 PINMUX_IPSR_DATA(IP8_21_19, VI0_DATA6_VI0_G0),
1153 PINMUX_IPSR_DATA(IP8_21_19, DU1_DB4),
1154 PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A),
1155 PINMUX_IPSR_DATA(IP8_21_19, PWM5),
1156
1157 PINMUX_IPSR_DATA(IP8_23_22, VI0_DATA7_VI0_G1),
1158 PINMUX_IPSR_DATA(IP8_23_22, DU1_DB5),
1159 PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A),
1160
1161 PINMUX_IPSR_DATA(IP8_26_24, VI0_G2),
1162 PINMUX_IPSR_DATA(IP8_26_24, SD2_CLK_B),
1163 PINMUX_IPSR_DATA(IP8_26_24, VI1_DATA4),
1164 PINMUX_IPSR_DATA(IP8_26_24, DU1_DR4),
1165 PINMUX_IPSR_DATA(IP8_26_24, HTX1_B),
1166
1167 PINMUX_IPSR_DATA(IP8_29_27, VI0_G3),
1168 PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B),
1169 PINMUX_IPSR_DATA(IP8_29_27, VI1_DATA5),
1170 PINMUX_IPSR_DATA(IP8_29_27, DU1_DR5),
1171 PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B),
1172
1173 /* IPSR9 */
1174 PINMUX_IPSR_DATA(IP9_2_0, VI0_G4),
1175 PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B),
1176 PINMUX_IPSR_DATA(IP9_2_0, VI1_DATA6),
1177 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR6),
1178 PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B),
1179
1180 PINMUX_IPSR_DATA(IP9_5_3, VI0_G5),
1181 PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B),
1182 PINMUX_IPSR_DATA(IP9_5_3, VI1_DATA7),
1183 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR7),
1184 PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B),
1185
1186 PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */
1187 PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */
1188 PINMUX_IPSR_DATA(IP9_8_6, VI1_CLK),
1189 PINMUX_IPSR_DATA(IP9_8_6, ETH_REF_CLK),
1190 PINMUX_IPSR_DATA(IP9_8_6, DU1_DOTCLKIN),
1191
1192 PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */
1193 PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */
1194 PINMUX_IPSR_DATA(IP9_11_9, VI1_DATA8),
1195 PINMUX_IPSR_DATA(IP9_11_9, DU1_DB6),
1196 PINMUX_IPSR_DATA(IP9_11_9, ETH_TXD0),
1197 PINMUX_IPSR_DATA(IP9_11_9, PWM2),
1198 PINMUX_IPSR_DATA(IP9_11_9, TCLK1),
1199
1200 PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */
1201 PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */
1202 PINMUX_IPSR_DATA(IP9_14_12, VI1_DATA9),
1203 PINMUX_IPSR_DATA(IP9_14_12, DU1_DB7),
1204 PINMUX_IPSR_DATA(IP9_14_12, ETH_TXD1),
1205 PINMUX_IPSR_DATA(IP9_14_12, PWM3),
1206
1207 PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A),
1208 PINMUX_IPSR_DATA(IP9_17_15, ETH_CRS_DV),
1209 PINMUX_IPSR_DATA(IP9_17_15, IECLK),
1210 PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C),
1211
1212 PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */
1213 PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */
1214 PINMUX_IPSR_DATA(IP9_20_18, ETH_TX_EN),
1215 PINMUX_IPSR_DATA(IP9_20_18, IETX),
1216 PINMUX_IPSR_DATA(IP9_20_18, TX2_C),
1217
1218 PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */
1219 PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */
1220 PINMUX_IPSR_DATA(IP9_23_21, ETH_RX_ER),
1221 PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C),
1222 PINMUX_IPSR_DATA(IP9_23_21, IERX),
1223 PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C),
1224
1225 PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A),
1226 PINMUX_IPSR_DATA(IP9_26_24, DU1_DOTCLKOUT),
1227 PINMUX_IPSR_DATA(IP9_26_24, ETH_RXD0),
1228 PINMUX_IPSR_DATA(IP9_26_24, BPFCLK_C),
1229 PINMUX_IPSR_DATA(IP9_26_24, TX2_D),
1230 PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C),
1231
1232 PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A),
1233 PINMUX_IPSR_DATA(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC),
1234 PINMUX_IPSR_DATA(IP9_29_27, ETH_RXD1),
1235 PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C),
1236 PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D),
1237 PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C),
1238
1239 /* IPSR10 */
1240 PINMUX_IPSR_DATA(IP10_2_0, SD2_CLK_A),
1241 PINMUX_IPSR_DATA(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC),
1242 PINMUX_IPSR_DATA(IP10_2_0, ATARD1),
1243 PINMUX_IPSR_DATA(IP10_2_0, ETH_MDC),
1244 PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B),
1245
1246 PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A),
1247 PINMUX_IPSR_DATA(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1248 PINMUX_IPSR_DATA(IP10_5_3, ATAWR1),
1249 PINMUX_IPSR_DATA(IP10_5_3, ETH_MDIO),
1250 PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B),
1251
1252 PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A),
1253 PINMUX_IPSR_DATA(IP10_8_6, DU1_DISP),
1254 PINMUX_IPSR_DATA(IP10_8_6, ATACS01),
1255 PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B),
1256 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1257 PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A),
1258
1259 PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A),
1260 PINMUX_IPSR_DATA(IP10_12_9, DU1_CDE),
1261 PINMUX_IPSR_DATA(IP10_12_9, ATACS11),
1262 PINMUX_IPSR_DATA(IP10_12_9, DACK1_B),
1263 PINMUX_IPSR_DATA(IP10_12_9, ETH_MAGIC),
1264 PINMUX_IPSR_DATA(IP10_12_9, CAN1_TX_A),
1265 PINMUX_IPSR_DATA(IP10_12_9, PWM6),
1266
1267 PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A),
1268 PINMUX_IPSR_DATA(IP10_15_13, VI1_DATA12),
1269 PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B),
1270 PINMUX_IPSR_DATA(IP10_15_13, ATADIR1),
1271 PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B),
1272 PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B),
1273
1274 PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A),
1275 PINMUX_IPSR_DATA(IP10_18_16, VI1_DATA13),
1276 PINMUX_IPSR_DATA(IP10_18_16, DACK2_B),
1277 PINMUX_IPSR_DATA(IP10_18_16, ATAG1),
1278 PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B),
1279 PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B),
1280
1281 PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A),
1282 PINMUX_IPSR_DATA(IP10_21_19, VI1_DATA14),
1283 PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B),
1284 PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B),
1285 PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B),
1286 PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A),
1287
1288 PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A),
1289 PINMUX_IPSR_DATA(IP10_24_22, VI1_DATA15),
1290 PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B),
1291 PINMUX_IPSR_DATA(IP10_24_22, DACK0_B),
1292 PINMUX_IPSR_DATA(IP10_24_22, HSPI_TX2_B),
1293 PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
1294};
1295
1296static struct sh_pfc_pin pinmux_pins[] = {
1297 PINMUX_GPIO_GP_ALL(),
1298};
1299
1300/* Pin numbers for pins without a corresponding GPIO port number are computed
1301 * from the row and column numbers with a 1000 offset to avoid collisions with
1302 * GPIO port numbers.
1303 */
1304#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
1305
1306/* - SCIF macro ------------------------------------------------------------- */
1307#define SCIF_PFC_PIN(name, args...) \
1308 static const unsigned int name ##_pins[] = { args }
1309#define SCIF_PFC_DAT(name, tx, rx) \
1310 static const unsigned int name ##_mux[] = { tx##_MARK, rx##_MARK, }
1311#define SCIF_PFC_CTR(name, cts, rts) \
1312 static const unsigned int name ##_mux[] = { cts##_MARK, rts##_MARK, }
1313#define SCIF_PFC_CLK(name, sck) \
1314 static const unsigned int name ##_mux[] = { sck##_MARK, }
1315
1316/* - HSCIF0 ----------------------------------------------------------------- */
1317SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
1318SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A);
1319SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30));
1320SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B);
1321SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1322SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A);
1323SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28));
1324SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B);
1325SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19));
1326SCIF_PFC_CLK(hscif0_clk, HSCK0);
1327
1328/* - HSCIF1 ----------------------------------------------------------------- */
1329SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20));
1330SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A);
1331SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
1332SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B);
1333SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
1334SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A);
1335SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7));
1336SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B);
1337SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23));
1338SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A);
1339SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2));
1340SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B);
1341
1342/* - SCIF CLOCK ------------------------------------------------------------- */
1343SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16));
1344SCIF_PFC_CLK(scif_clk, SCIF_CLK);
1345
1346/* - SCIF0 ------------------------------------------------------------------ */
1347SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
1348SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A);
1349SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2));
1350SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B);
1351SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31));
1352SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C);
1353SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1));
1354SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D);
1355SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
1356SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0);
1357SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19));
1358SCIF_PFC_CLK(scif0_clk, SCK0);
1359
1360/* - SCIF1 ------------------------------------------------------------------ */
1361SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1));
1362SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A);
1363SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
1364SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B);
1365SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
1366SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C);
1367SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
1368SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D);
1369SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
1370SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A);
1371SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19));
1372SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C);
1373SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2));
1374SCIF_PFC_CLK(scif1_clk_a, SCK1_A);
1375SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20));
1376SCIF_PFC_CLK(scif1_clk_c, SCK1_C);
1377
1378/* - SCIF2 ------------------------------------------------------------------ */
1379SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
1380SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A);
1381SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28));
1382SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B);
1383SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14));
1384SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C);
1385SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
1386SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D);
1387SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
1388SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E);
1389SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9));
1390SCIF_PFC_CLK(scif2_clk_a, SCK2_A);
1391SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20));
1392SCIF_PFC_CLK(scif2_clk_b, SCK2_B);
1393SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12));
1394SCIF_PFC_CLK(scif2_clk_c, SCK2_C);
1395
1396/* - SCIF3 ------------------------------------------------------------------ */
1397SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9));
1398SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A);
1399SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27));
1400SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B);
1401SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31));
1402SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C);
1403SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29));
1404SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D);
1405
1406/* - SCIF4 ------------------------------------------------------------------ */
1407SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4));
1408SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A);
1409SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25));
1410SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B);
1411SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31));
1412SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C);
1413
1414/* - SCIF5 ------------------------------------------------------------------ */
1415SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18));
1416SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A);
1417SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14));
1418SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
1419
1420static const struct sh_pfc_pin_group pinmux_groups[] = {
1421 SH_PFC_PIN_GROUP(hscif0_data_a),
1422 SH_PFC_PIN_GROUP(hscif0_data_b),
1423 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
1424 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
1425 SH_PFC_PIN_GROUP(hscif0_clk),
1426 SH_PFC_PIN_GROUP(hscif1_data_a),
1427 SH_PFC_PIN_GROUP(hscif1_data_b),
1428 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
1429 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
1430 SH_PFC_PIN_GROUP(hscif1_clk_a),
1431 SH_PFC_PIN_GROUP(hscif1_clk_b),
1432 SH_PFC_PIN_GROUP(scif_clk),
1433 SH_PFC_PIN_GROUP(scif0_data_a),
1434 SH_PFC_PIN_GROUP(scif0_data_b),
1435 SH_PFC_PIN_GROUP(scif0_data_c),
1436 SH_PFC_PIN_GROUP(scif0_data_d),
1437 SH_PFC_PIN_GROUP(scif0_ctrl),
1438 SH_PFC_PIN_GROUP(scif0_clk),
1439 SH_PFC_PIN_GROUP(scif1_data_a),
1440 SH_PFC_PIN_GROUP(scif1_data_b),
1441 SH_PFC_PIN_GROUP(scif1_data_c),
1442 SH_PFC_PIN_GROUP(scif1_data_d),
1443 SH_PFC_PIN_GROUP(scif1_ctrl_a),
1444 SH_PFC_PIN_GROUP(scif1_ctrl_c),
1445 SH_PFC_PIN_GROUP(scif1_clk_a),
1446 SH_PFC_PIN_GROUP(scif1_clk_c),
1447 SH_PFC_PIN_GROUP(scif2_data_a),
1448 SH_PFC_PIN_GROUP(scif2_data_b),
1449 SH_PFC_PIN_GROUP(scif2_data_c),
1450 SH_PFC_PIN_GROUP(scif2_data_d),
1451 SH_PFC_PIN_GROUP(scif2_data_e),
1452 SH_PFC_PIN_GROUP(scif2_clk_a),
1453 SH_PFC_PIN_GROUP(scif2_clk_b),
1454 SH_PFC_PIN_GROUP(scif2_clk_c),
1455 SH_PFC_PIN_GROUP(scif3_data_a),
1456 SH_PFC_PIN_GROUP(scif3_data_b),
1457 SH_PFC_PIN_GROUP(scif3_data_c),
1458 SH_PFC_PIN_GROUP(scif3_data_d),
1459 SH_PFC_PIN_GROUP(scif4_data_a),
1460 SH_PFC_PIN_GROUP(scif4_data_b),
1461 SH_PFC_PIN_GROUP(scif4_data_c),
1462 SH_PFC_PIN_GROUP(scif5_data_a),
1463 SH_PFC_PIN_GROUP(scif5_data_b),
1464};
1465
1466static const char * const hscif0_groups[] = {
1467 "hscif0_data_a",
1468 "hscif0_data_b",
1469 "hscif0_ctrl_a",
1470 "hscif0_ctrl_b",
1471 "hscif0_clk",
1472};
1473
1474static const char * const hscif1_groups[] = {
1475 "hscif1_data_a",
1476 "hscif1_data_b",
1477 "hscif1_ctrl_a",
1478 "hscif1_ctrl_b",
1479 "hscif1_clk_a",
1480 "hscif1_clk_b",
1481};
1482
1483static const char * const scif_clk_groups[] = {
1484 "scif_clk",
1485};
1486
1487static const char * const scif0_groups[] = {
1488 "scif0_data_a",
1489 "scif0_data_b",
1490 "scif0_data_c",
1491 "scif0_data_d",
1492 "scif0_ctrl",
1493 "scif0_clk",
1494};
1495
1496static const char * const scif1_groups[] = {
1497 "scif1_data_a",
1498 "scif1_data_b",
1499 "scif1_data_c",
1500 "scif1_data_d",
1501 "scif1_ctrl_a",
1502 "scif1_ctrl_c",
1503 "scif1_clk_a",
1504 "scif1_clk_c",
1505};
1506
1507static const char * const scif2_groups[] = {
1508 "scif2_data_a",
1509 "scif2_data_b",
1510 "scif2_data_c",
1511 "scif2_data_d",
1512 "scif2_data_e",
1513 "scif2_clk_a",
1514 "scif2_clk_b",
1515 "scif2_clk_c",
1516};
1517
1518static const char * const scif3_groups[] = {
1519 "scif3_data_a",
1520 "scif3_data_b",
1521 "scif3_data_c",
1522 "scif3_data_d",
1523};
1524
1525static const char * const scif4_groups[] = {
1526 "scif4_data_a",
1527 "scif4_data_b",
1528 "scif4_data_c",
1529};
1530
1531static const char * const scif5_groups[] = {
1532 "scif5_data_a",
1533 "scif5_data_b",
1534};
1535
1536static const struct sh_pfc_function pinmux_functions[] = {
1537 SH_PFC_FUNCTION(hscif0),
1538 SH_PFC_FUNCTION(hscif1),
1539 SH_PFC_FUNCTION(scif_clk),
1540 SH_PFC_FUNCTION(scif0),
1541 SH_PFC_FUNCTION(scif1),
1542 SH_PFC_FUNCTION(scif2),
1543 SH_PFC_FUNCTION(scif3),
1544 SH_PFC_FUNCTION(scif4),
1545 SH_PFC_FUNCTION(scif5),
1546};
1547
1548static struct pinmux_cfg_reg pinmux_config_regs[] = {
1549 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
1550 GP_0_31_FN, FN_IP1_14_11,
1551 GP_0_30_FN, FN_IP1_10_8,
1552 GP_0_29_FN, FN_IP1_7_5,
1553 GP_0_28_FN, FN_IP1_4_2,
1554 GP_0_27_FN, FN_IP1_1,
1555 GP_0_26_FN, FN_IP1_0,
1556 GP_0_25_FN, FN_IP0_30,
1557 GP_0_24_FN, FN_IP0_29,
1558 GP_0_23_FN, FN_IP0_28,
1559 GP_0_22_FN, FN_IP0_27,
1560 GP_0_21_FN, FN_IP0_26,
1561 GP_0_20_FN, FN_IP0_25,
1562 GP_0_19_FN, FN_IP0_24,
1563 GP_0_18_FN, FN_IP0_23,
1564 GP_0_17_FN, FN_IP0_22,
1565 GP_0_16_FN, FN_IP0_21,
1566 GP_0_15_FN, FN_IP0_20,
1567 GP_0_14_FN, FN_IP0_19,
1568 GP_0_13_FN, FN_IP0_18,
1569 GP_0_12_FN, FN_IP0_17,
1570 GP_0_11_FN, FN_IP0_16,
1571 GP_0_10_FN, FN_IP0_15,
1572 GP_0_9_FN, FN_A3,
1573 GP_0_8_FN, FN_A2,
1574 GP_0_7_FN, FN_A1,
1575 GP_0_6_FN, FN_IP0_14_12,
1576 GP_0_5_FN, FN_IP0_11_8,
1577 GP_0_4_FN, FN_IP0_7_5,
1578 GP_0_3_FN, FN_IP0_4_2,
1579 GP_0_2_FN, FN_PENC1,
1580 GP_0_1_FN, FN_PENC0,
1581 GP_0_0_FN, FN_IP0_1_0 }
1582 },
1583 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
1584 GP_1_31_FN, FN_IP4_6_4,
1585 GP_1_30_FN, FN_IP4_3_1,
1586 GP_1_29_FN, FN_IP4_0,
1587 GP_1_28_FN, FN_IP3_31,
1588 GP_1_27_FN, FN_IP3_30,
1589 GP_1_26_FN, FN_IP3_29,
1590 GP_1_25_FN, FN_IP3_28,
1591 GP_1_24_FN, FN_IP3_27,
1592 GP_1_23_FN, FN_IP3_26_24,
1593 GP_1_22_FN, FN_IP3_23_21,
1594 GP_1_21_FN, FN_IP3_20_19,
1595 GP_1_20_FN, FN_IP3_18_16,
1596 GP_1_19_FN, FN_IP3_15_13,
1597 GP_1_18_FN, FN_IP3_12_10,
1598 GP_1_17_FN, FN_IP3_9_8,
1599 GP_1_16_FN, FN_IP3_7_5,
1600 GP_1_15_FN, FN_IP3_4_2,
1601 GP_1_14_FN, FN_IP3_1_0,
1602 GP_1_13_FN, FN_IP2_31,
1603 GP_1_12_FN, FN_IP2_30,
1604 GP_1_11_FN, FN_IP2_17,
1605 GP_1_10_FN, FN_IP2_16_14,
1606 GP_1_9_FN, FN_IP2_13_12,
1607 GP_1_8_FN, FN_IP2_11_9,
1608 GP_1_7_FN, FN_IP2_8_6,
1609 GP_1_6_FN, FN_IP2_5_3,
1610 GP_1_5_FN, FN_IP2_2_0,
1611 GP_1_4_FN, FN_IP1_29_28,
1612 GP_1_3_FN, FN_IP1_27_25,
1613 GP_1_2_FN, FN_IP1_24,
1614 GP_1_1_FN, FN_WE0,
1615 GP_1_0_FN, FN_IP1_23_21 }
1616 },
1617 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
1618 GP_2_31_FN, FN_IP6_7,
1619 GP_2_30_FN, FN_IP6_6_5,
1620 GP_2_29_FN, FN_IP6_4_2,
1621 GP_2_28_FN, FN_IP6_1_0,
1622 GP_2_27_FN, FN_IP5_30_29,
1623 GP_2_26_FN, FN_IP5_28_26,
1624 GP_2_25_FN, FN_IP5_25_23,
1625 GP_2_24_FN, FN_IP5_22_21,
1626 GP_2_23_FN, FN_AUDIO_CLKB,
1627 GP_2_22_FN, FN_AUDIO_CLKA,
1628 GP_2_21_FN, FN_IP5_20_18,
1629 GP_2_20_FN, FN_IP5_17_15,
1630 GP_2_19_FN, FN_IP5_14_13,
1631 GP_2_18_FN, FN_IP5_12,
1632 GP_2_17_FN, FN_IP5_11_10,
1633 GP_2_16_FN, FN_IP5_9_8,
1634 GP_2_15_FN, FN_IP5_7,
1635 GP_2_14_FN, FN_IP5_6,
1636 GP_2_13_FN, FN_IP5_5_4,
1637 GP_2_12_FN, FN_IP5_3_2,
1638 GP_2_11_FN, FN_IP5_1_0,
1639 GP_2_10_FN, FN_IP4_30_29,
1640 GP_2_9_FN, FN_IP4_28_27,
1641 GP_2_8_FN, FN_IP4_26_25,
1642 GP_2_7_FN, FN_IP4_24_21,
1643 GP_2_6_FN, FN_IP4_20_17,
1644 GP_2_5_FN, FN_IP4_16_15,
1645 GP_2_4_FN, FN_IP4_14_13,
1646 GP_2_3_FN, FN_IP4_12_11,
1647 GP_2_2_FN, FN_IP4_10_9,
1648 GP_2_1_FN, FN_IP4_8,
1649 GP_2_0_FN, FN_IP4_7 }
1650 },
1651 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
1652 GP_3_31_FN, FN_IP8_10_9,
1653 GP_3_30_FN, FN_IP8_8_6,
1654 GP_3_29_FN, FN_IP8_5_3,
1655 GP_3_28_FN, FN_IP8_2_0,
1656 GP_3_27_FN, FN_IP7_31_29,
1657 GP_3_26_FN, FN_IP7_28_25,
1658 GP_3_25_FN, FN_IP7_24_22,
1659 GP_3_24_FN, FN_IP7_21,
1660 GP_3_23_FN, FN_IP7_20_18,
1661 GP_3_22_FN, FN_IP7_17_15,
1662 GP_3_21_FN, FN_IP7_14_12,
1663 GP_3_20_FN, FN_IP7_11_9,
1664 GP_3_19_FN, FN_IP7_8_6,
1665 GP_3_18_FN, FN_IP7_5_4,
1666 GP_3_17_FN, FN_IP7_3_2,
1667 GP_3_16_FN, FN_IP7_1_0,
1668 GP_3_15_FN, FN_IP6_31_30,
1669 GP_3_14_FN, FN_IP6_29_28,
1670 GP_3_13_FN, FN_IP6_27_26,
1671 GP_3_12_FN, FN_IP6_25_24,
1672 GP_3_11_FN, FN_IP6_23_22,
1673 GP_3_10_FN, FN_IP6_21,
1674 GP_3_9_FN, FN_IP6_20_19,
1675 GP_3_8_FN, FN_IP6_18_17,
1676 GP_3_7_FN, FN_IP6_16,
1677 GP_3_6_FN, FN_IP6_15_14,
1678 GP_3_5_FN, FN_IP6_13,
1679 GP_3_4_FN, FN_IP6_12_11,
1680 GP_3_3_FN, FN_IP6_10,
1681 GP_3_2_FN, FN_SSI_SCK34,
1682 GP_3_1_FN, FN_IP6_9,
1683 GP_3_0_FN, FN_IP6_8 }
1684 },
1685 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
1686 0, 0,
1687 0, 0,
1688 0, 0,
1689 0, 0,
1690 0, 0,
1691 GP_4_26_FN, FN_AVS2,
1692 GP_4_25_FN, FN_AVS1,
1693 GP_4_24_FN, FN_IP10_24_22,
1694 GP_4_23_FN, FN_IP10_21_19,
1695 GP_4_22_FN, FN_IP10_18_16,
1696 GP_4_21_FN, FN_IP10_15_13,
1697 GP_4_20_FN, FN_IP10_12_9,
1698 GP_4_19_FN, FN_IP10_8_6,
1699 GP_4_18_FN, FN_IP10_5_3,
1700 GP_4_17_FN, FN_IP10_2_0,
1701 GP_4_16_FN, FN_IP9_29_27,
1702 GP_4_15_FN, FN_IP9_26_24,
1703 GP_4_14_FN, FN_IP9_23_21,
1704 GP_4_13_FN, FN_IP9_20_18,
1705 GP_4_12_FN, FN_IP9_17_15,
1706 GP_4_11_FN, FN_IP9_14_12,
1707 GP_4_10_FN, FN_IP9_11_9,
1708 GP_4_9_FN, FN_IP9_8_6,
1709 GP_4_8_FN, FN_IP9_5_3,
1710 GP_4_7_FN, FN_IP9_2_0,
1711 GP_4_6_FN, FN_IP8_29_27,
1712 GP_4_5_FN, FN_IP8_26_24,
1713 GP_4_4_FN, FN_IP8_23_22,
1714 GP_4_3_FN, FN_IP8_21_19,
1715 GP_4_2_FN, FN_IP8_18_16,
1716 GP_4_1_FN, FN_IP8_15_14,
1717 GP_4_0_FN, FN_IP8_13_11 }
1718 },
1719
1720 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
1721 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1722 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
1723 /* IP0_31 [1] */
1724 0, 0,
1725 /* IP0_30 [1] */
1726 FN_A19, 0,
1727 /* IP0_29 [1] */
1728 FN_A18, 0,
1729 /* IP0_28 [1] */
1730 FN_A17, 0,
1731 /* IP0_27 [1] */
1732 FN_A16, 0,
1733 /* IP0_26 [1] */
1734 FN_A15, 0,
1735 /* IP0_25 [1] */
1736 FN_A14, 0,
1737 /* IP0_24 [1] */
1738 FN_A13, 0,
1739 /* IP0_23 [1] */
1740 FN_A12, 0,
1741 /* IP0_22 [1] */
1742 FN_A11, 0,
1743 /* IP0_21 [1] */
1744 FN_A10, 0,
1745 /* IP0_20 [1] */
1746 FN_A9, 0,
1747 /* IP0_19 [1] */
1748 FN_A8, 0,
1749 /* IP0_18 [1] */
1750 FN_A7, 0,
1751 /* IP0_17 [1] */
1752 FN_A6, 0,
1753 /* IP0_16 [1] */
1754 FN_A5, 0,
1755 /* IP0_15 [1] */
1756 FN_A4, 0,
1757 /* IP0_14_12 [3] */
1758 FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0,
1759 FN_ATAG0_A, 0, FN_REMOCON_B, 0,
1760 /* IP0_11_8 [4] */
1761 FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
1762 FN_ATADIR0_A, 0, FN_SDSELF_B, 0,
1763 FN_PWM4_B, 0, 0, 0,
1764 0, 0, 0, 0,
1765 /* IP0_7_5 [3] */
1766 FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1,
1767 FN_RX2_E, FN_SCL2_B, 0, 0,
1768 /* IP0_4_2 [3] */
1769 FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0,
1770 FN_TX2_E, FN_SDA2_B, 0, 0,
1771 /* IP0_1_0 [2] */
1772 FN_PRESETOUT, 0, FN_PWM1, 0,
1773 }
1774 },
1775 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
1776 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
1777 /* IP1_31 [1] */
1778 0, 0,
1779 /* IP1_30 [1] */
1780 0, 0,
1781 /* IP1_29_28 [2] */
1782 FN_EX_CS1, FN_MMC_D4, 0, 0,
1783 /* IP1_27_25 [3] */
1784 FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C,
1785 FN_TS_SCK0_A, 0, 0, 0,
1786 /* IP1_24 [1] */
1787 FN_WE1, FN_ATAWR0_B,
1788 /* IP1_23_21 [3] */
1789 FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR,
1790 0, 0, 0, 0,
1791 /* IP1_20_18 [3] */
1792 FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
1793 FN_SCK2_B, 0, 0, 0,
1794 /* IP1_17 [1] */
1795 FN_CS0, FN_HSPI_RX1_B,
1796 /* IP1_16_15 [2] */
1797 FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0,
1798 /* IP1_14_11 [4] */
1799 FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25,
1800 FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C,
1801 FN_TS_SDAT0_A, 0, 0, 0,
1802 0, 0, 0, 0,
1803 /* IP1_10_8 [3] */
1804 FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24,
1805 FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
1806 /* IP1_7_5 [3] */
1807 FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
1808 FN_TS_SDEN0_A, 0, 0, 0,
1809 /* IP1_4_2 [3] */
1810 FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
1811 0, 0, 0, 0,
1812 /* IP1_1 [1] */
1813 FN_A21, FN_HSPI_CLK1_B,
1814 /* IP1_0 [1] */
1815 FN_A20, FN_HSPI_CS1_B,
1816 }
1817 },
1818 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
1819 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1820 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
1821 /* IP2_31 [1] */
1822 FN_MLB_CLK, FN_IRQ3_A,
1823 /* IP2_30 [1] */
1824 FN_RD_WR_B, FN_IRQ0,
1825 /* IP2_29 [1] */
1826 FN_D11, 0,
1827 /* IP2_28 [1] */
1828 FN_D10, 0,
1829 /* IP2_27 [1] */
1830 FN_D9, 0,
1831 /* IP2_26 [1] */
1832 FN_D8, 0,
1833 /* IP2_25 [1] */
1834 FN_D7, 0,
1835 /* IP2_24 [1] */
1836 FN_D6, 0,
1837 /* IP2_23 [1] */
1838 FN_D5, 0,
1839 /* IP2_22 [1] */
1840 FN_D4, 0,
1841 /* IP2_21 [1] */
1842 FN_D3, 0,
1843 /* IP2_20 [1] */
1844 FN_D2, 0,
1845 /* IP2_19 [1] */
1846 FN_D1, 0,
1847 /* IP2_18 [1] */
1848 FN_D0, 0,
1849 /* IP2_17 [1] */
1850 FN_EX_WAIT0, FN_PWM0_C,
1851 /* IP2_16_14 [3] */
1852 FN_DACK0, 0, 0, FN_TX3_A,
1853 FN_DRACK0, 0, 0, 0,
1854 /* IP2_13_12 [2] */
1855 FN_DREQ0_A, 0, 0, FN_RX3_A,
1856 /* IP2_11_9 [3] */
1857 FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A,
1858 FN_EX_CS5, FN_EX_WAIT2_A, 0, 0,
1859 /* IP2_8_6 [3] */
1860 FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0,
1861 FN_EX_CS4, FN_EX_WAIT1_A, 0, 0,
1862 /* IP2_5_3 [3] */
1863 FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10,
1864 FN_EX_CS3, 0, 0, 0,
1865 /* IP2_2_0 [3] */
1866 FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
1867 FN_EX_CS2, 0, 0, 0,
1868 }
1869 },
1870 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
1871 1, 1, 1, 1, 1, 3, 3, 2,
1872 3, 3, 3, 2, 3, 3, 2) {
1873 /* IP3_31 [1] */
1874 FN_DU0_DR6, FN_LCDOUT6,
1875 /* IP3_30 [1] */
1876 FN_DU0_DR5, FN_LCDOUT5,
1877 /* IP3_29 [1] */
1878 FN_DU0_DR4, FN_LCDOUT4,
1879 /* IP3_28 [1] */
1880 FN_DU0_DR3, FN_LCDOUT3,
1881 /* IP3_27 [1] */
1882 FN_DU0_DR2, FN_LCDOUT2,
1883 /* IP3_26_24 [3] */
1884 FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3,
1885 FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
1886 /* IP3_23_21 [3] */
1887 FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2,
1888 FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B,
1889 /* IP3_20_19 [2] */
1890 FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0,
1891 /* IP3_18_16 [3] */
1892 FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0,
1893 0, 0, 0, 0,
1894 /* IP3_15_13 [3] */
1895 FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
1896 0, 0, 0, 0,
1897 /* IP3_12_10 [3] */
1898 FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0,
1899 0, 0, 0, 0,
1900 /* IP3_9_8 [2] */
1901 FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0,
1902 /* IP3_7_5 [3] */
1903 FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B,
1904 FN_SDA3_B, 0, 0, 0,
1905 /* IP3_4_2 [3] */
1906 FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
1907 FN_SDSELF_B, 0, 0, 0,
1908 /* IP3_1_0 [2] */
1909 FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
1910 }
1911 },
1912 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
1913 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
1914 /* IP4_31 [1] */
1915 0, 0,
1916 /* IP4_30_29 [2] */
1917 FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0,
1918 /* IP4_28_27 [2] */
1919 FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0,
1920 /* IP4_26_25 [2] */
1921 FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0,
1922 /* IP4_24_21 [4] */
1923 FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
1924 FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0,
1925 FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0,
1926 0, 0, 0, 0,
1927 /* IP4_20_17 [4] */
1928 FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16,
1929 FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A,
1930 FN_ADICLK, FN_TS_SDAT0_B, 0, 0,
1931 0, 0, 0, 0,
1932 /* IP4_16_15 [2] */
1933 FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0,
1934 /* IP4_14_13 [2] */
1935 FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0,
1936 /* IP4_12_11 [2] */
1937 FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0,
1938 /* IP4_10_9 [2] */
1939 FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0,
1940 /* IP4_8 [1] */
1941 FN_DU0_DG3, FN_LCDOUT11,
1942 /* IP4_7 [1] */
1943 FN_DU0_DG2, FN_LCDOUT10,
1944 /* IP4_6_4 [3] */
1945 FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5,
1946 FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0,
1947 /* IP4_3_1 [3] */
1948 FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4,
1949 FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
1950 /* IP4_0 [1] */
1951 FN_DU0_DR7, FN_LCDOUT7,
1952 }
1953 },
1954 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
1955 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
1956
1957 /* IP5_31 [1] */
1958 0, 0,
1959 /* IP5_30_29 [2] */
1960 FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B,
1961 /* IP5_28_26 [3] */
1962 FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A,
1963 FN_CAN0_TX_B, 0, 0, 0,
1964 /* IP5_25_23 [3] */
1965 FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
1966 FN_CAN_CLK_D, 0, 0, 0,
1967 /* IP5_22_21 [2] */
1968 FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
1969 /* IP5_20_18 [3] */
1970 FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC,
1971 FN_ARM_TRACECTL, FN_FMIN_D, 0, 0,
1972 /* IP5_17_15 [3] */
1973 FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK,
1974 FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0,
1975 /* IP5_14_13 [2] */
1976 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
1977 FN_FMCLK_D, 0,
1978 /* IP5_12 [1] */
1979 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
1980 /* IP5_11_10 [2] */
1981 FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
1982 FN_QSTH_QHS, 0,
1983 /* IP5_9_8 [2] */
1984 FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE,
1985 FN_AUDIO_CLKOUT_A, FN_REMOCON_C,
1986 /* IP5_7 [1] */
1987 FN_DU0_DOTCLKO_UT0, FN_QCLK,
1988 /* IP5_6 [1] */
1989 FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
1990 /* IP5_5_4 [2] */
1991 FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0,
1992 /* IP5_3_2 [2] */
1993 FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
1994 /* IP5_1_0 [2] */
1995 FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
1996 }
1997 },
1998 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
1999 2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
2000 1, 2, 1, 1, 1, 1, 2, 3, 2) {
2001 /* IP6_31_30 [2] */
2002 FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
2003 /* IP6_29_28 [2] */
2004 FN_SD0_DAT1, 0, FN_SUB_TCK, 0,
2005 /* IP6_27_26 [2] */
2006 FN_SD0_DAT0, 0, FN_SUB_TMS, 0,
2007 /* IP6_25_24 [2] */
2008 FN_SD0_CMD, 0, FN_SUB_TRST, 0,
2009 /* IP6_23_22 [2] */
2010 FN_SD0_CLK, 0, FN_SUB_TDO, 0,
2011 /* IP6_21 [1] */
2012 FN_SSI_SDATA0, FN_ARM_TRACEDATA_15,
2013 /* IP6_20_19 [2] */
2014 FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
2015 FN_SCL1_A, FN_SCK2_A,
2016 /* IP6_18_17 [2] */
2017 FN_SSI_SDATA2, FN_HSPI_CS2_A,
2018 FN_ARM_TRACEDATA_13, FN_SDA1_A,
2019 /* IP6_16 [1] */
2020 FN_SSI_WS012, FN_ARM_TRACEDATA_12,
2021 /* IP6_15_14 [2] */
2022 FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
2023 FN_TX0_D, 0,
2024 /* IP6_13 [1] */
2025 FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
2026 /* IP6_12_11 [2] */
2027 FN_SSI_SDATA4, FN_SSI_WS2_A,
2028 FN_ARM_TRACEDATA_9, 0,
2029 /* IP6_10 [1] */
2030 FN_SSI_WS34, FN_ARM_TRACEDATA_8,
2031 /* IP6_9 [1] */
2032 FN_SSI_SDATA5, FN_RX0_D,
2033 /* IP6_8 [1] */
2034 FN_SSI_WS5, FN_TX4_C,
2035 /* IP6_7 [1] */
2036 FN_SSI_SCK5, FN_RX4_C,
2037 /* IP6_6_5 [2] */
2038 FN_SSI_SDATA6, FN_HSPI_TX2_A,
2039 FN_FMIN_B, 0,
2040 /* IP6_4_2 [3] */
2041 FN_SSI_WS6, FN_HSPI_CLK2_A,
2042 FN_BPFCLK_B, FN_CAN1_RX_B,
2043 0, 0, 0, 0,
2044 /* IP6_1_0 [2] */
2045 FN_SSI_SCK6, FN_HSPI_RX2_A,
2046 FN_FMCLK_B, FN_CAN1_TX_B,
2047 }
2048 },
2049 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2050 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
2051
2052 /* IP7_31_29 [3] */
2053 FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
2054 0, FN_HSPI_CS1_A, FN_RX3_B, 0,
2055 /* IP7_28_25 [4] */
2056 FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1,
2057 FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B,
2058 0, 0, 0, 0,
2059 0, 0, 0, 0,
2060 /* IP7_24_22 [3] */
2061 FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
2062 0, FN_HSPI_RX1_A, FN_RX4_B, 0,
2063 /* IP7_21 [1] */
2064 FN_VI0_CLK, FN_CAN_CLK_A,
2065 /* IP7_20_18 [3] */
2066 FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0,
2067 FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0,
2068 /* IP7_17_15 [3] */
2069 FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A,
2070 0, FN_TX1_C, 0, 0,
2071 /* IP7_14_12 [3] */
2072 FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A,
2073 0, FN_RX1_C, 0, 0,
2074 /* IP7_11_9 [3] */
2075 FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0,
2076 FN_SCK1_C, 0, 0, 0,
2077 /* IP7_8_6 [3] */
2078 FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0,
2079 FN_RTS1_C, 0, 0, 0,
2080 /* IP7_5_4 [2] */
2081 FN_SD0_WP, 0, FN_RX5_A, 0,
2082 /* IP7_3_2 [2] */
2083 FN_SD0_CD, 0, FN_TX5_A, 0,
2084 /* IP7_1_0 [2] */
2085 FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
2086 }
2087 },
2088 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2089 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
2090 /* IP8_31 [1] */
2091 0, 0,
2092 /* IP8_30 [1] */
2093 0, 0,
2094 /* IP8_29_27 [3] */
2095 FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5,
2096 0, FN_HRX1_B, 0, 0,
2097 /* IP8_26_24 [3] */
2098 FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4,
2099 0, FN_HTX1_B, 0, 0,
2100 /* IP8_23_22 [2] */
2101 FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
2102 FN_RTS1_A, 0,
2103 /* IP8_21_19 [3] */
2104 FN_VI0_DATA6_VI0_G0, FN_DU1_DB4,
2105 FN_CTS1_A, FN_PWM5,
2106 0, 0, 0, 0,
2107 /* IP8_18_16 [3] */
2108 FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4,
2109 0, FN_HSCK1_B, 0, 0,
2110 /* IP8_15_14 [2] */
2111 FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0,
2112 /* IP8_13_11 [3] */
2113 FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C,
2114 0, 0, 0, 0,
2115 /* IP8_10_9 [2] */
2116 FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0,
2117 /* IP8_8_6 [3] */
2118 FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D,
2119 0, 0, 0, 0,
2120 /* IP8_5_3 [3] */
2121 FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D,
2122 0, 0, 0, 0,
2123 /* IP8_2_0 [3] */
2124 FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
2125 0, FN_HSPI_TX1_A, FN_TX3_B, 0,
2126 }
2127 },
2128 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2129 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2130 /* IP9_31 [1] */
2131 0, 0,
2132 /* IP9_30 [1] */
2133 0, 0,
2134 /* IP9_29_27 [3] */
2135 FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC,
2136 FN_ETH_RXD1, FN_FMIN_C,
2137 0, FN_RX2_D,
2138 FN_SCL2_C, 0,
2139 /* IP9_26_24 [3] */
2140 FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT,
2141 FN_ETH_RXD0, FN_BPFCLK_C,
2142 0, FN_TX2_D,
2143 FN_SDA2_C, 0,
2144 /* IP9_23_21 [3] */
2145 FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C,
2146 FN_IERX, FN_RX2_C, 0, 0,
2147 /* IP9_20_18 [3] */
2148 FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0,
2149 FN_IETX, FN_TX2_C, 0, 0,
2150 /* IP9_17_15 [3] */
2151 FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK,
2152 FN_SCK2_C, 0, 0, 0,
2153 /* IP9_14_12 [3] */
2154 FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1,
2155 0, FN_PWM3, 0, 0,
2156 /* IP9_11_9 [3] */
2157 FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0,
2158 0, FN_PWM2, FN_TCLK1, 0,
2159 /* IP9_8_6 [3] */
2160 FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
2161 0, 0, 0, 0,
2162 /* IP9_5_3 [3] */
2163 FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7,
2164 0, FN_HCTS1_B, 0, 0,
2165 /* IP9_2_0 [3] */
2166 FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
2167 0, FN_HRTS1_B, 0, 0,
2168 }
2169 },
2170 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2171 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
2172
2173 /* IP10_31 [1] */
2174 0, 0,
2175 /* IP10_30 [1] */
2176 0, 0,
2177 /* IP10_29 [1] */
2178 0, 0,
2179 /* IP10_28 [1] */
2180 0, 0,
2181 /* IP10_27 [1] */
2182 0, 0,
2183 /* IP10_26 [1] */
2184 0, 0,
2185 /* IP10_25 [1] */
2186 0, 0,
2187 /* IP10_24_22 [3] */
2188 FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B,
2189 FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0,
2190 /* IP10_21_19 [3] */
2191 FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B,
2192 FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0,
2193 /* IP10_18_16 [3] */
2194 FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1,
2195 FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0,
2196 /* IP10_15_13 [3] */
2197 FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1,
2198 FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0,
2199 /* IP10_12_9 [4] */
2200 FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
2201 FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6,
2202 0, 0, 0, 0,
2203 0, 0, 0, 0,
2204 /* IP10_8_6 [3] */
2205 FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B,
2206 FN_ETH_LINK, FN_CAN1_RX_A, 0, 0,
2207 /* IP10_5_3 [3] */
2208 FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2209 FN_ATAWR1, FN_ETH_MDIO,
2210 FN_SCL1_B, 0,
2211 0, 0,
2212 /* IP10_2_0 [3] */
2213 FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC,
2214 FN_ATARD1, FN_ETH_MDC,
2215 FN_SDA1_B, 0,
2216 0, 0,
2217 }
2218 },
2219 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
2220 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
2221 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2222
2223 /* SEL 31 [1] */
2224 0, 0,
2225 /* SEL_30 (SCIF5) [1] */
2226 FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
2227 /* SEL_29_28 (SCIF4) [2] */
2228 FN_SEL_SCIF4_A, FN_SEL_SCIF4_B,
2229 FN_SEL_SCIF4_C, 0,
2230 /* SEL_27_26 (SCIF3) [2] */
2231 FN_SEL_SCIF3_A, FN_SEL_SCIF3_B,
2232 FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
2233 /* SEL_25_23 (SCIF2) [3] */
2234 FN_SEL_SCIF2_A, FN_SEL_SCIF2_B,
2235 FN_SEL_SCIF2_C, FN_SEL_SCIF2_D,
2236 FN_SEL_SCIF2_E, 0,
2237 0, 0,
2238 /* SEL_22_21 (SCIF1) [2] */
2239 FN_SEL_SCIF1_A, FN_SEL_SCIF1_B,
2240 FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
2241 /* SEL_20_19 (SCIF0) [2] */
2242 FN_SEL_SCIF0_A, FN_SEL_SCIF0_B,
2243 FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
2244 /* SEL_18 [1] */
2245 0, 0,
2246 /* SEL_17 (SSI2) [1] */
2247 FN_SEL_SSI2_A, FN_SEL_SSI2_B,
2248 /* SEL_16 (SSI1) [1] */
2249 FN_SEL_SSI1_A, FN_SEL_SSI1_B,
2250 /* SEL_15 (VI1) [1] */
2251 FN_SEL_VI1_A, FN_SEL_VI1_B,
2252 /* SEL_14_13 (VI0) [2] */
2253 FN_SEL_VI0_A, FN_SEL_VI0_B,
2254 FN_SEL_VI0_C, FN_SEL_VI0_D,
2255 /* SEL_12 [1] */
2256 0, 0,
2257 /* SEL_11 (SD2) [1] */
2258 FN_SEL_SD2_A, FN_SEL_SD2_B,
2259 /* SEL_10 (SD1) [1] */
2260 FN_SEL_SD1_A, FN_SEL_SD1_B,
2261 /* SEL_9 (IRQ3) [1] */
2262 FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
2263 /* SEL_8_7 (IRQ2) [2] */
2264 FN_SEL_IRQ2_A, FN_SEL_IRQ2_B,
2265 FN_SEL_IRQ2_C, 0,
2266 /* SEL_6 (IRQ1) [1] */
2267 FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
2268 /* SEL_5 [1] */
2269 0, 0,
2270 /* SEL_4 (DREQ2) [1] */
2271 FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
2272 /* SEL_3 (DREQ1) [1] */
2273 FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
2274 /* SEL_2 (DREQ0) [1] */
2275 FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
2276 /* SEL_1 (WAIT2) [1] */
2277 FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
2278 /* SEL_0 (WAIT1) [1] */
2279 FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
2280 }
2281 },
2282 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
2283 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
2284 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
2285
2286 /* SEL_31 [1] */
2287 0, 0,
2288 /* SEL_30 [1] */
2289 0, 0,
2290 /* SEL_29 [1] */
2291 0, 0,
2292 /* SEL_28 [1] */
2293 0, 0,
2294 /* SEL_27 (CAN1) [1] */
2295 FN_SEL_CAN1_A, FN_SEL_CAN1_B,
2296 /* SEL_26 (CAN0) [1] */
2297 FN_SEL_CAN0_A, FN_SEL_CAN0_B,
2298 /* SEL_25_24 (CANCLK) [2] */
2299 FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
2300 FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
2301 /* SEL_23 (HSCIF1) [1] */
2302 FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
2303 /* SEL_22 (HSCIF0) [1] */
2304 FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
2305 /* SEL_21 [1] */
2306 0, 0,
2307 /* SEL_20 [1] */
2308 0, 0,
2309 /* SEL_19 [1] */
2310 0, 0,
2311 /* SEL_18 [1] */
2312 0, 0,
2313 /* SEL_17 [1] */
2314 0, 0,
2315 /* SEL_16 [1] */
2316 0, 0,
2317 /* SEL_15 [1] */
2318 0, 0,
2319 /* SEL_14_13 (REMOCON) [2] */
2320 FN_SEL_REMOCON_A, FN_SEL_REMOCON_B,
2321 FN_SEL_REMOCON_C, 0,
2322 /* SEL_12_11 (FM) [2] */
2323 FN_SEL_FM_A, FN_SEL_FM_B,
2324 FN_SEL_FM_C, FN_SEL_FM_D,
2325 /* SEL_10_9 (GPS) [2] */
2326 FN_SEL_GPS_A, FN_SEL_GPS_B,
2327 FN_SEL_GPS_C, 0,
2328 /* SEL_8 (TSIF0) [1] */
2329 FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
2330 /* SEL_7 (HSPI2) [1] */
2331 FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
2332 /* SEL_6 (HSPI1) [1] */
2333 FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
2334 /* SEL_5 (HSPI0) [1] */
2335 FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
2336 /* SEL_4_3 (I2C3) [2] */
2337 FN_SEL_I2C3_A, FN_SEL_I2C3_B,
2338 FN_SEL_I2C3_C, 0,
2339 /* SEL_2_1 (I2C2) [2] */
2340 FN_SEL_I2C2_A, FN_SEL_I2C2_B,
2341 FN_SEL_I2C2_C, 0,
2342 /* SEL_0 (I2C1) [1] */
2343 FN_SEL_I2C1_A, FN_SEL_I2C1_B,
2344 }
2345 },
2346 { },
2347};
2348
2349const struct sh_pfc_soc_info r8a7778_pinmux_info = {
2350 .name = "r8a7778_pfc",
2351
2352 .unlock_reg = 0xfffc0000, /* PMMR */
2353
2354 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2355
2356 .pins = pinmux_pins,
2357 .nr_pins = ARRAY_SIZE(pinmux_pins),
2358
2359 .groups = pinmux_groups,
2360 .nr_groups = ARRAY_SIZE(pinmux_groups),
2361
2362 .functions = pinmux_functions,
2363 .nr_functions = ARRAY_SIZE(pinmux_functions),
2364
2365 .cfg_regs = pinmux_config_regs,
2366
2367 .gpio_data = pinmux_data,
2368 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2369};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 15:13:11 -0500