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authorGabor Juhos <juhosg@openwrt.org>2011-06-20 15:26:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:02:45 -0500
commit7ee15d8a2837841d75f56319b94510ed950094b5 (patch)
tree03757b0eb2ae8d30c550c76b322719fcdfa341da
parent04225e1d227c8e68d685936ecf42ac175fec0e54 (diff)
MIPS: ath79: Add AR933X specific glue for ath79_device_reset_{set,clear}
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Kathy Giori <kgiori@qca.qualcomm.com> Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com> Patchwork: https://patchwork.linux-mips.org/patch/2523/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/ath79/common.c4
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h1
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 58f60e722a03..38c2ad7bd871 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -64,6 +64,8 @@ void ath79_device_reset_set(u32 mask)
64 reg = AR724X_RESET_REG_RESET_MODULE; 64 reg = AR724X_RESET_REG_RESET_MODULE;
65 else if (soc_is_ar913x()) 65 else if (soc_is_ar913x())
66 reg = AR913X_RESET_REG_RESET_MODULE; 66 reg = AR913X_RESET_REG_RESET_MODULE;
67 else if (soc_is_ar933x())
68 reg = AR933X_RESET_REG_RESET_MODULE;
67 else 69 else
68 BUG(); 70 BUG();
69 71
@@ -86,6 +88,8 @@ void ath79_device_reset_clear(u32 mask)
86 reg = AR724X_RESET_REG_RESET_MODULE; 88 reg = AR724X_RESET_REG_RESET_MODULE;
87 else if (soc_is_ar913x()) 89 else if (soc_is_ar913x())
88 reg = AR913X_RESET_REG_RESET_MODULE; 90 reg = AR913X_RESET_REG_RESET_MODULE;
91 else if (soc_is_ar933x())
92 reg = AR933X_RESET_REG_RESET_MODULE;
89 else 93 else
90 BUG(); 94 BUG();
91 95
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 418b7392e8c3..c7159e3479c2 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -173,6 +173,7 @@
173 173
174#define AR724X_RESET_REG_RESET_MODULE 0x1c 174#define AR724X_RESET_REG_RESET_MODULE 0x1c
175 175
176#define AR933X_RESET_REG_RESET_MODULE 0x1c
176#define AR933X_RESET_REG_BOOTSTRAP 0xac 177#define AR933X_RESET_REG_BOOTSTRAP 0xac
177 178
178#define MISC_INT_ETHSW BIT(12) 179#define MISC_INT_ETHSW BIT(12)