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authorManuel Lauss <manuel.lauss@googlemail.com>2011-08-12 05:39:40 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-10-24 18:34:24 -0400
commit7cc2e272da3d88c0de9e05b32729402785bd9206 (patch)
tree47abef81764180bad7399eba690a0407260cf3b0
parentb9581b84884eac4146720817a6eb0672074284fb (diff)
MIPS: Alchemy: more base address cleanup
remove all redundant peripheral base address defines, fix all affected boards and drivers. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/alchemy/common/platform.c12
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c52
-rw-r--r--arch/mips/alchemy/devboards/db1x00/platform.c40
-rw-r--r--arch/mips/alchemy/devboards/pb1100/platform.c20
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c42
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c22
-rw-r--r--arch/mips/alchemy/devboards/pb1550/platform.c40
-rw-r--r--arch/mips/alchemy/xxs1500/platform.c12
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h103
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_psc.h26
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h8
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h8
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h8
13 files changed, 146 insertions, 247 deletions
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 910a3bde9a52..bf1ac414d4bb 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -194,8 +194,8 @@ static void __init alchemy_setup_usb(int ctype)
194#ifdef CONFIG_FB_AU1100 194#ifdef CONFIG_FB_AU1100
195static struct resource au1100_lcd_resources[] = { 195static struct resource au1100_lcd_resources[] = {
196 [0] = { 196 [0] = {
197 .start = LCD_PHYS_ADDR, 197 .start = AU1100_LCD_PHYS_ADDR,
198 .end = LCD_PHYS_ADDR + 0x800 - 1, 198 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
199 .flags = IORESOURCE_MEM, 199 .flags = IORESOURCE_MEM,
200 }, 200 },
201 [1] = { 201 [1] = {
@@ -223,8 +223,8 @@ static struct platform_device au1100_lcd_device = {
223 223
224static struct resource au1200_lcd_resources[] = { 224static struct resource au1200_lcd_resources[] = {
225 [0] = { 225 [0] = {
226 .start = LCD_PHYS_ADDR, 226 .start = AU1200_LCD_PHYS_ADDR,
227 .end = LCD_PHYS_ADDR + 0x800 - 1, 227 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
228 .flags = IORESOURCE_MEM, 228 .flags = IORESOURCE_MEM,
229 }, 229 },
230 [1] = { 230 [1] = {
@@ -328,8 +328,8 @@ static struct platform_device au1200_mmc1_device = {
328#ifdef SMBUS_PSC_BASE 328#ifdef SMBUS_PSC_BASE
329static struct resource pbdb_smbus_resources[] = { 329static struct resource pbdb_smbus_resources[] = {
330 { 330 {
331 .start = CPHYSADDR(SMBUS_PSC_BASE), 331 .start = SMBUS_PSC_BASE,
332 .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff), 332 .end = SMBUS_PSC_BASE + 0xfff,
333 .flags = IORESOURCE_MEM, 333 .flags = IORESOURCE_MEM,
334 }, 334 },
335}; 335};
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index fbb55935b99e..95c7327affce 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -343,8 +343,8 @@ struct au1xmmc_platform_data au1xmmc_platdata[] = {
343 343
344static struct resource au1200_psc0_res[] = { 344static struct resource au1200_psc0_res[] = {
345 [0] = { 345 [0] = {
346 .start = PSC0_PHYS_ADDR, 346 .start = AU1550_PSC0_PHYS_ADDR,
347 .end = PSC0_PHYS_ADDR + 0x000fffff, 347 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
348 .flags = IORESOURCE_MEM, 348 .flags = IORESOURCE_MEM,
349 }, 349 },
350 [1] = { 350 [1] = {
@@ -401,8 +401,8 @@ static struct platform_device db1200_spi_dev = {
401 401
402static struct resource au1200_psc1_res[] = { 402static struct resource au1200_psc1_res[] = {
403 [0] = { 403 [0] = {
404 .start = PSC1_PHYS_ADDR, 404 .start = AU1550_PSC1_PHYS_ADDR,
405 .end = PSC1_PHYS_ADDR + 0x000fffff, 405 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
406 .flags = IORESOURCE_MEM, 406 .flags = IORESOURCE_MEM,
407 }, 407 },
408 [1] = { 408 [1] = {
@@ -510,32 +510,28 @@ static int __init db1200_dev_init(void)
510 510
511 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 511 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
512 __raw_writel(PSC_SEL_CLK_SERCLK, 512 __raw_writel(PSC_SEL_CLK_SERCLK,
513 (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 513 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
514 wmb(); 514 wmb();
515 515
516 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 516 db1x_register_pcmcia_socket(
517 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 517 AU1000_PCMCIA_ATTR_PHYS_ADDR,
518 PCMCIA_MEM_PHYS_ADDR, 518 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
519 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 519 AU1000_PCMCIA_MEM_PHYS_ADDR,
520 PCMCIA_IO_PHYS_ADDR, 520 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
521 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 521 AU1000_PCMCIA_IO_PHYS_ADDR,
522 DB1200_PC0_INT, 522 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
523 DB1200_PC0_INSERT_INT, 523 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
524 /*DB1200_PC0_STSCHG_INT*/0, 524 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
525 DB1200_PC0_EJECT_INT, 525
526 0); 526 db1x_register_pcmcia_socket(
527 527 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
528 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 528 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
529 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 529 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
530 PCMCIA_MEM_PHYS_ADDR + 0x004000000, 530 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
531 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 531 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
532 PCMCIA_IO_PHYS_ADDR + 0x004000000, 532 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
533 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 533 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
534 DB1200_PC1_INT, 534 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
535 DB1200_PC1_INSERT_INT,
536 /*DB1200_PC1_STSCHG_INT*/0,
537 DB1200_PC1_EJECT_INT,
538 1);
539 535
540 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 536 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
541 db1x_register_norflash(64 << 20, 2, swapped); 537 db1x_register_norflash(64 << 20, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
index 978d5ab3d678..ef8017f23cdc 100644
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -88,29 +88,25 @@
88static int __init db1xxx_dev_init(void) 88static int __init db1xxx_dev_init(void)
89{ 89{
90#ifdef DB1XXX_HAS_PCMCIA 90#ifdef DB1XXX_HAS_PCMCIA
91 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 91 db1x_register_pcmcia_socket(
92 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 92 AU1000_PCMCIA_ATTR_PHYS_ADDR,
93 PCMCIA_MEM_PHYS_ADDR, 93 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
94 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 94 AU1000_PCMCIA_MEM_PHYS_ADDR,
95 PCMCIA_IO_PHYS_ADDR, 95 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
96 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 96 AU1000_PCMCIA_IO_PHYS_ADDR,
97 DB1XXX_PCMCIA_CARD0, 97 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
98 DB1XXX_PCMCIA_CD0, 98 DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
99 /*DB1XXX_PCMCIA_STSCHG0*/0, 99 /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
100 0,
101 0);
102 100
103 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 101 db1x_register_pcmcia_socket(
104 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 102 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
105 PCMCIA_MEM_PHYS_ADDR + 0x004000000, 103 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
106 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 104 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
107 PCMCIA_IO_PHYS_ADDR + 0x004000000, 105 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
108 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 106 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
109 DB1XXX_PCMCIA_CARD1, 107 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
110 DB1XXX_PCMCIA_CD1, 108 DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
111 /*DB1XXX_PCMCIA_STSCHG1*/0, 109 /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
112 0,
113 1);
114#endif 110#endif
115 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED); 111 db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
116 return 0; 112 return 0;
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
index 2c8dc29759fd..8a4e733f0f9f 100644
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -30,17 +30,15 @@ static int __init pb1100_dev_init(void)
30 int swapped; 30 int swapped;
31 31
32 /* PCMCIA. single socket, identical to Pb1500 */ 32 /* PCMCIA. single socket, identical to Pb1500 */
33 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 33 db1x_register_pcmcia_socket(
34 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 34 AU1000_PCMCIA_ATTR_PHYS_ADDR,
35 PCMCIA_MEM_PHYS_ADDR, 35 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
36 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 36 AU1000_PCMCIA_MEM_PHYS_ADDR,
37 PCMCIA_IO_PHYS_ADDR, 37 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
38 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 38 AU1000_PCMCIA_IO_PHYS_ADDR,
39 AU1100_GPIO11_INT, /* card */ 39 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
40 AU1100_GPIO9_INT, /* insert */ 40 AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
41 /*AU1100_GPIO10_INT*/0, /* stschg */ 41 /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
42 0, /* eject */
43 0); /* id */
44 42
45 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 43 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
46 db1x_register_norflash(64 * 1024 * 1024, 4, swapped); 44 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 3ef2dceeb796..c52809d11155 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -170,29 +170,25 @@ static int __init board_register_devices(void)
170{ 170{
171 int swapped; 171 int swapped;
172 172
173 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 173 db1x_register_pcmcia_socket(
174 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 174 AU1000_PCMCIA_ATTR_PHYS_ADDR,
175 PCMCIA_MEM_PHYS_ADDR, 175 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
176 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 176 AU1000_PCMCIA_MEM_PHYS_ADDR,
177 PCMCIA_IO_PHYS_ADDR, 177 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
178 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 178 AU1000_PCMCIA_IO_PHYS_ADDR,
179 PB1200_PC0_INT, 179 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
180 PB1200_PC0_INSERT_INT, 180 PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
181 /*PB1200_PC0_STSCHG_INT*/0, 181 /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
182 PB1200_PC0_EJECT_INT, 182
183 0); 183 db1x_register_pcmcia_socket(
184 184 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
185 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, 185 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
186 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, 186 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
187 PCMCIA_MEM_PHYS_ADDR + 0x008000000, 187 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
188 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, 188 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
189 PCMCIA_IO_PHYS_ADDR + 0x008000000, 189 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
190 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, 190 PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
191 PB1200_PC1_INT, 191 /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
192 PB1200_PC1_INSERT_INT,
193 /*PB1200_PC1_STSCHG_INT*/0,
194 PB1200_PC1_EJECT_INT,
195 1);
196 192
197 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 193 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
198 db1x_register_norflash(128 * 1024 * 1024, 2, swapped); 194 db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
index d443bc7aa76e..42b0e6b8cd58 100644
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -28,18 +28,16 @@ static int __init pb1500_dev_init(void)
28{ 28{
29 int swapped; 29 int swapped;
30 30
31 /* PCMCIA. single socket, identical to Pb1500 */ 31 /* PCMCIA. single socket, identical to Pb1100 */
32 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 32 db1x_register_pcmcia_socket(
33 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 33 AU1000_PCMCIA_ATTR_PHYS_ADDR,
34 PCMCIA_MEM_PHYS_ADDR, 34 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
35 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 35 AU1000_PCMCIA_MEM_PHYS_ADDR,
36 PCMCIA_IO_PHYS_ADDR, 36 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
37 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 37 AU1000_PCMCIA_IO_PHYS_ADDR,
38 AU1500_GPIO11_INT, /* card */ 38 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
39 AU1500_GPIO9_INT, /* insert */ 39 AU1500_GPIO11_INT, AU1500_GPIO9_INT, /* card / insert */
40 /*AU1500_GPIO10_INT*/0, /* stschg */ 40 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
41 0, /* eject */
42 0); /* id */
43 41
44 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 42 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
45 db1x_register_norflash(64 * 1024 * 1024, 4, swapped); 43 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
index d7150d0f49c0..87c79b7f3123 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -37,29 +37,23 @@ static int __init pb1550_dev_init(void)
37 * drivers are used to shared irqs and b) statuschange isn't really use- 37 * drivers are used to shared irqs and b) statuschange isn't really use-
38 * ful anyway. 38 * ful anyway.
39 */ 39 */
40 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR, 40 db1x_register_pcmcia_socket(
41 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 41 AU1000_PCMCIA_ATTR_PHYS_ADDR,
42 PCMCIA_MEM_PHYS_ADDR, 42 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
43 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 43 AU1000_PCMCIA_MEM_PHYS_ADDR,
44 PCMCIA_IO_PHYS_ADDR, 44 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
45 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 45 AU1000_PCMCIA_IO_PHYS_ADDR,
46 AU1550_GPIO201_205_INT, 46 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
47 AU1550_GPIO0_INT, 47 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
48 0, 48
49 0, 49 db1x_register_pcmcia_socket(
50 0); 50 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
51 51 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
52 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000, 52 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
53 PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, 53 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
54 PCMCIA_MEM_PHYS_ADDR + 0x008000000, 54 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
55 PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, 55 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
56 PCMCIA_IO_PHYS_ADDR + 0x008000000, 56 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
57 PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
58 AU1550_GPIO201_205_INT,
59 AU1550_GPIO1_INT,
60 0,
61 0,
62 1);
63 57
64 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT; 58 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
65 db1x_register_norflash(128 * 1024 * 1024, 4, swapped); 59 db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
index e87c45cde61b..06a3a459b8aa 100644
--- a/arch/mips/alchemy/xxs1500/platform.c
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -27,20 +27,20 @@ static struct resource xxs1500_pcmcia_res[] = {
27 { 27 {
28 .name = "pcmcia-io", 28 .name = "pcmcia-io",
29 .flags = IORESOURCE_MEM, 29 .flags = IORESOURCE_MEM,
30 .start = PCMCIA_IO_PHYS_ADDR, 30 .start = AU1000_PCMCIA_IO_PHYS_ADDR,
31 .end = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1, 31 .end = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
32 }, 32 },
33 { 33 {
34 .name = "pcmcia-attr", 34 .name = "pcmcia-attr",
35 .flags = IORESOURCE_MEM, 35 .flags = IORESOURCE_MEM,
36 .start = PCMCIA_ATTR_PHYS_ADDR, 36 .start = AU1000_PCMCIA_ATTR_PHYS_ADDR,
37 .end = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 37 .end = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
38 }, 38 },
39 { 39 {
40 .name = "pcmcia-mem", 40 .name = "pcmcia-mem",
41 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
42 .start = PCMCIA_MEM_PHYS_ADDR, 42 .start = AU1000_PCMCIA_MEM_PHYS_ADDR,
43 .end = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 43 .end = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
44 }, 44 },
45}; 45};
46 46
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 7f610b370382..1bbcb30c4ab9 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -698,114 +698,61 @@ enum soc_au1200_ints {
698#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 698#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
699#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ 699#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
700#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ 700#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
701#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
702#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */
701#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 703#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
702#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ 704#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
703#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ 705#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
704#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ 706#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
705#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ 707#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */
706#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ 708#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
709#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
710#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
707#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ 711#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
708#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ 712#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
709#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ 713#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
710#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ 714#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
711#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ 715#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
716#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
712#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ 717#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
713#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ 718#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
714#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ 719#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
720#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
721#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
715#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ 722#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
716#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 723#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
717#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ 724#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */
725#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
726#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
727#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
728#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
718#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ 729#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
719#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 730#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
720#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 731#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
721#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ 732#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
722#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ 733#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
734#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */
735#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
736#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
737#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
738#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
723#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ 739#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
724#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ 740#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
725#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ 741#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
726#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ 742#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
727#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ 743#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
728#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ 744#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
745#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
746#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */
747#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
748#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
749#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
750#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
751#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */
752#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */
753#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */
729 754
730 755
731#ifdef CONFIG_SOC_AU1000
732#define MEM_PHYS_ADDR 0x14000000
733#define STATIC_MEM_PHYS_ADDR 0x14001000
734#define IRDA_PHYS_ADDR 0x10300000
735#define SSI0_PHYS_ADDR 0x11600000
736#define SSI1_PHYS_ADDR 0x11680000
737#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
738#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
739#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
740#endif
741
742/********************************************************************/
743
744#ifdef CONFIG_SOC_AU1500
745#define MEM_PHYS_ADDR 0x14000000
746#define STATIC_MEM_PHYS_ADDR 0x14001000
747#define PCI_PHYS_ADDR 0x14005000
748#define PCI_MEM_PHYS_ADDR 0x400000000ULL
749#define PCI_IO_PHYS_ADDR 0x500000000ULL
750#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
751#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
752#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
753#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
754#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
755#endif
756
757/********************************************************************/
758
759#ifdef CONFIG_SOC_AU1100
760#define MEM_PHYS_ADDR 0x14000000
761#define STATIC_MEM_PHYS_ADDR 0x14001000
762#define IRDA_PHYS_ADDR 0x10300000
763#define SSI0_PHYS_ADDR 0x11600000
764#define SSI1_PHYS_ADDR 0x11680000
765#define LCD_PHYS_ADDR 0x15000000
766#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
767#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
768#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
769#endif
770
771/***********************************************************************/
772
773#ifdef CONFIG_SOC_AU1550
774#define MEM_PHYS_ADDR 0x14000000
775#define STATIC_MEM_PHYS_ADDR 0x14001000
776#define PCI_PHYS_ADDR 0x14005000
777#define PE_PHYS_ADDR 0x14008000
778#define PSC0_PHYS_ADDR 0x11A00000
779#define PSC1_PHYS_ADDR 0x11B00000
780#define PSC2_PHYS_ADDR 0x10A00000
781#define PSC3_PHYS_ADDR 0x10B00000
782#define PCI_MEM_PHYS_ADDR 0x400000000ULL
783#define PCI_IO_PHYS_ADDR 0x500000000ULL
784#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
785#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
786#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
787#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
788#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
789#endif
790
791/***********************************************************************/
792
793#ifdef CONFIG_SOC_AU1200
794#define MEM_PHYS_ADDR 0x14000000
795#define STATIC_MEM_PHYS_ADDR 0x14001000
796#define AES_PHYS_ADDR 0x10300000
797#define CIM_PHYS_ADDR 0x14004000
798#define PSC0_PHYS_ADDR 0x11A00000
799#define PSC1_PHYS_ADDR 0x11B00000
800#define LCD_PHYS_ADDR 0x15000000
801#define SWCNT_PHYS_ADDR 0x1110010C
802#define MAEFE_PHYS_ADDR 0x14012000
803#define MAEBE_PHYS_ADDR 0x14010000
804#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
805#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
806#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
807#endif
808
809/* Static Bus Controller */ 756/* Static Bus Controller */
810#define MEM_STCFG0 0xB4001000 757#define MEM_STCFG0 0xB4001000
811#define MEM_STTIME0 0xB4001004 758#define MEM_STTIME0 0xB4001004
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 892b7f168eb4..8e2fa674be4a 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -33,19 +33,6 @@
33#ifndef _AU1000_PSC_H_ 33#ifndef _AU1000_PSC_H_
34#define _AU1000_PSC_H_ 34#define _AU1000_PSC_H_
35 35
36/* The PSC base addresses. */
37#ifdef CONFIG_SOC_AU1550
38#define PSC0_BASE_ADDR 0xb1a00000
39#define PSC1_BASE_ADDR 0xb1b00000
40#define PSC2_BASE_ADDR 0xb0a00000
41#define PSC3_BASE_ADDR 0xb0b00000
42#endif
43
44#ifdef CONFIG_SOC_AU1200
45#define PSC0_BASE_ADDR 0xb1a00000
46#define PSC1_BASE_ADDR 0xb1b00000
47#endif
48
49/* 36/*
50 * The PSC select and control registers are common to all protocols. 37 * The PSC select and control registers are common to all protocols.
51 */ 38 */
@@ -80,19 +67,6 @@
80#define PSC_AC97GPO_OFFSET 0x00000028 67#define PSC_AC97GPO_OFFSET 0x00000028
81#define PSC_AC97GPI_OFFSET 0x0000002c 68#define PSC_AC97GPI_OFFSET 0x0000002c
82 69
83#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
84#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
85#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
86#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
87#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
88#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
89#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
90#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
91#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
92#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
93#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
94#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
95
96/* AC97 Config Register. */ 70/* AC97 Config Register. */
97#define PSC_AC97CFG_RT_MASK (3 << 30) 71#define PSC_AC97CFG_RT_MASK (3 << 30)
98#define PSC_AC97CFG_RT_FIFO1 (0 << 30) 72#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index a919dac525a1..115cc7c44402 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -36,10 +36,10 @@
36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
38 38
39#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
40#define AC97_PSC_BASE PSC1_BASE_ADDR 40#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
41#define SMBUS_PSC_BASE PSC2_BASE_ADDR 41#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
42#define I2S_PSC_BASE PSC3_BASE_ADDR 42#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
43 43
44#define NAND_PHYS_ADDR 0x20000000 44#define NAND_PHYS_ADDR 0x20000000
45 45
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index fce4332ebb7f..0ecff1cb695a 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -37,14 +37,14 @@
37 * SPI and SMB are muxed on the Pb1200 board. 37 * SPI and SMB are muxed on the Pb1200 board.
38 * Refer to board documentation. 38 * Refer to board documentation.
39 */ 39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR 40#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR 41#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
42/* 42/*
43 * AC97 and I2S are muxed on the Pb1200 board. 43 * AC97 and I2S are muxed on the Pb1200 board.
44 * Refer to board documentation. 44 * Refer to board documentation.
45 */ 45 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 46#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 47#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
48 48
49 49
50#define BCSR_SYSTEM_VDDI 0x001F 50#define BCSR_SYSTEM_VDDI 0x001F
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index f835c88e9593..0b0f462e4bfb 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -35,10 +35,10 @@
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
37 37
38#define SPI_PSC_BASE PSC0_BASE_ADDR 38#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
39#define AC97_PSC_BASE PSC1_BASE_ADDR 39#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
42 42
43/* 43/*
44 * Timing values as described in databook, * ns value stripped of 44 * Timing values as described in databook, * ns value stripped of
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 10:14:53 -0500