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authorYan, Zheng <zheng.z.yan@intel.com>2012-06-15 02:31:37 -0400
committerIngo Molnar <mingo@kernel.org>2012-06-18 06:13:23 -0400
commit7c94ee2e0917b2ea56498bff939c8aa55da27207 (patch)
treeaf7ab6b43ae124f0c7a737e4692d184e3818b9bb
parent14371cce03c2fc393997e17f979e76674b7f392a (diff)
perf/x86: Add Intel Nehalem and Sandy Bridge-EP uncore support
The uncore subsystem in Sandy Bridge-EP consists of 8 components: Ubox, Cacheing Agent, Home Agent, Memory controller, Power Control, QPI Link Layer, R2PCIe, R3QPI. Signed-off-by: Zheng Yan <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1339741902-8449-9-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.c484
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.h86
-rw-r--r--include/linux/pci_ids.h11
3 files changed, 581 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index e20c65a0e108..d34f68bf990b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -21,6 +21,482 @@ DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
21DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 21DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
22DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28"); 22DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
23DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31"); 23DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
24DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
25DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
26DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
27DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
28DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
29
30/* Sandy Bridge-EP uncore support */
31static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
32{
33 struct pci_dev *pdev = box->pci_dev;
34 int box_ctl = uncore_pci_box_ctl(box);
35 u32 config;
36
37 pci_read_config_dword(pdev, box_ctl, &config);
38 config |= SNBEP_PMON_BOX_CTL_FRZ;
39 pci_write_config_dword(pdev, box_ctl, config);
40}
41
42static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
43{
44 struct pci_dev *pdev = box->pci_dev;
45 int box_ctl = uncore_pci_box_ctl(box);
46 u32 config;
47
48 pci_read_config_dword(pdev, box_ctl, &config);
49 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
50 pci_write_config_dword(pdev, box_ctl, config);
51}
52
53static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box,
54 struct perf_event *event)
55{
56 struct pci_dev *pdev = box->pci_dev;
57 struct hw_perf_event *hwc = &event->hw;
58
59 pci_write_config_dword(pdev, hwc->config_base, hwc->config |
60 SNBEP_PMON_CTL_EN);
61}
62
63static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box,
64 struct perf_event *event)
65{
66 struct pci_dev *pdev = box->pci_dev;
67 struct hw_perf_event *hwc = &event->hw;
68
69 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
70}
71
72static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box,
73 struct perf_event *event)
74{
75 struct pci_dev *pdev = box->pci_dev;
76 struct hw_perf_event *hwc = &event->hw;
77 u64 count;
78
79 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
80 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
81 return count;
82}
83
84static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
85{
86 struct pci_dev *pdev = box->pci_dev;
87 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL,
88 SNBEP_PMON_BOX_CTL_INT);
89}
90
91static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
92{
93 u64 config;
94 unsigned msr;
95
96 msr = uncore_msr_box_ctl(box);
97 if (msr) {
98 rdmsrl(msr, config);
99 config |= SNBEP_PMON_BOX_CTL_FRZ;
100 wrmsrl(msr, config);
101 return;
102 }
103}
104
105static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
106{
107 u64 config;
108 unsigned msr;
109
110 msr = uncore_msr_box_ctl(box);
111 if (msr) {
112 rdmsrl(msr, config);
113 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
114 wrmsrl(msr, config);
115 return;
116 }
117}
118
119static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box,
120 struct perf_event *event)
121{
122 struct hw_perf_event *hwc = &event->hw;
123
124 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
125}
126
127static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
128 struct perf_event *event)
129{
130 struct hw_perf_event *hwc = &event->hw;
131
132 wrmsrl(hwc->config_base, hwc->config);
133}
134
135static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box,
136 struct perf_event *event)
137{
138 struct hw_perf_event *hwc = &event->hw;
139 u64 count;
140
141 rdmsrl(hwc->event_base, count);
142 return count;
143}
144
145static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
146{
147 unsigned msr = uncore_msr_box_ctl(box);
148 if (msr)
149 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
150}
151
152static struct attribute *snbep_uncore_formats_attr[] = {
153 &format_attr_event.attr,
154 &format_attr_umask.attr,
155 &format_attr_edge.attr,
156 &format_attr_inv.attr,
157 &format_attr_thresh8.attr,
158 NULL,
159};
160
161static struct attribute *snbep_uncore_ubox_formats_attr[] = {
162 &format_attr_event.attr,
163 &format_attr_umask.attr,
164 &format_attr_edge.attr,
165 &format_attr_inv.attr,
166 &format_attr_thresh5.attr,
167 NULL,
168};
169
170static struct attribute *snbep_uncore_pcu_formats_attr[] = {
171 &format_attr_event.attr,
172 &format_attr_occ_sel.attr,
173 &format_attr_edge.attr,
174 &format_attr_inv.attr,
175 &format_attr_thresh5.attr,
176 &format_attr_occ_invert.attr,
177 &format_attr_occ_edge.attr,
178 NULL,
179};
180
181static struct uncore_event_desc snbep_uncore_imc_events[] = {
182 INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "config=0xffff"),
183 /* read */
184 INTEL_UNCORE_EVENT_DESC(CAS_COUNT_RD, "event=0x4,umask=0x3"),
185 /* write */
186 INTEL_UNCORE_EVENT_DESC(CAS_COUNT_WR, "event=0x4,umask=0xc"),
187 { /* end: all zeroes */ },
188};
189
190static struct uncore_event_desc snbep_uncore_qpi_events[] = {
191 INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "event=0x14"),
192 /* outgoing data+nondata flits */
193 INTEL_UNCORE_EVENT_DESC(TxL_FLITS_ACTIVE, "event=0x0,umask=0x6"),
194 /* DRS data received */
195 INTEL_UNCORE_EVENT_DESC(DRS_DATA, "event=0x2,umask=0x8"),
196 /* NCB data received */
197 INTEL_UNCORE_EVENT_DESC(NCB_DATA, "event=0x3,umask=0x4"),
198 { /* end: all zeroes */ },
199};
200
201static struct attribute_group snbep_uncore_format_group = {
202 .name = "format",
203 .attrs = snbep_uncore_formats_attr,
204};
205
206static struct attribute_group snbep_uncore_ubox_format_group = {
207 .name = "format",
208 .attrs = snbep_uncore_ubox_formats_attr,
209};
210
211static struct attribute_group snbep_uncore_pcu_format_group = {
212 .name = "format",
213 .attrs = snbep_uncore_pcu_formats_attr,
214};
215
216static struct intel_uncore_ops snbep_uncore_msr_ops = {
217 .init_box = snbep_uncore_msr_init_box,
218 .disable_box = snbep_uncore_msr_disable_box,
219 .enable_box = snbep_uncore_msr_enable_box,
220 .disable_event = snbep_uncore_msr_disable_event,
221 .enable_event = snbep_uncore_msr_enable_event,
222 .read_counter = snbep_uncore_msr_read_counter,
223};
224
225static struct intel_uncore_ops snbep_uncore_pci_ops = {
226 .init_box = snbep_uncore_pci_init_box,
227 .disable_box = snbep_uncore_pci_disable_box,
228 .enable_box = snbep_uncore_pci_enable_box,
229 .disable_event = snbep_uncore_pci_disable_event,
230 .enable_event = snbep_uncore_pci_enable_event,
231 .read_counter = snbep_uncore_pci_read_counter,
232};
233
234static struct event_constraint snbep_uncore_cbox_constraints[] = {
235 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
236 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
237 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
238 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
239 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
240 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
241 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
242 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
243 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
244 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
245 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
246 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
247 UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
248 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
249 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
250 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
251 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
252 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
253 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
254 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
255 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
256 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
257 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
258 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
259 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
260 EVENT_CONSTRAINT_END
261};
262
263static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
264 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
265 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
266 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
267 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
268 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
269 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
270 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
271 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
272 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
273 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
274 EVENT_CONSTRAINT_END
275};
276
277static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
278 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
279 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
280 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
281 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
282 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
283 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
284 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
285 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
286 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
287 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
288 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
289 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
290 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
291 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
292 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
293 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
294 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
295 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
296 EVENT_CONSTRAINT_END
297};
298
299static struct intel_uncore_type snbep_uncore_ubox = {
300 .name = "ubox",
301 .num_counters = 2,
302 .num_boxes = 1,
303 .perf_ctr_bits = 44,
304 .fixed_ctr_bits = 48,
305 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
306 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
307 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
308 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
309 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
310 .ops = &snbep_uncore_msr_ops,
311 .format_group = &snbep_uncore_ubox_format_group,
312};
313
314static struct intel_uncore_type snbep_uncore_cbox = {
315 .name = "cbox",
316 .num_counters = 4,
317 .num_boxes = 8,
318 .perf_ctr_bits = 44,
319 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
320 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
321 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
322 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
323 .msr_offset = SNBEP_CBO_MSR_OFFSET,
324 .constraints = snbep_uncore_cbox_constraints,
325 .ops = &snbep_uncore_msr_ops,
326 .format_group = &snbep_uncore_format_group,
327};
328
329static struct intel_uncore_type snbep_uncore_pcu = {
330 .name = "pcu",
331 .num_counters = 4,
332 .num_boxes = 1,
333 .perf_ctr_bits = 48,
334 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
335 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
336 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
337 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
338 .ops = &snbep_uncore_msr_ops,
339 .format_group = &snbep_uncore_pcu_format_group,
340};
341
342static struct intel_uncore_type *snbep_msr_uncores[] = {
343 &snbep_uncore_ubox,
344 &snbep_uncore_cbox,
345 &snbep_uncore_pcu,
346 NULL,
347};
348
349#define SNBEP_UNCORE_PCI_COMMON_INIT() \
350 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
351 .event_ctl = SNBEP_PCI_PMON_CTL0, \
352 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
353 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
354 .ops = &snbep_uncore_pci_ops, \
355 .format_group = &snbep_uncore_format_group
356
357static struct intel_uncore_type snbep_uncore_ha = {
358 .name = "ha",
359 .num_counters = 4,
360 .num_boxes = 1,
361 .perf_ctr_bits = 48,
362 SNBEP_UNCORE_PCI_COMMON_INIT(),
363};
364
365static struct intel_uncore_type snbep_uncore_imc = {
366 .name = "imc",
367 .num_counters = 4,
368 .num_boxes = 4,
369 .perf_ctr_bits = 48,
370 .fixed_ctr_bits = 48,
371 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
372 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
373 .event_descs = snbep_uncore_imc_events,
374 SNBEP_UNCORE_PCI_COMMON_INIT(),
375};
376
377static struct intel_uncore_type snbep_uncore_qpi = {
378 .name = "qpi",
379 .num_counters = 4,
380 .num_boxes = 2,
381 .perf_ctr_bits = 48,
382 .event_descs = snbep_uncore_qpi_events,
383 SNBEP_UNCORE_PCI_COMMON_INIT(),
384};
385
386
387static struct intel_uncore_type snbep_uncore_r2pcie = {
388 .name = "r2pcie",
389 .num_counters = 4,
390 .num_boxes = 1,
391 .perf_ctr_bits = 44,
392 .constraints = snbep_uncore_r2pcie_constraints,
393 SNBEP_UNCORE_PCI_COMMON_INIT(),
394};
395
396static struct intel_uncore_type snbep_uncore_r3qpi = {
397 .name = "r3qpi",
398 .num_counters = 3,
399 .num_boxes = 2,
400 .perf_ctr_bits = 44,
401 .constraints = snbep_uncore_r3qpi_constraints,
402 SNBEP_UNCORE_PCI_COMMON_INIT(),
403};
404
405static struct intel_uncore_type *snbep_pci_uncores[] = {
406 &snbep_uncore_ha,
407 &snbep_uncore_imc,
408 &snbep_uncore_qpi,
409 &snbep_uncore_r2pcie,
410 &snbep_uncore_r3qpi,
411 NULL,
412};
413
414static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
415 { /* Home Agent */
416 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
417 .driver_data = (unsigned long)&snbep_uncore_ha,
418 },
419 { /* MC Channel 0 */
420 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
421 .driver_data = (unsigned long)&snbep_uncore_imc,
422 },
423 { /* MC Channel 1 */
424 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
425 .driver_data = (unsigned long)&snbep_uncore_imc,
426 },
427 { /* MC Channel 2 */
428 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
429 .driver_data = (unsigned long)&snbep_uncore_imc,
430 },
431 { /* MC Channel 3 */
432 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
433 .driver_data = (unsigned long)&snbep_uncore_imc,
434 },
435 { /* QPI Port 0 */
436 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
437 .driver_data = (unsigned long)&snbep_uncore_qpi,
438 },
439 { /* QPI Port 1 */
440 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
441 .driver_data = (unsigned long)&snbep_uncore_qpi,
442 },
443 { /* P2PCIe */
444 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
445 .driver_data = (unsigned long)&snbep_uncore_r2pcie,
446 },
447 { /* R3QPI Link 0 */
448 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
449 .driver_data = (unsigned long)&snbep_uncore_r3qpi,
450 },
451 { /* R3QPI Link 1 */
452 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
453 .driver_data = (unsigned long)&snbep_uncore_r3qpi,
454 },
455 { /* end: all zeroes */ }
456};
457
458static struct pci_driver snbep_uncore_pci_driver = {
459 .name = "snbep_uncore",
460 .id_table = snbep_uncore_pci_ids,
461};
462
463/*
464 * build pci bus to socket mapping
465 */
466static void snbep_pci2phy_map_init(void)
467{
468 struct pci_dev *ubox_dev = NULL;
469 int i, bus, nodeid;
470 u32 config;
471
472 while (1) {
473 /* find the UBOX device */
474 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
475 PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
476 ubox_dev);
477 if (!ubox_dev)
478 break;
479 bus = ubox_dev->bus->number;
480 /* get the Node ID of the local register */
481 pci_read_config_dword(ubox_dev, 0x40, &config);
482 nodeid = config;
483 /* get the Node ID mapping */
484 pci_read_config_dword(ubox_dev, 0x54, &config);
485 /*
486 * every three bits in the Node ID mapping register maps
487 * to a particular node.
488 */
489 for (i = 0; i < 8; i++) {
490 if (nodeid == ((config >> (3 * i)) & 0x7)) {
491 pcibus_to_physid[bus] = i;
492 break;
493 }
494 }
495 };
496 return;
497}
498/* end of Sandy Bridge-EP uncore support */
499
24 500
25/* Sandy Bridge uncore support */ 501/* Sandy Bridge uncore support */
26static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, 502static void snb_uncore_msr_enable_event(struct intel_uncore_box *box,
@@ -894,6 +1370,11 @@ static int __init uncore_pci_init(void)
894 int ret; 1370 int ret;
895 1371
896 switch (boot_cpu_data.x86_model) { 1372 switch (boot_cpu_data.x86_model) {
1373 case 45: /* Sandy Bridge-EP */
1374 pci_uncores = snbep_pci_uncores;
1375 uncore_pci_driver = &snbep_uncore_pci_driver;
1376 snbep_pci2phy_map_init();
1377 break;
897 default: 1378 default:
898 return 0; 1379 return 0;
899 } 1380 }
@@ -1155,6 +1636,9 @@ static int __init uncore_cpu_init(void)
1155 case 42: /* Sandy Bridge */ 1636 case 42: /* Sandy Bridge */
1156 msr_uncores = snb_msr_uncores; 1637 msr_uncores = snb_msr_uncores;
1157 break; 1638 break;
1639 case 45: /* Sandy Birdge-EP */
1640 msr_uncores = snbep_msr_uncores;
1641 break;
1158 default: 1642 default:
1159 return 0; 1643 return 0;
1160 } 1644 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index aa01df87b8de..4d52db0d1dfe 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -65,6 +65,92 @@
65#define NHM_UNC_PERFEVTSEL0 0x3c0 65#define NHM_UNC_PERFEVTSEL0 0x3c0
66#define NHM_UNC_UNCORE_PMC0 0x3b0 66#define NHM_UNC_UNCORE_PMC0 0x3b0
67 67
68/* SNB-EP Box level control */
69#define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
70#define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1)
71#define SNBEP_PMON_BOX_CTL_FRZ (1 << 8)
72#define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16)
73#define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
74 SNBEP_PMON_BOX_CTL_RST_CTRS | \
75 SNBEP_PMON_BOX_CTL_FRZ_EN)
76/* SNB-EP event control */
77#define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
78#define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
79#define SNBEP_PMON_CTL_RST (1 << 17)
80#define SNBEP_PMON_CTL_EDGE_DET (1 << 18)
81#define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21) /* only for QPI */
82#define SNBEP_PMON_CTL_EN (1 << 22)
83#define SNBEP_PMON_CTL_INVERT (1 << 23)
84#define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
85#define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
86 SNBEP_PMON_CTL_UMASK_MASK | \
87 SNBEP_PMON_CTL_EDGE_DET | \
88 SNBEP_PMON_CTL_INVERT | \
89 SNBEP_PMON_CTL_TRESH_MASK)
90
91/* SNB-EP Ubox event control */
92#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
93#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \
94 (SNBEP_PMON_CTL_EV_SEL_MASK | \
95 SNBEP_PMON_CTL_UMASK_MASK | \
96 SNBEP_PMON_CTL_EDGE_DET | \
97 SNBEP_PMON_CTL_INVERT | \
98 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
99
100/* SNB-EP PCU event control */
101#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
102#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
103#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30)
104#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31)
105#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
106 (SNBEP_PMON_CTL_EV_SEL_MASK | \
107 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
108 SNBEP_PMON_CTL_EDGE_DET | \
109 SNBEP_PMON_CTL_INVERT | \
110 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
111 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
112 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
113
114/* SNB-EP pci control register */
115#define SNBEP_PCI_PMON_BOX_CTL 0xf4
116#define SNBEP_PCI_PMON_CTL0 0xd8
117/* SNB-EP pci counter register */
118#define SNBEP_PCI_PMON_CTR0 0xa0
119
120/* SNB-EP home agent register */
121#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40
122#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44
123#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48
124/* SNB-EP memory controller register */
125#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0
126#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0
127/* SNB-EP QPI register */
128#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228
129#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c
130#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238
131#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c
132
133/* SNB-EP Ubox register */
134#define SNBEP_U_MSR_PMON_CTR0 0xc16
135#define SNBEP_U_MSR_PMON_CTL0 0xc10
136
137#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08
138#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09
139
140/* SNB-EP Cbo register */
141#define SNBEP_C0_MSR_PMON_CTR0 0xd16
142#define SNBEP_C0_MSR_PMON_CTL0 0xd10
143#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
144#define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
145#define SNBEP_CBO_MSR_OFFSET 0x20
146
147/* SNB-EP PCU register */
148#define SNBEP_PCU_MSR_PMON_CTR0 0xc36
149#define SNBEP_PCU_MSR_PMON_CTL0 0xc30
150#define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
151#define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
152#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
153#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
68 154
69struct intel_uncore_ops; 155struct intel_uncore_ops;
70struct intel_uncore_pmu; 156struct intel_uncore_pmu;
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab741b0d0074..5f187026b812 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2755,6 +2755,17 @@
2755#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27 2755#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
2756#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e 2756#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
2757#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f 2757#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
2758#define PCI_DEVICE_ID_INTEL_UNC_HA 0x3c46
2759#define PCI_DEVICE_ID_INTEL_UNC_IMC0 0x3cb0
2760#define PCI_DEVICE_ID_INTEL_UNC_IMC1 0x3cb1
2761#define PCI_DEVICE_ID_INTEL_UNC_IMC2 0x3cb4
2762#define PCI_DEVICE_ID_INTEL_UNC_IMC3 0x3cb5
2763#define PCI_DEVICE_ID_INTEL_UNC_QPI0 0x3c41
2764#define PCI_DEVICE_ID_INTEL_UNC_QPI1 0x3c42
2765#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43
2766#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44
2767#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
2768#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
2758#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f 2769#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
2759#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 2770#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
2760#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 2771#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 09:00:35 -0500