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authorOlof Johansson <olof@lixom.net>2012-05-10 02:43:04 -0400
committerOlof Johansson <olof@lixom.net>2012-05-10 02:43:04 -0400
commit7488185d0777ef84be7b365b08037fc7213010f6 (patch)
treec23a3db331693f783228c2f5afb38fed26ac1205
parentb664ae6ff92f7ba5c597d4f1b74d478d712c01c4 (diff)
parentaef7704c6cc36db9618603b22194def441d30432 (diff)
Merge branch 'for-3.5/gpio-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/pinctrl
By Stephen Warren via Stephen Warren * 'for-3.5/gpio-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: pinctrl: tegra: error reporting cleanup pinctrl: tegra: debugfs enhancements pinctrl: tegra: refactor probe handling ARM: dt: tegra20: add pinmux to device tree ARM: dt: tegra cardhu: add pinmux to device tree ARM: tegra: Remove pre-pinctrl pinmux driver ARM: tegra: Switch to new pinctrl driver gpio: tegra: Hide tegra_gpio_enable/disable() ARM: tegra: seaboard: Don't gpio_request() ISL29018_IRQ gpio: tegra: configure pins during irq_set_type ARM: tegra: Remove VBUS_GPIO handling from board files usb: ehci-tegra: Add vbus_gpio to platform data
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts44
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts224
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts220
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts243
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts230
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts230
-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c31
-rw-r--r--arch/arm/mach-tegra/board-harmony-pinmux.c266
-rw-r--r--arch/arm/mach-tegra/board-paz00-pinmux.c263
-rw-r--r--arch/arm/mach-tegra/board-pinmux.c105
-rw-r--r--arch/arm/mach-tegra/board-pinmux.h40
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c346
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c21
-rw-r--r--arch/arm/mach-tegra/board-trimslice-pinmux.c264
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c15
-rw-r--r--arch/arm/mach-tegra/devices.c5
-rw-r--r--arch/arm/mach-tegra/include/mach/gpio-tegra.h9
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra20.h184
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra30.h320
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h302
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra20-tables.c244
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra30-tables.c376
-rw-r--r--arch/arm/mach-tegra/pinmux.c987
-rw-r--r--arch/arm/mach-tegra/usb_phy.c1
-rw-r--r--drivers/gpio/gpio-tegra.c39
-rw-r--r--drivers/mmc/host/sdhci-tegra.c24
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c236
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h23
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c40
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c40
-rw-r--r--drivers/usb/host/ehci-tegra.c13
-rw-r--r--include/linux/platform_data/tegra_usb.h1
33 files changed, 2055 insertions, 3334 deletions
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb7558459..0a9f34a2c3aa 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -10,6 +10,50 @@
10 reg = < 0x80000000 0x40000000 >; 10 reg = < 0x80000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
54 };
55 };
56
13 serial@70006000 { 57 serial@70006000 {
14 clock-frequency = < 408000000 >; 58 clock-frequency = < 408000000 >;
15 }; 59 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447dc0202..1a0b1f182944 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,6 +10,230 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
32 "spia", "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc";
69 nvidia,function = "i2c2";
70 };
71 dta {
72 nvidia,pins = "dta", "dtd";
73 nvidia,function = "sdio2";
74 };
75 dtb {
76 nvidia,pins = "dtb", "dtc", "dte";
77 nvidia,function = "rsvd1";
78 };
79 dtf {
80 nvidia,pins = "dtf";
81 nvidia,function = "i2c3";
82 };
83 gmc {
84 nvidia,pins = "gmc";
85 nvidia,function = "uartd";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint", "pta";
97 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uarta";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
114 "ld3", "ld4", "ld5", "ld6", "ld7",
115 "ld8", "ld9", "ld10", "ld11", "ld12",
116 "ld13", "ld14", "ld15", "ld16", "ld17",
117 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
118 "lhs", "lm0", "lm1", "lpp", "lpw0",
119 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
120 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
121 "lvs";
122 nvidia,function = "displaya";
123 };
124 owc {
125 nvidia,pins = "owc", "spdi", "spdo", "uac";
126 nvidia,function = "rsvd2";
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 };
132 rm {
133 nvidia,pins = "rm";
134 nvidia,function = "i2c1";
135 };
136 sdb {
137 nvidia,pins = "sdb", "sdc", "sdd";
138 nvidia,function = "pwm";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 slxc {
145 nvidia,pins = "slxc", "slxd";
146 nvidia,function = "spdif";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spif";
150 nvidia,function = "spi1";
151 };
152 spig {
153 nvidia,pins = "spig", "spih";
154 nvidia,function = "spi2_alt";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab", "uda";
158 nvidia,function = "ulpi";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 conf_ata {
169 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
170 "cdev1", "dap1", "dtb", "gma", "gmb",
171 "gmc", "gmd", "gme", "gpu7", "gpv",
172 "i2cp", "pta", "rm", "slxa", "slxk",
173 "spia", "spib";
174 nvidia,pull = <0>;
175 nvidia,tristate = <0>;
176 };
177 conf_cdev2 {
178 nvidia,pins = "cdev2", "csus", "spid", "spif";
179 nvidia,pull = <1>;
180 nvidia,tristate = <1>;
181 };
182 conf_ck32 {
183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185 nvidia,pull = <0>;
186 };
187 conf_crtp {
188 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
189 "dtc", "dte", "dtf", "gpu", "sdio1",
190 "slxc", "slxd", "spdi", "spdo", "spig",
191 "uac", "uda";
192 nvidia,pull = <0>;
193 nvidia,tristate = <1>;
194 };
195 conf_ddc {
196 nvidia,pins = "ddc", "dta", "dtd", "kbca",
197 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
198 "sdc";
199 nvidia,pull = <2>;
200 nvidia,tristate = <0>;
201 };
202 conf_hdint {
203 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
204 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
205 "lvp0", "owc", "sdb";
206 nvidia,tristate = <1>;
207 };
208 conf_irrx {
209 nvidia,pins = "irrx", "irtx", "sdd", "spic",
210 "spie", "spih", "uaa", "uab", "uad",
211 "uca", "ucb";
212 nvidia,pull = <2>;
213 nvidia,tristate = <1>;
214 };
215 conf_lc {
216 nvidia,pins = "lc", "ls";
217 nvidia,pull = <2>;
218 };
219 conf_ld0 {
220 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
221 "ld5", "ld6", "ld7", "ld8", "ld9",
222 "ld10", "ld11", "ld12", "ld13", "ld14",
223 "ld15", "ld16", "ld17", "ldi", "lhp0",
224 "lhp1", "lhp2", "lhs", "lm0", "lpp",
225 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
226 "lvs", "pmc";
227 nvidia,tristate = <0>;
228 };
229 conf_ld17_0 {
230 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
231 "ld23_22";
232 nvidia,pull = <1>;
233 };
234 };
235 };
236
13 pmc@7000f400 { 237 pmc@7000f400 {
14 nvidia,invert-interrupt; 238 nvidia,invert-interrupt;
15 }; 239 };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb469d4..10943fb2561c 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -10,6 +10,226 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atc", "atd", "ate",
20 "dap2", "gmb", "gmc", "gmd", "spia",
21 "spib", "spic", "spid", "spie";
22 nvidia,function = "gmi";
23 };
24 atb {
25 nvidia,pins = "atb", "gma", "gme";
26 nvidia,function = "sdio4";
27 };
28 cdev1 {
29 nvidia,pins = "cdev1";
30 nvidia,function = "plla_out";
31 };
32 cdev2 {
33 nvidia,pins = "cdev2";
34 nvidia,function = "pllp_out4";
35 };
36 crtp {
37 nvidia,pins = "crtp";
38 nvidia,function = "crt";
39 };
40 csus {
41 nvidia,pins = "csus";
42 nvidia,function = "pllc_out1";
43 };
44 dap1 {
45 nvidia,pins = "dap1";
46 nvidia,function = "dap1";
47 };
48 dap3 {
49 nvidia,pins = "dap3";
50 nvidia,function = "dap3";
51 };
52 dap4 {
53 nvidia,pins = "dap4";
54 nvidia,function = "dap4";
55 };
56 ddc {
57 nvidia,pins = "ddc";
58 nvidia,function = "i2c2";
59 };
60 dta {
61 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
62 nvidia,function = "rsvd1";
63 };
64 dtf {
65 nvidia,pins = "dtf";
66 nvidia,function = "i2c3";
67 };
68 gpu {
69 nvidia,pins = "gpu", "sdb", "sdd";
70 nvidia,function = "pwm";
71 };
72 gpu7 {
73 nvidia,pins = "gpu7";
74 nvidia,function = "rtck";
75 };
76 gpv {
77 nvidia,pins = "gpv", "slxa", "slxk";
78 nvidia,function = "pcie";
79 };
80 hdint {
81 nvidia,pins = "hdint", "pta";
82 nvidia,function = "hdmi";
83 };
84 i2cp {
85 nvidia,pins = "i2cp";
86 nvidia,function = "i2cp";
87 };
88 irrx {
89 nvidia,pins = "irrx", "irtx";
90 nvidia,function = "uarta";
91 };
92 kbca {
93 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
94 nvidia,function = "kbc";
95 };
96 kbcb {
97 nvidia,pins = "kbcb", "kbcd";
98 nvidia,function = "sdio2";
99 };
100 lcsn {
101 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
102 "ld3", "ld4", "ld5", "ld6", "ld7",
103 "ld8", "ld9", "ld10", "ld11", "ld12",
104 "ld13", "ld14", "ld15", "ld16", "ld17",
105 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
106 "lhs", "lm0", "lm1", "lpp", "lpw0",
107 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
108 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
109 "lvs";
110 nvidia,function = "displaya";
111 };
112 owc {
113 nvidia,pins = "owc";
114 nvidia,function = "owr";
115 };
116 pmc {
117 nvidia,pins = "pmc";
118 nvidia,function = "pwr_on";
119 };
120 rm {
121 nvidia,pins = "rm";
122 nvidia,function = "i2c1";
123 };
124 sdc {
125 nvidia,pins = "sdc";
126 nvidia,function = "twc";
127 };
128 sdio1 {
129 nvidia,pins = "sdio1";
130 nvidia,function = "sdio1";
131 };
132 slxc {
133 nvidia,pins = "slxc", "slxd";
134 nvidia,function = "spi4";
135 };
136 spdi {
137 nvidia,pins = "spdi", "spdo";
138 nvidia,function = "rsvd2";
139 };
140 spif {
141 nvidia,pins = "spif", "uac";
142 nvidia,function = "rsvd4";
143 };
144 spig {
145 nvidia,pins = "spig", "spih";
146 nvidia,function = "spi2_alt";
147 };
148 uaa {
149 nvidia,pins = "uaa", "uab", "uda";
150 nvidia,function = "ulpi";
151 };
152 uad {
153 nvidia,pins = "uad";
154 nvidia,function = "spdif";
155 };
156 uca {
157 nvidia,pins = "uca", "ucb";
158 nvidia,function = "uartc";
159 };
160 conf_ata {
161 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
162 "cdev1", "dap1", "dap2", "dtf", "gma",
163 "gmb", "gmc", "gmd", "gme", "gpu",
164 "gpu7", "gpv", "i2cp", "pta", "rm",
165 "sdio1", "slxk", "spdo", "uac", "uda";
166 nvidia,pull = <0>;
167 nvidia,tristate = <0>;
168 };
169 conf_cdev2 {
170 nvidia,pins = "cdev2";
171 nvidia,pull = <1>;
172 nvidia,tristate = <0>;
173 };
174 conf_ck32 {
175 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
176 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
177 nvidia,pull = <0>;
178 };
179 conf_crtp {
180 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
181 "dtc", "dte", "slxa", "slxc", "slxd",
182 "spdi";
183 nvidia,pull = <0>;
184 nvidia,tristate = <1>;
185 };
186 conf_csus {
187 nvidia,pins = "csus", "spia", "spib", "spid",
188 "spif";
189 nvidia,pull = <1>;
190 nvidia,tristate = <1>;
191 };
192 conf_ddc {
193 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
194 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
195 "spic", "spig", "uaa", "uab";
196 nvidia,pull = <2>;
197 nvidia,tristate = <0>;
198 };
199 conf_dta {
200 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
201 "spie", "spih", "uad", "uca", "ucb";
202 nvidia,pull = <2>;
203 nvidia,tristate = <1>;
204 };
205 conf_hdint {
206 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
207 "ld3", "ld4", "ld5", "ld6", "ld7",
208 "ld8", "ld9", "ld10", "ld11", "ld12",
209 "ld13", "ld14", "ld15", "ld16", "ld17",
210 "ldc", "ldi", "lhs", "lsc0", "lspi",
211 "lvs", "pmc";
212 nvidia,tristate = <0>;
213 };
214 conf_lc {
215 nvidia,pins = "lc", "ls";
216 nvidia,pull = <2>;
217 };
218 conf_lcsn {
219 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
220 "lm0", "lm1", "lpp", "lpw0", "lpw1",
221 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
222 "lvp0", "lvp1", "sdb";
223 nvidia,tristate = <1>;
224 };
225 conf_ld17_0 {
226 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
227 "ld23_22";
228 nvidia,pull = <1>;
229 };
230 };
231 };
232
13 i2c@7000c000 { 233 i2c@7000c000 {
14 clock-frequency = <400000>; 234 clock-frequency = <400000>;
15 235
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a171c2..ec33116f5df9 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -11,6 +11,249 @@
11 reg = < 0x00000000 0x40000000 >; 11 reg = < 0x00000000 0x40000000 >;
12 }; 12 };
13 13
14 pinmux@70000000 {
15 pinctrl-names = "default";
16 pinctrl-0 = <&state_default>;
17
18 state_default: pinmux {
19 ata {
20 nvidia,pins = "ata";
21 nvidia,function = "ide";
22 };
23 atb {
24 nvidia,pins = "atb", "gma", "gme";
25 nvidia,function = "sdio4";
26 };
27 atc {
28 nvidia,pins = "atc";
29 nvidia,function = "nand";
30 };
31 atd {
32 nvidia,pins = "atd", "ate", "gmb", "spia",
33 "spib", "spic";
34 nvidia,function = "gmi";
35 };
36 cdev1 {
37 nvidia,pins = "cdev1";
38 nvidia,function = "plla_out";
39 };
40 cdev2 {
41 nvidia,pins = "cdev2";
42 nvidia,function = "pllp_out4";
43 };
44 crtp {
45 nvidia,pins = "crtp", "lm1";
46 nvidia,function = "crt";
47 };
48 csus {
49 nvidia,pins = "csus";
50 nvidia,function = "vi_sensor_clk";
51 };
52 dap1 {
53 nvidia,pins = "dap1";
54 nvidia,function = "dap1";
55 };
56 dap2 {
57 nvidia,pins = "dap2";
58 nvidia,function = "dap2";
59 };
60 dap3 {
61 nvidia,pins = "dap3";
62 nvidia,function = "dap3";
63 };
64 dap4 {
65 nvidia,pins = "dap4";
66 nvidia,function = "dap4";
67 };
68 ddc {
69 nvidia,pins = "ddc", "owc", "spdi", "spdo",
70 "uac";
71 nvidia,function = "rsvd2";
72 };
73 dta {
74 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
75 nvidia,function = "vi";
76 };
77 dtf {
78 nvidia,pins = "dtf";
79 nvidia,function = "i2c3";
80 };
81 gmc {
82 nvidia,pins = "gmc";
83 nvidia,function = "uartd";
84 };
85 gmd {
86 nvidia,pins = "gmd";
87 nvidia,function = "sflash";
88 };
89 gpu {
90 nvidia,pins = "gpu";
91 nvidia,function = "pwm";
92 };
93 gpu7 {
94 nvidia,pins = "gpu7";
95 nvidia,function = "rtck";
96 };
97 gpv {
98 nvidia,pins = "gpv", "slxa", "slxk";
99 nvidia,function = "pcie";
100 };
101 hdint {
102 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
103 "lsck", "lsda", "pta";
104 nvidia,function = "hdmi";
105 };
106 i2cp {
107 nvidia,pins = "i2cp";
108 nvidia,function = "i2cp";
109 };
110 irrx {
111 nvidia,pins = "irrx", "irtx";
112 nvidia,function = "uartb";
113 };
114 kbca {
115 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
116 "kbce", "kbcf";
117 nvidia,function = "kbc";
118 };
119 lcsn {
120 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
121 "lsdi", "lvp0";
122 nvidia,function = "rsvd4";
123 };
124 ld0 {
125 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
126 "ld5", "ld6", "ld7", "ld8", "ld9",
127 "ld10", "ld11", "ld12", "ld13", "ld14",
128 "ld15", "ld16", "ld17", "ldi", "lhp0",
129 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
130 "lspi", "lvp1", "lvs";
131 nvidia,function = "displaya";
132 };
133 pmc {
134 nvidia,pins = "pmc";
135 nvidia,function = "pwr_on";
136 };
137 rm {
138 nvidia,pins = "rm";
139 nvidia,function = "i2c1";
140 };
141 sdb {
142 nvidia,pins = "sdb", "sdc", "sdd";
143 nvidia,function = "sdio3";
144 };
145 sdio1 {
146 nvidia,pins = "sdio1";
147 nvidia,function = "sdio1";
148 };
149 slxc {
150 nvidia,pins = "slxc", "slxd";
151 nvidia,function = "spdif";
152 };
153 spid {
154 nvidia,pins = "spid", "spie", "spif";
155 nvidia,function = "spi1";
156 };
157 spig {
158 nvidia,pins = "spig", "spih";
159 nvidia,function = "spi2_alt";
160 };
161 uaa {
162 nvidia,pins = "uaa", "uab", "uda";
163 nvidia,function = "ulpi";
164 };
165 uad {
166 nvidia,pins = "uad";
167 nvidia,function = "irda";
168 };
169 uca {
170 nvidia,pins = "uca", "ucb";
171 nvidia,function = "uartc";
172 };
173 conf_ata {
174 nvidia,pins = "ata", "atb", "atc", "atd",
175 "cdev1", "cdev2", "dap1", "dap2",
176 "dap4", "dtf", "gma", "gmc", "gmd",
177 "gme", "gpu", "gpu7", "i2cp", "irrx",
178 "irtx", "pta", "rm", "sdc", "sdd",
179 "slxd", "slxk", "spdi", "spdo", "uac",
180 "uad", "uca", "ucb", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <0>;
183 };
184 conf_ate {
185 nvidia,pins = "ate", "csus", "dap3", "ddc",
186 "gpv", "owc", "slxc", "spib", "spid",
187 "spie";
188 nvidia,pull = <0>;
189 nvidia,tristate = <1>;
190 };
191 conf_ck32 {
192 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
193 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
194 nvidia,pull = <0>;
195 };
196 conf_crtp {
197 nvidia,pins = "crtp", "gmb", "slxa", "spia",
198 "spig", "spih";
199 nvidia,pull = <2>;
200 nvidia,tristate = <1>;
201 };
202 conf_dta {
203 nvidia,pins = "dta", "dtb", "dtc", "dtd";
204 nvidia,pull = <1>;
205 nvidia,tristate = <0>;
206 };
207 conf_dte {
208 nvidia,pins = "dte", "spif";
209 nvidia,pull = <1>;
210 nvidia,tristate = <1>;
211 };
212 conf_hdint {
213 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
214 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
215 "lvp0";
216 nvidia,tristate = <1>;
217 };
218 conf_kbca {
219 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
220 "kbce", "kbcf", "sdio1", "spic", "uaa",
221 "uab";
222 nvidia,pull = <2>;
223 nvidia,tristate = <0>;
224 };
225 conf_lc {
226 nvidia,pins = "lc", "ls";
227 nvidia,pull = <2>;
228 };
229 conf_ld0 {
230 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
231 "ld5", "ld6", "ld7", "ld8", "ld9",
232 "ld10", "ld11", "ld12", "ld13", "ld14",
233 "ld15", "ld16", "ld17", "ldi", "lhp0",
234 "lhp1", "lhp2", "lhs", "lm0", "lpp",
235 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
236 "lvs", "pmc", "sdb";
237 nvidia,tristate = <0>;
238 };
239 conf_ld17_0 {
240 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
241 "ld23_22";
242 nvidia,pull = <1>;
243 };
244 drive_sdio1 {
245 nvidia,pins = "drive_sdio1";
246 nvidia,high-speed-mode = <0>;
247 nvidia,schmitt = <0>;
248 nvidia,low-power-mode = <3>;
249 nvidia,pull-down-strength = <31>;
250 nvidia,pull-up-strength = <31>;
251 nvidia,slew-rate-rising = <3>;
252 nvidia,slew-rate-falling = <3>;
253 };
254 };
255 };
256
14 i2c@7000c000 { 257 i2c@7000c000 {
15 clock-frequency = <400000>; 258 clock-frequency = <400000>;
16 259
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 252476867b54..98efd5b0d7f9 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -10,6 +10,236 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc", "gmb";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gme", "pta";
32 nvidia,function = "gmi";
33 };
34 cdev1 {
35 nvidia,pins = "cdev1";
36 nvidia,function = "plla_out";
37 };
38 cdev2 {
39 nvidia,pins = "cdev2";
40 nvidia,function = "pllp_out4";
41 };
42 crtp {
43 nvidia,pins = "crtp";
44 nvidia,function = "crt";
45 };
46 csus {
47 nvidia,pins = "csus";
48 nvidia,function = "vi_sensor_clk";
49 };
50 dap1 {
51 nvidia,pins = "dap1";
52 nvidia,function = "dap1";
53 };
54 dap2 {
55 nvidia,pins = "dap2";
56 nvidia,function = "dap2";
57 };
58 dap3 {
59 nvidia,pins = "dap3";
60 nvidia,function = "dap3";
61 };
62 dap4 {
63 nvidia,pins = "dap4";
64 nvidia,function = "dap4";
65 };
66 ddc {
67 nvidia,pins = "ddc";
68 nvidia,function = "i2c2";
69 };
70 dta {
71 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
72 nvidia,function = "vi";
73 };
74 dtf {
75 nvidia,pins = "dtf";
76 nvidia,function = "i2c3";
77 };
78 gmc {
79 nvidia,pins = "gmc", "gmd";
80 nvidia,function = "sflash";
81 };
82 gpu {
83 nvidia,pins = "gpu";
84 nvidia,function = "uarta";
85 };
86 gpu7 {
87 nvidia,pins = "gpu7";
88 nvidia,function = "rtck";
89 };
90 gpv {
91 nvidia,pins = "gpv", "slxa", "slxk";
92 nvidia,function = "pcie";
93 };
94 hdint {
95 nvidia,pins = "hdint";
96 nvidia,function = "hdmi";
97 };
98 i2cp {
99 nvidia,pins = "i2cp";
100 nvidia,function = "i2cp";
101 };
102 irrx {
103 nvidia,pins = "irrx", "irtx";
104 nvidia,function = "uartb";
105 };
106 kbca {
107 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
108 "kbce", "kbcf";
109 nvidia,function = "kbc";
110 };
111 lcsn {
112 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
113 "ld3", "ld4", "ld5", "ld6", "ld7",
114 "ld8", "ld9", "ld10", "ld11", "ld12",
115 "ld13", "ld14", "ld15", "ld16", "ld17",
116 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
117 "lhs", "lm0", "lm1", "lpp", "lpw0",
118 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
119 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "rsvd2";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd";
137 nvidia,function = "pwm";
138 };
139 sdio1 {
140 nvidia,pins = "sdio1";
141 nvidia,function = "sdio1";
142 };
143 slxc {
144 nvidia,pins = "slxc", "slxd";
145 nvidia,function = "sdio3";
146 };
147 spdi {
148 nvidia,pins = "spdi", "spdo";
149 nvidia,function = "spdif";
150 };
151 spia {
152 nvidia,pins = "spia", "spib", "spic";
153 nvidia,function = "spi2";
154 };
155 spid {
156 nvidia,pins = "spid", "spie", "spif";
157 nvidia,function = "spi1";
158 };
159 spig {
160 nvidia,pins = "spig", "spih";
161 nvidia,function = "spi2_alt";
162 };
163 uaa {
164 nvidia,pins = "uaa", "uab", "uda";
165 nvidia,function = "ulpi";
166 };
167 uad {
168 nvidia,pins = "uad";
169 nvidia,function = "irda";
170 };
171 uca {
172 nvidia,pins = "uca", "ucb";
173 nvidia,function = "uartc";
174 };
175 conf_ata {
176 nvidia,pins = "ata", "atc", "atd", "ate",
177 "crtp", "dap2", "dap3", "dap4", "dta",
178 "dtb", "dtc", "dtd", "dte", "gmb",
179 "gme", "i2cp", "pta", "slxc", "slxd",
180 "spdi", "spdo", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <1>;
183 };
184 conf_atb {
185 nvidia,pins = "atb", "cdev1", "dap1", "gma",
186 "gmc", "gmd", "gpu", "gpu7", "gpv",
187 "sdio1", "slxa", "slxk", "uac";
188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
191 conf_cdev2 {
192 nvidia,pins = "cdev2", "csus", "spia", "spib",
193 "spid", "spif";
194 nvidia,pull = <1>;
195 nvidia,tristate = <1>;
196 };
197 conf_ck32 {
198 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
199 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
200 nvidia,pull = <0>;
201 };
202 conf_ddc {
203 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
204 nvidia,pull = <2>;
205 nvidia,tristate = <0>;
206 };
207 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "pmc";
211 nvidia,tristate = <1>;
212 };
213 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
215 "kbcc", "kbcd", "kbce", "kbcf", "owc",
216 "spic", "spie", "spig", "spih", "uaa",
217 "uab", "uad", "uca", "ucb";
218 nvidia,pull = <2>;
219 nvidia,tristate = <1>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
232 "lvs", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
13 i2c@7000c000 { 243 i2c@7000c000 {
14 clock-frequency = <400000>; 244 clock-frequency = <400000>;
15 }; 245 };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff8728e90..71eb2e50a668 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -10,6 +10,236 @@
10 reg = < 0x00000000 0x40000000 >; 10 reg = < 0x00000000 0x40000000 >;
11 }; 11 };
12 12
13 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "pta";
102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uartb";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
119 "lsdi", "lvp0";
120 nvidia,function = "rsvd4";
121 };
122 ld0 {
123 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
124 "ld5", "ld6", "ld7", "ld8", "ld9",
125 "ld10", "ld11", "ld12", "ld13", "ld14",
126 "ld15", "ld16", "ld17", "ldi", "lhp0",
127 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
128 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
142 nvidia,function = "sdio3";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxd {
149 nvidia,pins = "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd",
174 "cdev1", "cdev2", "dap1", "dap2",
175 "dap4", "ddc", "dtf", "gma", "gmc",
176 "gme", "gpu", "gpu7", "i2cp", "irrx",
177 "irtx", "pta", "rm", "sdc", "sdd",
178 "slxc", "slxd", "slxk", "spdi", "spdo",
179 "uac", "uad", "uca", "ucb", "uda";
180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
183 conf_ate {
184 nvidia,pins = "ate", "csus", "dap3", "gmd",
185 "gpv", "owc", "spia", "spib", "spic",
186 "spid", "spie", "spig";
187 nvidia,pull = <0>;
188 nvidia,tristate = <1>;
189 };
190 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>;
194 };
195 conf_crtp {
196 nvidia,pins = "crtp", "gmb", "slxa", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
213 nvidia,tristate = <1>;
214 };
215 conf_kbca {
216 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
217 "kbce", "kbcf", "sdio1", "uaa", "uab";
218 nvidia,pull = <2>;
219 nvidia,tristate = <0>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
232 "lvp1", "lvs", "pmc", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
13 i2c@7000c000 { 243 i2c@7000c000 {
14 clock-frequency = <400000>; 244 clock-frequency = <400000>;
15 245
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d87d968115ec..2eb4445ddb14 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -5,7 +5,6 @@ obj-y += io.o
5obj-y += irq.o 5obj-y += irq.o
6obj-y += clock.o 6obj-y += clock.o
7obj-y += timer.o 7obj-y += timer.o
8obj-y += pinmux.o
9obj-y += fuse.o 8obj-y += fuse.o
10obj-y += pmc.o 9obj-y += pmc.o
11obj-y += flowctrl.o 10obj-y += flowctrl.o
@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o 13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o 16obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 18obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 0952494f481a..5b9d5f4c0686 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -47,15 +47,7 @@
47#include "clock.h" 47#include "clock.h"
48#include "devices.h" 48#include "devices.h"
49 49
50void harmony_pinmux_init(void);
51void paz00_pinmux_init(void);
52void seaboard_pinmux_init(void);
53void trimslice_pinmux_init(void);
54void ventana_pinmux_init(void);
55
56struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 50struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
57 OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
58 OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
59 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), 51 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
60 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), 52 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
61 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), 53 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -95,33 +87,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
95 {} 87 {}
96}; 88};
97 89
98static struct {
99 char *machine;
100 void (*init)(void);
101} pinmux_configs[] = {
102 { "compulab,trimslice", trimslice_pinmux_init },
103 { "nvidia,harmony", harmony_pinmux_init },
104 { "compal,paz00", paz00_pinmux_init },
105 { "nvidia,seaboard", seaboard_pinmux_init },
106 { "nvidia,ventana", ventana_pinmux_init },
107};
108
109static void __init tegra_dt_init(void) 90static void __init tegra_dt_init(void)
110{ 91{
111 int i;
112
113 tegra_clk_init_from_table(tegra_dt_clk_init_table); 92 tegra_clk_init_from_table(tegra_dt_clk_init_table);
114 93
115 for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
116 if (of_machine_is_compatible(pinmux_configs[i].machine)) {
117 pinmux_configs[i].init();
118 break;
119 }
120 }
121
122 WARN(i == ARRAY_SIZE(pinmux_configs),
123 "Unknown platform! Pinmuxing not initialized\n");
124
125 /* 94 /*
126 * Finished with the static registrations now; fill in the missing 95 * Finished with the static registrations now; fill in the missing
127 * devices 96 * devices
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 1af85bccc0f1..83d420fbc58c 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-harmony-pinmux.c 2 * arch/arm/mach-tegra/board-harmony-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,153 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 19
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-harmony.h" 20#include "board-harmony.h"
26#include "board-pinmux.h" 21#include "board-pinmux.h"
27 22
28static struct tegra_pingroup_config harmony_pinmux[] = { 23static struct pinctrl_map harmony_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 38 TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 41 TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 49 TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
145}; 140 TEGRA_MAP_CONF("ls", up, na),
146 141 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 142 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, 143 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, 144 TEGRA_MAP_CONF("ld21_20", down, na),
150 { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, 145 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TEGRA_GPIO_SD4_CD, .enable = true },
152 { .gpio = TEGRA_GPIO_SD4_WP, .enable = true },
153 { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true },
154 { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
155 { .gpio = TEGRA_GPIO_HP_DET, .enable = true },
156 { .gpio = TEGRA_GPIO_INT_MIC_EN, .enable = true },
157 { .gpio = TEGRA_GPIO_EXT_MIC_EN, .enable = true },
158}; 146};
159 147
160static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
161 .pgs = harmony_pinmux, 149 .maps = harmony_map,
162 .pg_count = ARRAY_SIZE(harmony_pinmux), 150 .map_count = ARRAY_SIZE(harmony_map),
163 .gpios = gpio_table,
164 .gpio_count = ARRAY_SIZE(gpio_table),
165}; 151};
166 152
167void harmony_pinmux_init(void) 153void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572dcea4..6f1111b48e7c 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-paz00-pinmux.c 2 * arch/arm/mach-tegra/board-paz00-pinmux.c
3 * 3 *
4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de> 4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -15,150 +16,138 @@
15 */ 16 */
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 19
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-paz00.h" 20#include "board-paz00.h"
26#include "board-pinmux.h" 21#include "board-pinmux.h"
27 22
28static struct tegra_pingroup_config paz00_pinmux[] = { 23static struct pinctrl_map paz00_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 25 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 26 TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 27 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 29 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 30 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_PLLC_OUT1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 32 TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 33 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 34 TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 36 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 37 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_RSVD1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 42 TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 44 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 47 TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 52 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 53 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 54 TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 55 TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 56 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 57 TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 58 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 59 TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 60 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 61 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 62 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 80 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 83 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 84 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 85 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 88 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 89 TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 91 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 92 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 93 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 97 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 98 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 99 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 100 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 101 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 103 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 106 TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_TWC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 107 TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 108 TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 112 TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 118 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 122 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 124 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 126 TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 139 TEGRA_MAP_CONF("xm2d", none, na),
145}; 140 TEGRA_MAP_CONF("ls", up, na),
146 141 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 142 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TEGRA_GPIO_SD1_CD, .enable = true }, 143 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, 144 TEGRA_MAP_CONF("ld21_20", down, na),
150 { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, 145 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TEGRA_ULPI_RST, .enable = true },
152 { .gpio = TEGRA_WIFI_PWRN, .enable = true },
153 { .gpio = TEGRA_WIFI_RST, .enable = true },
154 { .gpio = TEGRA_WIFI_LED, .enable = true },
155}; 146};
156 147
157static struct tegra_board_pinmux_conf conf = { 148static struct tegra_board_pinmux_conf conf = {
158 .pgs = paz00_pinmux, 149 .maps = paz00_map,
159 .pg_count = ARRAY_SIZE(paz00_pinmux), 150 .map_count = ARRAY_SIZE(paz00_map),
160 .gpios = gpio_table,
161 .gpio_count = ARRAY_SIZE(gpio_table),
162}; 151};
163 152
164void paz00_pinmux_init(void) 153void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe979b3..a5574c71b931 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -15,75 +15,59 @@
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/notifier.h> 17#include <linux/notifier.h>
18#include <linux/of.h>
19#include <linux/string.h> 18#include <linux/string.h>
20 19
21#include <mach/gpio-tegra.h>
22#include <mach/pinmux.h>
23
24#include "board-pinmux.h" 20#include "board-pinmux.h"
25#include "devices.h" 21#include "devices.h"
26 22
27struct tegra_board_pinmux_conf *confs[2]; 23unsigned long tegra_pincfg_pullnone_driven[2] = {
28 24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
29static void tegra_board_pinmux_setup_gpios(void) 25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
30{ 26};
31 int i;
32
33 for (i = 0; i < ARRAY_SIZE(confs); i++) {
34 if (!confs[i])
35 continue;
36
37 tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
38 }
39}
40
41static void tegra_board_pinmux_setup_pinmux(void)
42{
43 int i;
44 27
45 for (i = 0; i < ARRAY_SIZE(confs); i++) { 28unsigned long tegra_pincfg_pullnone_tristate[2] = {
46 if (!confs[i]) 29 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
47 continue; 30 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
31};
48 32
49 tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count); 33unsigned long tegra_pincfg_pullnone_na[1] = {
34 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
35};
50 36
51 if (confs[i]->drives) 37unsigned long tegra_pincfg_pullup_driven[2] = {
52 tegra_drive_pinmux_config_table(confs[i]->drives, 38 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
53 confs[i]->drive_count); 39 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
54 } 40};
55}
56 41
57static int tegra_board_pinmux_bus_notify(struct notifier_block *nb, 42unsigned long tegra_pincfg_pullup_tristate[2] = {
58 unsigned long event, void *vdev) 43 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
59{ 44 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
60 static bool had_gpio; 45};
61 static bool had_pinmux;
62 46
63 struct device *dev = vdev; 47unsigned long tegra_pincfg_pullup_na[1] = {
64 const char *devname; 48 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
49};
65 50
66 if (event != BUS_NOTIFY_BOUND_DRIVER) 51unsigned long tegra_pincfg_pulldown_driven[2] = {
67 return NOTIFY_DONE; 52 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
53 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
54};
68 55
69 devname = dev_name(dev); 56unsigned long tegra_pincfg_pulldown_tristate[2] = {
57 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
58 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
59};
70 60
71 if (!had_gpio && !strcmp(devname, GPIO_DEV)) { 61unsigned long tegra_pincfg_pulldown_na[1] = {
72 tegra_board_pinmux_setup_gpios(); 62 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
73 had_gpio = true; 63};
74 } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
75 tegra_board_pinmux_setup_pinmux();
76 had_pinmux = true;
77 }
78 64
79 if (had_gpio && had_pinmux) 65unsigned long tegra_pincfg_pullna_driven[1] = {
80 return NOTIFY_STOP_MASK; 66 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
81 else 67};
82 return NOTIFY_DONE;
83}
84 68
85static struct notifier_block nb = { 69unsigned long tegra_pincfg_pullna_tristate[1] = {
86 .notifier_call = tegra_board_pinmux_bus_notify, 70 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
87}; 71};
88 72
89static struct platform_device *devices[] = { 73static struct platform_device *devices[] = {
@@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
94void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 78void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
95 struct tegra_board_pinmux_conf *conf_b) 79 struct tegra_board_pinmux_conf *conf_b)
96{ 80{
97 confs[0] = conf_a; 81 if (conf_a)
98 confs[1] = conf_b; 82 pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
99 83 if (conf_b)
100 bus_register_notifier(&platform_bus_type, &nb); 84 pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
101 85
102 if (!of_machine_is_compatible("nvidia,tegra20")) 86 platform_add_devices(devices, ARRAY_SIZE(devices));
103 platform_add_devices(devices, ARRAY_SIZE(devices));
104} 87}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac73546f54..c5f3f3381e86 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This software is licensed under the terms of the GNU General Public 4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and 5 * License version 2, as published by the Free Software Foundation, and
@@ -15,21 +15,37 @@
15#ifndef __MACH_TEGRA_BOARD_PINMUX_H 15#ifndef __MACH_TEGRA_BOARD_PINMUX_H
16#define __MACH_TEGRA_BOARD_PINMUX_H 16#define __MACH_TEGRA_BOARD_PINMUX_H
17 17
18#define GPIO_DEV "tegra-gpio" 18#include <linux/pinctrl/machine.h>
19#define PINMUX_DEV "tegra-pinmux"
20 19
21struct tegra_pingroup_config; 20#include <mach/pinconf-tegra.h>
22struct tegra_gpio_table;
23 21
24struct tegra_board_pinmux_conf { 22#define PINMUX_DEV "tegra20-pinctrl"
25 struct tegra_pingroup_config *pgs; 23
26 int pg_count; 24#define TEGRA_MAP_MUX(_group_, _function_) \
25 PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
26
27#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
28 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
27 29
28 struct tegra_drive_pingroup_config *drives; 30#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
29 int drive_count; 31 TEGRA_MAP_MUX(_group_, _function_), \
32 TEGRA_MAP_CONF(_group_, _pull_, _drive_)
30 33
31 struct tegra_gpio_table *gpios; 34extern unsigned long tegra_pincfg_pullnone_driven[2];
32 int gpio_count; 35extern unsigned long tegra_pincfg_pullnone_tristate[2];
36extern unsigned long tegra_pincfg_pullnone_na[1];
37extern unsigned long tegra_pincfg_pullup_driven[2];
38extern unsigned long tegra_pincfg_pullup_tristate[2];
39extern unsigned long tegra_pincfg_pullup_na[1];
40extern unsigned long tegra_pincfg_pulldown_driven[2];
41extern unsigned long tegra_pincfg_pulldown_tristate[2];
42extern unsigned long tegra_pincfg_pulldown_na[1];
43extern unsigned long tegra_pincfg_pullna_driven[1];
44extern unsigned long tegra_pincfg_pullna_tristate[1];
45
46struct tegra_board_pinmux_conf {
47 struct pinctrl_map *maps;
48 int map_count;
33}; 49};
34 50
35void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a, 51void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43a14ad..11fc8a568c64 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010,2011 NVIDIA Corporation 2 * Copyright (C) 2010-2012 NVIDIA Corporation
3 * Copyright (C) 2011 Google, Inc. 3 * Copyright (C) 2011 Google, Inc.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
@@ -14,216 +14,176 @@
14 */ 14 */
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20 17
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-pinmux.h"
26#include "board-seaboard.h" 18#include "board-seaboard.h"
19#include "board-pinmux.h"
27 20
28#define DEFAULT_DRIVE(_name) \ 21static unsigned long seaboard_pincfg_drive_sdio1[] = {
29 { \ 22 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
30 .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ 23 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
31 .hsm = TEGRA_HSM_DISABLE, \ 24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
32 .schmitt = TEGRA_SCHMITT_ENABLE, \ 25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
33 .drive = TEGRA_DRIVE_DIV_1, \ 26 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
34 .pull_down = TEGRA_PULL_31, \ 27 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
35 .pull_up = TEGRA_PULL_31, \ 28 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
36 .slew_rising = TEGRA_SLEW_SLOWEST, \
37 .slew_falling = TEGRA_SLEW_SLOWEST, \
38 }
39
40static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
41 DEFAULT_DRIVE(SDIO1),
42};
43
44static struct tegra_pingroup_config common_pinmux[] = {
45 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
46 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
47 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
48 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
49 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
50 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
51 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
52 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
53 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
54 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
55 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
56 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
57 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
58 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
59 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
60 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
61 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
62 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
63 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
64 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
65 {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
66 {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
67 {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
68 {TEGRA_PINGROUP_GPU, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
69 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
70 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
71 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
72 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
73 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
74 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
75 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
76 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
77 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
78 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
79 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
80 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
81 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
82 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
83 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
84 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
85 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
86 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
87 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
88 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
89 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
90 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
91 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
92 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
93 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
94 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
95 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
96 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
97 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
98 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
99 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
100 {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
101 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
102 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
103 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
104 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
105 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
106 {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
107 {TEGRA_PINGROUP_LM1, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
108 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
109 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
110 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
111 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
112 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
113 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
114 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
115 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
116 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
117 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
118 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
119 {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
120 {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
121 {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
122 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
123 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
124 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
125 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
126 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
127 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
128 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
129 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
130 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
131 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
132 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
133 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
134 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
135 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
136 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
137 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
138 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
139 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
140 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
141 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
142 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
143 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
144 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
145 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
146 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
147 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
148};
149
150static struct tegra_pingroup_config seaboard_pinmux[] = {
151 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
152 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
153 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
154 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
155 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
156 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
157 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
158 {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
159 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
160 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
161 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
162 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
163 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
164};
165
166static struct tegra_pingroup_config ventana_pinmux[] = {
167 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
168 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
169 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
170 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
171 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
172 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
173 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
174 {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
175 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
176 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
177 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
178 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
179 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
180}; 29};
181 30
182static struct tegra_gpio_table common_gpio_table[] = { 31static struct pinctrl_map common_map[] = {
183 { .gpio = TEGRA_GPIO_SD2_CD, .enable = true }, 32 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
184 { .gpio = TEGRA_GPIO_SD2_WP, .enable = true }, 33 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
185 { .gpio = TEGRA_GPIO_SD2_POWER, .enable = true }, 34 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
186 { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true }, 35 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
36 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
37 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
38 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven),
39 TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate),
40 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate),
41 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
42 TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven),
43 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
44 TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven),
45 TEGRA_MAP_MUXCONF("dta", "vi", down, driven),
46 TEGRA_MAP_MUXCONF("dtb", "vi", down, driven),
47 TEGRA_MAP_MUXCONF("dtc", "vi", down, driven),
48 TEGRA_MAP_MUXCONF("dtd", "vi", down, driven),
49 TEGRA_MAP_MUXCONF("dte", "vi", down, tristate),
50 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
51 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
52 TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate),
53 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
54 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
55 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
56 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
57 TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate),
58 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
59 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
60 TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven),
61 TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven),
62 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
63 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
64 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
65 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
66 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
67 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
68 TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate),
69 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
70 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
71 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
72 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
73 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
74 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
75 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
76 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
77 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
78 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
79 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
80 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
81 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
82 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
83 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
84 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
85 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
86 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
87 TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate),
88 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
89 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
90 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
91 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
92 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
93 TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven),
94 TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate),
95 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
96 TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate),
97 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
98 TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate),
99 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
100 TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate),
101 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
102 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
103 TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate),
104 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
105 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
106 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
107 TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven),
108 TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven),
109 TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven),
110 TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven),
111 TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate),
112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven),
113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven),
115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
116 TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate),
117 TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate),
118 TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate),
119 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
120 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
121 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
122 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
123 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
124 TEGRA_MAP_MUXCONF("uad", "irda", none, driven),
125 TEGRA_MAP_MUXCONF("uca", "uartc", none, driven),
126 TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven),
127 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
128 TEGRA_MAP_CONF("ck32", none, na),
129 TEGRA_MAP_CONF("ddrc", none, na),
130 TEGRA_MAP_CONF("pmca", none, na),
131 TEGRA_MAP_CONF("pmcb", none, na),
132 TEGRA_MAP_CONF("pmcc", none, na),
133 TEGRA_MAP_CONF("pmcd", none, na),
134 TEGRA_MAP_CONF("pmce", none, na),
135 TEGRA_MAP_CONF("xm2c", none, na),
136 TEGRA_MAP_CONF("xm2d", none, na),
137 TEGRA_MAP_CONF("ls", up, na),
138 TEGRA_MAP_CONF("lc", up, na),
139 TEGRA_MAP_CONF("ld17_0", down, na),
140 TEGRA_MAP_CONF("ld19_18", down, na),
141 TEGRA_MAP_CONF("ld21_20", down, na),
142 TEGRA_MAP_CONF("ld23_22", down, na),
187}; 143};
188 144
189static struct tegra_gpio_table seaboard_gpio_table[] = { 145static struct pinctrl_map seaboard_map[] = {
190 { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, 146 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate),
191 { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, 147 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
192 { .gpio = TEGRA_GPIO_HP_DET, .enable = true }, 148 TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven),
193 { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, 149 TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven),
194 { .gpio = TEGRA_GPIO_USB1, .enable = true }, 150 TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate),
151 TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate),
152 TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate),
153 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
154 TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate),
155 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
156 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
157 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
195}; 158};
196 159
197static struct tegra_gpio_table ventana_gpio_table[] = { 160static struct pinctrl_map ventana_map[] = {
198 /* hp_det */ 161 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven),
199 { .gpio = TEGRA_GPIO_PW2, .enable = true }, 162 TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate),
200 /* int_mic_en */ 163 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
201 { .gpio = TEGRA_GPIO_PX0, .enable = true }, 164 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
202 /* ext_mic_en */ 165 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven),
203 { .gpio = TEGRA_GPIO_PX1, .enable = true }, 166 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
167 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
168 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven),
169 TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate),
170 TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate),
171 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
204}; 172};
205 173
206static struct tegra_board_pinmux_conf common_conf = { 174static struct tegra_board_pinmux_conf common_conf = {
207 .pgs = common_pinmux, 175 .maps = common_map,
208 .pg_count = ARRAY_SIZE(common_pinmux), 176 .map_count = ARRAY_SIZE(common_map),
209 .gpios = common_gpio_table,
210 .gpio_count = ARRAY_SIZE(common_gpio_table),
211}; 177};
212 178
213static struct tegra_board_pinmux_conf seaboard_conf = { 179static struct tegra_board_pinmux_conf seaboard_conf = {
214 .pgs = seaboard_pinmux, 180 .maps = seaboard_map,
215 .pg_count = ARRAY_SIZE(seaboard_pinmux), 181 .map_count = ARRAY_SIZE(seaboard_map),
216 .drives = seaboard_drive_pinmux,
217 .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
218 .gpios = seaboard_gpio_table,
219 .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
220}; 182};
221 183
222static struct tegra_board_pinmux_conf ventana_conf = { 184static struct tegra_board_pinmux_conf ventana_conf = {
223 .pgs = ventana_pinmux, 185 .maps = ventana_map,
224 .pg_count = ARRAY_SIZE(ventana_pinmux), 186 .map_count = ARRAY_SIZE(ventana_map),
225 .gpios = ventana_gpio_table,
226 .gpio_count = ARRAY_SIZE(ventana_gpio_table),
227}; 187};
228 188
229void seaboard_pinmux_init(void) 189void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index d669847f0485..a0184fb44222 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -24,6 +24,7 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/gpio_keys.h> 26#include <linux/gpio_keys.h>
27#include <linux/platform_data/tegra_usb.h>
27 28
28#include <sound/wm8903.h> 29#include <sound/wm8903.h>
29 30
@@ -186,20 +187,10 @@ static struct i2c_board_info __initdata wm8903_device = {
186 187
187static int seaboard_ehci_init(void) 188static int seaboard_ehci_init(void)
188{ 189{
189 int gpio_status; 190 struct tegra_ehci_platform_data *pdata;
190 191
191 gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1"); 192 pdata = tegra_ehci1_device.dev.platform_data;
192 if (gpio_status < 0) { 193 pdata->vbus_gpio = TEGRA_GPIO_USB1;
193 pr_err("VBUS_USB1 request GPIO FAILED\n");
194 WARN_ON(1);
195 }
196
197 gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
198 if (gpio_status < 0) {
199 pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
200 WARN_ON(1);
201 }
202 gpio_set_value(TEGRA_GPIO_USB1, 1);
203 194
204 platform_device_register(&tegra_ehci1_device); 195 platform_device_register(&tegra_ehci1_device);
205 platform_device_register(&tegra_ehci3_device); 196 platform_device_register(&tegra_ehci3_device);
@@ -209,9 +200,6 @@ static int seaboard_ehci_init(void)
209 200
210static void __init seaboard_i2c_init(void) 201static void __init seaboard_i2c_init(void)
211{ 202{
212 gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
213 gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
214
215 isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ); 203 isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
216 i2c_register_board_info(0, &isl29018_device, 1); 204 i2c_register_board_info(0, &isl29018_device, 1);
217 205
@@ -261,7 +249,6 @@ static void __init tegra_kaen_init(void)
261 debug_uart_platform_data[0].irq = INT_UARTB; 249 debug_uart_platform_data[0].irq = INT_UARTB;
262 250
263 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE; 251 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
264 tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
265 252
266 seaboard_common_init(); 253 seaboard_common_init();
267 254
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be57cb6..7b39511c0d4d 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
2 * arch/arm/mach-tegra/board-trimslice-pinmux.c 2 * arch/arm/mach-tegra/board-trimslice-pinmux.c
3 * 3 *
4 * Copyright (C) 2011 CompuLab, Ltd. 4 * Copyright (C) 2011 CompuLab, Ltd.
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -13,150 +14,139 @@
13 * GNU General Public License for more details. 14 * GNU General Public License for more details.
14 * 15 *
15 */ 16 */
16#include <linux/gpio.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/of.h>
20 18
21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
23
24#include "gpio-names.h"
25#include "board-pinmux.h"
26#include "board-trimslice.h" 19#include "board-trimslice.h"
20#include "board-pinmux.h"
27 21
28static struct tegra_pingroup_config trimslice_pinmux[] = { 22static struct pinctrl_map trimslice_map[] = {
29 {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 23 TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
30 {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 24 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
31 {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 25 TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
32 {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 26 TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
33 {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 27 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
34 {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 28 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
35 {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 29 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
36 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 30 TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
37 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 31 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
38 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 32 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
39 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 33 TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
40 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 34 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
41 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 35 TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
42 {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 36 TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
43 {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 37 TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
44 {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 38 TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
45 {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 39 TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
46 {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 40 TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
47 {TEGRA_PINGROUP_DTE, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 41 TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
48 {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 42 TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
49 {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 43 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
50 {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 44 TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
51 {TEGRA_PINGROUP_GMC, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 45 TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
52 {TEGRA_PINGROUP_GMD, TEGRA_MUX_SFLASH, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 46 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
53 {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 47 TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
54 {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 48 TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
55 {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 49 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
56 {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 50 TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
57 {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 51 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
58 {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 52 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
59 {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 53 TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
60 {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 54 TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
61 {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 55 TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
62 {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 56 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
63 {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 57 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
64 {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 58 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
65 {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 59 TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
66 {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 60 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
67 {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 61 TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
68 {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 62 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
69 {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 63 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
70 {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 64 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
71 {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 65 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
72 {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 66 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
73 {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 67 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
74 {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 68 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
75 {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 69 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
76 {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 70 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
77 {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 71 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
78 {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 72 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
79 {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 73 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
80 {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 74 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
81 {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 75 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
82 {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 76 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
83 {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 77 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
84 {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 78 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
85 {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 79 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
86 {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 80 TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
87 {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 81 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
88 {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 82 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
89 {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 83 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
90 {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 84 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
91 {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 85 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
92 {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 86 TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
93 {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 87 TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
94 {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 88 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
95 {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 89 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
96 {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 90 TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
97 {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 91 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
98 {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 92 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
99 {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 93 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
100 {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 94 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
101 {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 95 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
102 {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 96 TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
103 {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 97 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
104 {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 98 TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
105 {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, 99 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
106 {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 100 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
107 {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 101 TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
108 {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 102 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
109 {TEGRA_PINGROUP_PTA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 103 TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
110 {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 104 TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
111 {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 105 TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
112 {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 106 TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
113 {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, 107 TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
114 {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 108 TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
115 {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 109 TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
116 {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 110 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
117 {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SDIO3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 111 TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
118 {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 112 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
119 {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 113 TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
120 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 114 TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
121 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 115 TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
122 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 116 TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
123 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 117 TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
124 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 118 TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
125 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 119 TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
126 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 120 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
127 {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 121 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
128 {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 122 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
129 {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 123 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
130 {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 124 TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
131 {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 125 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
132 {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 126 TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
133 {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 127 TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
134 {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 128 TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
135 {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 129 TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
136 {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 130 TEGRA_MAP_CONF("ck32", none, na),
137 {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 131 TEGRA_MAP_CONF("ddrc", none, na),
138 {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 132 TEGRA_MAP_CONF("pmca", none, na),
139 {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 TEGRA_MAP_CONF("pmcb", none, na),
140 {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 134 TEGRA_MAP_CONF("pmcc", none, na),
141 {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 135 TEGRA_MAP_CONF("pmcd", none, na),
142 {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 136 TEGRA_MAP_CONF("pmce", none, na),
143 {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 137 TEGRA_MAP_CONF("xm2c", none, na),
144 {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 138 TEGRA_MAP_CONF("xm2d", none, na),
145}; 139 TEGRA_MAP_CONF("ls", up, na),
146 140 TEGRA_MAP_CONF("lc", up, na),
147static struct tegra_gpio_table gpio_table[] = { 141 TEGRA_MAP_CONF("ld17_0", down, na),
148 { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */ 142 TEGRA_MAP_CONF("ld19_18", down, na),
149 { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */ 143 TEGRA_MAP_CONF("ld21_20", down, na),
150 144 TEGRA_MAP_CONF("ld23_22", down, na),
151 { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
152 { .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */
153}; 145};
154 146
155static struct tegra_board_pinmux_conf conf = { 147static struct tegra_board_pinmux_conf conf = {
156 .pgs = trimslice_pinmux, 148 .maps = trimslice_map,
157 .pg_count = ARRAY_SIZE(trimslice_pinmux), 149 .map_count = ARRAY_SIZE(trimslice_map),
158 .gpios = gpio_table,
159 .gpio_count = ARRAY_SIZE(gpio_table),
160}; 150};
161 151
162void trimslice_pinmux_init(void) 152void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cd52820a3e37..f6f5b6a11325 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -25,6 +25,7 @@
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/platform_data/tegra_usb.h>
28 29
29#include <asm/hardware/gic.h> 30#include <asm/hardware/gic.h>
30#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -111,19 +112,13 @@ static void trimslice_i2c_init(void)
111 112
112static void trimslice_usb_init(void) 113static void trimslice_usb_init(void)
113{ 114{
114 int err; 115 struct tegra_ehci_platform_data *pdata;
115 116
116 platform_device_register(&tegra_ehci3_device); 117 pdata = tegra_ehci1_device.dev.platform_data;
118 pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
117 119
120 platform_device_register(&tegra_ehci3_device);
118 platform_device_register(&tegra_ehci2_device); 121 platform_device_register(&tegra_ehci2_device);
119
120 err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
121 "usb1mode");
122 if (err) {
123 pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
124 return;
125 }
126
127 platform_device_register(&tegra_ehci1_device); 122 platform_device_register(&tegra_ehci1_device);
128} 123}
129 124
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 5f6b867e20b4..bd3035e0cea1 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
110}; 110};
111 111
112struct platform_device tegra_pinmux_device = { 112struct platform_device tegra_pinmux_device = {
113 .name = "tegra-pinmux", 113 .name = "tegra20-pinctrl",
114 .id = -1, 114 .id = -1,
115 .resource = pinmux_resource, 115 .resource = pinmux_resource,
116 .num_resources = ARRAY_SIZE(pinmux_resource), 116 .num_resources = ARRAY_SIZE(pinmux_resource),
@@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
448struct tegra_ehci_platform_data tegra_ehci1_pdata = { 448struct tegra_ehci_platform_data tegra_ehci1_pdata = {
449 .operating_mode = TEGRA_USB_OTG, 449 .operating_mode = TEGRA_USB_OTG,
450 .power_down_on_bus_suspend = 1, 450 .power_down_on_bus_suspend = 1,
451 .vbus_gpio = -1,
451}; 452};
452 453
453struct tegra_ehci_platform_data tegra_ehci2_pdata = { 454struct tegra_ehci_platform_data tegra_ehci2_pdata = {
454 .phy_config = &tegra_ehci2_ulpi_phy_config, 455 .phy_config = &tegra_ehci2_ulpi_phy_config,
455 .operating_mode = TEGRA_USB_HOST, 456 .operating_mode = TEGRA_USB_HOST,
456 .power_down_on_bus_suspend = 1, 457 .power_down_on_bus_suspend = 1,
458 .vbus_gpio = -1,
457}; 459};
458 460
459struct tegra_ehci_platform_data tegra_ehci3_pdata = { 461struct tegra_ehci_platform_data tegra_ehci3_pdata = {
460 .operating_mode = TEGRA_USB_HOST, 462 .operating_mode = TEGRA_USB_HOST,
461 .power_down_on_bus_suspend = 1, 463 .power_down_on_bus_suspend = 1,
464 .vbus_gpio = -1,
462}; 465};
463 466
464static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32); 467static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 6140820555e1..a978b3cc3a8d 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,13 +25,4 @@
25 25
26#define TEGRA_NR_GPIOS INT_GPIO_NR 26#define TEGRA_NR_GPIOS INT_GPIO_NR
27 27
28struct tegra_gpio_table {
29 int gpio; /* GPIO number */
30 bool enable; /* Enable for GPIO at init? */
31};
32
33void tegra_gpio_config(struct tegra_gpio_table *table, int num);
34void tegra_gpio_enable(int gpio);
35void tegra_gpio_disable(int gpio);
36
37#endif 28#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
deleted file mode 100644
index 6a40c1dbab17..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
18#define __MACH_TEGRA_PINMUX_TEGRA20_H
19
20enum tegra_pingroup {
21 TEGRA_PINGROUP_ATA = 0,
22 TEGRA_PINGROUP_ATB,
23 TEGRA_PINGROUP_ATC,
24 TEGRA_PINGROUP_ATD,
25 TEGRA_PINGROUP_ATE,
26 TEGRA_PINGROUP_CDEV1,
27 TEGRA_PINGROUP_CDEV2,
28 TEGRA_PINGROUP_CRTP,
29 TEGRA_PINGROUP_CSUS,
30 TEGRA_PINGROUP_DAP1,
31 TEGRA_PINGROUP_DAP2,
32 TEGRA_PINGROUP_DAP3,
33 TEGRA_PINGROUP_DAP4,
34 TEGRA_PINGROUP_DDC,
35 TEGRA_PINGROUP_DTA,
36 TEGRA_PINGROUP_DTB,
37 TEGRA_PINGROUP_DTC,
38 TEGRA_PINGROUP_DTD,
39 TEGRA_PINGROUP_DTE,
40 TEGRA_PINGROUP_DTF,
41 TEGRA_PINGROUP_GMA,
42 TEGRA_PINGROUP_GMB,
43 TEGRA_PINGROUP_GMC,
44 TEGRA_PINGROUP_GMD,
45 TEGRA_PINGROUP_GME,
46 TEGRA_PINGROUP_GPU,
47 TEGRA_PINGROUP_GPU7,
48 TEGRA_PINGROUP_GPV,
49 TEGRA_PINGROUP_HDINT,
50 TEGRA_PINGROUP_I2CP,
51 TEGRA_PINGROUP_IRRX,
52 TEGRA_PINGROUP_IRTX,
53 TEGRA_PINGROUP_KBCA,
54 TEGRA_PINGROUP_KBCB,
55 TEGRA_PINGROUP_KBCC,
56 TEGRA_PINGROUP_KBCD,
57 TEGRA_PINGROUP_KBCE,
58 TEGRA_PINGROUP_KBCF,
59 TEGRA_PINGROUP_LCSN,
60 TEGRA_PINGROUP_LD0,
61 TEGRA_PINGROUP_LD1,
62 TEGRA_PINGROUP_LD10,
63 TEGRA_PINGROUP_LD11,
64 TEGRA_PINGROUP_LD12,
65 TEGRA_PINGROUP_LD13,
66 TEGRA_PINGROUP_LD14,
67 TEGRA_PINGROUP_LD15,
68 TEGRA_PINGROUP_LD16,
69 TEGRA_PINGROUP_LD17,
70 TEGRA_PINGROUP_LD2,
71 TEGRA_PINGROUP_LD3,
72 TEGRA_PINGROUP_LD4,
73 TEGRA_PINGROUP_LD5,
74 TEGRA_PINGROUP_LD6,
75 TEGRA_PINGROUP_LD7,
76 TEGRA_PINGROUP_LD8,
77 TEGRA_PINGROUP_LD9,
78 TEGRA_PINGROUP_LDC,
79 TEGRA_PINGROUP_LDI,
80 TEGRA_PINGROUP_LHP0,
81 TEGRA_PINGROUP_LHP1,
82 TEGRA_PINGROUP_LHP2,
83 TEGRA_PINGROUP_LHS,
84 TEGRA_PINGROUP_LM0,
85 TEGRA_PINGROUP_LM1,
86 TEGRA_PINGROUP_LPP,
87 TEGRA_PINGROUP_LPW0,
88 TEGRA_PINGROUP_LPW1,
89 TEGRA_PINGROUP_LPW2,
90 TEGRA_PINGROUP_LSC0,
91 TEGRA_PINGROUP_LSC1,
92 TEGRA_PINGROUP_LSCK,
93 TEGRA_PINGROUP_LSDA,
94 TEGRA_PINGROUP_LSDI,
95 TEGRA_PINGROUP_LSPI,
96 TEGRA_PINGROUP_LVP0,
97 TEGRA_PINGROUP_LVP1,
98 TEGRA_PINGROUP_LVS,
99 TEGRA_PINGROUP_OWC,
100 TEGRA_PINGROUP_PMC,
101 TEGRA_PINGROUP_PTA,
102 TEGRA_PINGROUP_RM,
103 TEGRA_PINGROUP_SDB,
104 TEGRA_PINGROUP_SDC,
105 TEGRA_PINGROUP_SDD,
106 TEGRA_PINGROUP_SDIO1,
107 TEGRA_PINGROUP_SLXA,
108 TEGRA_PINGROUP_SLXC,
109 TEGRA_PINGROUP_SLXD,
110 TEGRA_PINGROUP_SLXK,
111 TEGRA_PINGROUP_SPDI,
112 TEGRA_PINGROUP_SPDO,
113 TEGRA_PINGROUP_SPIA,
114 TEGRA_PINGROUP_SPIB,
115 TEGRA_PINGROUP_SPIC,
116 TEGRA_PINGROUP_SPID,
117 TEGRA_PINGROUP_SPIE,
118 TEGRA_PINGROUP_SPIF,
119 TEGRA_PINGROUP_SPIG,
120 TEGRA_PINGROUP_SPIH,
121 TEGRA_PINGROUP_UAA,
122 TEGRA_PINGROUP_UAB,
123 TEGRA_PINGROUP_UAC,
124 TEGRA_PINGROUP_UAD,
125 TEGRA_PINGROUP_UCA,
126 TEGRA_PINGROUP_UCB,
127 TEGRA_PINGROUP_UDA,
128 /* these pin groups only have pullup and pull down control */
129 TEGRA_PINGROUP_CK32,
130 TEGRA_PINGROUP_DDRC,
131 TEGRA_PINGROUP_PMCA,
132 TEGRA_PINGROUP_PMCB,
133 TEGRA_PINGROUP_PMCC,
134 TEGRA_PINGROUP_PMCD,
135 TEGRA_PINGROUP_PMCE,
136 TEGRA_PINGROUP_XM2C,
137 TEGRA_PINGROUP_XM2D,
138 TEGRA_MAX_PINGROUP,
139};
140
141enum tegra_drive_pingroup {
142 TEGRA_DRIVE_PINGROUP_AO1 = 0,
143 TEGRA_DRIVE_PINGROUP_AO2,
144 TEGRA_DRIVE_PINGROUP_AT1,
145 TEGRA_DRIVE_PINGROUP_AT2,
146 TEGRA_DRIVE_PINGROUP_CDEV1,
147 TEGRA_DRIVE_PINGROUP_CDEV2,
148 TEGRA_DRIVE_PINGROUP_CSUS,
149 TEGRA_DRIVE_PINGROUP_DAP1,
150 TEGRA_DRIVE_PINGROUP_DAP2,
151 TEGRA_DRIVE_PINGROUP_DAP3,
152 TEGRA_DRIVE_PINGROUP_DAP4,
153 TEGRA_DRIVE_PINGROUP_DBG,
154 TEGRA_DRIVE_PINGROUP_LCD1,
155 TEGRA_DRIVE_PINGROUP_LCD2,
156 TEGRA_DRIVE_PINGROUP_SDMMC2,
157 TEGRA_DRIVE_PINGROUP_SDMMC3,
158 TEGRA_DRIVE_PINGROUP_SPI,
159 TEGRA_DRIVE_PINGROUP_UAA,
160 TEGRA_DRIVE_PINGROUP_UAB,
161 TEGRA_DRIVE_PINGROUP_UART2,
162 TEGRA_DRIVE_PINGROUP_UART3,
163 TEGRA_DRIVE_PINGROUP_VI1,
164 TEGRA_DRIVE_PINGROUP_VI2,
165 TEGRA_DRIVE_PINGROUP_XM2A,
166 TEGRA_DRIVE_PINGROUP_XM2C,
167 TEGRA_DRIVE_PINGROUP_XM2D,
168 TEGRA_DRIVE_PINGROUP_XM2CLK,
169 TEGRA_DRIVE_PINGROUP_MEMCOMP,
170 TEGRA_DRIVE_PINGROUP_SDIO1,
171 TEGRA_DRIVE_PINGROUP_CRT,
172 TEGRA_DRIVE_PINGROUP_DDC,
173 TEGRA_DRIVE_PINGROUP_GMA,
174 TEGRA_DRIVE_PINGROUP_GMB,
175 TEGRA_DRIVE_PINGROUP_GMC,
176 TEGRA_DRIVE_PINGROUP_GMD,
177 TEGRA_DRIVE_PINGROUP_GME,
178 TEGRA_DRIVE_PINGROUP_OWR,
179 TEGRA_DRIVE_PINGROUP_UAD,
180 TEGRA_MAX_DRIVE_PINGROUP,
181};
182
183#endif
184
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
deleted file mode 100644
index c1aee3eb2df1..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+++ /dev/null
@@ -1,320 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
19#define __MACH_TEGRA_PINMUX_TEGRA30_H
20
21enum tegra_pingroup {
22 TEGRA_PINGROUP_ULPI_DATA0 = 0,
23 TEGRA_PINGROUP_ULPI_DATA1,
24 TEGRA_PINGROUP_ULPI_DATA2,
25 TEGRA_PINGROUP_ULPI_DATA3,
26 TEGRA_PINGROUP_ULPI_DATA4,
27 TEGRA_PINGROUP_ULPI_DATA5,
28 TEGRA_PINGROUP_ULPI_DATA6,
29 TEGRA_PINGROUP_ULPI_DATA7,
30 TEGRA_PINGROUP_ULPI_CLK,
31 TEGRA_PINGROUP_ULPI_DIR,
32 TEGRA_PINGROUP_ULPI_NXT,
33 TEGRA_PINGROUP_ULPI_STP,
34 TEGRA_PINGROUP_DAP3_FS,
35 TEGRA_PINGROUP_DAP3_DIN,
36 TEGRA_PINGROUP_DAP3_DOUT,
37 TEGRA_PINGROUP_DAP3_SCLK,
38 TEGRA_PINGROUP_GPIO_PV0,
39 TEGRA_PINGROUP_GPIO_PV1,
40 TEGRA_PINGROUP_SDMMC1_CLK,
41 TEGRA_PINGROUP_SDMMC1_CMD,
42 TEGRA_PINGROUP_SDMMC1_DAT3,
43 TEGRA_PINGROUP_SDMMC1_DAT2,
44 TEGRA_PINGROUP_SDMMC1_DAT1,
45 TEGRA_PINGROUP_SDMMC1_DAT0,
46 TEGRA_PINGROUP_GPIO_PV2,
47 TEGRA_PINGROUP_GPIO_PV3,
48 TEGRA_PINGROUP_CLK2_OUT,
49 TEGRA_PINGROUP_CLK2_REQ,
50 TEGRA_PINGROUP_LCD_PWR1,
51 TEGRA_PINGROUP_LCD_PWR2,
52 TEGRA_PINGROUP_LCD_SDIN,
53 TEGRA_PINGROUP_LCD_SDOUT,
54 TEGRA_PINGROUP_LCD_WR_N,
55 TEGRA_PINGROUP_LCD_CS0_N,
56 TEGRA_PINGROUP_LCD_DC0,
57 TEGRA_PINGROUP_LCD_SCK,
58 TEGRA_PINGROUP_LCD_PWR0,
59 TEGRA_PINGROUP_LCD_PCLK,
60 TEGRA_PINGROUP_LCD_DE,
61 TEGRA_PINGROUP_LCD_HSYNC,
62 TEGRA_PINGROUP_LCD_VSYNC,
63 TEGRA_PINGROUP_LCD_D0,
64 TEGRA_PINGROUP_LCD_D1,
65 TEGRA_PINGROUP_LCD_D2,
66 TEGRA_PINGROUP_LCD_D3,
67 TEGRA_PINGROUP_LCD_D4,
68 TEGRA_PINGROUP_LCD_D5,
69 TEGRA_PINGROUP_LCD_D6,
70 TEGRA_PINGROUP_LCD_D7,
71 TEGRA_PINGROUP_LCD_D8,
72 TEGRA_PINGROUP_LCD_D9,
73 TEGRA_PINGROUP_LCD_D10,
74 TEGRA_PINGROUP_LCD_D11,
75 TEGRA_PINGROUP_LCD_D12,
76 TEGRA_PINGROUP_LCD_D13,
77 TEGRA_PINGROUP_LCD_D14,
78 TEGRA_PINGROUP_LCD_D15,
79 TEGRA_PINGROUP_LCD_D16,
80 TEGRA_PINGROUP_LCD_D17,
81 TEGRA_PINGROUP_LCD_D18,
82 TEGRA_PINGROUP_LCD_D19,
83 TEGRA_PINGROUP_LCD_D20,
84 TEGRA_PINGROUP_LCD_D21,
85 TEGRA_PINGROUP_LCD_D22,
86 TEGRA_PINGROUP_LCD_D23,
87 TEGRA_PINGROUP_LCD_CS1_N,
88 TEGRA_PINGROUP_LCD_M1,
89 TEGRA_PINGROUP_LCD_DC1,
90 TEGRA_PINGROUP_HDMI_INT,
91 TEGRA_PINGROUP_DDC_SCL,
92 TEGRA_PINGROUP_DDC_SDA,
93 TEGRA_PINGROUP_CRT_HSYNC,
94 TEGRA_PINGROUP_CRT_VSYNC,
95 TEGRA_PINGROUP_VI_D0,
96 TEGRA_PINGROUP_VI_D1,
97 TEGRA_PINGROUP_VI_D2,
98 TEGRA_PINGROUP_VI_D3,
99 TEGRA_PINGROUP_VI_D4,
100 TEGRA_PINGROUP_VI_D5,
101 TEGRA_PINGROUP_VI_D6,
102 TEGRA_PINGROUP_VI_D7,
103 TEGRA_PINGROUP_VI_D8,
104 TEGRA_PINGROUP_VI_D9,
105 TEGRA_PINGROUP_VI_D10,
106 TEGRA_PINGROUP_VI_D11,
107 TEGRA_PINGROUP_VI_PCLK,
108 TEGRA_PINGROUP_VI_MCLK,
109 TEGRA_PINGROUP_VI_VSYNC,
110 TEGRA_PINGROUP_VI_HSYNC,
111 TEGRA_PINGROUP_UART2_RXD,
112 TEGRA_PINGROUP_UART2_TXD,
113 TEGRA_PINGROUP_UART2_RTS_N,
114 TEGRA_PINGROUP_UART2_CTS_N,
115 TEGRA_PINGROUP_UART3_TXD,
116 TEGRA_PINGROUP_UART3_RXD,
117 TEGRA_PINGROUP_UART3_CTS_N,
118 TEGRA_PINGROUP_UART3_RTS_N,
119 TEGRA_PINGROUP_GPIO_PU0,
120 TEGRA_PINGROUP_GPIO_PU1,
121 TEGRA_PINGROUP_GPIO_PU2,
122 TEGRA_PINGROUP_GPIO_PU3,
123 TEGRA_PINGROUP_GPIO_PU4,
124 TEGRA_PINGROUP_GPIO_PU5,
125 TEGRA_PINGROUP_GPIO_PU6,
126 TEGRA_PINGROUP_GEN1_I2C_SDA,
127 TEGRA_PINGROUP_GEN1_I2C_SCL,
128 TEGRA_PINGROUP_DAP4_FS,
129 TEGRA_PINGROUP_DAP4_DIN,
130 TEGRA_PINGROUP_DAP4_DOUT,
131 TEGRA_PINGROUP_DAP4_SCLK,
132 TEGRA_PINGROUP_CLK3_OUT,
133 TEGRA_PINGROUP_CLK3_REQ,
134 TEGRA_PINGROUP_GMI_WP_N,
135 TEGRA_PINGROUP_GMI_IORDY,
136 TEGRA_PINGROUP_GMI_WAIT,
137 TEGRA_PINGROUP_GMI_ADV_N,
138 TEGRA_PINGROUP_GMI_CLK,
139 TEGRA_PINGROUP_GMI_CS0_N,
140 TEGRA_PINGROUP_GMI_CS1_N,
141 TEGRA_PINGROUP_GMI_CS2_N,
142 TEGRA_PINGROUP_GMI_CS3_N,
143 TEGRA_PINGROUP_GMI_CS4_N,
144 TEGRA_PINGROUP_GMI_CS6_N,
145 TEGRA_PINGROUP_GMI_CS7_N,
146 TEGRA_PINGROUP_GMI_AD0,
147 TEGRA_PINGROUP_GMI_AD1,
148 TEGRA_PINGROUP_GMI_AD2,
149 TEGRA_PINGROUP_GMI_AD3,
150 TEGRA_PINGROUP_GMI_AD4,
151 TEGRA_PINGROUP_GMI_AD5,
152 TEGRA_PINGROUP_GMI_AD6,
153 TEGRA_PINGROUP_GMI_AD7,
154 TEGRA_PINGROUP_GMI_AD8,
155 TEGRA_PINGROUP_GMI_AD9,
156 TEGRA_PINGROUP_GMI_AD10,
157 TEGRA_PINGROUP_GMI_AD11,
158 TEGRA_PINGROUP_GMI_AD12,
159 TEGRA_PINGROUP_GMI_AD13,
160 TEGRA_PINGROUP_GMI_AD14,
161 TEGRA_PINGROUP_GMI_AD15,
162 TEGRA_PINGROUP_GMI_A16,
163 TEGRA_PINGROUP_GMI_A17,
164 TEGRA_PINGROUP_GMI_A18,
165 TEGRA_PINGROUP_GMI_A19,
166 TEGRA_PINGROUP_GMI_WR_N,
167 TEGRA_PINGROUP_GMI_OE_N,
168 TEGRA_PINGROUP_GMI_DQS,
169 TEGRA_PINGROUP_GMI_RST_N,
170 TEGRA_PINGROUP_GEN2_I2C_SCL,
171 TEGRA_PINGROUP_GEN2_I2C_SDA,
172 TEGRA_PINGROUP_SDMMC4_CLK,
173 TEGRA_PINGROUP_SDMMC4_CMD,
174 TEGRA_PINGROUP_SDMMC4_DAT0,
175 TEGRA_PINGROUP_SDMMC4_DAT1,
176 TEGRA_PINGROUP_SDMMC4_DAT2,
177 TEGRA_PINGROUP_SDMMC4_DAT3,
178 TEGRA_PINGROUP_SDMMC4_DAT4,
179 TEGRA_PINGROUP_SDMMC4_DAT5,
180 TEGRA_PINGROUP_SDMMC4_DAT6,
181 TEGRA_PINGROUP_SDMMC4_DAT7,
182 TEGRA_PINGROUP_SDMMC4_RST_N,
183 TEGRA_PINGROUP_CAM_MCLK,
184 TEGRA_PINGROUP_GPIO_PCC1,
185 TEGRA_PINGROUP_GPIO_PBB0,
186 TEGRA_PINGROUP_CAM_I2C_SCL,
187 TEGRA_PINGROUP_CAM_I2C_SDA,
188 TEGRA_PINGROUP_GPIO_PBB3,
189 TEGRA_PINGROUP_GPIO_PBB4,
190 TEGRA_PINGROUP_GPIO_PBB5,
191 TEGRA_PINGROUP_GPIO_PBB6,
192 TEGRA_PINGROUP_GPIO_PBB7,
193 TEGRA_PINGROUP_GPIO_PCC2,
194 TEGRA_PINGROUP_JTAG_RTCK,
195 TEGRA_PINGROUP_PWR_I2C_SCL,
196 TEGRA_PINGROUP_PWR_I2C_SDA,
197 TEGRA_PINGROUP_KB_ROW0,
198 TEGRA_PINGROUP_KB_ROW1,
199 TEGRA_PINGROUP_KB_ROW2,
200 TEGRA_PINGROUP_KB_ROW3,
201 TEGRA_PINGROUP_KB_ROW4,
202 TEGRA_PINGROUP_KB_ROW5,
203 TEGRA_PINGROUP_KB_ROW6,
204 TEGRA_PINGROUP_KB_ROW7,
205 TEGRA_PINGROUP_KB_ROW8,
206 TEGRA_PINGROUP_KB_ROW9,
207 TEGRA_PINGROUP_KB_ROW10,
208 TEGRA_PINGROUP_KB_ROW11,
209 TEGRA_PINGROUP_KB_ROW12,
210 TEGRA_PINGROUP_KB_ROW13,
211 TEGRA_PINGROUP_KB_ROW14,
212 TEGRA_PINGROUP_KB_ROW15,
213 TEGRA_PINGROUP_KB_COL0,
214 TEGRA_PINGROUP_KB_COL1,
215 TEGRA_PINGROUP_KB_COL2,
216 TEGRA_PINGROUP_KB_COL3,
217 TEGRA_PINGROUP_KB_COL4,
218 TEGRA_PINGROUP_KB_COL5,
219 TEGRA_PINGROUP_KB_COL6,
220 TEGRA_PINGROUP_KB_COL7,
221 TEGRA_PINGROUP_CLK_32K_OUT,
222 TEGRA_PINGROUP_SYS_CLK_REQ,
223 TEGRA_PINGROUP_CORE_PWR_REQ,
224 TEGRA_PINGROUP_CPU_PWR_REQ,
225 TEGRA_PINGROUP_PWR_INT_N,
226 TEGRA_PINGROUP_CLK_32K_IN,
227 TEGRA_PINGROUP_OWR,
228 TEGRA_PINGROUP_DAP1_FS,
229 TEGRA_PINGROUP_DAP1_DIN,
230 TEGRA_PINGROUP_DAP1_DOUT,
231 TEGRA_PINGROUP_DAP1_SCLK,
232 TEGRA_PINGROUP_CLK1_REQ,
233 TEGRA_PINGROUP_CLK1_OUT,
234 TEGRA_PINGROUP_SPDIF_IN,
235 TEGRA_PINGROUP_SPDIF_OUT,
236 TEGRA_PINGROUP_DAP2_FS,
237 TEGRA_PINGROUP_DAP2_DIN,
238 TEGRA_PINGROUP_DAP2_DOUT,
239 TEGRA_PINGROUP_DAP2_SCLK,
240 TEGRA_PINGROUP_SPI2_MOSI,
241 TEGRA_PINGROUP_SPI2_MISO,
242 TEGRA_PINGROUP_SPI2_CS0_N,
243 TEGRA_PINGROUP_SPI2_SCK,
244 TEGRA_PINGROUP_SPI1_MOSI,
245 TEGRA_PINGROUP_SPI1_SCK,
246 TEGRA_PINGROUP_SPI1_CS0_N,
247 TEGRA_PINGROUP_SPI1_MISO,
248 TEGRA_PINGROUP_SPI2_CS1_N,
249 TEGRA_PINGROUP_SPI2_CS2_N,
250 TEGRA_PINGROUP_SDMMC3_CLK,
251 TEGRA_PINGROUP_SDMMC3_CMD,
252 TEGRA_PINGROUP_SDMMC3_DAT0,
253 TEGRA_PINGROUP_SDMMC3_DAT1,
254 TEGRA_PINGROUP_SDMMC3_DAT2,
255 TEGRA_PINGROUP_SDMMC3_DAT3,
256 TEGRA_PINGROUP_SDMMC3_DAT4,
257 TEGRA_PINGROUP_SDMMC3_DAT5,
258 TEGRA_PINGROUP_SDMMC3_DAT6,
259 TEGRA_PINGROUP_SDMMC3_DAT7,
260 TEGRA_PINGROUP_PEX_L0_PRSNT_N,
261 TEGRA_PINGROUP_PEX_L0_RST_N,
262 TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
263 TEGRA_PINGROUP_PEX_WAKE_N,
264 TEGRA_PINGROUP_PEX_L1_PRSNT_N,
265 TEGRA_PINGROUP_PEX_L1_RST_N,
266 TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
267 TEGRA_PINGROUP_PEX_L2_PRSNT_N,
268 TEGRA_PINGROUP_PEX_L2_RST_N,
269 TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
270 TEGRA_PINGROUP_HDMI_CEC,
271 TEGRA_MAX_PINGROUP,
272};
273
274enum tegra_drive_pingroup {
275 TEGRA_DRIVE_PINGROUP_AO1 = 0,
276 TEGRA_DRIVE_PINGROUP_AO2,
277 TEGRA_DRIVE_PINGROUP_AT1,
278 TEGRA_DRIVE_PINGROUP_AT2,
279 TEGRA_DRIVE_PINGROUP_AT3,
280 TEGRA_DRIVE_PINGROUP_AT4,
281 TEGRA_DRIVE_PINGROUP_AT5,
282 TEGRA_DRIVE_PINGROUP_CDEV1,
283 TEGRA_DRIVE_PINGROUP_CDEV2,
284 TEGRA_DRIVE_PINGROUP_CSUS,
285 TEGRA_DRIVE_PINGROUP_DAP1,
286 TEGRA_DRIVE_PINGROUP_DAP2,
287 TEGRA_DRIVE_PINGROUP_DAP3,
288 TEGRA_DRIVE_PINGROUP_DAP4,
289 TEGRA_DRIVE_PINGROUP_DBG,
290 TEGRA_DRIVE_PINGROUP_LCD1,
291 TEGRA_DRIVE_PINGROUP_LCD2,
292 TEGRA_DRIVE_PINGROUP_SDIO2,
293 TEGRA_DRIVE_PINGROUP_SDIO3,
294 TEGRA_DRIVE_PINGROUP_SPI,
295 TEGRA_DRIVE_PINGROUP_UAA,
296 TEGRA_DRIVE_PINGROUP_UAB,
297 TEGRA_DRIVE_PINGROUP_UART2,
298 TEGRA_DRIVE_PINGROUP_UART3,
299 TEGRA_DRIVE_PINGROUP_VI1,
300 TEGRA_DRIVE_PINGROUP_SDIO1,
301 TEGRA_DRIVE_PINGROUP_CRT,
302 TEGRA_DRIVE_PINGROUP_DDC,
303 TEGRA_DRIVE_PINGROUP_GMA,
304 TEGRA_DRIVE_PINGROUP_GMB,
305 TEGRA_DRIVE_PINGROUP_GMC,
306 TEGRA_DRIVE_PINGROUP_GMD,
307 TEGRA_DRIVE_PINGROUP_GME,
308 TEGRA_DRIVE_PINGROUP_GMF,
309 TEGRA_DRIVE_PINGROUP_GMG,
310 TEGRA_DRIVE_PINGROUP_GMH,
311 TEGRA_DRIVE_PINGROUP_OWR,
312 TEGRA_DRIVE_PINGROUP_UAD,
313 TEGRA_DRIVE_PINGROUP_GPV,
314 TEGRA_DRIVE_PINGROUP_DEV3,
315 TEGRA_DRIVE_PINGROUP_CEC,
316 TEGRA_MAX_DRIVE_PINGROUP,
317};
318
319#endif
320
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
deleted file mode 100644
index 055f1792c8ff..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_H
19#define __MACH_TEGRA_PINMUX_H
20
21enum tegra_mux_func {
22 TEGRA_MUX_RSVD = 0x8000,
23 TEGRA_MUX_RSVD1 = 0x8000,
24 TEGRA_MUX_RSVD2 = 0x8001,
25 TEGRA_MUX_RSVD3 = 0x8002,
26 TEGRA_MUX_RSVD4 = 0x8003,
27 TEGRA_MUX_INVALID = 0x4000,
28 TEGRA_MUX_NONE = -1,
29 TEGRA_MUX_AHB_CLK,
30 TEGRA_MUX_APB_CLK,
31 TEGRA_MUX_AUDIO_SYNC,
32 TEGRA_MUX_CRT,
33 TEGRA_MUX_DAP1,
34 TEGRA_MUX_DAP2,
35 TEGRA_MUX_DAP3,
36 TEGRA_MUX_DAP4,
37 TEGRA_MUX_DAP5,
38 TEGRA_MUX_DISPLAYA,
39 TEGRA_MUX_DISPLAYB,
40 TEGRA_MUX_EMC_TEST0_DLL,
41 TEGRA_MUX_EMC_TEST1_DLL,
42 TEGRA_MUX_GMI,
43 TEGRA_MUX_GMI_INT,
44 TEGRA_MUX_HDMI,
45 TEGRA_MUX_I2C,
46 TEGRA_MUX_I2C2,
47 TEGRA_MUX_I2C3,
48 TEGRA_MUX_IDE,
49 TEGRA_MUX_IRDA,
50 TEGRA_MUX_KBC,
51 TEGRA_MUX_MIO,
52 TEGRA_MUX_MIPI_HS,
53 TEGRA_MUX_NAND,
54 TEGRA_MUX_OSC,
55 TEGRA_MUX_OWR,
56 TEGRA_MUX_PCIE,
57 TEGRA_MUX_PLLA_OUT,
58 TEGRA_MUX_PLLC_OUT1,
59 TEGRA_MUX_PLLM_OUT1,
60 TEGRA_MUX_PLLP_OUT2,
61 TEGRA_MUX_PLLP_OUT3,
62 TEGRA_MUX_PLLP_OUT4,
63 TEGRA_MUX_PWM,
64 TEGRA_MUX_PWR_INTR,
65 TEGRA_MUX_PWR_ON,
66 TEGRA_MUX_RTCK,
67 TEGRA_MUX_SDIO1,
68 TEGRA_MUX_SDIO2,
69 TEGRA_MUX_SDIO3,
70 TEGRA_MUX_SDIO4,
71 TEGRA_MUX_SFLASH,
72 TEGRA_MUX_SPDIF,
73 TEGRA_MUX_SPI1,
74 TEGRA_MUX_SPI2,
75 TEGRA_MUX_SPI2_ALT,
76 TEGRA_MUX_SPI3,
77 TEGRA_MUX_SPI4,
78 TEGRA_MUX_TRACE,
79 TEGRA_MUX_TWC,
80 TEGRA_MUX_UARTA,
81 TEGRA_MUX_UARTB,
82 TEGRA_MUX_UARTC,
83 TEGRA_MUX_UARTD,
84 TEGRA_MUX_UARTE,
85 TEGRA_MUX_ULPI,
86 TEGRA_MUX_VI,
87 TEGRA_MUX_VI_SENSOR_CLK,
88 TEGRA_MUX_XIO,
89 TEGRA_MUX_BLINK,
90 TEGRA_MUX_CEC,
91 TEGRA_MUX_CLK12,
92 TEGRA_MUX_DAP,
93 TEGRA_MUX_DAPSDMMC2,
94 TEGRA_MUX_DDR,
95 TEGRA_MUX_DEV3,
96 TEGRA_MUX_DTV,
97 TEGRA_MUX_VI_ALT1,
98 TEGRA_MUX_VI_ALT2,
99 TEGRA_MUX_VI_ALT3,
100 TEGRA_MUX_EMC_DLL,
101 TEGRA_MUX_EXTPERIPH1,
102 TEGRA_MUX_EXTPERIPH2,
103 TEGRA_MUX_EXTPERIPH3,
104 TEGRA_MUX_GMI_ALT,
105 TEGRA_MUX_HDA,
106 TEGRA_MUX_HSI,
107 TEGRA_MUX_I2C4,
108 TEGRA_MUX_I2C5,
109 TEGRA_MUX_I2CPWR,
110 TEGRA_MUX_I2S0,
111 TEGRA_MUX_I2S1,
112 TEGRA_MUX_I2S2,
113 TEGRA_MUX_I2S3,
114 TEGRA_MUX_I2S4,
115 TEGRA_MUX_NAND_ALT,
116 TEGRA_MUX_POPSDIO4,
117 TEGRA_MUX_POPSDMMC4,
118 TEGRA_MUX_PWM0,
119 TEGRA_MUX_PWM1,
120 TEGRA_MUX_PWM2,
121 TEGRA_MUX_PWM3,
122 TEGRA_MUX_SATA,
123 TEGRA_MUX_SPI5,
124 TEGRA_MUX_SPI6,
125 TEGRA_MUX_SYSCLK,
126 TEGRA_MUX_VGP1,
127 TEGRA_MUX_VGP2,
128 TEGRA_MUX_VGP3,
129 TEGRA_MUX_VGP4,
130 TEGRA_MUX_VGP5,
131 TEGRA_MUX_VGP6,
132 TEGRA_MUX_SAFE,
133 TEGRA_MAX_MUX,
134};
135
136enum tegra_pullupdown {
137 TEGRA_PUPD_NORMAL = 0,
138 TEGRA_PUPD_PULL_DOWN,
139 TEGRA_PUPD_PULL_UP,
140};
141
142enum tegra_tristate {
143 TEGRA_TRI_NORMAL = 0,
144 TEGRA_TRI_TRISTATE = 1,
145};
146
147enum tegra_pin_io {
148 TEGRA_PIN_OUTPUT = 0,
149 TEGRA_PIN_INPUT = 1,
150};
151
152enum tegra_vddio {
153 TEGRA_VDDIO_BB = 0,
154 TEGRA_VDDIO_LCD,
155 TEGRA_VDDIO_VI,
156 TEGRA_VDDIO_UART,
157 TEGRA_VDDIO_DDR,
158 TEGRA_VDDIO_NAND,
159 TEGRA_VDDIO_SYS,
160 TEGRA_VDDIO_AUDIO,
161 TEGRA_VDDIO_SD,
162 TEGRA_VDDIO_CAM,
163 TEGRA_VDDIO_GMI,
164 TEGRA_VDDIO_PEXCTL,
165 TEGRA_VDDIO_SDMMC1,
166 TEGRA_VDDIO_SDMMC3,
167 TEGRA_VDDIO_SDMMC4,
168};
169
170struct tegra_pingroup_config {
171 int pingroup;
172 enum tegra_mux_func func;
173 enum tegra_pullupdown pupd;
174 enum tegra_tristate tristate;
175};
176
177enum tegra_slew {
178 TEGRA_SLEW_FASTEST = 0,
179 TEGRA_SLEW_FAST,
180 TEGRA_SLEW_SLOW,
181 TEGRA_SLEW_SLOWEST,
182 TEGRA_MAX_SLEW,
183};
184
185enum tegra_pull_strength {
186 TEGRA_PULL_0 = 0,
187 TEGRA_PULL_1,
188 TEGRA_PULL_2,
189 TEGRA_PULL_3,
190 TEGRA_PULL_4,
191 TEGRA_PULL_5,
192 TEGRA_PULL_6,
193 TEGRA_PULL_7,
194 TEGRA_PULL_8,
195 TEGRA_PULL_9,
196 TEGRA_PULL_10,
197 TEGRA_PULL_11,
198 TEGRA_PULL_12,
199 TEGRA_PULL_13,
200 TEGRA_PULL_14,
201 TEGRA_PULL_15,
202 TEGRA_PULL_16,
203 TEGRA_PULL_17,
204 TEGRA_PULL_18,
205 TEGRA_PULL_19,
206 TEGRA_PULL_20,
207 TEGRA_PULL_21,
208 TEGRA_PULL_22,
209 TEGRA_PULL_23,
210 TEGRA_PULL_24,
211 TEGRA_PULL_25,
212 TEGRA_PULL_26,
213 TEGRA_PULL_27,
214 TEGRA_PULL_28,
215 TEGRA_PULL_29,
216 TEGRA_PULL_30,
217 TEGRA_PULL_31,
218 TEGRA_MAX_PULL,
219};
220
221enum tegra_drive {
222 TEGRA_DRIVE_DIV_8 = 0,
223 TEGRA_DRIVE_DIV_4,
224 TEGRA_DRIVE_DIV_2,
225 TEGRA_DRIVE_DIV_1,
226 TEGRA_MAX_DRIVE,
227};
228
229enum tegra_hsm {
230 TEGRA_HSM_DISABLE = 0,
231 TEGRA_HSM_ENABLE,
232};
233
234enum tegra_schmitt {
235 TEGRA_SCHMITT_DISABLE = 0,
236 TEGRA_SCHMITT_ENABLE,
237};
238
239struct tegra_drive_pingroup_config {
240 int pingroup;
241 enum tegra_hsm hsm;
242 enum tegra_schmitt schmitt;
243 enum tegra_drive drive;
244 enum tegra_pull_strength pull_down;
245 enum tegra_pull_strength pull_up;
246 enum tegra_slew slew_rising;
247 enum tegra_slew slew_falling;
248};
249
250struct tegra_drive_pingroup_desc {
251 const char *name;
252 s16 reg_bank;
253 s16 reg;
254};
255
256struct tegra_pingroup_desc {
257 const char *name;
258 int funcs[4];
259 int func_safe;
260 int vddio;
261 enum tegra_pin_io io_default;
262 s16 tri_bank; /* Register bank the tri_reg exists within */
263 s16 mux_bank; /* Register bank the mux_reg exists within */
264 s16 pupd_bank; /* Register bank the pupd_reg exists within */
265 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
266 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
267 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
268 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
269 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
270 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
271 s8 lock_bit; /* offset of the LOCK bit into mux register bit */
272 s8 od_bit; /* offset of the OD bit into mux register bit */
273 s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
274};
275
276typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
277 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
278 int *pgdrive_max);
279
280void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
281 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
282
283void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
284 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
285
286int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
287int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
288
289void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
290 int len);
291
292void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
293 int len);
294void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
295 int len);
296void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
297 int len);
298void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
299 int len, enum tegra_tristate tristate);
300void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
301 int len, enum tegra_pullupdown pupd);
302#endif
diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
deleted file mode 100644
index 734add1280b7..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c
+++ /dev/null
@@ -1,244 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
3 *
4 * Common pinmux configurations for Tegra20 SoCs
5 *
6 * Copyright (C) 2010 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/spinlock.h>
26#include <linux/io.h>
27#include <linux/init.h>
28#include <linux/string.h>
29
30#include <mach/iomap.h>
31#include <mach/pinmux.h>
32#include <mach/pinmux-tegra20.h>
33#include <mach/suspend.h>
34
35#define TRISTATE_REG_A 0x14
36#define PIN_MUX_CTL_REG_A 0x80
37#define PULLUPDOWN_REG_A 0xa0
38#define PINGROUP_REG_A 0x868
39
40#define DRIVE_PINGROUP(pg_name, r) \
41 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
42 .name = #pg_name, \
43 .reg_bank = 3, \
44 .reg = ((r) - PINGROUP_REG_A) \
45 }
46
47static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
48 DRIVE_PINGROUP(AO1, 0x868),
49 DRIVE_PINGROUP(AO2, 0x86c),
50 DRIVE_PINGROUP(AT1, 0x870),
51 DRIVE_PINGROUP(AT2, 0x874),
52 DRIVE_PINGROUP(CDEV1, 0x878),
53 DRIVE_PINGROUP(CDEV2, 0x87c),
54 DRIVE_PINGROUP(CSUS, 0x880),
55 DRIVE_PINGROUP(DAP1, 0x884),
56 DRIVE_PINGROUP(DAP2, 0x888),
57 DRIVE_PINGROUP(DAP3, 0x88c),
58 DRIVE_PINGROUP(DAP4, 0x890),
59 DRIVE_PINGROUP(DBG, 0x894),
60 DRIVE_PINGROUP(LCD1, 0x898),
61 DRIVE_PINGROUP(LCD2, 0x89c),
62 DRIVE_PINGROUP(SDMMC2, 0x8a0),
63 DRIVE_PINGROUP(SDMMC3, 0x8a4),
64 DRIVE_PINGROUP(SPI, 0x8a8),
65 DRIVE_PINGROUP(UAA, 0x8ac),
66 DRIVE_PINGROUP(UAB, 0x8b0),
67 DRIVE_PINGROUP(UART2, 0x8b4),
68 DRIVE_PINGROUP(UART3, 0x8b8),
69 DRIVE_PINGROUP(VI1, 0x8bc),
70 DRIVE_PINGROUP(VI2, 0x8c0),
71 DRIVE_PINGROUP(XM2A, 0x8c4),
72 DRIVE_PINGROUP(XM2C, 0x8c8),
73 DRIVE_PINGROUP(XM2D, 0x8cc),
74 DRIVE_PINGROUP(XM2CLK, 0x8d0),
75 DRIVE_PINGROUP(MEMCOMP, 0x8d4),
76 DRIVE_PINGROUP(SDIO1, 0x8e0),
77 DRIVE_PINGROUP(CRT, 0x8ec),
78 DRIVE_PINGROUP(DDC, 0x8f0),
79 DRIVE_PINGROUP(GMA, 0x8f4),
80 DRIVE_PINGROUP(GMB, 0x8f8),
81 DRIVE_PINGROUP(GMC, 0x8fc),
82 DRIVE_PINGROUP(GMD, 0x900),
83 DRIVE_PINGROUP(GME, 0x904),
84 DRIVE_PINGROUP(OWR, 0x908),
85 DRIVE_PINGROUP(UAD, 0x90c),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \
89 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
90 [TEGRA_PINGROUP_ ## pg_name] = { \
91 .name = #pg_name, \
92 .vddio = TEGRA_VDDIO_ ## vdd, \
93 .funcs = { \
94 TEGRA_MUX_ ## f0, \
95 TEGRA_MUX_ ## f1, \
96 TEGRA_MUX_ ## f2, \
97 TEGRA_MUX_ ## f3, \
98 }, \
99 .func_safe = TEGRA_MUX_ ## f_safe, \
100 .tri_bank = 0, \
101 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
102 .tri_bit = tri_b, \
103 .mux_bank = 1, \
104 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
105 .mux_bit = mux_b, \
106 .pupd_bank = 2, \
107 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
108 .pupd_bit = pupd_b, \
109 .lock_bit = -1, \
110 .od_bit = -1, \
111 .ioreset_bit = -1, \
112 .io_default = -1, \
113 }
114
115static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
116 PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
117 PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
118 PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
119 PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6),
120 PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8),
121 PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0),
122 PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2),
123 PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24),
124 PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24),
125 PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10),
126 PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12),
127 PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14),
128 PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16),
129 PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28),
130 PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18),
131 PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20),
132 PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22),
133 PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24),
134 PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26),
135 PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28),
136 PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20),
137 PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22),
138 PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24),
139 PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26),
140 PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24),
141 PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20),
142 PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6),
143 PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30),
144 PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22),
145 PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2),
146 PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22),
147 PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20),
148 PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8),
149 PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10),
150 PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12),
151 PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14),
152 PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2),
153 PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0),
154 PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20),
155 PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12),
156 PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12),
157 PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12),
158 PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12),
159 PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12),
160 PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12),
161 PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12),
162 PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12),
163 PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12),
164 PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12),
165 PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12),
166 PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12),
167 PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12),
168 PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12),
169 PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12),
170 PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12),
171 PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12),
172 PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12),
173 PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20),
174 PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18),
175 PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16),
176 PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14),
177 PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14),
178 PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22),
179 PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22),
180 PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22),
181 PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18),
182 PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20),
183 PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20),
184 PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20),
185 PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22),
186 PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20),
187 PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20),
188 PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20),
189 PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20),
190 PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22),
191 PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22),
192 PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16),
193 PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22),
194 PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30),
195 PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
196 PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4),
197 PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0),
198 PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1),
199 PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28),
200 PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30),
201 PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18),
202 PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22),
203 PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26),
204 PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28),
205 PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30),
206 PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16),
207 PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18),
208 PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4),
209 PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6),
210 PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8),
211 PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10),
212 PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12),
213 PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14),
214 PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16),
215 PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18),
216 PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0),
217 PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2),
218 PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4),
219 PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6),
220 PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8),
221 PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10),
222 PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16),
223 /* these pin groups only have pullup and pull down control */
224 PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14),
225 PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26),
226 PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4),
227 PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6),
228 PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8),
229 PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10),
230 PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12),
231 PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
232 PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
233};
234
235void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
236 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
237 int *pgdrive_max)
238{
239 *pg = tegra_soc_pingroups;
240 *pg_max = TEGRA_MAX_PINGROUP;
241 *pgdrive = tegra_soc_drive_pingroups;
242 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
243}
244
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
deleted file mode 100644
index 14fc0e4c1c44..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+++ /dev/null
@@ -1,376 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
3 *
4 * Common pinmux configurations for Tegra30 SoCs
5 *
6 * Copyright (C) 2010,2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/errno.h>
24#include <linux/spinlock.h>
25#include <linux/io.h>
26#include <linux/init.h>
27#include <linux/string.h>
28
29#include <mach/iomap.h>
30#include <mach/pinmux.h>
31#include <mach/pinmux-tegra30.h>
32#include <mach/suspend.h>
33
34#define PINGROUP_REG_A 0x868
35#define MUXCTL_REG_A 0x3000
36
37#define DRIVE_PINGROUP(pg_name, r) \
38 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
39 .name = #pg_name, \
40 .reg_bank = 0, \
41 .reg = ((r) - PINGROUP_REG_A) \
42 }
43
44static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
45 DRIVE_PINGROUP(AO1, 0x868),
46 DRIVE_PINGROUP(AO2, 0x86c),
47 DRIVE_PINGROUP(AT1, 0x870),
48 DRIVE_PINGROUP(AT2, 0x874),
49 DRIVE_PINGROUP(AT3, 0x878),
50 DRIVE_PINGROUP(AT4, 0x87c),
51 DRIVE_PINGROUP(AT5, 0x880),
52 DRIVE_PINGROUP(CDEV1, 0x884),
53 DRIVE_PINGROUP(CDEV2, 0x888),
54 DRIVE_PINGROUP(CSUS, 0x88c),
55 DRIVE_PINGROUP(DAP1, 0x890),
56 DRIVE_PINGROUP(DAP2, 0x894),
57 DRIVE_PINGROUP(DAP3, 0x898),
58 DRIVE_PINGROUP(DAP4, 0x89c),
59 DRIVE_PINGROUP(DBG, 0x8a0),
60 DRIVE_PINGROUP(LCD1, 0x8a4),
61 DRIVE_PINGROUP(LCD2, 0x8a8),
62 DRIVE_PINGROUP(SDIO2, 0x8ac),
63 DRIVE_PINGROUP(SDIO3, 0x8b0),
64 DRIVE_PINGROUP(SPI, 0x8b4),
65 DRIVE_PINGROUP(UAA, 0x8b8),
66 DRIVE_PINGROUP(UAB, 0x8bc),
67 DRIVE_PINGROUP(UART2, 0x8c0),
68 DRIVE_PINGROUP(UART3, 0x8c4),
69 DRIVE_PINGROUP(VI1, 0x8c8),
70 DRIVE_PINGROUP(SDIO1, 0x8ec),
71 DRIVE_PINGROUP(CRT, 0x8f8),
72 DRIVE_PINGROUP(DDC, 0x8fc),
73 DRIVE_PINGROUP(GMA, 0x900),
74 DRIVE_PINGROUP(GMB, 0x904),
75 DRIVE_PINGROUP(GMC, 0x908),
76 DRIVE_PINGROUP(GMD, 0x90c),
77 DRIVE_PINGROUP(GME, 0x910),
78 DRIVE_PINGROUP(GMF, 0x914),
79 DRIVE_PINGROUP(GMG, 0x918),
80 DRIVE_PINGROUP(GMH, 0x91c),
81 DRIVE_PINGROUP(OWR, 0x920),
82 DRIVE_PINGROUP(UAD, 0x924),
83 DRIVE_PINGROUP(GPV, 0x928),
84 DRIVE_PINGROUP(DEV3, 0x92c),
85 DRIVE_PINGROUP(CEC, 0x938),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
89 [TEGRA_PINGROUP_ ## pg_name] = { \
90 .name = #pg_name, \
91 .vddio = TEGRA_VDDIO_ ## vdd, \
92 .funcs = { \
93 TEGRA_MUX_ ## f0, \
94 TEGRA_MUX_ ## f1, \
95 TEGRA_MUX_ ## f2, \
96 TEGRA_MUX_ ## f3, \
97 }, \
98 .func_safe = TEGRA_MUX_ ## fs, \
99 .tri_bank = 1, \
100 .tri_reg = ((reg) - MUXCTL_REG_A), \
101 .tri_bit = 4, \
102 .mux_bank = 1, \
103 .mux_reg = ((reg) - MUXCTL_REG_A), \
104 .mux_bit = 0, \
105 .pupd_bank = 1, \
106 .pupd_reg = ((reg) - MUXCTL_REG_A), \
107 .pupd_bit = 2, \
108 .io_default = TEGRA_PIN_ ## iod, \
109 .od_bit = 6, \
110 .lock_bit = 7, \
111 .ioreset_bit = 8, \
112 }
113
114static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
115 /* NAME VDD f0 f1 f2 f3 fSafe io reg */
116 PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
117 PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
118 PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
119 PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
120 PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
121 PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
122 PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
123 PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
124 PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
125 PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
126 PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
127 PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
128 PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
129 PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
130 PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
131 PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
132 PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
133 PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
134 PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
135 PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
136 PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
137 PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
138 PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
139 PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
140 PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
141 PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
142 PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
143 PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
144 PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
145 PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
146 PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
147 PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
148 PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
149 PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
150 PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
151 PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
152 PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
153 PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
154 PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
155 PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
156 PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
157 PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
158 PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
159 PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
160 PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
161 PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
162 PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
163 PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
164 PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
165 PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
166 PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
167 PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
168 PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
169 PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
170 PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
171 PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
172 PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
173 PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
174 PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
175 PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
176 PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
177 PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
178 PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
179 PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
180 PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
181 PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
182 PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
183 PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
184 PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
185 PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
186 PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
187 PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
188 PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
189 PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
190 PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
191 PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
192 PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
193 PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
194 PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
195 PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
196 PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
197 PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
198 PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
199 PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
200 PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
201 PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
202 PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
203 PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
204 PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
205 PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
206 PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
207 PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
208 PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
209 PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
210 PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
211 PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
212 PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
213 PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
214 PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
215 PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
216 PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
217 PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
218 PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
219 PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
220 PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
221 PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
222 PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
223 PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
224 PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
225 PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
226 PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
227 PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
228 PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
229 PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
230 PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
231 PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
232 PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
233 PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
234 PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
235 PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
236 PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
237 PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
238 PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
239 PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
240 PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
241 PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
242 PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
243 PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
244 PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
245 PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
246 PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
247 PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
248 PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
249 PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
250 PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
251 PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
252 PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
253 PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
254 PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
255 PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
256 PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
257 PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
258 PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
259 PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
260 PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
261 PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
262 PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
263 PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
264 PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
265 PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
266 PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
267 PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
268 PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
269 PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
270 PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
271 PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
272 PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
273 PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
274 PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
275 PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
276 PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
277 PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
278 PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
279 PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
280 PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
281 PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
282 PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
283 PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
284 PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
285 PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
286 PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
287 PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
288 PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
289 PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
290 PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
291 PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
292 PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
293 PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
294 PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
295 PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
296 PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
297 PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
298 PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
299 PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
300 PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
301 PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
302 PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
303 PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
304 PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
305 PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
306 PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
307 PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
308 PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
309 PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
310 PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
311 PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
312 PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
313 PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
314 PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
315 PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
316 PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
317 PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
318 PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
319 PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
320 PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
321 PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
322 PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
323 PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
324 PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
325 PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
326 PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
327 PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
328 PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
329 PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
330 PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
331 PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
332 PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
333 PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
334 PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
335 PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
336 PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
337 PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
338 PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
339 PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
340 PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
341 PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
342 PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
343 PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
344 PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
345 PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
346 PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
347 PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
348 PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
349 PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
350 PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
351 PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
352 PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
353 PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
354 PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
355 PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
356 PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
357 PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
358 PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
359 PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
360 PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
361 PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
362 PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
363 PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
364 PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
365};
366
367void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
368 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
369 int *pgdrive_max)
370{
371 *pg = tegra_soc_pingroups;
372 *pg_max = TEGRA_MAX_PINGROUP;
373 *pgdrive = tegra_soc_drive_pingroups;
374 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
375}
376
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
deleted file mode 100644
index ac35d2b76850..000000000000
--- a/arch/arm/mach-tegra/pinmux.c
+++ /dev/null
@@ -1,987 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/spinlock.h>
22#include <linux/io.h>
23#include <linux/platform_device.h>
24#include <linux/of_device.h>
25
26#include <mach/iomap.h>
27#include <mach/pinmux.h>
28
29#define HSM_EN(reg) (((reg) >> 2) & 0x1)
30#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
31#define LPMD(reg) (((reg) >> 4) & 0x3)
32#define DRVDN(reg) (((reg) >> 12) & 0x1f)
33#define DRVUP(reg) (((reg) >> 20) & 0x1f)
34#define SLWR(reg) (((reg) >> 28) & 0x3)
35#define SLWF(reg) (((reg) >> 30) & 0x3)
36
37static const struct tegra_pingroup_desc *pingroups;
38static const struct tegra_drive_pingroup_desc *drive_pingroups;
39static int pingroup_max;
40static int drive_max;
41
42static char *tegra_mux_names[TEGRA_MAX_MUX] = {
43 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
44 [TEGRA_MUX_APB_CLK] = "APB_CLK",
45 [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
46 [TEGRA_MUX_CRT] = "CRT",
47 [TEGRA_MUX_DAP1] = "DAP1",
48 [TEGRA_MUX_DAP2] = "DAP2",
49 [TEGRA_MUX_DAP3] = "DAP3",
50 [TEGRA_MUX_DAP4] = "DAP4",
51 [TEGRA_MUX_DAP5] = "DAP5",
52 [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
53 [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
54 [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
55 [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
56 [TEGRA_MUX_GMI] = "GMI",
57 [TEGRA_MUX_GMI_INT] = "GMI_INT",
58 [TEGRA_MUX_HDMI] = "HDMI",
59 [TEGRA_MUX_I2C] = "I2C",
60 [TEGRA_MUX_I2C2] = "I2C2",
61 [TEGRA_MUX_I2C3] = "I2C3",
62 [TEGRA_MUX_IDE] = "IDE",
63 [TEGRA_MUX_IRDA] = "IRDA",
64 [TEGRA_MUX_KBC] = "KBC",
65 [TEGRA_MUX_MIO] = "MIO",
66 [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
67 [TEGRA_MUX_NAND] = "NAND",
68 [TEGRA_MUX_OSC] = "OSC",
69 [TEGRA_MUX_OWR] = "OWR",
70 [TEGRA_MUX_PCIE] = "PCIE",
71 [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
72 [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
73 [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
74 [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
75 [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
76 [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
77 [TEGRA_MUX_PWM] = "PWM",
78 [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
79 [TEGRA_MUX_PWR_ON] = "PWR_ON",
80 [TEGRA_MUX_RTCK] = "RTCK",
81 [TEGRA_MUX_SDIO1] = "SDIO1",
82 [TEGRA_MUX_SDIO2] = "SDIO2",
83 [TEGRA_MUX_SDIO3] = "SDIO3",
84 [TEGRA_MUX_SDIO4] = "SDIO4",
85 [TEGRA_MUX_SFLASH] = "SFLASH",
86 [TEGRA_MUX_SPDIF] = "SPDIF",
87 [TEGRA_MUX_SPI1] = "SPI1",
88 [TEGRA_MUX_SPI2] = "SPI2",
89 [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
90 [TEGRA_MUX_SPI3] = "SPI3",
91 [TEGRA_MUX_SPI4] = "SPI4",
92 [TEGRA_MUX_TRACE] = "TRACE",
93 [TEGRA_MUX_TWC] = "TWC",
94 [TEGRA_MUX_UARTA] = "UARTA",
95 [TEGRA_MUX_UARTB] = "UARTB",
96 [TEGRA_MUX_UARTC] = "UARTC",
97 [TEGRA_MUX_UARTD] = "UARTD",
98 [TEGRA_MUX_UARTE] = "UARTE",
99 [TEGRA_MUX_ULPI] = "ULPI",
100 [TEGRA_MUX_VI] = "VI",
101 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
102 [TEGRA_MUX_XIO] = "XIO",
103 [TEGRA_MUX_BLINK] = "BLINK",
104 [TEGRA_MUX_CEC] = "CEC",
105 [TEGRA_MUX_CLK12] = "CLK12",
106 [TEGRA_MUX_DAP] = "DAP",
107 [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
108 [TEGRA_MUX_DDR] = "DDR",
109 [TEGRA_MUX_DEV3] = "DEV3",
110 [TEGRA_MUX_DTV] = "DTV",
111 [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
112 [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
113 [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
114 [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
115 [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
116 [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
117 [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
118 [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
119 [TEGRA_MUX_HDA] = "HDA",
120 [TEGRA_MUX_HSI] = "HSI",
121 [TEGRA_MUX_I2C4] = "I2C4",
122 [TEGRA_MUX_I2C5] = "I2C5",
123 [TEGRA_MUX_I2CPWR] = "I2CPWR",
124 [TEGRA_MUX_I2S0] = "I2S0",
125 [TEGRA_MUX_I2S1] = "I2S1",
126 [TEGRA_MUX_I2S2] = "I2S2",
127 [TEGRA_MUX_I2S3] = "I2S3",
128 [TEGRA_MUX_I2S4] = "I2S4",
129 [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
130 [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
131 [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
132 [TEGRA_MUX_PWM0] = "PWM0",
133 [TEGRA_MUX_PWM1] = "PWM2",
134 [TEGRA_MUX_PWM2] = "PWM2",
135 [TEGRA_MUX_PWM3] = "PWM3",
136 [TEGRA_MUX_SATA] = "SATA",
137 [TEGRA_MUX_SPI5] = "SPI5",
138 [TEGRA_MUX_SPI6] = "SPI6",
139 [TEGRA_MUX_SYSCLK] = "SYSCLK",
140 [TEGRA_MUX_VGP1] = "VGP1",
141 [TEGRA_MUX_VGP2] = "VGP2",
142 [TEGRA_MUX_VGP3] = "VGP3",
143 [TEGRA_MUX_VGP4] = "VGP4",
144 [TEGRA_MUX_VGP5] = "VGP5",
145 [TEGRA_MUX_VGP6] = "VGP6",
146 [TEGRA_MUX_SAFE] = "<safe>",
147};
148
149static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
150 [TEGRA_DRIVE_DIV_8] = "DIV_8",
151 [TEGRA_DRIVE_DIV_4] = "DIV_4",
152 [TEGRA_DRIVE_DIV_2] = "DIV_2",
153 [TEGRA_DRIVE_DIV_1] = "DIV_1",
154};
155
156static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
157 [TEGRA_SLEW_FASTEST] = "FASTEST",
158 [TEGRA_SLEW_FAST] = "FAST",
159 [TEGRA_SLEW_SLOW] = "SLOW",
160 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
161};
162
163static DEFINE_SPINLOCK(mux_lock);
164
165static const char *pingroup_name(int pg)
166{
167 if (pg < 0 || pg >= pingroup_max)
168 return "<UNKNOWN>";
169
170 return pingroups[pg].name;
171}
172
173static const char *func_name(enum tegra_mux_func func)
174{
175 if (func == TEGRA_MUX_RSVD1)
176 return "RSVD1";
177
178 if (func == TEGRA_MUX_RSVD2)
179 return "RSVD2";
180
181 if (func == TEGRA_MUX_RSVD3)
182 return "RSVD3";
183
184 if (func == TEGRA_MUX_RSVD4)
185 return "RSVD4";
186
187 if (func == TEGRA_MUX_NONE)
188 return "NONE";
189
190 if (func < 0 || func >= TEGRA_MAX_MUX)
191 return "<UNKNOWN>";
192
193 return tegra_mux_names[func];
194}
195
196
197static const char *tri_name(unsigned long val)
198{
199 return val ? "TRISTATE" : "NORMAL";
200}
201
202static const char *pupd_name(unsigned long val)
203{
204 switch (val) {
205 case 0:
206 return "NORMAL";
207
208 case 1:
209 return "PULL_DOWN";
210
211 case 2:
212 return "PULL_UP";
213
214 default:
215 return "RSVD";
216 }
217}
218
219static int nbanks;
220static void __iomem **regs;
221
222static inline u32 pg_readl(u32 bank, u32 reg)
223{
224 return readl(regs[bank] + reg);
225}
226
227static inline void pg_writel(u32 val, u32 bank, u32 reg)
228{
229 writel(val, regs[bank] + reg);
230}
231
232static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
233{
234 int mux = -1;
235 int i;
236 unsigned long reg;
237 unsigned long flags;
238 int pg = config->pingroup;
239 enum tegra_mux_func func = config->func;
240
241 if (pg < 0 || pg >= pingroup_max)
242 return -ERANGE;
243
244 if (pingroups[pg].mux_reg < 0)
245 return -EINVAL;
246
247 if (func < 0)
248 return -ERANGE;
249
250 if (func == TEGRA_MUX_SAFE)
251 func = pingroups[pg].func_safe;
252
253 if (func & TEGRA_MUX_RSVD) {
254 mux = func & 0x3;
255 } else {
256 for (i = 0; i < 4; i++) {
257 if (pingroups[pg].funcs[i] == func) {
258 mux = i;
259 break;
260 }
261 }
262 }
263
264 if (mux < 0)
265 return -EINVAL;
266
267 spin_lock_irqsave(&mux_lock, flags);
268
269 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
270 reg &= ~(0x3 << pingroups[pg].mux_bit);
271 reg |= mux << pingroups[pg].mux_bit;
272 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
273
274 spin_unlock_irqrestore(&mux_lock, flags);
275
276 return 0;
277}
278
279int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
280{
281 unsigned long reg;
282 unsigned long flags;
283
284 if (pg < 0 || pg >= pingroup_max)
285 return -ERANGE;
286
287 if (pingroups[pg].tri_reg < 0)
288 return -EINVAL;
289
290 spin_lock_irqsave(&mux_lock, flags);
291
292 reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
293 reg &= ~(0x1 << pingroups[pg].tri_bit);
294 if (tristate)
295 reg |= 1 << pingroups[pg].tri_bit;
296 pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
297
298 spin_unlock_irqrestore(&mux_lock, flags);
299
300 return 0;
301}
302
303int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
304{
305 unsigned long reg;
306 unsigned long flags;
307
308 if (pg < 0 || pg >= pingroup_max)
309 return -ERANGE;
310
311 if (pingroups[pg].pupd_reg < 0)
312 return -EINVAL;
313
314 if (pupd != TEGRA_PUPD_NORMAL &&
315 pupd != TEGRA_PUPD_PULL_DOWN &&
316 pupd != TEGRA_PUPD_PULL_UP)
317 return -EINVAL;
318
319
320 spin_lock_irqsave(&mux_lock, flags);
321
322 reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
323 reg &= ~(0x3 << pingroups[pg].pupd_bit);
324 reg |= pupd << pingroups[pg].pupd_bit;
325 pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
326
327 spin_unlock_irqrestore(&mux_lock, flags);
328
329 return 0;
330}
331
332static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
333{
334 int pingroup = config->pingroup;
335 enum tegra_mux_func func = config->func;
336 enum tegra_pullupdown pupd = config->pupd;
337 enum tegra_tristate tristate = config->tristate;
338 int err;
339
340 if (pingroups[pingroup].mux_reg >= 0) {
341 err = tegra_pinmux_set_func(config);
342 if (err < 0)
343 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
344 pingroup_name(pingroup), func_name(func), err);
345 }
346
347 if (pingroups[pingroup].pupd_reg >= 0) {
348 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
349 if (err < 0)
350 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
351 pingroup_name(pingroup), pupd_name(pupd), err);
352 }
353
354 if (pingroups[pingroup].tri_reg >= 0) {
355 err = tegra_pinmux_set_tristate(pingroup, tristate);
356 if (err < 0)
357 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
358 pingroup_name(pingroup), tri_name(func), err);
359 }
360}
361
362void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
363{
364 int i;
365
366 for (i = 0; i < len; i++)
367 tegra_pinmux_config_pingroup(&config[i]);
368}
369
370static const char *drive_pinmux_name(int pg)
371{
372 if (pg < 0 || pg >= drive_max)
373 return "<UNKNOWN>";
374
375 return drive_pingroups[pg].name;
376}
377
378static const char *enable_name(unsigned long val)
379{
380 return val ? "ENABLE" : "DISABLE";
381}
382
383static const char *drive_name(unsigned long val)
384{
385 if (val >= TEGRA_MAX_DRIVE)
386 return "<UNKNOWN>";
387
388 return tegra_drive_names[val];
389}
390
391static const char *slew_name(unsigned long val)
392{
393 if (val >= TEGRA_MAX_SLEW)
394 return "<UNKNOWN>";
395
396 return tegra_slew_names[val];
397}
398
399static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
400{
401 unsigned long flags;
402 u32 reg;
403 if (pg < 0 || pg >= drive_max)
404 return -ERANGE;
405
406 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
407 return -EINVAL;
408
409 spin_lock_irqsave(&mux_lock, flags);
410
411 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
412 if (hsm == TEGRA_HSM_ENABLE)
413 reg |= (1 << 2);
414 else
415 reg &= ~(1 << 2);
416 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
417
418 spin_unlock_irqrestore(&mux_lock, flags);
419
420 return 0;
421}
422
423static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
424{
425 unsigned long flags;
426 u32 reg;
427 if (pg < 0 || pg >= drive_max)
428 return -ERANGE;
429
430 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
431 return -EINVAL;
432
433 spin_lock_irqsave(&mux_lock, flags);
434
435 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
436 if (schmitt == TEGRA_SCHMITT_ENABLE)
437 reg |= (1 << 3);
438 else
439 reg &= ~(1 << 3);
440 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
441
442 spin_unlock_irqrestore(&mux_lock, flags);
443
444 return 0;
445}
446
447static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
448{
449 unsigned long flags;
450 u32 reg;
451 if (pg < 0 || pg >= drive_max)
452 return -ERANGE;
453
454 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
455 return -EINVAL;
456
457 spin_lock_irqsave(&mux_lock, flags);
458
459 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
460 reg &= ~(0x3 << 4);
461 reg |= drive << 4;
462 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
463
464 spin_unlock_irqrestore(&mux_lock, flags);
465
466 return 0;
467}
468
469static int tegra_drive_pinmux_set_pull_down(int pg,
470 enum tegra_pull_strength pull_down)
471{
472 unsigned long flags;
473 u32 reg;
474 if (pg < 0 || pg >= drive_max)
475 return -ERANGE;
476
477 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
478 return -EINVAL;
479
480 spin_lock_irqsave(&mux_lock, flags);
481
482 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
483 reg &= ~(0x1f << 12);
484 reg |= pull_down << 12;
485 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
486
487 spin_unlock_irqrestore(&mux_lock, flags);
488
489 return 0;
490}
491
492static int tegra_drive_pinmux_set_pull_up(int pg,
493 enum tegra_pull_strength pull_up)
494{
495 unsigned long flags;
496 u32 reg;
497 if (pg < 0 || pg >= drive_max)
498 return -ERANGE;
499
500 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
501 return -EINVAL;
502
503 spin_lock_irqsave(&mux_lock, flags);
504
505 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
506 reg &= ~(0x1f << 12);
507 reg |= pull_up << 12;
508 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
509
510 spin_unlock_irqrestore(&mux_lock, flags);
511
512 return 0;
513}
514
515static int tegra_drive_pinmux_set_slew_rising(int pg,
516 enum tegra_slew slew_rising)
517{
518 unsigned long flags;
519 u32 reg;
520 if (pg < 0 || pg >= drive_max)
521 return -ERANGE;
522
523 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
524 return -EINVAL;
525
526 spin_lock_irqsave(&mux_lock, flags);
527
528 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
529 reg &= ~(0x3 << 28);
530 reg |= slew_rising << 28;
531 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
532
533 spin_unlock_irqrestore(&mux_lock, flags);
534
535 return 0;
536}
537
538static int tegra_drive_pinmux_set_slew_falling(int pg,
539 enum tegra_slew slew_falling)
540{
541 unsigned long flags;
542 u32 reg;
543 if (pg < 0 || pg >= drive_max)
544 return -ERANGE;
545
546 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
547 return -EINVAL;
548
549 spin_lock_irqsave(&mux_lock, flags);
550
551 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
552 reg &= ~(0x3 << 30);
553 reg |= slew_falling << 30;
554 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
555
556 spin_unlock_irqrestore(&mux_lock, flags);
557
558 return 0;
559}
560
561static void tegra_drive_pinmux_config_pingroup(int pingroup,
562 enum tegra_hsm hsm,
563 enum tegra_schmitt schmitt,
564 enum tegra_drive drive,
565 enum tegra_pull_strength pull_down,
566 enum tegra_pull_strength pull_up,
567 enum tegra_slew slew_rising,
568 enum tegra_slew slew_falling)
569{
570 int err;
571
572 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
573 if (err < 0)
574 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
575 drive_pinmux_name(pingroup),
576 enable_name(hsm), err);
577
578 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
579 if (err < 0)
580 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
581 drive_pinmux_name(pingroup),
582 enable_name(schmitt), err);
583
584 err = tegra_drive_pinmux_set_drive(pingroup, drive);
585 if (err < 0)
586 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
587 drive_pinmux_name(pingroup),
588 drive_name(drive), err);
589
590 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
591 if (err < 0)
592 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
593 drive_pinmux_name(pingroup),
594 pull_down, err);
595
596 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
597 if (err < 0)
598 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
599 drive_pinmux_name(pingroup),
600 pull_up, err);
601
602 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
603 if (err < 0)
604 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
605 drive_pinmux_name(pingroup),
606 slew_name(slew_rising), err);
607
608 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
609 if (err < 0)
610 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
611 drive_pinmux_name(pingroup),
612 slew_name(slew_falling), err);
613}
614
615void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
616 int len)
617{
618 int i;
619
620 for (i = 0; i < len; i++)
621 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
622 config[i].hsm,
623 config[i].schmitt,
624 config[i].drive,
625 config[i].pull_down,
626 config[i].pull_up,
627 config[i].slew_rising,
628 config[i].slew_falling);
629}
630
631void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
632 int len)
633{
634 int i;
635 struct tegra_pingroup_config c;
636
637 for (i = 0; i < len; i++) {
638 int err;
639 c = config[i];
640 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
641 WARN_ON(1);
642 continue;
643 }
644 c.func = pingroups[c.pingroup].func_safe;
645 err = tegra_pinmux_set_func(&c);
646 if (err < 0)
647 pr_err("%s: tegra_pinmux_set_func returned %d setting "
648 "%s to %s\n", __func__, err,
649 pingroup_name(c.pingroup), func_name(c.func));
650 }
651}
652
653void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
654 int len)
655{
656 int i;
657
658 for (i = 0; i < len; i++) {
659 int err;
660 if (config[i].pingroup < 0 ||
661 config[i].pingroup >= pingroup_max) {
662 WARN_ON(1);
663 continue;
664 }
665 err = tegra_pinmux_set_func(&config[i]);
666 if (err < 0)
667 pr_err("%s: tegra_pinmux_set_func returned %d setting "
668 "%s to %s\n", __func__, err,
669 pingroup_name(config[i].pingroup),
670 func_name(config[i].func));
671 }
672}
673
674void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
675 int len, enum tegra_tristate tristate)
676{
677 int i;
678 int err;
679 int pingroup;
680
681 for (i = 0; i < len; i++) {
682 pingroup = config[i].pingroup;
683 if (pingroups[pingroup].tri_reg >= 0) {
684 err = tegra_pinmux_set_tristate(pingroup, tristate);
685 if (err < 0)
686 pr_err("pinmux: can't set pingroup %s tristate"
687 " to %s: %d\n", pingroup_name(pingroup),
688 tri_name(tristate), err);
689 }
690 }
691}
692
693void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
694 int len, enum tegra_pullupdown pupd)
695{
696 int i;
697 int err;
698 int pingroup;
699
700 for (i = 0; i < len; i++) {
701 pingroup = config[i].pingroup;
702 if (pingroups[pingroup].pupd_reg >= 0) {
703 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
704 if (err < 0)
705 pr_err("pinmux: can't set pingroup %s pullupdown"
706 " to %s: %d\n", pingroup_name(pingroup),
707 pupd_name(pupd), err);
708 }
709 }
710}
711
712static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
713#ifdef CONFIG_ARCH_TEGRA_2x_SOC
714 { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
715#endif
716#ifdef CONFIG_ARCH_TEGRA_3x_SOC
717 { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
718#endif
719 { },
720};
721
722static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
723{
724 struct resource *res;
725 int i;
726 int config_bad = 0;
727 const struct of_device_id *match;
728
729 match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
730
731 if (match)
732 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
733 &drive_pingroups, &drive_max);
734#ifdef CONFIG_ARCH_TEGRA_2x_SOC
735 else
736 /* no device tree available, so we must be on tegra20 */
737 tegra20_pinmux_init(&pingroups, &pingroup_max,
738 &drive_pingroups, &drive_max);
739#else
740 pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
741#endif
742
743 for (i = 0; ; i++) {
744 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
745 if (!res)
746 break;
747 }
748 nbanks = i;
749
750 for (i = 0; i < pingroup_max; i++) {
751 if (pingroups[i].tri_bank >= nbanks) {
752 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
753 config_bad = 1;
754 }
755
756 if (pingroups[i].mux_bank >= nbanks) {
757 dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
758 config_bad = 1;
759 }
760
761 if (pingroups[i].pupd_bank >= nbanks) {
762 dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
763 config_bad = 1;
764 }
765 }
766
767 for (i = 0; i < drive_max; i++) {
768 if (drive_pingroups[i].reg_bank >= nbanks) {
769 dev_err(&pdev->dev,
770 "drive pingroup %d: bad reg_bank\n", i);
771 config_bad = 1;
772 }
773 }
774
775 if (config_bad)
776 return -ENODEV;
777
778 regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
779 if (!regs) {
780 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
781 return -ENODEV;
782 }
783
784 for (i = 0; i < nbanks; i++) {
785 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
786 if (!res) {
787 dev_err(&pdev->dev, "Missing MEM resource\n");
788 return -ENODEV;
789 }
790
791 if (!devm_request_mem_region(&pdev->dev, res->start,
792 resource_size(res),
793 dev_name(&pdev->dev))) {
794 dev_err(&pdev->dev,
795 "Couldn't request MEM resource %d\n", i);
796 return -ENODEV;
797 }
798
799 regs[i] = devm_ioremap(&pdev->dev, res->start,
800 resource_size(res));
801 if (!regs) {
802 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
803 return -ENODEV;
804 }
805 }
806
807 return 0;
808}
809
810static struct platform_driver tegra_pinmux_driver = {
811 .driver = {
812 .name = "tegra-pinmux",
813 .owner = THIS_MODULE,
814 .of_match_table = tegra_pinmux_of_match,
815 },
816 .probe = tegra_pinmux_probe,
817};
818
819static int __init tegra_pinmux_init(void)
820{
821 return platform_driver_register(&tegra_pinmux_driver);
822}
823postcore_initcall(tegra_pinmux_init);
824
825#ifdef CONFIG_DEBUG_FS
826
827#include <linux/debugfs.h>
828#include <linux/seq_file.h>
829
830static void dbg_pad_field(struct seq_file *s, int len)
831{
832 seq_putc(s, ',');
833
834 while (len-- > -1)
835 seq_putc(s, ' ');
836}
837
838static int dbg_pinmux_show(struct seq_file *s, void *unused)
839{
840 int i;
841 int len;
842
843 for (i = 0; i < pingroup_max; i++) {
844 unsigned long reg;
845 unsigned long tri;
846 unsigned long mux;
847 unsigned long pupd;
848
849 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
850 len = strlen(pingroups[i].name);
851 dbg_pad_field(s, 5 - len);
852
853 if (pingroups[i].mux_reg < 0) {
854 seq_printf(s, "TEGRA_MUX_NONE");
855 len = strlen("NONE");
856 } else {
857 reg = pg_readl(pingroups[i].mux_bank,
858 pingroups[i].mux_reg);
859 mux = (reg >> pingroups[i].mux_bit) & 0x3;
860 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
861 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
862 len = 5;
863 } else {
864 seq_printf(s, "TEGRA_MUX_%s",
865 tegra_mux_names[pingroups[i].funcs[mux]]);
866 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
867 }
868 }
869 dbg_pad_field(s, 13-len);
870
871 if (pingroups[i].pupd_reg < 0) {
872 seq_printf(s, "TEGRA_PUPD_NORMAL");
873 len = strlen("NORMAL");
874 } else {
875 reg = pg_readl(pingroups[i].pupd_bank,
876 pingroups[i].pupd_reg);
877 pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
878 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
879 len = strlen(pupd_name(pupd));
880 }
881 dbg_pad_field(s, 9 - len);
882
883 if (pingroups[i].tri_reg < 0) {
884 seq_printf(s, "TEGRA_TRI_NORMAL");
885 } else {
886 reg = pg_readl(pingroups[i].tri_bank,
887 pingroups[i].tri_reg);
888 tri = (reg >> pingroups[i].tri_bit) & 0x1;
889
890 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
891 }
892 seq_printf(s, "},\n");
893 }
894 return 0;
895}
896
897static int dbg_pinmux_open(struct inode *inode, struct file *file)
898{
899 return single_open(file, dbg_pinmux_show, &inode->i_private);
900}
901
902static const struct file_operations debug_fops = {
903 .open = dbg_pinmux_open,
904 .read = seq_read,
905 .llseek = seq_lseek,
906 .release = single_release,
907};
908
909static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
910{
911 int i;
912 int len;
913
914 for (i = 0; i < drive_max; i++) {
915 u32 reg;
916
917 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
918 drive_pingroups[i].name);
919 len = strlen(drive_pingroups[i].name);
920 dbg_pad_field(s, 7 - len);
921
922
923 reg = pg_readl(drive_pingroups[i].reg_bank,
924 drive_pingroups[i].reg);
925 if (HSM_EN(reg)) {
926 seq_printf(s, "TEGRA_HSM_ENABLE");
927 len = 16;
928 } else {
929 seq_printf(s, "TEGRA_HSM_DISABLE");
930 len = 17;
931 }
932 dbg_pad_field(s, 17 - len);
933
934 if (SCHMT_EN(reg)) {
935 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
936 len = 21;
937 } else {
938 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
939 len = 22;
940 }
941 dbg_pad_field(s, 22 - len);
942
943 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
944 len = strlen(drive_name(LPMD(reg)));
945 dbg_pad_field(s, 5 - len);
946
947 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
948 len = DRVDN(reg) < 10 ? 1 : 2;
949 dbg_pad_field(s, 2 - len);
950
951 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
952 len = DRVUP(reg) < 10 ? 1 : 2;
953 dbg_pad_field(s, 2 - len);
954
955 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
956 len = strlen(slew_name(SLWR(reg)));
957 dbg_pad_field(s, 7 - len);
958
959 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
960
961 seq_printf(s, "},\n");
962 }
963 return 0;
964}
965
966static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
967{
968 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
969}
970
971static const struct file_operations debug_drive_fops = {
972 .open = dbg_drive_pinmux_open,
973 .read = seq_read,
974 .llseek = seq_lseek,
975 .release = single_release,
976};
977
978static int __init tegra_pinmux_debuginit(void)
979{
980 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
981 NULL, NULL, &debug_fops);
982 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
983 NULL, NULL, &debug_drive_fops);
984 return 0;
985}
986late_initcall(tegra_pinmux_debuginit);
987#endif
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index c5b2ac04e2a0..d71d2fed6721 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
711 err = -ENXIO; 711 err = -ENXIO;
712 goto err1; 712 goto err1;
713 } 713 }
714 tegra_gpio_enable(ulpi_config->reset_gpio);
715 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); 714 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
716 gpio_direction_output(ulpi_config->reset_gpio, 0); 715 gpio_direction_output(ulpi_config->reset_gpio, 0);
717 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); 716 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 12f349b3830d..dc5184d57892 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -26,10 +26,10 @@
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/irqdomain.h> 28#include <linux/irqdomain.h>
29#include <linux/pinctrl/consumer.h>
29 30
30#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
31 32
32#include <mach/gpio-tegra.h>
33#include <mach/iomap.h> 33#include <mach/iomap.h>
34#include <mach/suspend.h> 34#include <mach/suspend.h>
35 35
@@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
108 tegra_gpio_writel(val, reg); 108 tegra_gpio_writel(val, reg);
109} 109}
110 110
111void tegra_gpio_enable(int gpio) 111static void tegra_gpio_enable(int gpio)
112{ 112{
113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); 113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
114} 114}
115EXPORT_SYMBOL_GPL(tegra_gpio_enable); 115EXPORT_SYMBOL_GPL(tegra_gpio_enable);
116 116
117void tegra_gpio_disable(int gpio) 117static void tegra_gpio_disable(int gpio)
118{ 118{
119 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); 119 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
120} 120}
121EXPORT_SYMBOL_GPL(tegra_gpio_disable); 121EXPORT_SYMBOL_GPL(tegra_gpio_disable);
122 122
123int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
124{
125 return pinctrl_request_gpio(offset);
126}
127
128void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
129{
130 pinctrl_free_gpio(offset);
131 tegra_gpio_disable(offset);
132}
133
123static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 134static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
124{ 135{
125 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); 136 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
@@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
133static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 144static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
134{ 145{
135 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); 146 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
147 tegra_gpio_enable(offset);
136 return 0; 148 return 0;
137} 149}
138 150
@@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
141{ 153{
142 tegra_gpio_set(chip, offset, value); 154 tegra_gpio_set(chip, offset, value);
143 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); 155 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
156 tegra_gpio_enable(offset);
144 return 0; 157 return 0;
145} 158}
146 159
@@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
151 164
152static struct gpio_chip tegra_gpio_chip = { 165static struct gpio_chip tegra_gpio_chip = {
153 .label = "tegra-gpio", 166 .label = "tegra-gpio",
167 .request = tegra_gpio_request,
168 .free = tegra_gpio_free,
154 .direction_input = tegra_gpio_direction_input, 169 .direction_input = tegra_gpio_direction_input,
155 .get = tegra_gpio_get, 170 .get = tegra_gpio_get,
156 .direction_output = tegra_gpio_direction_output, 171 .direction_output = tegra_gpio_direction_output,
157 .set = tegra_gpio_set, 172 .set = tegra_gpio_set,
158 .to_irq = tegra_gpio_to_irq, 173 .to_irq = tegra_gpio_to_irq,
159 .base = 0, 174 .base = 0,
160 .ngpio = TEGRA_NR_GPIOS,
161}; 175};
162 176
163static void tegra_gpio_irq_ack(struct irq_data *d) 177static void tegra_gpio_irq_ack(struct irq_data *d)
@@ -224,6 +238,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
224 238
225 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 239 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
226 240
241 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
242 tegra_gpio_enable(gpio);
243
227 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 244 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
228 __irq_set_handler_locked(d->irq, handle_level_irq); 245 __irq_set_handler_locked(d->irq, handle_level_irq);
229 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 246 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -490,20 +507,6 @@ static int __init tegra_gpio_init(void)
490} 507}
491postcore_initcall(tegra_gpio_init); 508postcore_initcall(tegra_gpio_init);
492 509
493void tegra_gpio_config(struct tegra_gpio_table *table, int num)
494{
495 int i;
496
497 for (i = 0; i < num; i++) {
498 int gpio = table[i].gpio;
499
500 if (table[i].enable)
501 tegra_gpio_enable(gpio);
502 else
503 tegra_gpio_disable(gpio);
504 }
505}
506
507#ifdef CONFIG_DEBUG_FS 510#ifdef CONFIG_DEBUG_FS
508 511
509#include <linux/debugfs.h> 512#include <linux/debugfs.h>
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 53b26502f6e2..ff5a16991939 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
269 "failed to allocate power gpio\n"); 269 "failed to allocate power gpio\n");
270 goto err_power_req; 270 goto err_power_req;
271 } 271 }
272 tegra_gpio_enable(plat->power_gpio);
273 gpio_direction_output(plat->power_gpio, 1); 272 gpio_direction_output(plat->power_gpio, 1);
274 } 273 }
275 274
@@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
280 "failed to allocate cd gpio\n"); 279 "failed to allocate cd gpio\n");
281 goto err_cd_req; 280 goto err_cd_req;
282 } 281 }
283 tegra_gpio_enable(plat->cd_gpio);
284 gpio_direction_input(plat->cd_gpio); 282 gpio_direction_input(plat->cd_gpio);
285 283
286 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, 284 rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
@@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
301 "failed to allocate wp gpio\n"); 299 "failed to allocate wp gpio\n");
302 goto err_wp_req; 300 goto err_wp_req;
303 } 301 }
304 tegra_gpio_enable(plat->wp_gpio);
305 gpio_direction_input(plat->wp_gpio); 302 gpio_direction_input(plat->wp_gpio);
306 } 303 }
307 304
@@ -329,23 +326,17 @@ err_add_host:
329 clk_disable(pltfm_host->clk); 326 clk_disable(pltfm_host->clk);
330 clk_put(pltfm_host->clk); 327 clk_put(pltfm_host->clk);
331err_clk_get: 328err_clk_get:
332 if (gpio_is_valid(plat->wp_gpio)) { 329 if (gpio_is_valid(plat->wp_gpio))
333 tegra_gpio_disable(plat->wp_gpio);
334 gpio_free(plat->wp_gpio); 330 gpio_free(plat->wp_gpio);
335 }
336err_wp_req: 331err_wp_req:
337 if (gpio_is_valid(plat->cd_gpio)) 332 if (gpio_is_valid(plat->cd_gpio))
338 free_irq(gpio_to_irq(plat->cd_gpio), host); 333 free_irq(gpio_to_irq(plat->cd_gpio), host);
339err_cd_irq_req: 334err_cd_irq_req:
340 if (gpio_is_valid(plat->cd_gpio)) { 335 if (gpio_is_valid(plat->cd_gpio))
341 tegra_gpio_disable(plat->cd_gpio);
342 gpio_free(plat->cd_gpio); 336 gpio_free(plat->cd_gpio);
343 }
344err_cd_req: 337err_cd_req:
345 if (gpio_is_valid(plat->power_gpio)) { 338 if (gpio_is_valid(plat->power_gpio))
346 tegra_gpio_disable(plat->power_gpio);
347 gpio_free(plat->power_gpio); 339 gpio_free(plat->power_gpio);
348 }
349err_power_req: 340err_power_req:
350err_no_plat: 341err_no_plat:
351 sdhci_pltfm_free(pdev); 342 sdhci_pltfm_free(pdev);
@@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
362 353
363 sdhci_remove_host(host, dead); 354 sdhci_remove_host(host, dead);
364 355
365 if (gpio_is_valid(plat->wp_gpio)) { 356 if (gpio_is_valid(plat->wp_gpio))
366 tegra_gpio_disable(plat->wp_gpio);
367 gpio_free(plat->wp_gpio); 357 gpio_free(plat->wp_gpio);
368 }
369 358
370 if (gpio_is_valid(plat->cd_gpio)) { 359 if (gpio_is_valid(plat->cd_gpio)) {
371 free_irq(gpio_to_irq(plat->cd_gpio), host); 360 free_irq(gpio_to_irq(plat->cd_gpio), host);
372 tegra_gpio_disable(plat->cd_gpio);
373 gpio_free(plat->cd_gpio); 361 gpio_free(plat->cd_gpio);
374 } 362 }
375 363
376 if (gpio_is_valid(plat->power_gpio)) { 364 if (gpio_is_valid(plat->power_gpio))
377 tegra_gpio_disable(plat->power_gpio);
378 gpio_free(plat->power_gpio); 365 gpio_free(plat->power_gpio);
379 }
380 366
381 clk_disable(pltfm_host->clk); 367 clk_disable(pltfm_host->clk);
382 clk_put(pltfm_host->clk); 368 clk_put(pltfm_host->clk);
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 2c98fba01ca5..b6934867d8d3 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Driver for the NVIDIA Tegra pinmux 2 * Driver for the NVIDIA Tegra pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Derived from code: 6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc. 7 * Copyright (C) 2010 Google, Inc.
@@ -22,7 +22,8 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/of_device.h> 25#include <linux/of.h>
26#include <linux/platform_device.h>
26#include <linux/pinctrl/machine.h> 27#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinctrl.h> 28#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h> 29#include <linux/pinctrl/pinmux.h>
@@ -31,10 +32,9 @@
31 32
32#include <mach/pinconf-tegra.h> 33#include <mach/pinconf-tegra.h>
33 34
35#include "core.h"
34#include "pinctrl-tegra.h" 36#include "pinctrl-tegra.h"
35 37
36#define DRIVER_NAME "tegra-pinmux-disabled"
37
38struct tegra_pmx { 38struct tegra_pmx {
39 struct device *dev; 39 struct device *dev;
40 struct pinctrl_dev *pctl; 40 struct pinctrl_dev *pctl;
@@ -83,15 +83,18 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
83 return 0; 83 return 0;
84} 84}
85 85
86#ifdef CONFIG_DEBUG_FS
86static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 87static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
87 struct seq_file *s, 88 struct seq_file *s,
88 unsigned offset) 89 unsigned offset)
89{ 90{
90 seq_printf(s, " " DRIVER_NAME); 91 seq_printf(s, " %s", dev_name(pctldev->dev));
91} 92}
93#endif
92 94
93static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, 95static int reserve_map(struct device *dev, struct pinctrl_map **map,
94 unsigned *num_maps, unsigned reserve) 96 unsigned *reserved_maps, unsigned *num_maps,
97 unsigned reserve)
95{ 98{
96 unsigned old_num = *reserved_maps; 99 unsigned old_num = *reserved_maps;
97 unsigned new_num = *num_maps + reserve; 100 unsigned new_num = *num_maps + reserve;
@@ -101,8 +104,10 @@ static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
101 return 0; 104 return 0;
102 105
103 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); 106 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
104 if (!new_map) 107 if (!new_map) {
108 dev_err(dev, "krealloc(map) failed\n");
105 return -ENOMEM; 109 return -ENOMEM;
110 }
106 111
107 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); 112 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
108 113
@@ -116,7 +121,7 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
116 unsigned *num_maps, const char *group, 121 unsigned *num_maps, const char *group,
117 const char *function) 122 const char *function)
118{ 123{
119 if (*num_maps == *reserved_maps) 124 if (WARN_ON(*num_maps == *reserved_maps))
120 return -ENOSPC; 125 return -ENOSPC;
121 126
122 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; 127 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
@@ -127,19 +132,22 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
127 return 0; 132 return 0;
128} 133}
129 134
130static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps, 135static int add_map_configs(struct device *dev, struct pinctrl_map **map,
131 unsigned *num_maps, const char *group, 136 unsigned *reserved_maps, unsigned *num_maps,
132 unsigned long *configs, unsigned num_configs) 137 const char *group, unsigned long *configs,
138 unsigned num_configs)
133{ 139{
134 unsigned long *dup_configs; 140 unsigned long *dup_configs;
135 141
136 if (*num_maps == *reserved_maps) 142 if (WARN_ON(*num_maps == *reserved_maps))
137 return -ENOSPC; 143 return -ENOSPC;
138 144
139 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), 145 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
140 GFP_KERNEL); 146 GFP_KERNEL);
141 if (!dup_configs) 147 if (!dup_configs) {
148 dev_err(dev, "kmemdup(configs) failed\n");
142 return -ENOMEM; 149 return -ENOMEM;
150 }
143 151
144 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 152 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
145 (*map)[*num_maps].data.configs.group_or_pin = group; 153 (*map)[*num_maps].data.configs.group_or_pin = group;
@@ -150,8 +158,8 @@ static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
150 return 0; 158 return 0;
151} 159}
152 160
153static int add_config(unsigned long **configs, unsigned *num_configs, 161static int add_config(struct device *dev, unsigned long **configs,
154 unsigned long config) 162 unsigned *num_configs, unsigned long config)
155{ 163{
156 unsigned old_num = *num_configs; 164 unsigned old_num = *num_configs;
157 unsigned new_num = old_num + 1; 165 unsigned new_num = old_num + 1;
@@ -159,8 +167,10 @@ static int add_config(unsigned long **configs, unsigned *num_configs,
159 167
160 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, 168 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
161 GFP_KERNEL); 169 GFP_KERNEL);
162 if (!new_configs) 170 if (!new_configs) {
171 dev_err(dev, "krealloc(configs) failed\n");
163 return -ENOMEM; 172 return -ENOMEM;
173 }
164 174
165 new_configs[old_num] = config; 175 new_configs[old_num] = config;
166 176
@@ -201,7 +211,8 @@ static const struct cfg_param {
201 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 211 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
202}; 212};
203 213
204int tegra_pinctrl_dt_subnode_to_map(struct device_node *np, 214int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
215 struct device_node *np,
205 struct pinctrl_map **map, 216 struct pinctrl_map **map,
206 unsigned *reserved_maps, 217 unsigned *reserved_maps,
207 unsigned *num_maps) 218 unsigned *num_maps)
@@ -217,16 +228,25 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
217 const char *group; 228 const char *group;
218 229
219 ret = of_property_read_string(np, "nvidia,function", &function); 230 ret = of_property_read_string(np, "nvidia,function", &function);
220 if (ret < 0) 231 if (ret < 0) {
232 /* EINVAL=missing, which is fine since it's optional */
233 if (ret != -EINVAL)
234 dev_err(dev,
235 "could not parse property nvidia,function\n");
221 function = NULL; 236 function = NULL;
237 }
222 238
223 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { 239 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
224 ret = of_property_read_u32(np, cfg_params[i].property, &val); 240 ret = of_property_read_u32(np, cfg_params[i].property, &val);
225 if (!ret) { 241 if (!ret) {
226 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); 242 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
227 ret = add_config(&configs, &num_configs, config); 243 ret = add_config(dev, &configs, &num_configs, config);
228 if (ret < 0) 244 if (ret < 0)
229 goto exit; 245 goto exit;
246 /* EINVAL=missing, which is fine since it's optional */
247 } else if (ret != -EINVAL) {
248 dev_err(dev, "could not parse property %s\n",
249 cfg_params[i].property);
230 } 250 }
231 } 251 }
232 252
@@ -236,11 +256,13 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
236 if (num_configs) 256 if (num_configs)
237 reserve++; 257 reserve++;
238 ret = of_property_count_strings(np, "nvidia,pins"); 258 ret = of_property_count_strings(np, "nvidia,pins");
239 if (ret < 0) 259 if (ret < 0) {
260 dev_err(dev, "could not parse property nvidia,pins\n");
240 goto exit; 261 goto exit;
262 }
241 reserve *= ret; 263 reserve *= ret;
242 264
243 ret = reserve_map(map, reserved_maps, num_maps, reserve); 265 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
244 if (ret < 0) 266 if (ret < 0)
245 goto exit; 267 goto exit;
246 268
@@ -253,8 +275,9 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
253 } 275 }
254 276
255 if (num_configs) { 277 if (num_configs) {
256 ret = add_map_configs(map, reserved_maps, num_maps, 278 ret = add_map_configs(dev, map, reserved_maps,
257 group, configs, num_configs); 279 num_maps, group, configs,
280 num_configs);
258 if (ret < 0) 281 if (ret < 0)
259 goto exit; 282 goto exit;
260 } 283 }
@@ -280,8 +303,8 @@ int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
280 *num_maps = 0; 303 *num_maps = 0;
281 304
282 for_each_child_of_node(np_config, np) { 305 for_each_child_of_node(np_config, np) {
283 ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps, 306 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
284 num_maps); 307 &reserved_maps, num_maps);
285 if (ret < 0) { 308 if (ret < 0) {
286 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); 309 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
287 return ret; 310 return ret;
@@ -295,7 +318,9 @@ static struct pinctrl_ops tegra_pinctrl_ops = {
295 .get_groups_count = tegra_pinctrl_get_groups_count, 318 .get_groups_count = tegra_pinctrl_get_groups_count,
296 .get_group_name = tegra_pinctrl_get_group_name, 319 .get_group_name = tegra_pinctrl_get_group_name,
297 .get_group_pins = tegra_pinctrl_get_group_pins, 320 .get_group_pins = tegra_pinctrl_get_group_pins,
321#ifdef CONFIG_DEBUG_FS
298 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 322 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
323#endif
299 .dt_node_to_map = tegra_pinctrl_dt_node_to_map, 324 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
300 .dt_free_map = tegra_pinctrl_dt_free_map, 325 .dt_free_map = tegra_pinctrl_dt_free_map,
301}; 326};
@@ -338,14 +363,14 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
338 363
339 g = &pmx->soc->groups[group]; 364 g = &pmx->soc->groups[group];
340 365
341 if (g->mux_reg < 0) 366 if (WARN_ON(g->mux_reg < 0))
342 return -EINVAL; 367 return -EINVAL;
343 368
344 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 369 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
345 if (g->funcs[i] == function) 370 if (g->funcs[i] == function)
346 break; 371 break;
347 } 372 }
348 if (i == ARRAY_SIZE(g->funcs)) 373 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
349 return -EINVAL; 374 return -EINVAL;
350 375
351 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 376 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -365,7 +390,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
365 390
366 g = &pmx->soc->groups[group]; 391 g = &pmx->soc->groups[group];
367 392
368 if (g->mux_reg < 0) 393 if (WARN_ON(g->mux_reg < 0))
369 return; 394 return;
370 395
371 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 396 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -385,6 +410,7 @@ static struct pinmux_ops tegra_pinmux_ops = {
385static int tegra_pinconf_reg(struct tegra_pmx *pmx, 410static int tegra_pinconf_reg(struct tegra_pmx *pmx,
386 const struct tegra_pingroup *g, 411 const struct tegra_pingroup *g,
387 enum tegra_pinconf_param param, 412 enum tegra_pinconf_param param,
413 bool report_err,
388 s8 *bank, s16 *reg, s8 *bit, s8 *width) 414 s8 *bank, s16 *reg, s8 *bit, s8 *width)
389{ 415{
390 switch (param) { 416 switch (param) {
@@ -472,9 +498,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
472 } 498 }
473 499
474 if (*reg < 0) { 500 if (*reg < 0) {
475 dev_err(pmx->dev, 501 if (report_err)
476 "Config param %04x not supported on group %s\n", 502 dev_err(pmx->dev,
477 param, g->name); 503 "Config param %04x not supported on group %s\n",
504 param, g->name);
478 return -ENOTSUPP; 505 return -ENOTSUPP;
479 } 506 }
480 507
@@ -484,12 +511,14 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
484static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 511static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
485 unsigned pin, unsigned long *config) 512 unsigned pin, unsigned long *config)
486{ 513{
514 dev_err(pctldev->dev, "pin_config_get op not supported\n");
487 return -ENOTSUPP; 515 return -ENOTSUPP;
488} 516}
489 517
490static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 518static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
491 unsigned pin, unsigned long config) 519 unsigned pin, unsigned long config)
492{ 520{
521 dev_err(pctldev->dev, "pin_config_set op not supported\n");
493 return -ENOTSUPP; 522 return -ENOTSUPP;
494} 523}
495 524
@@ -507,7 +536,8 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
507 536
508 g = &pmx->soc->groups[group]; 537 g = &pmx->soc->groups[group];
509 538
510 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 539 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
540 &width);
511 if (ret < 0) 541 if (ret < 0)
512 return ret; 542 return ret;
513 543
@@ -534,7 +564,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
534 564
535 g = &pmx->soc->groups[group]; 565 g = &pmx->soc->groups[group];
536 566
537 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 567 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
568 &width);
538 if (ret < 0) 569 if (ret < 0)
539 return ret; 570 return ret;
540 571
@@ -542,8 +573,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
542 573
543 /* LOCK can't be cleared */ 574 /* LOCK can't be cleared */
544 if (param == TEGRA_PINCONF_PARAM_LOCK) { 575 if (param == TEGRA_PINCONF_PARAM_LOCK) {
545 if ((val & BIT(bit)) && !arg) 576 if ((val & BIT(bit)) && !arg) {
577 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
546 return -EINVAL; 578 return -EINVAL;
579 }
547 } 580 }
548 581
549 /* Special-case Boolean values; allow any non-zero as true */ 582 /* Special-case Boolean values; allow any non-zero as true */
@@ -552,8 +585,12 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
552 585
553 /* Range-check user-supplied value */ 586 /* Range-check user-supplied value */
554 mask = (1 << width) - 1; 587 mask = (1 << width) - 1;
555 if (arg & ~mask) 588 if (arg & ~mask) {
589 dev_err(pctldev->dev,
590 "config %lx: %x too big for %d bit register\n",
591 config, arg, width);
556 return -EINVAL; 592 return -EINVAL;
593 }
557 594
558 /* Update register */ 595 /* Update register */
559 val &= ~(mask << bit); 596 val &= ~(mask << bit);
@@ -563,23 +600,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
563 return 0; 600 return 0;
564} 601}
565 602
603#ifdef CONFIG_DEBUG_FS
566static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 604static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
567 struct seq_file *s, unsigned offset) 605 struct seq_file *s, unsigned offset)
568{ 606{
569} 607}
570 608
609static const char *strip_prefix(const char *s)
610{
611 const char *comma = strchr(s, ',');
612 if (!comma)
613 return s;
614
615 return comma + 1;
616}
617
571static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 618static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
572 struct seq_file *s, unsigned selector) 619 struct seq_file *s, unsigned group)
620{
621 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
622 const struct tegra_pingroup *g;
623 int i, ret;
624 s8 bank, bit, width;
625 s16 reg;
626 u32 val;
627
628 g = &pmx->soc->groups[group];
629
630 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
631 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
632 &bank, &reg, &bit, &width);
633 if (ret < 0)
634 continue;
635
636 val = pmx_readl(pmx, bank, reg);
637 val >>= bit;
638 val &= (1 << width) - 1;
639
640 seq_printf(s, "\n\t%s=%u",
641 strip_prefix(cfg_params[i].property), val);
642 }
643}
644
645static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
646 struct seq_file *s,
647 unsigned long config)
573{ 648{
649 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
650 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
651 const char *pname = "unknown";
652 int i;
653
654 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
655 if (cfg_params[i].param == param) {
656 pname = cfg_params[i].property;
657 break;
658 }
659 }
660
661 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
574} 662}
663#endif
575 664
576struct pinconf_ops tegra_pinconf_ops = { 665struct pinconf_ops tegra_pinconf_ops = {
577 .pin_config_get = tegra_pinconf_get, 666 .pin_config_get = tegra_pinconf_get,
578 .pin_config_set = tegra_pinconf_set, 667 .pin_config_set = tegra_pinconf_set,
579 .pin_config_group_get = tegra_pinconf_group_get, 668 .pin_config_group_get = tegra_pinconf_group_get,
580 .pin_config_group_set = tegra_pinconf_group_set, 669 .pin_config_group_set = tegra_pinconf_group_set,
670#ifdef CONFIG_DEBUG_FS
581 .pin_config_dbg_show = tegra_pinconf_dbg_show, 671 .pin_config_dbg_show = tegra_pinconf_dbg_show,
582 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 672 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
673 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
674#endif
583}; 675};
584 676
585static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { 677static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
@@ -589,60 +681,29 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
589}; 681};
590 682
591static struct pinctrl_desc tegra_pinctrl_desc = { 683static struct pinctrl_desc tegra_pinctrl_desc = {
592 .name = DRIVER_NAME,
593 .pctlops = &tegra_pinctrl_ops, 684 .pctlops = &tegra_pinctrl_ops,
594 .pmxops = &tegra_pinmux_ops, 685 .pmxops = &tegra_pinmux_ops,
595 .confops = &tegra_pinconf_ops, 686 .confops = &tegra_pinconf_ops,
596 .owner = THIS_MODULE, 687 .owner = THIS_MODULE,
597}; 688};
598 689
599static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = { 690int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
600#ifdef CONFIG_PINCTRL_TEGRA20 691 const struct tegra_pinctrl_soc_data *soc_data)
601 {
602 .compatible = "nvidia,tegra20-pinmux-disabled",
603 .data = tegra20_pinctrl_init,
604 },
605#endif
606#ifdef CONFIG_PINCTRL_TEGRA30
607 {
608 .compatible = "nvidia,tegra30-pinmux-disabled",
609 .data = tegra30_pinctrl_init,
610 },
611#endif
612 {},
613};
614
615static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
616{ 692{
617 const struct of_device_id *match;
618 tegra_pinctrl_soc_initf initf = NULL;
619 struct tegra_pmx *pmx; 693 struct tegra_pmx *pmx;
620 struct resource *res; 694 struct resource *res;
621 int i; 695 int i;
622 696
623 match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
624 if (match)
625 initf = (tegra_pinctrl_soc_initf)match->data;
626#ifdef CONFIG_PINCTRL_TEGRA20
627 if (!initf)
628 initf = tegra20_pinctrl_init;
629#endif
630 if (!initf) {
631 dev_err(&pdev->dev,
632 "Could not determine SoC-specific init func\n");
633 return -EINVAL;
634 }
635
636 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 697 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
637 if (!pmx) { 698 if (!pmx) {
638 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); 699 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
639 return -ENOMEM; 700 return -ENOMEM;
640 } 701 }
641 pmx->dev = &pdev->dev; 702 pmx->dev = &pdev->dev;
642 703 pmx->soc = soc_data;
643 (*initf)(&pmx->soc);
644 704
645 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; 705 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
706 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
646 tegra_pinctrl_desc.pins = pmx->soc->pins; 707 tegra_pinctrl_desc.pins = pmx->soc->pins;
647 tegra_pinctrl_desc.npins = pmx->soc->npins; 708 tegra_pinctrl_desc.npins = pmx->soc->npins;
648 709
@@ -697,8 +758,9 @@ static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
697 758
698 return 0; 759 return 0;
699} 760}
761EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
700 762
701static int __devexit tegra_pinctrl_remove(struct platform_device *pdev) 763int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
702{ 764{
703 struct tegra_pmx *pmx = platform_get_drvdata(pdev); 765 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
704 766
@@ -707,30 +769,4 @@ static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
707 769
708 return 0; 770 return 0;
709} 771}
710 772EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
711static struct platform_driver tegra_pinctrl_driver = {
712 .driver = {
713 .name = DRIVER_NAME,
714 .owner = THIS_MODULE,
715 .of_match_table = tegra_pinctrl_of_match,
716 },
717 .probe = tegra_pinctrl_probe,
718 .remove = __devexit_p(tegra_pinctrl_remove),
719};
720
721static int __init tegra_pinctrl_init(void)
722{
723 return platform_driver_register(&tegra_pinctrl_driver);
724}
725arch_initcall(tegra_pinctrl_init);
726
727static void __exit tegra_pinctrl_exit(void)
728{
729 platform_driver_unregister(&tegra_pinctrl_driver);
730}
731module_exit(tegra_pinctrl_exit);
732
733MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
734MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
735MODULE_LICENSE("GPL v2");
736MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 782c795326ef..705c007a38cc 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data {
139 unsigned ngroups; 139 unsigned ngroups;
140}; 140};
141 141
142/** 142int tegra_pinctrl_probe(struct platform_device *pdev,
143 * tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC. 143 const struct tegra_pinctrl_soc_data *soc_data);
144 * @soc_data: This pointer must be updated to point at a struct containing 144int tegra_pinctrl_remove(struct platform_device *pdev);
145 * details of the SoC.
146 */
147typedef void (*tegra_pinctrl_soc_initf)(
148 const struct tegra_pinctrl_soc_data **soc_data);
149
150/**
151 * tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20
152 * @soc_data: This pointer will be updated to point at a struct containing
153 * details of Tegra20's pin controller.
154 */
155void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
156/**
157 * tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20
158 * @soc_data: This pointer will be updated to point at a struct containing
159 * details of Tegra30's pin controller.
160 */
161void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
162 145
163#endif 146#endif
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index f69ff96aa292..a74f9a568536 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pinctrl data for the NVIDIA Tegra20 pinmux 2 * Pinctrl data for the NVIDIA Tegra20 pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Derived from code: 6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc. 7 * Copyright (C) 2010 Google, Inc.
@@ -17,6 +17,8 @@
17 * more details. 17 * more details.
18 */ 18 */
19 19
20#include <linux/module.h>
21#include <linux/of.h>
20#include <linux/platform_device.h> 22#include <linux/platform_device.h>
21#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h> 24#include <linux/pinctrl/pinmux.h>
@@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2854 .ngroups = ARRAY_SIZE(tegra20_groups), 2856 .ngroups = ARRAY_SIZE(tegra20_groups),
2855}; 2857};
2856 2858
2857void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) 2859static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
2858{ 2860{
2859 *soc = &tegra20_pinctrl; 2861 return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2860} 2862}
2863
2864static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
2865 { .compatible = "nvidia,tegra20-pinmux", },
2866 { },
2867};
2868
2869static struct platform_driver tegra20_pinctrl_driver = {
2870 .driver = {
2871 .name = "tegra20-pinctrl",
2872 .owner = THIS_MODULE,
2873 .of_match_table = tegra20_pinctrl_of_match,
2874 },
2875 .probe = tegra20_pinctrl_probe,
2876 .remove = __devexit_p(tegra_pinctrl_remove),
2877};
2878
2879static int __init tegra20_pinctrl_init(void)
2880{
2881 return platform_driver_register(&tegra20_pinctrl_driver);
2882}
2883arch_initcall(tegra20_pinctrl_init);
2884
2885static void __exit tegra20_pinctrl_exit(void)
2886{
2887 platform_driver_unregister(&tegra20_pinctrl_driver);
2888}
2889module_exit(tegra20_pinctrl_exit);
2890
2891MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
2892MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
2893MODULE_LICENSE("GPL v2");
2894MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 4d7571d4a431..0386fdf0da16 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pinctrl data for the NVIDIA Tegra30 pinmux 2 * Pinctrl data for the NVIDIA Tegra30 pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -13,6 +13,8 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#include <linux/module.h>
17#include <linux/of.h>
16#include <linux/platform_device.h> 18#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h> 19#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h> 20#include <linux/pinctrl/pinmux.h>
@@ -3720,7 +3722,39 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
3720 .ngroups = ARRAY_SIZE(tegra30_groups), 3722 .ngroups = ARRAY_SIZE(tegra30_groups),
3721}; 3723};
3722 3724
3723void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) 3725static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev)
3724{ 3726{
3725 *soc = &tegra30_pinctrl; 3727 return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
3726} 3728}
3729
3730static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = {
3731 { .compatible = "nvidia,tegra30-pinmux", },
3732 { },
3733};
3734
3735static struct platform_driver tegra30_pinctrl_driver = {
3736 .driver = {
3737 .name = "tegra30-pinctrl",
3738 .owner = THIS_MODULE,
3739 .of_match_table = tegra30_pinctrl_of_match,
3740 },
3741 .probe = tegra30_pinctrl_probe,
3742 .remove = __devexit_p(tegra_pinctrl_remove),
3743};
3744
3745static int __init tegra30_pinctrl_init(void)
3746{
3747 return platform_driver_register(&tegra30_pinctrl_driver);
3748}
3749arch_initcall(tegra30_pinctrl_init);
3750
3751static void __exit tegra30_pinctrl_exit(void)
3752{
3753 platform_driver_unregister(&tegra30_pinctrl_driver);
3754}
3755module_exit(tegra30_pinctrl_exit);
3756
3757MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
3758MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
3759MODULE_LICENSE("GPL v2");
3760MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 86183366647f..826c2fd8c402 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -581,15 +581,16 @@ static const struct hc_driver tegra_ehci_hc_driver = {
581 .port_handed_over = ehci_port_handed_over, 581 .port_handed_over = ehci_port_handed_over,
582}; 582};
583 583
584static int setup_vbus_gpio(struct platform_device *pdev) 584static int setup_vbus_gpio(struct platform_device *pdev,
585 struct tegra_ehci_platform_data *pdata)
585{ 586{
586 int err = 0; 587 int err = 0;
587 int gpio; 588 int gpio;
588 589
589 if (!pdev->dev.of_node) 590 gpio = pdata->vbus_gpio;
590 return 0; 591 if (!gpio_is_valid(gpio))
591 592 gpio = of_get_named_gpio(pdev->dev.of_node,
592 gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); 593 "nvidia,vbus-gpio", 0);
593 if (!gpio_is_valid(gpio)) 594 if (!gpio_is_valid(gpio))
594 return 0; 595 return 0;
595 596
@@ -633,7 +634,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
633 if (!pdev->dev.dma_mask) 634 if (!pdev->dev.dma_mask)
634 pdev->dev.dma_mask = &tegra_ehci_dma_mask; 635 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
635 636
636 setup_vbus_gpio(pdev); 637 setup_vbus_gpio(pdev, pdata);
637 638
638 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); 639 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
639 if (!tegra) 640 if (!tegra)
diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h
index 6bca5b569acb..66c673fef408 100644
--- a/include/linux/platform_data/tegra_usb.h
+++ b/include/linux/platform_data/tegra_usb.h
@@ -26,6 +26,7 @@ struct tegra_ehci_platform_data {
26 /* power down the phy on bus suspend */ 26 /* power down the phy on bus suspend */
27 int power_down_on_bus_suspend; 27 int power_down_on_bus_suspend;
28 void *phy_config; 28 void *phy_config;
29 int vbus_gpio;
29}; 30};
30 31
31#endif /* _TEGRA_USB_H_ */ 32#endif /* _TEGRA_USB_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 07:03:00 -0500