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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-26 17:40:10 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-26 17:40:10 -0400
commit6c504ecf506705a6575541b28824e13090bd223b (patch)
tree5e69c968c72dbd08c4d00555905daa9205d6d83e
parent2408c2e5294144b7af34636ce0ac894b3195a136 (diff)
parentbf903e4141fce4b35072d5b8fa0ddd299aaf01ea (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "This is just a regular fixes pull apart from the qxl one, it has radeon and intel bits in it, The intel fixes are for a regression with the RC6 fix and a 3.10 hdmi regression, whereas radeon is more DPM fixes, a few lockup fixes and some rn50/r100 DAC fixes" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon/dpm: fix r600_enable_sclk_control() drm/radeon/dpm: implement force performance levels for rv6xx drm/radeon/dpm: fix displaygap programming on rv6xx drm/radeon/dpm: fix a typo in the rv6xx mclk setup drm/i915: initialize gt_lock early with other spin locks drm/i915: fix hdmi portclock limits drm/radeon: fix combios tables on older cards drm/radeon: improve dac adjust heuristics for legacy pdac drm/radeon: Another card with wrong primary dac adj drm/radeon: fix endian issues with DP handling (v3) drm/radeon/vm: only align the pt base to 32k drm/radeon: wait for 3D idle before using CP DMA
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c1
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c19
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c2
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c43
-rw-r--r--drivers/gpu/drm/radeon/r600.c5
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c159
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c8
-rw-r--r--drivers/gpu/drm/radeon/rv6xx_dpm.c41
11 files changed, 158 insertions, 127 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index abf158da9b30..66c63808fa35 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1498,6 +1498,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1498 spin_lock_init(&dev_priv->irq_lock); 1498 spin_lock_init(&dev_priv->irq_lock);
1499 spin_lock_init(&dev_priv->gpu_error.lock); 1499 spin_lock_init(&dev_priv->gpu_error.lock);
1500 spin_lock_init(&dev_priv->rps.lock); 1500 spin_lock_init(&dev_priv->rps.lock);
1501 spin_lock_init(&dev_priv->gt_lock);
1501 spin_lock_init(&dev_priv->backlight.lock); 1502 spin_lock_init(&dev_priv->backlight.lock);
1502 mutex_init(&dev_priv->dpio_lock); 1503 mutex_init(&dev_priv->dpio_lock);
1503 mutex_init(&dev_priv->rps.hw_lock); 1504 mutex_init(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 98df2a0c85bd..2fd3fd5b943e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -785,10 +785,22 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
785 } 785 }
786} 786}
787 787
788static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
789{
790 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
791
792 if (IS_G4X(dev))
793 return 165000;
794 else if (IS_HASWELL(dev))
795 return 300000;
796 else
797 return 225000;
798}
799
788static int intel_hdmi_mode_valid(struct drm_connector *connector, 800static int intel_hdmi_mode_valid(struct drm_connector *connector,
789 struct drm_display_mode *mode) 801 struct drm_display_mode *mode)
790{ 802{
791 if (mode->clock > 165000) 803 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
792 return MODE_CLOCK_HIGH; 804 return MODE_CLOCK_HIGH;
793 if (mode->clock < 20000) 805 if (mode->clock < 20000)
794 return MODE_CLOCK_LOW; 806 return MODE_CLOCK_LOW;
@@ -806,6 +818,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
806 struct drm_device *dev = encoder->base.dev; 818 struct drm_device *dev = encoder->base.dev;
807 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 819 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
808 int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2; 820 int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
821 int portclock_limit = hdmi_portclock_limit(intel_hdmi);
809 int desired_bpp; 822 int desired_bpp;
810 823
811 if (intel_hdmi->color_range_auto) { 824 if (intel_hdmi->color_range_auto) {
@@ -829,7 +842,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
829 * outputs. We also need to check that the higher clock still fits 842 * outputs. We also need to check that the higher clock still fits
830 * within limits. 843 * within limits.
831 */ 844 */
832 if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000 845 if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit
833 && HAS_PCH_SPLIT(dev)) { 846 && HAS_PCH_SPLIT(dev)) {
834 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); 847 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
835 desired_bpp = 12*3; 848 desired_bpp = 12*3;
@@ -846,7 +859,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
846 pipe_config->pipe_bpp = desired_bpp; 859 pipe_config->pipe_bpp = desired_bpp;
847 } 860 }
848 861
849 if (adjusted_mode->clock > 225000) { 862 if (adjusted_mode->clock > portclock_limit) {
850 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); 863 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
851 return false; 864 return false;
852 } 865 }
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6a347f54d39f..51a2a60f5bfc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5497,8 +5497,6 @@ void intel_gt_init(struct drm_device *dev)
5497{ 5497{
5498 struct drm_i915_private *dev_priv = dev->dev_private; 5498 struct drm_i915_private *dev_priv = dev->dev_private;
5499 5499
5500 spin_lock_init(&dev_priv->gt_lock);
5501
5502 if (IS_VALLEYVIEW(dev)) { 5500 if (IS_VALLEYVIEW(dev)) {
5503 dev_priv->gt.force_wake_get = vlv_force_wake_get; 5501 dev_priv->gt.force_wake_get = vlv_force_wake_get;
5504 dev_priv->gt.force_wake_put = vlv_force_wake_put; 5502 dev_priv->gt.force_wake_put = vlv_force_wake_put;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 064023bed480..32501f6ec991 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -44,6 +44,41 @@ static char *pre_emph_names[] = {
44}; 44};
45 45
46/***** radeon AUX functions *****/ 46/***** radeon AUX functions *****/
47
48/* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
51 * dw units.
52 */
53static void radeon_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
54{
55#ifdef __BIG_ENDIAN
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57 u32 *dst32, *src32;
58 int i;
59
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
63 if (to_le) {
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
67 } else {
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
72 if (num_bytes % 4) {
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
75 }
76 }
77#else
78 memcpy(dst, src, num_bytes);
79#endif
80}
81
47union aux_channel_transaction { 82union aux_channel_transaction {
48 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
49 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
@@ -65,10 +100,10 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
65 100
66 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
67 102
68 memcpy(base, send, send_bytes); 103 radeon_copy_swap(base, send, send_bytes, true);
69 104
70 args.v1.lpAuxRequest = 0 + 4; 105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
71 args.v1.lpDataOut = 16 + 4; 106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
72 args.v1.ucDataOutLen = 0; 107 args.v1.ucDataOutLen = 0;
73 args.v1.ucChannelID = chan->rec.i2c_id; 108 args.v1.ucChannelID = chan->rec.i2c_id;
74 args.v1.ucDelay = delay / 10; 109 args.v1.ucDelay = delay / 10;
@@ -102,7 +137,7 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
102 recv_bytes = recv_size; 137 recv_bytes = recv_size;
103 138
104 if (recv && recv_size) 139 if (recv && recv_size)
105 memcpy(recv, base + 16, recv_bytes); 140 radeon_copy_swap(recv, base + 16, recv_bytes, false);
106 141
107 return recv_bytes; 142 return recv_bytes;
108} 143}
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 393880a09412..10f712e37003 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3166,7 +3166,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
3166 3166
3167 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 3167 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3168 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); 3168 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3169 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 21); 3169 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
3170 if (r) { 3170 if (r) {
3171 DRM_ERROR("radeon: moving bo (%d).\n", r); 3171 DRM_ERROR("radeon: moving bo (%d).\n", r);
3172 radeon_semaphore_free(rdev, &sem, NULL); 3172 radeon_semaphore_free(rdev, &sem, NULL);
@@ -3181,6 +3181,9 @@ int r600_copy_cpdma(struct radeon_device *rdev,
3181 radeon_semaphore_free(rdev, &sem, NULL); 3181 radeon_semaphore_free(rdev, &sem, NULL);
3182 } 3182 }
3183 3183
3184 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3185 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3186 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
3184 for (i = 0; i < num_loops; i++) { 3187 for (i = 0; i < num_loops; i++) {
3185 cur_size_in_bytes = size_in_bytes; 3188 cur_size_in_bytes = size_in_bytes;
3186 if (cur_size_in_bytes > 0x1fffff) 3189 if (cur_size_in_bytes > 0x1fffff)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index b88f54b134ab..e5c860f4ccbe 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -278,9 +278,9 @@ bool r600_dynamicpm_enabled(struct radeon_device *rdev)
278void r600_enable_sclk_control(struct radeon_device *rdev, bool enable) 278void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
279{ 279{
280 if (enable) 280 if (enable)
281 WREG32_P(GENERAL_PWRMGT, 0, ~SCLK_PWRMGT_OFF); 281 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
282 else 282 else
283 WREG32_P(GENERAL_PWRMGT, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 283 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
284} 284}
285 285
286void r600_enable_mclk_control(struct radeon_device *rdev, bool enable) 286void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 78bec1a58ed1..f8f8b3113ddd 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1161,6 +1161,7 @@ static struct radeon_asic rv6xx_asic = {
1161 .get_mclk = &rv6xx_dpm_get_mclk, 1161 .get_mclk = &rv6xx_dpm_get_mclk,
1162 .print_power_state = &rv6xx_dpm_print_power_state, 1162 .print_power_state = &rv6xx_dpm_print_power_state,
1163 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, 1163 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1164 .force_performance_level = &rv6xx_dpm_force_performance_level,
1164 }, 1165 },
1165 .pflip = { 1166 .pflip = {
1166 .pre_page_flip = &rs600_pre_page_flip, 1167 .pre_page_flip = &rs600_pre_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index ca1895709908..902479fa737f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -421,6 +421,8 @@ void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
421 struct radeon_ps *ps); 421 struct radeon_ps *ps);
422void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 422void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
423 struct seq_file *m); 423 struct seq_file *m);
424int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
425 enum radeon_dpm_forced_level level);
424/* rs780 dpm */ 426/* rs780 dpm */
425int rs780_dpm_init(struct radeon_device *rdev); 427int rs780_dpm_init(struct radeon_device *rdev);
426int rs780_dpm_enable(struct radeon_device *rdev); 428int rs780_dpm_enable(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 78edadc9e86b..68ce36056019 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -147,7 +147,7 @@ static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table) 147 enum radeon_combios_table_offset table)
148{ 148{
149 struct radeon_device *rdev = dev->dev_private; 149 struct radeon_device *rdev = dev->dev_private;
150 int rev; 150 int rev, size;
151 uint16_t offset = 0, check_offset; 151 uint16_t offset = 0, check_offset;
152 152
153 if (!rdev->bios) 153 if (!rdev->bios)
@@ -156,174 +156,106 @@ static uint16_t combios_get_table_offset(struct drm_device *dev,
156 switch (table) { 156 switch (table) {
157 /* absolute offset tables */ 157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE: 158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc); 159 check_offset = 0xc;
160 if (check_offset)
161 offset = check_offset;
162 break; 160 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE: 161 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14); 162 check_offset = 0x14;
165 if (check_offset)
166 offset = check_offset;
167 break; 163 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE: 164 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a); 165 check_offset = 0x2a;
170 if (check_offset)
171 offset = check_offset;
172 break; 166 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 167 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c); 168 check_offset = 0x2c;
175 if (check_offset)
176 offset = check_offset;
177 break; 169 break;
178 case COMBIOS_CRTC_INFO_TABLE: 170 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e); 171 check_offset = 0x2e;
180 if (check_offset)
181 offset = check_offset;
182 break; 172 break;
183 case COMBIOS_PLL_INFO_TABLE: 173 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30); 174 check_offset = 0x30;
185 if (check_offset)
186 offset = check_offset;
187 break; 175 break;
188 case COMBIOS_TV_INFO_TABLE: 176 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32); 177 check_offset = 0x32;
190 if (check_offset)
191 offset = check_offset;
192 break; 178 break;
193 case COMBIOS_DFP_INFO_TABLE: 179 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34); 180 check_offset = 0x34;
195 if (check_offset)
196 offset = check_offset;
197 break; 181 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE: 182 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36); 183 check_offset = 0x36;
200 if (check_offset)
201 offset = check_offset;
202 break; 184 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE: 185 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38); 186 check_offset = 0x38;
205 if (check_offset)
206 offset = check_offset;
207 break; 187 break;
208 case COMBIOS_TV_STD_PATCH_TABLE: 188 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e); 189 check_offset = 0x3e;
210 if (check_offset)
211 offset = check_offset;
212 break; 190 break;
213 case COMBIOS_LCD_INFO_TABLE: 191 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40); 192 check_offset = 0x40;
215 if (check_offset)
216 offset = check_offset;
217 break; 193 break;
218 case COMBIOS_MOBILE_INFO_TABLE: 194 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42); 195 check_offset = 0x42;
220 if (check_offset)
221 offset = check_offset;
222 break; 196 break;
223 case COMBIOS_PLL_INIT_TABLE: 197 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46); 198 check_offset = 0x46;
225 if (check_offset)
226 offset = check_offset;
227 break; 199 break;
228 case COMBIOS_MEM_CONFIG_TABLE: 200 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48); 201 check_offset = 0x48;
230 if (check_offset)
231 offset = check_offset;
232 break; 202 break;
233 case COMBIOS_SAVE_MASK_TABLE: 203 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a); 204 check_offset = 0x4a;
235 if (check_offset)
236 offset = check_offset;
237 break; 205 break;
238 case COMBIOS_HARDCODED_EDID_TABLE: 206 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c); 207 check_offset = 0x4c;
240 if (check_offset)
241 offset = check_offset;
242 break; 208 break;
243 case COMBIOS_ASIC_INIT_2_TABLE: 209 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e); 210 check_offset = 0x4e;
245 if (check_offset)
246 offset = check_offset;
247 break; 211 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE: 212 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50); 213 check_offset = 0x50;
250 if (check_offset)
251 offset = check_offset;
252 break; 214 break;
253 case COMBIOS_DYN_CLK_1_TABLE: 215 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52); 216 check_offset = 0x52;
255 if (check_offset)
256 offset = check_offset;
257 break; 217 break;
258 case COMBIOS_RESERVED_MEM_TABLE: 218 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54); 219 check_offset = 0x54;
260 if (check_offset)
261 offset = check_offset;
262 break; 220 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE: 221 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58); 222 check_offset = 0x58;
265 if (check_offset)
266 offset = check_offset;
267 break; 223 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE: 224 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a); 225 check_offset = 0x5a;
270 if (check_offset)
271 offset = check_offset;
272 break; 226 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE: 227 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c); 228 check_offset = 0x5c;
275 if (check_offset)
276 offset = check_offset;
277 break; 229 break;
278 case COMBIOS_MISC_INFO_TABLE: 230 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e); 231 check_offset = 0x5e;
280 if (check_offset)
281 offset = check_offset;
282 break; 232 break;
283 case COMBIOS_CRT_INFO_TABLE: 233 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60); 234 check_offset = 0x60;
285 if (check_offset)
286 offset = check_offset;
287 break; 235 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 236 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62); 237 check_offset = 0x62;
290 if (check_offset)
291 offset = check_offset;
292 break; 238 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 239 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64); 240 check_offset = 0x64;
295 if (check_offset)
296 offset = check_offset;
297 break; 241 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE: 242 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66); 243 check_offset = 0x66;
300 if (check_offset)
301 offset = check_offset;
302 break; 244 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE: 245 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68); 246 check_offset = 0x68;
305 if (check_offset)
306 offset = check_offset;
307 break; 247 break;
308 case COMBIOS_OEM_INFO_TABLE: 248 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a); 249 check_offset = 0x6a;
310 if (check_offset)
311 offset = check_offset;
312 break; 250 break;
313 case COMBIOS_DYN_CLK_2_TABLE: 251 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c); 252 check_offset = 0x6c;
315 if (check_offset)
316 offset = check_offset;
317 break; 253 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 254 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e); 255 check_offset = 0x6e;
320 if (check_offset)
321 offset = check_offset;
322 break; 256 break;
323 case COMBIOS_I2C_INFO_TABLE: 257 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70); 258 check_offset = 0x70;
325 if (check_offset)
326 offset = check_offset;
327 break; 259 break;
328 /* relative offset tables */ 260 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 261 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
@@ -439,11 +371,16 @@ static uint16_t combios_get_table_offset(struct drm_device *dev,
439 } 371 }
440 break; 372 break;
441 default: 373 default:
374 check_offset = 0;
442 break; 375 break;
443 } 376 }
444 377
445 return offset; 378 size = RBIOS8(rdev->bios_header_start + 0x6);
379 /* check absolute offset tables */
380 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
381 offset = RBIOS16(rdev->bios_header_start + check_offset);
446 382
383 return offset;
447} 384}
448 385
449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 386bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
@@ -965,16 +902,22 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
965 dac = RBIOS8(dac_info + 0x3) & 0xf; 902 dac = RBIOS8(dac_info + 0x3) & 0xf;
966 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 903 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
967 } 904 }
968 /* if the values are all zeros, use the table */ 905 /* if the values are zeros, use the table */
969 if (p_dac->ps2_pdac_adj) 906 if ((dac == 0) || (bg == 0))
907 found = 0;
908 else
970 found = 1; 909 found = 1;
971 } 910 }
972 911
973 /* quirks */ 912 /* quirks */
913 /* Radeon 7000 (RV100) */
914 if (((dev->pdev->device == 0x5159) &&
915 (dev->pdev->subsystem_vendor == 0x174B) &&
916 (dev->pdev->subsystem_device == 0x7c28)) ||
974 /* Radeon 9100 (R200) */ 917 /* Radeon 9100 (R200) */
975 if ((dev->pdev->device == 0x514D) && 918 ((dev->pdev->device == 0x514D) &&
976 (dev->pdev->subsystem_vendor == 0x174B) && 919 (dev->pdev->subsystem_vendor == 0x174B) &&
977 (dev->pdev->subsystem_device == 0x7149)) { 920 (dev->pdev->subsystem_device == 0x7149))) {
978 /* vbios value is bad, use the default */ 921 /* vbios value is bad, use the default */
979 found = 0; 922 found = 0;
980 } 923 }
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index d9d31a383276..6a51d943ccf4 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -466,7 +466,7 @@ int radeon_vm_manager_init(struct radeon_device *rdev)
466 size += rdev->vm_manager.max_pfn * 8; 466 size += rdev->vm_manager.max_pfn * 8;
467 size *= 2; 467 size *= 2;
468 r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager, 468 r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
469 RADEON_VM_PTB_ALIGN(size), 469 RADEON_GPU_PAGE_ALIGN(size),
470 RADEON_VM_PTB_ALIGN_SIZE, 470 RADEON_VM_PTB_ALIGN_SIZE,
471 RADEON_GEM_DOMAIN_VRAM); 471 RADEON_GEM_DOMAIN_VRAM);
472 if (r) { 472 if (r) {
@@ -621,7 +621,7 @@ int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm)
621 } 621 }
622 622
623retry: 623retry:
624 pd_size = RADEON_VM_PTB_ALIGN(radeon_vm_directory_size(rdev)); 624 pd_size = radeon_vm_directory_size(rdev);
625 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager, 625 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
626 &vm->page_directory, pd_size, 626 &vm->page_directory, pd_size,
627 RADEON_VM_PTB_ALIGN_SIZE, false); 627 RADEON_VM_PTB_ALIGN_SIZE, false);
@@ -953,8 +953,8 @@ static int radeon_vm_update_pdes(struct radeon_device *rdev,
953retry: 953retry:
954 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager, 954 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
955 &vm->page_tables[pt_idx], 955 &vm->page_tables[pt_idx],
956 RADEON_VM_PTB_ALIGN(RADEON_VM_PTE_COUNT * 8), 956 RADEON_VM_PTE_COUNT * 8,
957 RADEON_VM_PTB_ALIGN_SIZE, false); 957 RADEON_GPU_PAGE_SIZE, false);
958 958
959 if (r == -ENOMEM) { 959 if (r == -ENOMEM) {
960 r = radeon_vm_evict(rdev, vm); 960 r = radeon_vm_evict(rdev, vm);
diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c
index 65e33f387341..363018c60412 100644
--- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
+++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
@@ -819,7 +819,7 @@ static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
819 POWERMODE1(calculate_memory_refresh_rate(rdev, 819 POWERMODE1(calculate_memory_refresh_rate(rdev,
820 pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) | 820 pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
821 POWERMODE2(calculate_memory_refresh_rate(rdev, 821 POWERMODE2(calculate_memory_refresh_rate(rdev,
822 pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) | 822 pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
823 POWERMODE3(calculate_memory_refresh_rate(rdev, 823 POWERMODE3(calculate_memory_refresh_rate(rdev,
824 pi->hw.sclks[R600_POWER_LEVEL_HIGH]))); 824 pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
825 WREG32(ARB_RFSH_RATE, arb_refresh_rate); 825 WREG32(ARB_RFSH_RATE, arb_refresh_rate);
@@ -1182,10 +1182,10 @@ static void rv6xx_program_display_gap(struct radeon_device *rdev)
1182 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 1182 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1183 1183
1184 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 1184 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1185 if (RREG32(AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) { 1185 if (rdev->pm.dpm.new_active_crtcs & 1) {
1186 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK); 1186 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1187 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE); 1187 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1188 } else if (RREG32(AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) { 1188 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1189 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE); 1189 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1190 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK); 1190 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1191 } else { 1191 } else {
@@ -1670,6 +1670,8 @@ int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
1670 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; 1670 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1671 int ret; 1671 int ret;
1672 1672
1673 pi->restricted_levels = 0;
1674
1673 rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 1675 rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1674 1676
1675 rv6xx_clear_vc(rdev); 1677 rv6xx_clear_vc(rdev);
@@ -1756,6 +1758,8 @@ int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
1756 1758
1757 rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 1759 rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1758 1760
1761 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1762
1759 return 0; 1763 return 0;
1760} 1764}
1761 1765
@@ -2085,3 +2089,34 @@ u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
2085 else 2089 else
2086 return requested_state->high.mclk; 2090 return requested_state->high.mclk;
2087} 2091}
2092
2093int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
2094 enum radeon_dpm_forced_level level)
2095{
2096 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
2097
2098 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
2099 pi->restricted_levels = 3;
2100 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
2101 pi->restricted_levels = 2;
2102 } else {
2103 pi->restricted_levels = 0;
2104 }
2105
2106 rv6xx_clear_vc(rdev);
2107 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
2108 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
2109 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
2110 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
2111 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
2112 rv6xx_enable_medium(rdev);
2113 rv6xx_enable_high(rdev);
2114 if (pi->restricted_levels == 3)
2115 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
2116 rv6xx_program_vc(rdev);
2117 rv6xx_program_at(rdev);
2118
2119 rdev->pm.dpm.forced_level = level;
2120
2121 return 0;
2122}