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authorLi Peng <peng.li@linux.intel.com>2010-01-27 12:05:09 -0500
committerEric Anholt <eric@anholt.net>2010-01-29 17:22:09 -0500
commit643ced9b0b4810b5725910667604f1a373f30f2f (patch)
treebf5780faae3711bb43ded8f984d377c7f94c462b
parentde3f440f8c9922afe8770dd16c84f1c87d779b59 (diff)
drm/i915: don't trigger ironlake vblank interrupt at irq install
Zhenyu noticed that the ironlake vblank enabling patch has one issue that it will trigger vblank starting from irq postinstall, this isn't necessary. This patch addresses this issue by only adding the vblank into DEIER but mask them in DEIMR, so that it won't trigger vblank interrupt at irq install. Signed-off-by: Li Peng <peng.li@intel.com> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e7472d82132a..fcd87ad75fec 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1022,14 +1022,13 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1022{ 1022{
1023 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1023 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1024 /* enable kind of interrupts always enabled */ 1024 /* enable kind of interrupts always enabled */
1025 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1025 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT;
1026 DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1027 u32 render_mask = GT_USER_INTERRUPT; 1026 u32 render_mask = GT_USER_INTERRUPT;
1028 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | 1027 u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1029 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; 1028 SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1030 1029
1031 dev_priv->irq_mask_reg = ~display_mask; 1030 dev_priv->irq_mask_reg = ~display_mask;
1032 dev_priv->de_irq_enable_reg = display_mask; 1031 dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1033 1032
1034 /* should always can generate irq */ 1033 /* should always can generate irq */
1035 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1034 I915_WRITE(DEIIR, I915_READ(DEIIR));