diff options
author | Grazvydas Ignotas <notasas@gmail.com> | 2012-04-06 17:53:21 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2012-04-17 13:21:58 -0400 |
commit | 63878acfafbc7a6ff90a2f8b3e31f0889bc61af6 (patch) | |
tree | a602a817e6894b2c935378693581dc64dedda083 | |
parent | 907025e3bae0e9e96361dab5b157383cbfbafda0 (diff) |
ARM: OMAP: sram: fix BUG in dpll code for !PM case
_omap3_sram_configure_core_dpll is called when SDRC is reprogrammed,
which is done regardless of CONFIG_PM setting, so we always need it's
setup code too. Without this, we hit a BUG() on OMAP3 when kernel is
built without CONFIG_PM:
Reprogramming SDRC clock to 332000000 Hz
------------[ cut here ]------------
kernel BUG at arch/arm/plat-omap/sram.c:342!
Internal error: Oops - BUG: 0 [#1] ARM
...
[<c001c694>] (omap3_configure_core_dpll+0x68/0x6c) from [<c001b2dc>] (omap3_core_dpll_m2_set_rate+0x1)
[<c001b2dc>] (omap3_core_dpll_m2_set_rate+0x138/0x1b0) from [<c001a478>] (omap2_clk_set_rate+0x14/0x2)
[<c001a478>] (omap2_clk_set_rate+0x14/0x20) from [<c001c9dc>] (clk_set_rate+0x54/0x74)
[<c001c9dc>] (clk_set_rate+0x54/0x74) from [<c022b9c8>] (omap_sdrc_init+0x70/0x90)
[<c022b9c8>] (omap_sdrc_init+0x70/0x90) from [<c022f178>] (omap3pandora_init+0x11c/0x164)
[<c022f178>] (omap3pandora_init+0x11c/0x164) from [<c022849c>] (customize_machine+0x20/0x28)
[<c022849c>] (customize_machine+0x20/0x28) from [<c0225810>] (do_one_initcall+0xa0/0x16c)
[<c0225810>] (do_one_initcall+0xa0/0x16c) from [<c02259e0>] (kernel_init+0x104/0x1ac)
[<c02259e0>] (kernel_init+0x104/0x1ac) from [<c0009cec>] (kernel_thread_exit+0x0/0x8)
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/plat-omap/sram.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index eec98afa0f83..f9a8c5341ee9 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
@@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, | |||
348 | sdrc_actim_ctrl_b_1, sdrc_mr_1); | 348 | sdrc_actim_ctrl_b_1, sdrc_mr_1); |
349 | } | 349 | } |
350 | 350 | ||
351 | #ifdef CONFIG_PM | ||
352 | void omap3_sram_restore_context(void) | 351 | void omap3_sram_restore_context(void) |
353 | { | 352 | { |
354 | omap_sram_ceil = omap_sram_base + omap_sram_size; | 353 | omap_sram_ceil = omap_sram_base + omap_sram_size; |
@@ -358,17 +357,18 @@ void omap3_sram_restore_context(void) | |||
358 | omap3_sram_configure_core_dpll_sz); | 357 | omap3_sram_configure_core_dpll_sz); |
359 | omap_push_sram_idle(); | 358 | omap_push_sram_idle(); |
360 | } | 359 | } |
361 | #endif /* CONFIG_PM */ | ||
362 | |||
363 | #endif /* CONFIG_ARCH_OMAP3 */ | ||
364 | 360 | ||
365 | static inline int omap34xx_sram_init(void) | 361 | static inline int omap34xx_sram_init(void) |
366 | { | 362 | { |
367 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | ||
368 | omap3_sram_restore_context(); | 363 | omap3_sram_restore_context(); |
369 | #endif | ||
370 | return 0; | 364 | return 0; |
371 | } | 365 | } |
366 | #else | ||
367 | static inline int omap34xx_sram_init(void) | ||
368 | { | ||
369 | return 0; | ||
370 | } | ||
371 | #endif /* CONFIG_ARCH_OMAP3 */ | ||
372 | 372 | ||
373 | static inline int am33xx_sram_init(void) | 373 | static inline int am33xx_sram_init(void) |
374 | { | 374 | { |