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authorAkira Takeuchi <takeuchi.akr@jp.panasonic.com>2010-10-27 12:28:47 -0400
committerDavid Howells <dhowells@redhat.com>2010-10-27 12:28:47 -0400
commit633171861a3120af011bb1ee8dd40069951dfeac (patch)
treef2b8fdd8108d4d7f2f3e948e64f882e18b7e2a35
parent8be062892365b09f41d64cda7fa63d306e95e0c9 (diff)
MN10300: Make the boot wrapper able to use writeback caching
Make the boot wrapper able to use writeback caching, including flushing the cache before jumping to the main kernel. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
-rw-r--r--arch/mn10300/boot/compressed/head.S49
1 files changed, 48 insertions, 1 deletions
diff --git a/arch/mn10300/boot/compressed/head.S b/arch/mn10300/boot/compressed/head.S
index 502e1eb56709..4ef608a62416 100644
--- a/arch/mn10300/boot/compressed/head.S
+++ b/arch/mn10300/boot/compressed/head.S
@@ -14,6 +14,7 @@
14 14
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <asm/cpu-regs.h> 16#include <asm/cpu-regs.h>
17#include <asm/cache.h>
17 18
18 .globl startup_32 19 .globl startup_32
19startup_32: 20startup_32:
@@ -37,8 +38,15 @@ startup_32:
37 mov (a0),d0 38 mov (a0),d0
38 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy 39 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
39 lne 40 lne
40 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD,d0 # writethru dcache 41
42#ifdef CONFIG_MN10300_CACHE_ENABLED
43#ifdef CONFIG_MN10300_CACHE_WBACK
44 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
45#else
46 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
47#endif /* WBACK */
41 movhu d0,(a0) # enable 48 movhu d0,(a0) # enable
49#endif /* !ENABLED */
42 50
43 # clear the BSS area 51 # clear the BSS area
44 mov __bss_start,a0 52 mov __bss_start,a0
@@ -54,6 +62,9 @@ bssclear_end:
54 62
55 # decompress the kernel 63 # decompress the kernel
56 call decompress_kernel[],0 64 call decompress_kernel[],0
65#ifdef CONFIG_MN10300_CACHE_WBACK
66 call mn10300_dcache_flush_inv[],0
67#endif
57 68
58 # disable caches again 69 # disable caches again
59 mov CHCTR,a0 70 mov CHCTR,a0
@@ -69,10 +80,46 @@ bssclear_end:
69 mov (4,a0),d1 80 mov (4,a0),d1
70 mov (8,a0),d2 81 mov (8,a0),d2
71 82
83 # jump to the kernel proper entry point
72 mov a3,sp 84 mov a3,sp
73 mov CONFIG_KERNEL_TEXT_ADDRESS,a0 85 mov CONFIG_KERNEL_TEXT_ADDRESS,a0
74 jmp (a0) 86 jmp (a0)
75 87
88
89###############################################################################
90#
91# Cache flush routines
92#
93###############################################################################
94#ifdef CONFIG_MN10300_CACHE_WBACK
95mn10300_dcache_flush_inv:
96 movhu (CHCTR),d0
97 btst CHCTR_DCEN,d0
98 beq mn10300_dcache_flush_inv_end
99
100 mov L1_CACHE_NENTRIES,d1
101 clr a1
102
103mn10300_dcache_flush_inv_loop:
104 mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge
105 mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge
106 mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge
107 mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
108
109 add L1_CACHE_BYTES,a1
110 add -1,d1
111 bne mn10300_dcache_flush_inv_loop
112
113mn10300_dcache_flush_inv_end:
114 ret [],0
115#endif /* CONFIG_MN10300_CACHE_WBACK */
116
117
118###############################################################################
119#
120# Data areas
121#
122###############################################################################
76 .data 123 .data
77 .align 4 124 .align 4
78param_save_area: 125param_save_area: