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authorBen Skeggs <bskeggs@redhat.com>2010-09-26 19:47:56 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-10-04 19:57:41 -0400
commit5c6dc6575460a0afe56d8cae7666e769e08ef942 (patch)
treeec0ccbac221f82212b99247249ee9cbb78f88100
parentfe224bb7e12f1ea9a785ec942bc5d59950543888 (diff)
drm/nouveau: pass perflvl struct to clock_pre()
On certain boards, there's BIOS scripts and memory timings that need to be modified with the memclk. Just pass in the entire perflvl struct and let the chipset-specific code decide what to do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.c13
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.h6
-rw-r--r--drivers/gpu/drm/nouveau/nv04_pm.c3
-rw-r--r--drivers/gpu/drm/nouveau/nv50_pm.c3
5 files changed, 17 insertions, 11 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index e1fb2c95eb90..01ee63a70cc9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -432,7 +432,8 @@ struct nouveau_pm_engine {
432 struct device *hwmon; 432 struct device *hwmon;
433 433
434 int (*clock_get)(struct drm_device *, u32 id); 434 int (*clock_get)(struct drm_device *, u32 id);
435 void *(*clock_pre)(struct drm_device *, u32 id, int khz); 435 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
436 u32 id, int khz);
436 void (*clock_set)(struct drm_device *, void *); 437 void (*clock_set)(struct drm_device *, void *);
437 int (*voltage_get)(struct drm_device *); 438 int (*voltage_get)(struct drm_device *);
438 int (*voltage_set)(struct drm_device *, int voltage); 439 int (*voltage_set)(struct drm_device *, int voltage);
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c
index 01437f1753a7..1c99c55d6d46 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -31,7 +31,8 @@
31#include <linux/hwmon-sysfs.h> 31#include <linux/hwmon-sysfs.h>
32 32
33static int 33static int
34nouveau_pm_clock_set(struct drm_device *dev, u8 id, u32 khz) 34nouveau_pm_clock_set(struct drm_device *dev, struct nouveau_pm_level *perflvl,
35 u8 id, u32 khz)
35{ 36{
36 struct drm_nouveau_private *dev_priv = dev->dev_private; 37 struct drm_nouveau_private *dev_priv = dev->dev_private;
37 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 38 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
@@ -40,7 +41,7 @@ nouveau_pm_clock_set(struct drm_device *dev, u8 id, u32 khz)
40 if (khz == 0) 41 if (khz == 0)
41 return 0; 42 return 0;
42 43
43 pre_state = pm->clock_pre(dev, id, khz); 44 pre_state = pm->clock_pre(dev, perflvl, id, khz);
44 if (IS_ERR(pre_state)) 45 if (IS_ERR(pre_state))
45 return PTR_ERR(pre_state); 46 return PTR_ERR(pre_state);
46 47
@@ -67,10 +68,10 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
67 } 68 }
68 } 69 }
69 70
70 nouveau_pm_clock_set(dev, PLL_CORE, perflvl->core); 71 nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core);
71 nouveau_pm_clock_set(dev, PLL_SHADER, perflvl->shader); 72 nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader);
72 nouveau_pm_clock_set(dev, PLL_MEMORY, perflvl->memory); 73 nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory);
73 nouveau_pm_clock_set(dev, PLL_UNK05, perflvl->unk05); 74 nouveau_pm_clock_set(dev, perflvl, PLL_UNK05, perflvl->unk05);
74 75
75 pm->cur = perflvl; 76 pm->cur = perflvl;
76 return 0; 77 return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h
index 7504e3b8c023..babe64ac33c0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.h
@@ -48,12 +48,14 @@ void nouveau_mem_timing_fini(struct drm_device *);
48 48
49/* nv04_pm.c */ 49/* nv04_pm.c */
50int nv04_pm_clock_get(struct drm_device *, u32 id); 50int nv04_pm_clock_get(struct drm_device *, u32 id);
51void *nv04_pm_clock_pre(struct drm_device *, u32 id, int khz); 51void *nv04_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *,
52 u32 id, int khz);
52void nv04_pm_clock_set(struct drm_device *, void *); 53void nv04_pm_clock_set(struct drm_device *, void *);
53 54
54/* nv50_pm.c */ 55/* nv50_pm.c */
55int nv50_pm_clock_get(struct drm_device *, u32 id); 56int nv50_pm_clock_get(struct drm_device *, u32 id);
56void *nv50_pm_clock_pre(struct drm_device *, u32 id, int khz); 57void *nv50_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *,
58 u32 id, int khz);
57void nv50_pm_clock_set(struct drm_device *, void *); 59void nv50_pm_clock_set(struct drm_device *, void *);
58 60
59/* nouveau_temp.c */ 61/* nouveau_temp.c */
diff --git a/drivers/gpu/drm/nouveau/nv04_pm.c b/drivers/gpu/drm/nouveau/nv04_pm.c
index 61ca92744f93..6a6eb697d38e 100644
--- a/drivers/gpu/drm/nouveau/nv04_pm.c
+++ b/drivers/gpu/drm/nouveau/nv04_pm.c
@@ -39,7 +39,8 @@ nv04_pm_clock_get(struct drm_device *dev, u32 id)
39} 39}
40 40
41void * 41void *
42nv04_pm_clock_pre(struct drm_device *dev, u32 id, int khz) 42nv04_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
43 u32 id, int khz)
43{ 44{
44 struct nv04_pm_state *state; 45 struct nv04_pm_state *state;
45 int ret; 46 int ret;
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
index 64bc29c39c3a..eaf69c83ce92 100644
--- a/drivers/gpu/drm/nouveau/nv50_pm.c
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -67,7 +67,8 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id)
67} 67}
68 68
69void * 69void *
70nv50_pm_clock_pre(struct drm_device *dev, u32 id, int khz) 70nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
71 u32 id, int khz)
71{ 72{
72 struct nv50_pm_state *state; 73 struct nv50_pm_state *state;
73 int dummy, ret; 74 int dummy, ret;