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authorJing Huang <huangj@brocade.com>2010-10-18 20:12:29 -0400
committerJames Bottomley <James.Bottomley@suse.de>2010-10-25 17:18:20 -0400
commit5344026065f79b102fcc44bc6332f856a111962a (patch)
treec28f91eb4593e3e89b030a65a4fd71b8b43cc1f1
parentba816ea8e2eacbf3d198ad1859f413c2d6213434 (diff)
[SCSI] bfa: remove os wrapper functions and macros
This patch replaces register access functions and macros with the the ones provided by linux. Signed-off-by: Jing Huang <huangj@brocade.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat
-rw-r--r--drivers/scsi/bfa/bfa.h24
-rw-r--r--drivers/scsi/bfa/bfa_core.c32
-rw-r--r--drivers/scsi/bfa/bfa_hw_cb.c10
-rw-r--r--drivers/scsi/bfa/bfa_hw_ct.c16
-rw-r--r--drivers/scsi/bfa/bfa_ioc.c117
-rw-r--r--drivers/scsi/bfa/bfa_ioc.h66
-rw-r--r--drivers/scsi/bfa/bfa_ioc_cb.c64
-rw-r--r--drivers/scsi/bfa/bfa_ioc_ct.c119
-rw-r--r--drivers/scsi/bfa/bfa_os_inc.h32
-rw-r--r--drivers/scsi/bfa/bfad_debugfs.c4
10 files changed, 226 insertions, 258 deletions
diff --git a/drivers/scsi/bfa/bfa.h b/drivers/scsi/bfa/bfa.h
index ceaac65a91ff..c3981df31722 100644
--- a/drivers/scsi/bfa/bfa.h
+++ b/drivers/scsi/bfa/bfa.h
@@ -59,8 +59,8 @@ void bfa_isr_bind(enum bfi_mclass mc, bfa_isr_func_t isr_func);
59 (__bfa)->iocfc.req_cq_pi[__reqq]++; \ 59 (__bfa)->iocfc.req_cq_pi[__reqq]++; \
60 (__bfa)->iocfc.req_cq_pi[__reqq] &= \ 60 (__bfa)->iocfc.req_cq_pi[__reqq] &= \
61 ((__bfa)->iocfc.cfg.drvcfg.num_reqq_elems - 1); \ 61 ((__bfa)->iocfc.cfg.drvcfg.num_reqq_elems - 1); \
62 bfa_reg_write((__bfa)->iocfc.bfa_regs.cpe_q_pi[__reqq], \ 62 writel((__bfa)->iocfc.req_cq_pi[__reqq], \
63 (__bfa)->iocfc.req_cq_pi[__reqq]); \ 63 (__bfa)->iocfc.bfa_regs.cpe_q_pi[__reqq]); \
64 mmiowb(); \ 64 mmiowb(); \
65 } while (0) 65 } while (0)
66 66
@@ -202,16 +202,16 @@ struct bfa_meminfo_s {
202 ((_m)->meminfo[BFA_MEM_TYPE_DMA - 1].dma_curp) 202 ((_m)->meminfo[BFA_MEM_TYPE_DMA - 1].dma_curp)
203 203
204struct bfa_iocfc_regs_s { 204struct bfa_iocfc_regs_s {
205 bfa_os_addr_t intr_status; 205 void __iomem *intr_status;
206 bfa_os_addr_t intr_mask; 206 void __iomem *intr_mask;
207 bfa_os_addr_t cpe_q_pi[BFI_IOC_MAX_CQS]; 207 void __iomem *cpe_q_pi[BFI_IOC_MAX_CQS];
208 bfa_os_addr_t cpe_q_ci[BFI_IOC_MAX_CQS]; 208 void __iomem *cpe_q_ci[BFI_IOC_MAX_CQS];
209 bfa_os_addr_t cpe_q_depth[BFI_IOC_MAX_CQS]; 209 void __iomem *cpe_q_depth[BFI_IOC_MAX_CQS];
210 bfa_os_addr_t cpe_q_ctrl[BFI_IOC_MAX_CQS]; 210 void __iomem *cpe_q_ctrl[BFI_IOC_MAX_CQS];
211 bfa_os_addr_t rme_q_ci[BFI_IOC_MAX_CQS]; 211 void __iomem *rme_q_ci[BFI_IOC_MAX_CQS];
212 bfa_os_addr_t rme_q_pi[BFI_IOC_MAX_CQS]; 212 void __iomem *rme_q_pi[BFI_IOC_MAX_CQS];
213 bfa_os_addr_t rme_q_depth[BFI_IOC_MAX_CQS]; 213 void __iomem *rme_q_depth[BFI_IOC_MAX_CQS];
214 bfa_os_addr_t rme_q_ctrl[BFI_IOC_MAX_CQS]; 214 void __iomem *rme_q_ctrl[BFI_IOC_MAX_CQS];
215}; 215};
216 216
217/** 217/**
diff --git a/drivers/scsi/bfa/bfa_core.c b/drivers/scsi/bfa/bfa_core.c
index 73669245c2cf..f75c6be7b843 100644
--- a/drivers/scsi/bfa/bfa_core.c
+++ b/drivers/scsi/bfa/bfa_core.c
@@ -113,7 +113,7 @@ bfa_intx(struct bfa_s *bfa)
113 u32 intr, qintr; 113 u32 intr, qintr;
114 int queue; 114 int queue;
115 115
116 intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status); 116 intr = readl(bfa->iocfc.bfa_regs.intr_status);
117 if (!intr) 117 if (!intr)
118 return BFA_FALSE; 118 return BFA_FALSE;
119 119
@@ -121,7 +121,7 @@ bfa_intx(struct bfa_s *bfa)
121 * RME completion queue interrupt 121 * RME completion queue interrupt
122 */ 122 */
123 qintr = intr & __HFN_INT_RME_MASK; 123 qintr = intr & __HFN_INT_RME_MASK;
124 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr); 124 writel(qintr, bfa->iocfc.bfa_regs.intr_status);
125 125
126 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) { 126 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
127 if (intr & (__HFN_INT_RME_Q0 << queue)) 127 if (intr & (__HFN_INT_RME_Q0 << queue))
@@ -135,7 +135,7 @@ bfa_intx(struct bfa_s *bfa)
135 * CPE completion queue interrupt 135 * CPE completion queue interrupt
136 */ 136 */
137 qintr = intr & __HFN_INT_CPE_MASK; 137 qintr = intr & __HFN_INT_CPE_MASK;
138 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr); 138 writel(qintr, bfa->iocfc.bfa_regs.intr_status);
139 139
140 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) { 140 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
141 if (intr & (__HFN_INT_CPE_Q0 << queue)) 141 if (intr & (__HFN_INT_CPE_Q0 << queue))
@@ -153,13 +153,13 @@ bfa_intx(struct bfa_s *bfa)
153void 153void
154bfa_intx_enable(struct bfa_s *bfa) 154bfa_intx_enable(struct bfa_s *bfa)
155{ 155{
156 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, bfa->iocfc.intr_mask); 156 writel(bfa->iocfc.intr_mask, bfa->iocfc.bfa_regs.intr_mask);
157} 157}
158 158
159void 159void
160bfa_intx_disable(struct bfa_s *bfa) 160bfa_intx_disable(struct bfa_s *bfa)
161{ 161{
162 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, -1L); 162 writel(-1L, bfa->iocfc.bfa_regs.intr_mask);
163} 163}
164 164
165void 165void
@@ -188,8 +188,8 @@ bfa_isr_enable(struct bfa_s *bfa)
188 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | 188 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
189 __HFN_INT_MBOX_LPU1); 189 __HFN_INT_MBOX_LPU1);
190 190
191 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr_unmask); 191 writel(intr_unmask, bfa->iocfc.bfa_regs.intr_status);
192 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, ~intr_unmask); 192 writel(~intr_unmask, bfa->iocfc.bfa_regs.intr_mask);
193 bfa->iocfc.intr_mask = ~intr_unmask; 193 bfa->iocfc.intr_mask = ~intr_unmask;
194 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0); 194 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0);
195} 195}
@@ -198,7 +198,7 @@ void
198bfa_isr_disable(struct bfa_s *bfa) 198bfa_isr_disable(struct bfa_s *bfa)
199{ 199{
200 bfa_isr_mode_set(bfa, BFA_FALSE); 200 bfa_isr_mode_set(bfa, BFA_FALSE);
201 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, -1L); 201 writel(-1L, bfa->iocfc.bfa_regs.intr_mask);
202 bfa_msix_uninstall(bfa); 202 bfa_msix_uninstall(bfa);
203} 203}
204 204
@@ -263,7 +263,7 @@ bfa_msix_rspq(struct bfa_s *bfa, int qid)
263 * update CI 263 * update CI
264 */ 264 */
265 bfa_rspq_ci(bfa, qid) = pi; 265 bfa_rspq_ci(bfa, qid) = pi;
266 bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ci[qid], pi); 266 writel(pi, bfa->iocfc.bfa_regs.rme_q_ci[qid]);
267 mmiowb(); 267 mmiowb();
268 268
269 /** 269 /**
@@ -279,7 +279,7 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
279{ 279{
280 u32 intr, curr_value; 280 u32 intr, curr_value;
281 281
282 intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status); 282 intr = readl(bfa->iocfc.bfa_regs.intr_status);
283 283
284 if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1)) 284 if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1))
285 bfa_msix_lpu(bfa); 285 bfa_msix_lpu(bfa);
@@ -294,9 +294,9 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
294 * Register needs to be cleared as well so Interrupt 294 * Register needs to be cleared as well so Interrupt
295 * Status Register will be cleared. 295 * Status Register will be cleared.
296 */ 296 */
297 curr_value = bfa_reg_read(bfa->ioc.ioc_regs.ll_halt); 297 curr_value = readl(bfa->ioc.ioc_regs.ll_halt);
298 curr_value &= ~__FW_INIT_HALT_P; 298 curr_value &= ~__FW_INIT_HALT_P;
299 bfa_reg_write(bfa->ioc.ioc_regs.ll_halt, curr_value); 299 writel(curr_value, bfa->ioc.ioc_regs.ll_halt);
300 } 300 }
301 301
302 if (intr & __HFN_INT_ERR_PSS) { 302 if (intr & __HFN_INT_ERR_PSS) {
@@ -305,14 +305,14 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
305 * interrups are shared so driver's interrupt handler is 305 * interrups are shared so driver's interrupt handler is
306 * still called eventhough it is already masked out. 306 * still called eventhough it is already masked out.
307 */ 307 */
308 curr_value = bfa_reg_read( 308 curr_value = readl(
309 bfa->ioc.ioc_regs.pss_err_status_reg); 309 bfa->ioc.ioc_regs.pss_err_status_reg);
310 curr_value &= __PSS_ERR_STATUS_SET; 310 curr_value &= __PSS_ERR_STATUS_SET;
311 bfa_reg_write(bfa->ioc.ioc_regs.pss_err_status_reg, 311 writel(curr_value,
312 curr_value); 312 bfa->ioc.ioc_regs.pss_err_status_reg);
313 } 313 }
314 314
315 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr); 315 writel(intr, bfa->iocfc.bfa_regs.intr_status);
316 bfa_msix_errint(bfa, intr); 316 bfa_msix_errint(bfa, intr);
317 } 317 }
318} 318}
diff --git a/drivers/scsi/bfa/bfa_hw_cb.c b/drivers/scsi/bfa/bfa_hw_cb.c
index c787d3af0886..422e44cfa074 100644
--- a/drivers/scsi/bfa/bfa_hw_cb.c
+++ b/drivers/scsi/bfa/bfa_hw_cb.c
@@ -22,7 +22,7 @@ void
22bfa_hwcb_reginit(struct bfa_s *bfa) 22bfa_hwcb_reginit(struct bfa_s *bfa)
23{ 23{
24 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 24 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
25 bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc); 25 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
26 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); 26 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc);
27 27
28 if (fn == 0) { 28 if (fn == 0) {
@@ -60,8 +60,8 @@ bfa_hwcb_reqq_ack(struct bfa_s *bfa, int reqq)
60static void 60static void
61bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq) 61bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq)
62{ 62{
63 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, 63 writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq),
64 __HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq)); 64 bfa->iocfc.bfa_regs.intr_status);
65} 65}
66 66
67void 67void
@@ -72,8 +72,8 @@ bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq)
72static void 72static void
73bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq) 73bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq)
74{ 74{
75 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, 75 writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq),
76 __HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq)); 76 bfa->iocfc.bfa_regs.intr_status);
77} 77}
78 78
79void 79void
diff --git a/drivers/scsi/bfa/bfa_hw_ct.c b/drivers/scsi/bfa/bfa_hw_ct.c
index c97ebafec5ea..81e670e9c6a6 100644
--- a/drivers/scsi/bfa/bfa_hw_ct.c
+++ b/drivers/scsi/bfa/bfa_hw_ct.c
@@ -31,12 +31,12 @@ static void
31bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec) 31bfa_hwct_msix_lpu_err_set(struct bfa_s *bfa, bfa_boolean_t msix, int vec)
32{ 32{
33 int fn = bfa_ioc_pcifn(&bfa->ioc); 33 int fn = bfa_ioc_pcifn(&bfa->ioc);
34 bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc); 34 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
35 35
36 if (msix) 36 if (msix)
37 bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], vec); 37 writel(vec, kva + __ct_msix_err_vec_reg[fn]);
38 else 38 else
39 bfa_reg_write(kva + __ct_msix_err_vec_reg[fn], 0); 39 writel(0, kva + __ct_msix_err_vec_reg[fn]);
40} 40}
41 41
42/** 42/**
@@ -51,7 +51,7 @@ void
51bfa_hwct_reginit(struct bfa_s *bfa) 51bfa_hwct_reginit(struct bfa_s *bfa)
52{ 52{
53 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 53 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
54 bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc); 54 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
55 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc); 55 int i, q, fn = bfa_ioc_pcifn(&bfa->ioc);
56 56
57 if (fn == 0) { 57 if (fn == 0) {
@@ -88,8 +88,8 @@ bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
88{ 88{
89 u32 r32; 89 u32 r32;
90 90
91 r32 = bfa_reg_read(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]); 91 r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
92 bfa_reg_write(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq], r32); 92 writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
93} 93}
94 94
95void 95void
@@ -97,8 +97,8 @@ bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq)
97{ 97{
98 u32 r32; 98 u32 r32;
99 99
100 r32 = bfa_reg_read(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); 100 r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
101 bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq], r32); 101 writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
102} 102}
103 103
104void 104void
diff --git a/drivers/scsi/bfa/bfa_ioc.c b/drivers/scsi/bfa/bfa_ioc.c
index 8d3bf404229d..fddab8857e8c 100644
--- a/drivers/scsi/bfa/bfa_ioc.c
+++ b/drivers/scsi/bfa/bfa_ioc.c
@@ -73,7 +73,7 @@ BFA_TRC_FILE(CNA, IOC);
73 73
74#define bfa_ioc_mbox_cmd_pending(__ioc) \ 74#define bfa_ioc_mbox_cmd_pending(__ioc) \
75 (!list_empty(&((__ioc)->mbox_mod.cmd_q)) || \ 75 (!list_empty(&((__ioc)->mbox_mod.cmd_q)) || \
76 bfa_reg_read((__ioc)->ioc_regs.hfn_mbox_cmd)) 76 readl((__ioc)->ioc_regs.hfn_mbox_cmd))
77 77
78bfa_boolean_t bfa_auto_recover = BFA_TRUE; 78bfa_boolean_t bfa_auto_recover = BFA_TRUE;
79 79
@@ -866,8 +866,7 @@ bfa_iocpf_sm_enabling(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
866 case IOCPF_E_TIMEOUT: 866 case IOCPF_E_TIMEOUT:
867 iocpf->retry_count++; 867 iocpf->retry_count++;
868 if (iocpf->retry_count < BFA_IOC_HWINIT_MAX) { 868 if (iocpf->retry_count < BFA_IOC_HWINIT_MAX) {
869 bfa_reg_write(ioc->ioc_regs.ioc_fwstate, 869 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
870 BFI_IOC_UNINIT);
871 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit); 870 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
872 break; 871 break;
873 } 872 }
@@ -968,7 +967,7 @@ bfa_iocpf_sm_disabling(struct bfa_iocpf_s *iocpf, enum iocpf_event event)
968 */ 967 */
969 968
970 case IOCPF_E_TIMEOUT: 969 case IOCPF_E_TIMEOUT:
971 bfa_reg_write(ioc->ioc_regs.ioc_fwstate, BFI_IOC_FAIL); 970 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
972 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled); 971 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
973 break; 972 break;
974 973
@@ -1057,7 +1056,7 @@ bfa_iocpf_sm_fail_entry(struct bfa_iocpf_s *iocpf)
1057 * Mark IOC as failed in hardware and stop firmware. 1056 * Mark IOC as failed in hardware and stop firmware.
1058 */ 1057 */
1059 bfa_ioc_lpu_stop(iocpf->ioc); 1058 bfa_ioc_lpu_stop(iocpf->ioc);
1060 bfa_reg_write(iocpf->ioc->ioc_regs.ioc_fwstate, BFI_IOC_FAIL); 1059 writel(BFI_IOC_FAIL, iocpf->ioc->ioc_regs.ioc_fwstate);
1061 1060
1062 /** 1061 /**
1063 * Notify other functions on HB failure. 1062 * Notify other functions on HB failure.
@@ -1123,18 +1122,18 @@ bfa_ioc_disable_comp(struct bfa_ioc_s *ioc)
1123} 1122}
1124 1123
1125bfa_boolean_t 1124bfa_boolean_t
1126bfa_ioc_sem_get(bfa_os_addr_t sem_reg) 1125bfa_ioc_sem_get(void __iomem *sem_reg)
1127{ 1126{
1128 u32 r32; 1127 u32 r32;
1129 int cnt = 0; 1128 int cnt = 0;
1130#define BFA_SEM_SPINCNT 3000 1129#define BFA_SEM_SPINCNT 3000
1131 1130
1132 r32 = bfa_reg_read(sem_reg); 1131 r32 = readl(sem_reg);
1133 1132
1134 while (r32 && (cnt < BFA_SEM_SPINCNT)) { 1133 while (r32 && (cnt < BFA_SEM_SPINCNT)) {
1135 cnt++; 1134 cnt++;
1136 udelay(2); 1135 udelay(2);
1137 r32 = bfa_reg_read(sem_reg); 1136 r32 = readl(sem_reg);
1138 } 1137 }
1139 1138
1140 if (r32 == 0) 1139 if (r32 == 0)
@@ -1145,9 +1144,9 @@ bfa_ioc_sem_get(bfa_os_addr_t sem_reg)
1145} 1144}
1146 1145
1147void 1146void
1148bfa_ioc_sem_release(bfa_os_addr_t sem_reg) 1147bfa_ioc_sem_release(void __iomem *sem_reg)
1149{ 1148{
1150 bfa_reg_write(sem_reg, 1); 1149 writel(1, sem_reg);
1151} 1150}
1152 1151
1153static void 1152static void
@@ -1159,7 +1158,7 @@ bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc)
1159 * First read to the semaphore register will return 0, subsequent reads 1158 * First read to the semaphore register will return 0, subsequent reads
1160 * will return 1. Semaphore is released by writing 1 to the register 1159 * will return 1. Semaphore is released by writing 1 to the register
1161 */ 1160 */
1162 r32 = bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); 1161 r32 = readl(ioc->ioc_regs.ioc_sem_reg);
1163 if (r32 == 0) { 1162 if (r32 == 0) {
1164 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED); 1163 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED);
1165 return; 1164 return;
@@ -1171,7 +1170,7 @@ bfa_ioc_hw_sem_get(struct bfa_ioc_s *ioc)
1171void 1170void
1172bfa_ioc_hw_sem_release(struct bfa_ioc_s *ioc) 1171bfa_ioc_hw_sem_release(struct bfa_ioc_s *ioc)
1173{ 1172{
1174 bfa_reg_write(ioc->ioc_regs.ioc_sem_reg, 1); 1173 writel(1, ioc->ioc_regs.ioc_sem_reg);
1175} 1174}
1176 1175
1177static void 1176static void
@@ -1190,7 +1189,7 @@ bfa_ioc_lmem_init(struct bfa_ioc_s *ioc)
1190 int i; 1189 int i;
1191#define PSS_LMEM_INIT_TIME 10000 1190#define PSS_LMEM_INIT_TIME 10000
1192 1191
1193 pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg); 1192 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1194 pss_ctl &= ~__PSS_LMEM_RESET; 1193 pss_ctl &= ~__PSS_LMEM_RESET;
1195 pss_ctl |= __PSS_LMEM_INIT_EN; 1194 pss_ctl |= __PSS_LMEM_INIT_EN;
1196 1195
@@ -1198,14 +1197,14 @@ bfa_ioc_lmem_init(struct bfa_ioc_s *ioc)
1198 * i2c workaround 12.5khz clock 1197 * i2c workaround 12.5khz clock
1199 */ 1198 */
1200 pss_ctl |= __PSS_I2C_CLK_DIV(3UL); 1199 pss_ctl |= __PSS_I2C_CLK_DIV(3UL);
1201 bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl); 1200 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1202 1201
1203 /** 1202 /**
1204 * wait for memory initialization to be complete 1203 * wait for memory initialization to be complete
1205 */ 1204 */
1206 i = 0; 1205 i = 0;
1207 do { 1206 do {
1208 pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg); 1207 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1209 i++; 1208 i++;
1210 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME)); 1209 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME));
1211 1210
@@ -1217,7 +1216,7 @@ bfa_ioc_lmem_init(struct bfa_ioc_s *ioc)
1217 bfa_trc(ioc, pss_ctl); 1216 bfa_trc(ioc, pss_ctl);
1218 1217
1219 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN); 1218 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN);
1220 bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl); 1219 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1221} 1220}
1222 1221
1223static void 1222static void
@@ -1228,10 +1227,10 @@ bfa_ioc_lpu_start(struct bfa_ioc_s *ioc)
1228 /** 1227 /**
1229 * Take processor out of reset. 1228 * Take processor out of reset.
1230 */ 1229 */
1231 pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg); 1230 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1232 pss_ctl &= ~__PSS_LPU0_RESET; 1231 pss_ctl &= ~__PSS_LPU0_RESET;
1233 1232
1234 bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl); 1233 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1235} 1234}
1236 1235
1237static void 1236static void
@@ -1242,10 +1241,10 @@ bfa_ioc_lpu_stop(struct bfa_ioc_s *ioc)
1242 /** 1241 /**
1243 * Put processors in reset. 1242 * Put processors in reset.
1244 */ 1243 */
1245 pss_ctl = bfa_reg_read(ioc->ioc_regs.pss_ctl_reg); 1244 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
1246 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET); 1245 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
1247 1246
1248 bfa_reg_write(ioc->ioc_regs.pss_ctl_reg, pss_ctl); 1247 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
1249} 1248}
1250 1249
1251/** 1250/**
@@ -1261,7 +1260,7 @@ bfa_ioc_fwver_get(struct bfa_ioc_s *ioc, struct bfi_ioc_image_hdr_s *fwhdr)
1261 1260
1262 pgnum = bfa_ioc_smem_pgnum(ioc, loff); 1261 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
1263 pgoff = bfa_ioc_smem_pgoff(ioc, loff); 1262 pgoff = bfa_ioc_smem_pgoff(ioc, loff);
1264 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum); 1263 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1265 1264
1266 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr_s) / sizeof(u32)); 1265 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr_s) / sizeof(u32));
1267 i++) { 1266 i++) {
@@ -1321,7 +1320,7 @@ bfa_ioc_fwver_valid(struct bfa_ioc_s *ioc, u32 boot_env)
1321 return BFA_FALSE; 1320 return BFA_FALSE;
1322 } 1321 }
1323 1322
1324 if (bfa_os_swap32(fwhdr.param) != boot_env) { 1323 if (swab32(fwhdr.param) != boot_env) {
1325 bfa_trc(ioc, fwhdr.param); 1324 bfa_trc(ioc, fwhdr.param);
1326 bfa_trc(ioc, boot_env); 1325 bfa_trc(ioc, boot_env);
1327 return BFA_FALSE; 1326 return BFA_FALSE;
@@ -1338,9 +1337,9 @@ bfa_ioc_msgflush(struct bfa_ioc_s *ioc)
1338{ 1337{
1339 u32 r32; 1338 u32 r32;
1340 1339
1341 r32 = bfa_reg_read(ioc->ioc_regs.lpu_mbox_cmd); 1340 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
1342 if (r32) 1341 if (r32)
1343 bfa_reg_write(ioc->ioc_regs.lpu_mbox_cmd, 1); 1342 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1344} 1343}
1345 1344
1346 1345
@@ -1352,7 +1351,7 @@ bfa_ioc_hwinit(struct bfa_ioc_s *ioc, bfa_boolean_t force)
1352 u32 boot_type; 1351 u32 boot_type;
1353 u32 boot_env; 1352 u32 boot_env;
1354 1353
1355 ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate); 1354 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
1356 1355
1357 if (force) 1356 if (force)
1358 ioc_fwstate = BFI_IOC_UNINIT; 1357 ioc_fwstate = BFI_IOC_UNINIT;
@@ -1449,17 +1448,17 @@ bfa_ioc_mbox_send(struct bfa_ioc_s *ioc, void *ioc_msg, int len)
1449 * first write msg to mailbox registers 1448 * first write msg to mailbox registers
1450 */ 1449 */
1451 for (i = 0; i < len / sizeof(u32); i++) 1450 for (i = 0; i < len / sizeof(u32); i++)
1452 bfa_reg_write(ioc->ioc_regs.hfn_mbox + i * sizeof(u32), 1451 writel(cpu_to_le32(msgp[i]),
1453 cpu_to_le32(msgp[i])); 1452 ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1454 1453
1455 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++) 1454 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++)
1456 bfa_reg_write(ioc->ioc_regs.hfn_mbox + i * sizeof(u32), 0); 1455 writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
1457 1456
1458 /* 1457 /*
1459 * write 1 to mailbox CMD to trigger LPU event 1458 * write 1 to mailbox CMD to trigger LPU event
1460 */ 1459 */
1461 bfa_reg_write(ioc->ioc_regs.hfn_mbox_cmd, 1); 1460 writel(1, ioc->ioc_regs.hfn_mbox_cmd);
1462 (void) bfa_reg_read(ioc->ioc_regs.hfn_mbox_cmd); 1461 (void) readl(ioc->ioc_regs.hfn_mbox_cmd);
1463} 1462}
1464 1463
1465static void 1464static void
@@ -1503,7 +1502,7 @@ bfa_ioc_hb_check(void *cbarg)
1503 struct bfa_ioc_s *ioc = cbarg; 1502 struct bfa_ioc_s *ioc = cbarg;
1504 u32 hb_count; 1503 u32 hb_count;
1505 1504
1506 hb_count = bfa_reg_read(ioc->ioc_regs.heartbeat); 1505 hb_count = readl(ioc->ioc_regs.heartbeat);
1507 if (ioc->hb_count == hb_count) { 1506 if (ioc->hb_count == hb_count) {
1508 printk(KERN_CRIT "Firmware heartbeat failure at %d", hb_count); 1507 printk(KERN_CRIT "Firmware heartbeat failure at %d", hb_count);
1509 bfa_ioc_recover(ioc); 1508 bfa_ioc_recover(ioc);
@@ -1519,7 +1518,7 @@ bfa_ioc_hb_check(void *cbarg)
1519static void 1518static void
1520bfa_ioc_hb_monitor(struct bfa_ioc_s *ioc) 1519bfa_ioc_hb_monitor(struct bfa_ioc_s *ioc)
1521{ 1520{
1522 ioc->hb_count = bfa_reg_read(ioc->ioc_regs.heartbeat); 1521 ioc->hb_count = readl(ioc->ioc_regs.heartbeat);
1523 bfa_hb_timer_start(ioc); 1522 bfa_hb_timer_start(ioc);
1524} 1523}
1525 1524
@@ -1554,7 +1553,7 @@ bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type,
1554 pgnum = bfa_ioc_smem_pgnum(ioc, loff); 1553 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
1555 pgoff = bfa_ioc_smem_pgoff(ioc, loff); 1554 pgoff = bfa_ioc_smem_pgoff(ioc, loff);
1556 1555
1557 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum); 1556 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1558 1557
1559 for (i = 0; i < bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)); i++) { 1558 for (i = 0; i < bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)); i++) {
1560 1559
@@ -1578,21 +1577,19 @@ bfa_ioc_download_fw(struct bfa_ioc_s *ioc, u32 boot_type,
1578 loff = PSS_SMEM_PGOFF(loff); 1577 loff = PSS_SMEM_PGOFF(loff);
1579 if (loff == 0) { 1578 if (loff == 0) {
1580 pgnum++; 1579 pgnum++;
1581 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, 1580 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1582 pgnum);
1583 } 1581 }
1584 } 1582 }
1585 1583
1586 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, 1584 writel(bfa_ioc_smem_pgnum(ioc, 0), ioc->ioc_regs.host_page_num_fn);
1587 bfa_ioc_smem_pgnum(ioc, 0));
1588 1585
1589 /* 1586 /*
1590 * Set boot type and boot param at the end. 1587 * Set boot type and boot param at the end.
1591 */ 1588 */
1592 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_TYPE_OFF, 1589 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_TYPE_OFF,
1593 bfa_os_swap32(boot_type)); 1590 swab32(boot_type));
1594 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_LOADER_OFF, 1591 bfa_mem_write(ioc->ioc_regs.smem_page_start, BFI_BOOT_LOADER_OFF,
1595 bfa_os_swap32(boot_env)); 1592 swab32(boot_env));
1596} 1593}
1597 1594
1598static void 1595static void
@@ -1651,7 +1648,7 @@ bfa_ioc_mbox_poll(struct bfa_ioc_s *ioc)
1651 /** 1648 /**
1652 * If previous command is not yet fetched by firmware, do nothing 1649 * If previous command is not yet fetched by firmware, do nothing
1653 */ 1650 */
1654 stat = bfa_reg_read(ioc->ioc_regs.hfn_mbox_cmd); 1651 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
1655 if (stat) 1652 if (stat)
1656 return; 1653 return;
1657 1654
@@ -1704,7 +1701,7 @@ bfa_ioc_smem_read(struct bfa_ioc_s *ioc, void *tbuf, u32 soff, u32 sz)
1704 return BFA_STATUS_FAILED; 1701 return BFA_STATUS_FAILED;
1705 } 1702 }
1706 1703
1707 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum); 1704 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1708 1705
1709 len = sz/sizeof(u32); 1706 len = sz/sizeof(u32);
1710 bfa_trc(ioc, len); 1707 bfa_trc(ioc, len);
@@ -1719,11 +1716,10 @@ bfa_ioc_smem_read(struct bfa_ioc_s *ioc, void *tbuf, u32 soff, u32 sz)
1719 loff = PSS_SMEM_PGOFF(loff); 1716 loff = PSS_SMEM_PGOFF(loff);
1720 if (loff == 0) { 1717 if (loff == 0) {
1721 pgnum++; 1718 pgnum++;
1722 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum); 1719 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1723 } 1720 }
1724 } 1721 }
1725 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, 1722 writel(bfa_ioc_smem_pgnum(ioc, 0), ioc->ioc_regs.host_page_num_fn);
1726 bfa_ioc_smem_pgnum(ioc, 0));
1727 /* 1723 /*
1728 * release semaphore. 1724 * release semaphore.
1729 */ 1725 */
@@ -1760,7 +1756,7 @@ bfa_ioc_smem_clr(struct bfa_ioc_s *ioc, u32 soff, u32 sz)
1760 return BFA_STATUS_FAILED; 1756 return BFA_STATUS_FAILED;
1761 } 1757 }
1762 1758
1763 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum); 1759 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1764 1760
1765 len = sz/sizeof(u32); /* len in words */ 1761 len = sz/sizeof(u32); /* len in words */
1766 bfa_trc(ioc, len); 1762 bfa_trc(ioc, len);
@@ -1774,11 +1770,10 @@ bfa_ioc_smem_clr(struct bfa_ioc_s *ioc, u32 soff, u32 sz)
1774 loff = PSS_SMEM_PGOFF(loff); 1770 loff = PSS_SMEM_PGOFF(loff);
1775 if (loff == 0) { 1771 if (loff == 0) {
1776 pgnum++; 1772 pgnum++;
1777 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, pgnum); 1773 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1778 } 1774 }
1779 } 1775 }
1780 bfa_reg_write(ioc->ioc_regs.host_page_num_fn, 1776 writel(bfa_ioc_smem_pgnum(ioc, 0), ioc->ioc_regs.host_page_num_fn);
1781 bfa_ioc_smem_pgnum(ioc, 0));
1782 1777
1783 /* 1778 /*
1784 * release semaphore. 1779 * release semaphore.
@@ -1855,7 +1850,7 @@ bfa_ioc_pll_init(struct bfa_ioc_s *ioc)
1855void 1850void
1856bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_env) 1851bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_env)
1857{ 1852{
1858 bfa_os_addr_t rb; 1853 void __iomem *rb;
1859 1854
1860 bfa_ioc_stats(ioc, ioc_boots); 1855 bfa_ioc_stats(ioc, ioc_boots);
1861 1856
@@ -1867,11 +1862,11 @@ bfa_ioc_boot(struct bfa_ioc_s *ioc, u32 boot_type, u32 boot_env)
1867 */ 1862 */
1868 rb = ioc->pcidev.pci_bar_kva; 1863 rb = ioc->pcidev.pci_bar_kva;
1869 if (boot_type == BFI_BOOT_TYPE_MEMTEST) { 1864 if (boot_type == BFI_BOOT_TYPE_MEMTEST) {
1870 bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_MEMTEST); 1865 writel(BFI_IOC_MEMTEST, (rb + BFA_IOC0_STATE_REG));
1871 bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_MEMTEST); 1866 writel(BFI_IOC_MEMTEST, (rb + BFA_IOC1_STATE_REG));
1872 } else { 1867 } else {
1873 bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_INITING); 1868 writel(BFI_IOC_INITING, (rb + BFA_IOC0_STATE_REG));
1874 bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_INITING); 1869 writel(BFI_IOC_INITING, (rb + BFA_IOC1_STATE_REG));
1875 } 1870 }
1876 1871
1877 bfa_ioc_msgflush(ioc); 1872 bfa_ioc_msgflush(ioc);
@@ -1904,7 +1899,7 @@ bfa_ioc_is_operational(struct bfa_ioc_s *ioc)
1904bfa_boolean_t 1899bfa_boolean_t
1905bfa_ioc_is_initialized(struct bfa_ioc_s *ioc) 1900bfa_ioc_is_initialized(struct bfa_ioc_s *ioc)
1906{ 1901{
1907 u32 r32 = bfa_reg_read(ioc->ioc_regs.ioc_fwstate); 1902 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
1908 1903
1909 return ((r32 != BFI_IOC_UNINIT) && 1904 return ((r32 != BFI_IOC_UNINIT) &&
1910 (r32 != BFI_IOC_INITING) && 1905 (r32 != BFI_IOC_INITING) &&
@@ -1923,7 +1918,7 @@ bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg)
1923 */ 1918 */
1924 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32)); 1919 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32));
1925 i++) { 1920 i++) {
1926 r32 = bfa_reg_read(ioc->ioc_regs.lpu_mbox + 1921 r32 = readl(ioc->ioc_regs.lpu_mbox +
1927 i * sizeof(u32)); 1922 i * sizeof(u32));
1928 msgp[i] = cpu_to_be32(r32); 1923 msgp[i] = cpu_to_be32(r32);
1929 } 1924 }
@@ -1931,8 +1926,8 @@ bfa_ioc_msgget(struct bfa_ioc_s *ioc, void *mbmsg)
1931 /** 1926 /**
1932 * turn off mailbox interrupt by clearing mailbox status 1927 * turn off mailbox interrupt by clearing mailbox status
1933 */ 1928 */
1934 bfa_reg_write(ioc->ioc_regs.lpu_mbox_cmd, 1); 1929 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1935 bfa_reg_read(ioc->ioc_regs.lpu_mbox_cmd); 1930 readl(ioc->ioc_regs.lpu_mbox_cmd);
1936} 1931}
1937 1932
1938void 1933void
@@ -2162,7 +2157,7 @@ bfa_ioc_mbox_queue(struct bfa_ioc_s *ioc, struct bfa_mbox_cmd_s *cmd)
2162 /** 2157 /**
2163 * If mailbox is busy, queue command for poll timer 2158 * If mailbox is busy, queue command for poll timer
2164 */ 2159 */
2165 stat = bfa_reg_read(ioc->ioc_regs.hfn_mbox_cmd); 2160 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
2166 if (stat) { 2161 if (stat) {
2167 list_add_tail(&cmd->qe, &mod->cmd_q); 2162 list_add_tail(&cmd->qe, &mod->cmd_q);
2168 return; 2163 return;
@@ -2251,17 +2246,17 @@ bfa_boolean_t
2251bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc) 2246bfa_ioc_adapter_is_disabled(struct bfa_ioc_s *ioc)
2252{ 2247{
2253 u32 ioc_state; 2248 u32 ioc_state;
2254 bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; 2249 void __iomem *rb = ioc->pcidev.pci_bar_kva;
2255 2250
2256 if (!bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled)) 2251 if (!bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled))
2257 return BFA_FALSE; 2252 return BFA_FALSE;
2258 2253
2259 ioc_state = bfa_reg_read(rb + BFA_IOC0_STATE_REG); 2254 ioc_state = readl(rb + BFA_IOC0_STATE_REG);
2260 if (!bfa_ioc_state_disabled(ioc_state)) 2255 if (!bfa_ioc_state_disabled(ioc_state))
2261 return BFA_FALSE; 2256 return BFA_FALSE;
2262 2257
2263 if (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_FC_8G1P) { 2258 if (ioc->pcidev.device_id != BFA_PCI_DEVICE_ID_FC_8G1P) {
2264 ioc_state = bfa_reg_read(rb + BFA_IOC1_STATE_REG); 2259 ioc_state = readl(rb + BFA_IOC1_STATE_REG);
2265 if (!bfa_ioc_state_disabled(ioc_state)) 2260 if (!bfa_ioc_state_disabled(ioc_state))
2266 return BFA_FALSE; 2261 return BFA_FALSE;
2267 } 2262 }
diff --git a/drivers/scsi/bfa/bfa_ioc.h b/drivers/scsi/bfa/bfa_ioc.h
index 71c0b5ac4af5..d60e4721f240 100644
--- a/drivers/scsi/bfa/bfa_ioc.h
+++ b/drivers/scsi/bfa/bfa_ioc.h
@@ -62,9 +62,9 @@ struct bfa_sge_s {
62}; 62};
63 63
64#define bfa_sge_word_swap(__sge) do { \ 64#define bfa_sge_word_swap(__sge) do { \
65 ((u32 *)(__sge))[0] = bfa_os_swap32(((u32 *)(__sge))[0]); \ 65 ((u32 *)(__sge))[0] = swab32(((u32 *)(__sge))[0]); \
66 ((u32 *)(__sge))[1] = bfa_os_swap32(((u32 *)(__sge))[1]); \ 66 ((u32 *)(__sge))[1] = swab32(((u32 *)(__sge))[1]); \
67 ((u32 *)(__sge))[2] = bfa_os_swap32(((u32 *)(__sge))[2]); \ 67 ((u32 *)(__sge))[2] = swab32(((u32 *)(__sge))[2]); \
68} while (0) 68} while (0)
69 69
70#define bfa_swap_words(_x) ( \ 70#define bfa_swap_words(_x) ( \
@@ -87,7 +87,7 @@ struct bfa_pcidev_s {
87 int pci_slot; 87 int pci_slot;
88 u8 pci_func; 88 u8 pci_func;
89 u16 device_id; 89 u16 device_id;
90 bfa_os_addr_t pci_bar_kva; 90 void __iomem *pci_bar_kva;
91}; 91};
92 92
93/** 93/**
@@ -130,34 +130,32 @@ __bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
130} 130}
131 131
132struct bfa_ioc_regs_s { 132struct bfa_ioc_regs_s {
133 bfa_os_addr_t hfn_mbox_cmd; 133 void __iomem *hfn_mbox_cmd;
134 bfa_os_addr_t hfn_mbox; 134 void __iomem *hfn_mbox;
135 bfa_os_addr_t lpu_mbox_cmd; 135 void __iomem *lpu_mbox_cmd;
136 bfa_os_addr_t lpu_mbox; 136 void __iomem *lpu_mbox;
137 bfa_os_addr_t pss_ctl_reg; 137 void __iomem *pss_ctl_reg;
138 bfa_os_addr_t pss_err_status_reg; 138 void __iomem *pss_err_status_reg;
139 bfa_os_addr_t app_pll_fast_ctl_reg; 139 void __iomem *app_pll_fast_ctl_reg;
140 bfa_os_addr_t app_pll_slow_ctl_reg; 140 void __iomem *app_pll_slow_ctl_reg;
141 bfa_os_addr_t ioc_sem_reg; 141 void __iomem *ioc_sem_reg;
142 bfa_os_addr_t ioc_usage_sem_reg; 142 void __iomem *ioc_usage_sem_reg;
143 bfa_os_addr_t ioc_init_sem_reg; 143 void __iomem *ioc_init_sem_reg;
144 bfa_os_addr_t ioc_usage_reg; 144 void __iomem *ioc_usage_reg;
145 bfa_os_addr_t host_page_num_fn; 145 void __iomem *host_page_num_fn;
146 bfa_os_addr_t heartbeat; 146 void __iomem *heartbeat;
147 bfa_os_addr_t ioc_fwstate; 147 void __iomem *ioc_fwstate;
148 bfa_os_addr_t ll_halt; 148 void __iomem *ll_halt;
149 bfa_os_addr_t err_set; 149 void __iomem *err_set;
150 bfa_os_addr_t shirq_isr_next; 150 void __iomem *shirq_isr_next;
151 bfa_os_addr_t shirq_msk_next; 151 void __iomem *shirq_msk_next;
152 bfa_os_addr_t smem_page_start; 152 void __iomem *smem_page_start;
153 u32 smem_pg0; 153 u32 smem_pg0;
154}; 154};
155 155
156#define bfa_reg_read(_raddr) bfa_os_reg_read(_raddr) 156#define bfa_mem_read(_raddr, _off) swab32(readl(((_raddr) + (_off))))
157#define bfa_reg_write(_raddr, _val) bfa_os_reg_write(_raddr, _val)
158#define bfa_mem_read(_raddr, _off) bfa_os_mem_read(_raddr, _off)
159#define bfa_mem_write(_raddr, _off, _val) \ 157#define bfa_mem_write(_raddr, _off, _val) \
160 bfa_os_mem_write(_raddr, _off, _val) 158 writel(swab32((_val)), ((_raddr) + (_off)))
161/** 159/**
162 * IOC Mailbox structures 160 * IOC Mailbox structures
163 */ 161 */
@@ -249,7 +247,7 @@ struct bfa_ioc_s {
249}; 247};
250 248
251struct bfa_ioc_hwif_s { 249struct bfa_ioc_hwif_s {
252 bfa_status_t (*ioc_pll_init) (bfa_os_addr_t rb, bfa_boolean_t fcmode); 250 bfa_status_t (*ioc_pll_init) (void __iomem *rb, bfa_boolean_t fcmode);
253 bfa_boolean_t (*ioc_firmware_lock) (struct bfa_ioc_s *ioc); 251 bfa_boolean_t (*ioc_firmware_lock) (struct bfa_ioc_s *ioc);
254 void (*ioc_firmware_unlock) (struct bfa_ioc_s *ioc); 252 void (*ioc_firmware_unlock) (struct bfa_ioc_s *ioc);
255 void (*ioc_reg_init) (struct bfa_ioc_s *ioc); 253 void (*ioc_reg_init) (struct bfa_ioc_s *ioc);
@@ -308,9 +306,9 @@ void bfa_ioc_mbox_regisr(struct bfa_ioc_s *ioc, enum bfi_mclass mc,
308 (__ioc)->fcmode)) 306 (__ioc)->fcmode))
309 307
310bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc); 308bfa_status_t bfa_ioc_pll_init(struct bfa_ioc_s *ioc);
311bfa_status_t bfa_ioc_cb_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode); 309bfa_status_t bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode);
312bfa_boolean_t bfa_ioc_ct_pll_init_complete(bfa_os_addr_t rb); 310bfa_boolean_t bfa_ioc_ct_pll_init_complete(void __iomem *rb);
313bfa_status_t bfa_ioc_ct_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode); 311bfa_status_t bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode);
314 312
315#define bfa_ioc_isr_mode_set(__ioc, __msix) \ 313#define bfa_ioc_isr_mode_set(__ioc, __msix) \
316 ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix)) 314 ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
@@ -370,8 +368,8 @@ void bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc);
370bfa_boolean_t bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc); 368bfa_boolean_t bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc);
371void bfa_ioc_hbfail_register(struct bfa_ioc_s *ioc, 369void bfa_ioc_hbfail_register(struct bfa_ioc_s *ioc,
372 struct bfa_ioc_hbfail_notify_s *notify); 370 struct bfa_ioc_hbfail_notify_s *notify);
373bfa_boolean_t bfa_ioc_sem_get(bfa_os_addr_t sem_reg); 371bfa_boolean_t bfa_ioc_sem_get(void __iomem *sem_reg);
374void bfa_ioc_sem_release(bfa_os_addr_t sem_reg); 372void bfa_ioc_sem_release(void __iomem *sem_reg);
375void bfa_ioc_hw_sem_release(struct bfa_ioc_s *ioc); 373void bfa_ioc_hw_sem_release(struct bfa_ioc_s *ioc);
376void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc, 374void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc,
377 struct bfi_ioc_image_hdr_s *fwhdr); 375 struct bfi_ioc_image_hdr_s *fwhdr);
diff --git a/drivers/scsi/bfa/bfa_ioc_cb.c b/drivers/scsi/bfa/bfa_ioc_cb.c
index a32c8601c51f..86210a5f7249 100644
--- a/drivers/scsi/bfa/bfa_ioc_cb.c
+++ b/drivers/scsi/bfa/bfa_ioc_cb.c
@@ -72,8 +72,8 @@ bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
72static void 72static void
73bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc) 73bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc)
74{ 74{
75 bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET); 75 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
76 bfa_reg_read(ioc->ioc_regs.err_set); 76 readl(ioc->ioc_regs.err_set);
77} 77}
78 78
79/** 79/**
@@ -96,7 +96,7 @@ static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
96static void 96static void
97bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) 97bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
98{ 98{
99 bfa_os_addr_t rb; 99 void __iomem *rb;
100 int pcifn = bfa_ioc_pcifn(ioc); 100 int pcifn = bfa_ioc_pcifn(ioc);
101 101
102 rb = bfa_ioc_bar0(ioc); 102 rb = bfa_ioc_bar0(ioc);
@@ -180,14 +180,14 @@ bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
180 * before we clear it. If it is not locked, writing 1 180 * before we clear it. If it is not locked, writing 1
181 * will lock it instead of clearing it. 181 * will lock it instead of clearing it.
182 */ 182 */
183 bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); 183 readl(ioc->ioc_regs.ioc_sem_reg);
184 bfa_ioc_hw_sem_release(ioc); 184 bfa_ioc_hw_sem_release(ioc);
185} 185}
186 186
187 187
188 188
189bfa_status_t 189bfa_status_t
190bfa_ioc_cb_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode) 190bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
191{ 191{
192 u32 pll_sclk, pll_fclk; 192 u32 pll_sclk, pll_fclk;
193 193
@@ -199,38 +199,32 @@ bfa_ioc_cb_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode)
199 __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) | 199 __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) |
200 __APP_PLL_400_JITLMT0_1(3U) | 200 __APP_PLL_400_JITLMT0_1(3U) |
201 __APP_PLL_400_CNTLMT0_1(3U); 201 __APP_PLL_400_CNTLMT0_1(3U);
202 bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT); 202 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
203 bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT); 203 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
204 bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); 204 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
205 bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); 205 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
206 bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); 206 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
207 bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); 207 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
208 bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); 208 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
209 bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); 209 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
210 bfa_reg_write(rb + APP_PLL_212_CTL_REG, 210 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
211 __APP_PLL_212_LOGIC_SOFT_RESET); 211 writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET,
212 bfa_reg_write(rb + APP_PLL_212_CTL_REG, 212 rb + APP_PLL_212_CTL_REG);
213 __APP_PLL_212_BYPASS | 213 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
214 __APP_PLL_212_LOGIC_SOFT_RESET); 214 writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET,
215 bfa_reg_write(rb + APP_PLL_400_CTL_REG, 215 rb + APP_PLL_400_CTL_REG);
216 __APP_PLL_400_LOGIC_SOFT_RESET);
217 bfa_reg_write(rb + APP_PLL_400_CTL_REG,
218 __APP_PLL_400_BYPASS |
219 __APP_PLL_400_LOGIC_SOFT_RESET);
220 udelay(2); 216 udelay(2);
221 bfa_reg_write(rb + APP_PLL_212_CTL_REG, 217 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
222 __APP_PLL_212_LOGIC_SOFT_RESET); 218 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
223 bfa_reg_write(rb + APP_PLL_400_CTL_REG, 219 writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET,
224 __APP_PLL_400_LOGIC_SOFT_RESET); 220 rb + APP_PLL_212_CTL_REG);
225 bfa_reg_write(rb + APP_PLL_212_CTL_REG, 221 writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET,
226 pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET); 222 rb + APP_PLL_400_CTL_REG);
227 bfa_reg_write(rb + APP_PLL_400_CTL_REG,
228 pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET);
229 udelay(2000); 223 udelay(2000);
230 bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); 224 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
231 bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); 225 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
232 bfa_reg_write((rb + APP_PLL_212_CTL_REG), pll_sclk); 226 writel(pll_sclk, (rb + APP_PLL_212_CTL_REG));
233 bfa_reg_write((rb + APP_PLL_400_CTL_REG), pll_fclk); 227 writel(pll_fclk, (rb + APP_PLL_400_CTL_REG));
234 228
235 return BFA_STATUS_OK; 229 return BFA_STATUS_OK;
236} 230}
diff --git a/drivers/scsi/bfa/bfa_ioc_ct.c b/drivers/scsi/bfa/bfa_ioc_ct.c
index 5008afe96c99..c852d985e198 100644
--- a/drivers/scsi/bfa/bfa_ioc_ct.c
+++ b/drivers/scsi/bfa/bfa_ioc_ct.c
@@ -76,19 +76,19 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
76 return BFA_TRUE; 76 return BFA_TRUE;
77 77
78 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); 78 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
79 usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg); 79 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
80 80
81 /** 81 /**
82 * If usage count is 0, always return TRUE. 82 * If usage count is 0, always return TRUE.
83 */ 83 */
84 if (usecnt == 0) { 84 if (usecnt == 0) {
85 bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 1); 85 writel(1, ioc->ioc_regs.ioc_usage_reg);
86 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); 86 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
87 bfa_trc(ioc, usecnt); 87 bfa_trc(ioc, usecnt);
88 return BFA_TRUE; 88 return BFA_TRUE;
89 } 89 }
90 90
91 ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate); 91 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
92 bfa_trc(ioc, ioc_fwstate); 92 bfa_trc(ioc, ioc_fwstate);
93 93
94 /** 94 /**
@@ -110,7 +110,7 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
110 * Same firmware version. Increment the reference count. 110 * Same firmware version. Increment the reference count.
111 */ 111 */
112 usecnt++; 112 usecnt++;
113 bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt); 113 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
114 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); 114 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
115 bfa_trc(ioc, usecnt); 115 bfa_trc(ioc, usecnt);
116 return BFA_TRUE; 116 return BFA_TRUE;
@@ -138,11 +138,11 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc)
138 * decrement usage count 138 * decrement usage count
139 */ 139 */
140 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); 140 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
141 usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg); 141 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
142 bfa_assert(usecnt > 0); 142 bfa_assert(usecnt > 0);
143 143
144 usecnt--; 144 usecnt--;
145 bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt); 145 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
146 bfa_trc(ioc, usecnt); 146 bfa_trc(ioc, usecnt);
147 147
148 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); 148 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
@@ -155,12 +155,12 @@ static void
155bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc) 155bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc)
156{ 156{
157 if (ioc->cna) { 157 if (ioc->cna) {
158 bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P); 158 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
159 /* Wait for halt to take effect */ 159 /* Wait for halt to take effect */
160 bfa_reg_read(ioc->ioc_regs.ll_halt); 160 readl(ioc->ioc_regs.ll_halt);
161 } else { 161 } else {
162 bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET); 162 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
163 bfa_reg_read(ioc->ioc_regs.err_set); 163 readl(ioc->ioc_regs.err_set);
164 } 164 }
165} 165}
166 166
@@ -197,7 +197,7 @@ static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
197static void 197static void
198bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc) 198bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
199{ 199{
200 bfa_os_addr_t rb; 200 void __iomem *rb;
201 int pcifn = bfa_ioc_pcifn(ioc); 201 int pcifn = bfa_ioc_pcifn(ioc);
202 202
203 rb = bfa_ioc_bar0(ioc); 203 rb = bfa_ioc_bar0(ioc);
@@ -256,13 +256,13 @@ bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
256static void 256static void
257bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc) 257bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc)
258{ 258{
259 bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; 259 void __iomem *rb = ioc->pcidev.pci_bar_kva;
260 u32 r32; 260 u32 r32;
261 261
262 /** 262 /**
263 * For catapult, base port id on personality register and IOC type 263 * For catapult, base port id on personality register and IOC type
264 */ 264 */
265 r32 = bfa_reg_read(rb + FNC_PERS_REG); 265 r32 = readl(rb + FNC_PERS_REG);
266 r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)); 266 r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
267 ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH; 267 ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
268 268
@@ -276,10 +276,10 @@ bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc)
276static void 276static void
277bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) 277bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
278{ 278{
279 bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva; 279 void __iomem *rb = ioc->pcidev.pci_bar_kva;
280 u32 r32, mode; 280 u32 r32, mode;
281 281
282 r32 = bfa_reg_read(rb + FNC_PERS_REG); 282 r32 = readl(rb + FNC_PERS_REG);
283 bfa_trc(ioc, r32); 283 bfa_trc(ioc, r32);
284 284
285 mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) & 285 mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
@@ -300,7 +300,7 @@ bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
300 r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))); 300 r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
301 bfa_trc(ioc, r32); 301 bfa_trc(ioc, r32);
302 302
303 bfa_reg_write(rb + FNC_PERS_REG, r32); 303 writel(r32, rb + FNC_PERS_REG);
304} 304}
305 305
306/** 306/**
@@ -312,7 +312,7 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
312 312
313 if (ioc->cna) { 313 if (ioc->cna) {
314 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg); 314 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
315 bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 0); 315 writel(0, ioc->ioc_regs.ioc_usage_reg);
316 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg); 316 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
317 } 317 }
318 318
@@ -321,7 +321,7 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
321 * before we clear it. If it is not locked, writing 1 321 * before we clear it. If it is not locked, writing 1
322 * will lock it instead of clearing it. 322 * will lock it instead of clearing it.
323 */ 323 */
324 bfa_reg_read(ioc->ioc_regs.ioc_sem_reg); 324 readl(ioc->ioc_regs.ioc_sem_reg);
325 bfa_ioc_hw_sem_release(ioc); 325 bfa_ioc_hw_sem_release(ioc);
326} 326}
327 327
@@ -331,17 +331,17 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
331 * Check the firmware state to know if pll_init has been completed already 331 * Check the firmware state to know if pll_init has been completed already
332 */ 332 */
333bfa_boolean_t 333bfa_boolean_t
334bfa_ioc_ct_pll_init_complete(bfa_os_addr_t rb) 334bfa_ioc_ct_pll_init_complete(void __iomem *rb)
335{ 335{
336 if ((bfa_reg_read(rb + BFA_IOC0_STATE_REG) == BFI_IOC_OP) || 336 if ((readl(rb + BFA_IOC0_STATE_REG) == BFI_IOC_OP) ||
337 (bfa_reg_read(rb + BFA_IOC1_STATE_REG) == BFI_IOC_OP)) 337 (readl(rb + BFA_IOC1_STATE_REG) == BFI_IOC_OP))
338 return BFA_TRUE; 338 return BFA_TRUE;
339 339
340 return BFA_FALSE; 340 return BFA_FALSE;
341} 341}
342 342
343bfa_status_t 343bfa_status_t
344bfa_ioc_ct_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode) 344bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
345{ 345{
346 u32 pll_sclk, pll_fclk, r32; 346 u32 pll_sclk, pll_fclk, r32;
347 347
@@ -354,56 +354,51 @@ bfa_ioc_ct_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode)
354 __APP_PLL_425_JITLMT0_1(3U) | 354 __APP_PLL_425_JITLMT0_1(3U) |
355 __APP_PLL_425_CNTLMT0_1(1U); 355 __APP_PLL_425_CNTLMT0_1(1U);
356 if (fcmode) { 356 if (fcmode) {
357 bfa_reg_write((rb + OP_MODE), 0); 357 writel(0, (rb + OP_MODE));
358 bfa_reg_write((rb + ETH_MAC_SER_REG), 358 writel(__APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 |
359 __APP_EMS_CMLCKSEL | 359 __APP_EMS_CHANNEL_SEL, (rb + ETH_MAC_SER_REG));
360 __APP_EMS_REFCKBUFEN2 |
361 __APP_EMS_CHANNEL_SEL);
362 } else { 360 } else {
363 bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE); 361 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
364 bfa_reg_write((rb + ETH_MAC_SER_REG), 362 writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG));
365 __APP_EMS_REFCKBUFEN1);
366 } 363 }
367 bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT); 364 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
368 bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT); 365 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
369 bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); 366 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
370 bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); 367 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
371 bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); 368 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
372 bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); 369 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
373 bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU); 370 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
374 bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU); 371 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
375 bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk | 372 writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET,
376 __APP_PLL_312_LOGIC_SOFT_RESET); 373 rb + APP_PLL_312_CTL_REG);
377 bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk | 374 writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET,
378 __APP_PLL_425_LOGIC_SOFT_RESET); 375 rb + APP_PLL_425_CTL_REG);
379 bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk | 376 writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE,
380 __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE); 377 rb + APP_PLL_312_CTL_REG);
381 bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk | 378 writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE,
382 __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE); 379 rb + APP_PLL_425_CTL_REG);
383 bfa_reg_read(rb + HOSTFN0_INT_MSK); 380 readl(rb + HOSTFN0_INT_MSK);
384 udelay(2000); 381 udelay(2000);
385 bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU); 382 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
386 bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU); 383 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
387 bfa_reg_write(rb + APP_PLL_312_CTL_REG, pll_sclk | 384 writel(pll_sclk | __APP_PLL_312_ENABLE, rb + APP_PLL_312_CTL_REG);
388 __APP_PLL_312_ENABLE); 385 writel(pll_fclk | __APP_PLL_425_ENABLE, rb + APP_PLL_425_CTL_REG);
389 bfa_reg_write(rb + APP_PLL_425_CTL_REG, pll_fclk |
390 __APP_PLL_425_ENABLE);
391 if (!fcmode) { 386 if (!fcmode) {
392 bfa_reg_write((rb + PMM_1T_RESET_REG_P0), __PMM_1T_RESET_P); 387 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
393 bfa_reg_write((rb + PMM_1T_RESET_REG_P1), __PMM_1T_RESET_P); 388 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
394 } 389 }
395 r32 = bfa_reg_read((rb + PSS_CTL_REG)); 390 r32 = readl((rb + PSS_CTL_REG));
396 r32 &= ~__PSS_LMEM_RESET; 391 r32 &= ~__PSS_LMEM_RESET;
397 bfa_reg_write((rb + PSS_CTL_REG), r32); 392 writel(r32, (rb + PSS_CTL_REG));
398 udelay(1000); 393 udelay(1000);
399 if (!fcmode) { 394 if (!fcmode) {
400 bfa_reg_write((rb + PMM_1T_RESET_REG_P0), 0); 395 writel(0, (rb + PMM_1T_RESET_REG_P0));
401 bfa_reg_write((rb + PMM_1T_RESET_REG_P1), 0); 396 writel(0, (rb + PMM_1T_RESET_REG_P1));
402 } 397 }
403 398
404 bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START); 399 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
405 udelay(1000); 400 udelay(1000);
406 r32 = bfa_reg_read((rb + MBIST_STAT_REG)); 401 r32 = readl((rb + MBIST_STAT_REG));
407 bfa_reg_write((rb + MBIST_CTL_REG), 0); 402 writel(0, (rb + MBIST_CTL_REG));
408 return BFA_STATUS_OK; 403 return BFA_STATUS_OK;
409} 404}
diff --git a/drivers/scsi/bfa/bfa_os_inc.h b/drivers/scsi/bfa/bfa_os_inc.h
index d928dcaa5080..f9edc758c12e 100644
--- a/drivers/scsi/bfa/bfa_os_inc.h
+++ b/drivers/scsi/bfa/bfa_os_inc.h
@@ -65,12 +65,6 @@ do { \
65 ((_x) & 0x00ff00) | \ 65 ((_x) & 0x00ff00) | \
66 (((_x) & 0xff0000) >> 16)) 66 (((_x) & 0xff0000) >> 16))
67 67
68#define bfa_os_swap32(_x) \
69 ((((_x) & 0xff) << 24) | \
70 (((_x) & 0x0000ff00) << 8) | \
71 (((_x) & 0x00ff0000) >> 8) | \
72 (((_x) & 0xff000000) >> 24))
73
74#define bfa_os_swap_sgaddr(_x) ((u64)( \ 68#define bfa_os_swap_sgaddr(_x) ((u64)( \
75 (((u64)(_x) & (u64)0x00000000000000ffull) << 32) | \ 69 (((u64)(_x) & (u64)0x00000000000000ffull) << 32) | \
76 (((u64)(_x) & (u64)0x000000000000ff00ull) << 32) | \ 70 (((u64)(_x) & (u64)0x000000000000ff00ull) << 32) | \
@@ -82,7 +76,7 @@ do { \
82 (((u64)(_x) & (u64)0xff00000000000000ull) >> 32))) 76 (((u64)(_x) & (u64)0xff00000000000000ull) >> 32)))
83 77
84#ifndef __BIGENDIAN 78#ifndef __BIGENDIAN
85#define bfa_os_hton3b(_x) bfa_swap_3b(_x) 79#define bfa_os_hton3b(_x) bfa_swap_3b(_x)
86#define bfa_os_sgaddr(_x) (_x) 80#define bfa_os_sgaddr(_x) (_x)
87#else 81#else
88#define bfa_os_hton3b(_x) (_x) 82#define bfa_os_hton3b(_x) (_x)
@@ -91,22 +85,14 @@ do { \
91 85
92#define bfa_os_ntoh3b(_x) bfa_os_hton3b(_x) 86#define bfa_os_ntoh3b(_x) bfa_os_hton3b(_x)
93#define bfa_os_u32(__pa64) ((__pa64) >> 32) 87#define bfa_os_u32(__pa64) ((__pa64) >> 32)
94#define bfa_os_addr_t void __iomem * 88
95 89#define BFA_TRC_TS(_trcm) \
96#define bfa_os_reg_read(_raddr) readl(_raddr) 90 ({ \
97#define bfa_os_reg_write(_raddr, _val) writel((_val), (_raddr)) 91 struct timeval tv; \
98#define bfa_os_mem_read(_raddr, _off) \ 92 \
99 bfa_os_swap32(readl(((_raddr) + (_off)))) 93 do_gettimeofday(&tv); \
100#define bfa_os_mem_write(_raddr, _off, _val) \ 94 (tv.tv_sec*1000000+tv.tv_usec); \
101 writel(bfa_os_swap32((_val)), ((_raddr) + (_off))) 95 })
102
103#define BFA_TRC_TS(_trcm) \
104 ({ \
105 struct timeval tv; \
106 \
107 do_gettimeofday(&tv); \
108 (tv.tv_sec*1000000+tv.tv_usec); \
109 })
110 96
111#define boolean_t int 97#define boolean_t int
112 98
diff --git a/drivers/scsi/bfa/bfad_debugfs.c b/drivers/scsi/bfa/bfad_debugfs.c
index 69ed1c4a903e..1fedeeb4ac1f 100644
--- a/drivers/scsi/bfa/bfad_debugfs.c
+++ b/drivers/scsi/bfa/bfad_debugfs.c
@@ -318,7 +318,7 @@ bfad_debugfs_write_regrd(struct file *file, const char __user *buf,
318 regbuf = (u32 *)bfad->regdata; 318 regbuf = (u32 *)bfad->regdata;
319 spin_lock_irqsave(&bfad->bfad_lock, flags); 319 spin_lock_irqsave(&bfad->bfad_lock, flags);
320 for (i = 0; i < len; i++) { 320 for (i = 0; i < len; i++) {
321 *regbuf = bfa_reg_read(reg_addr); 321 *regbuf = readl(reg_addr);
322 regbuf++; 322 regbuf++;
323 reg_addr += sizeof(u32); 323 reg_addr += sizeof(u32);
324 } 324 }
@@ -361,7 +361,7 @@ bfad_debugfs_write_regwr(struct file *file, const char __user *buf,
361 361
362 reg_addr = (u32 *) ((u8 *) bfa_ioc_bar0(ioc) + addr); 362 reg_addr = (u32 *) ((u8 *) bfa_ioc_bar0(ioc) + addr);
363 spin_lock_irqsave(&bfad->bfad_lock, flags); 363 spin_lock_irqsave(&bfad->bfad_lock, flags);
364 bfa_reg_write(reg_addr, val); 364 writel(val, reg_addr);
365 spin_unlock_irqrestore(&bfad->bfad_lock, flags); 365 spin_unlock_irqrestore(&bfad->bfad_lock, flags);
366 366
367 return nbytes; 367 return nbytes;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 05:54:10 -0500