diff options
author | Eric Anholt <eric@anholt.net> | 2009-10-26 19:44:17 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-02-26 16:23:18 -0500 |
commit | 4e901fdc263d32d4cb4c59ec16ff0874129ec8c9 (patch) | |
tree | 969a4593a63fc4c1f510f5f85fae7c71571b3179 | |
parent | bad720ff3e8e47a04bd88d9bbc8317e7d7e049d3 (diff) |
drm/i915: Set up fence registers on sandybridge.
Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 33 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
2 files changed, 33 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a35dc8c0882b..715eaac62dbd 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -2261,6 +2261,28 @@ i915_gem_object_get_pages(struct drm_gem_object *obj, | |||
2261 | return 0; | 2261 | return 0; |
2262 | } | 2262 | } |
2263 | 2263 | ||
2264 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) | ||
2265 | { | ||
2266 | struct drm_gem_object *obj = reg->obj; | ||
2267 | struct drm_device *dev = obj->dev; | ||
2268 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
2269 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | ||
2270 | int regnum = obj_priv->fence_reg; | ||
2271 | uint64_t val; | ||
2272 | |||
2273 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | ||
2274 | 0xfffff000) << 32; | ||
2275 | val |= obj_priv->gtt_offset & 0xfffff000; | ||
2276 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | ||
2277 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | ||
2278 | |||
2279 | if (obj_priv->tiling_mode == I915_TILING_Y) | ||
2280 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | ||
2281 | val |= I965_FENCE_REG_VALID; | ||
2282 | |||
2283 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | ||
2284 | } | ||
2285 | |||
2264 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) | 2286 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2265 | { | 2287 | { |
2266 | struct drm_gem_object *obj = reg->obj; | 2288 | struct drm_gem_object *obj = reg->obj; |
@@ -2478,7 +2500,9 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |||
2478 | 2500 | ||
2479 | reg->obj = obj; | 2501 | reg->obj = obj; |
2480 | 2502 | ||
2481 | if (IS_I965G(dev)) | 2503 | if (IS_GEN6(dev)) |
2504 | sandybridge_write_fence_reg(reg); | ||
2505 | else if (IS_I965G(dev)) | ||
2482 | i965_write_fence_reg(reg); | 2506 | i965_write_fence_reg(reg); |
2483 | else if (IS_I9XX(dev)) | 2507 | else if (IS_I9XX(dev)) |
2484 | i915_write_fence_reg(reg); | 2508 | i915_write_fence_reg(reg); |
@@ -2504,9 +2528,12 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |||
2504 | drm_i915_private_t *dev_priv = dev->dev_private; | 2528 | drm_i915_private_t *dev_priv = dev->dev_private; |
2505 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | 2529 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
2506 | 2530 | ||
2507 | if (IS_I965G(dev)) | 2531 | if (IS_GEN6(dev)) { |
2532 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + | ||
2533 | (obj_priv->fence_reg * 8), 0); | ||
2534 | } else if (IS_I965G(dev)) { | ||
2508 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); | 2535 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
2509 | else { | 2536 | } else { |
2510 | uint32_t fence_reg; | 2537 | uint32_t fence_reg; |
2511 | 2538 | ||
2512 | if (obj_priv->fence_reg < 8) | 2539 | if (obj_priv->fence_reg < 8) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eff8d850a758..1232229450e7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -235,6 +235,9 @@ | |||
235 | #define I965_FENCE_REG_VALID (1<<0) | 235 | #define I965_FENCE_REG_VALID (1<<0) |
236 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 | 236 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
237 | 237 | ||
238 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 | ||
239 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 | ||
240 | |||
238 | /* | 241 | /* |
239 | * Instruction and interrupt control regs | 242 | * Instruction and interrupt control regs |
240 | */ | 243 | */ |