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authorChen-Yu Tsai <wens@csie.org>2014-06-17 10:52:51 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-07-11 08:08:30 -0400
commit4c821d1c934c741b995d37cab206b7fca5ffd6a5 (patch)
tree3d3e8be646c4d1085fb3b1a0ad88508356a35163
parentd9ff081d9123af59144d3617668c8274b2cc3254 (diff)
pinctrl: sunxi: Add A23 PIO controller support
The A23 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt1
-rw-r--r--drivers/pinctrl/sunxi/Kconfig4
-rw-r--r--drivers/pinctrl/sunxi/Makefile1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c593
4 files changed, 599 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index d8d065608ec0..44a78c1fee83 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -13,6 +13,7 @@ Required properties:
13 "allwinner,sun6i-a31-pinctrl" 13 "allwinner,sun6i-a31-pinctrl"
14 "allwinner,sun6i-a31-r-pinctrl" 14 "allwinner,sun6i-a31-r-pinctrl"
15 "allwinner,sun7i-a20-pinctrl" 15 "allwinner,sun7i-a20-pinctrl"
16 "allwinner,sun8i-a23-pinctrl"
16- reg: Should contain the register physical address and length for the 17- reg: Should contain the register physical address and length for the
17 pin controller. 18 pin controller.
18 19
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 4cbf458579d5..7e6a2684949a 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -30,4 +30,8 @@ config PINCTRL_SUN7I_A20
30 def_bool MACH_SUN7I 30 def_bool MACH_SUN7I
31 select PINCTRL_SUNXI_COMMON 31 select PINCTRL_SUNXI_COMMON
32 32
33config PINCTRL_SUN8I_A23
34 def_bool MACH_SUN8I
35 select PINCTRL_SUNXI_COMMON
36
33endif 37endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 0f4461cbe11d..850cd5014dd8 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o 8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o 9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o 10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
11obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
new file mode 100644
index 000000000000..ac71e8c5901b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -0,0 +1,593 @@
1/*
2 * Allwinner A23 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Chen-Yu Tsai
5 *
6 * Chen-Yu Tsai <wens@csie.org>
7 *
8 * Copyright (C) 2014 Maxime Ripard
9 *
10 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-sunxi.h"
24
25static const struct sunxi_desc_pin sun8i_a23_pins[] = {
26 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
27 SUNXI_FUNCTION(0x0, "gpio_in"),
28 SUNXI_FUNCTION(0x1, "gpio_out"),
29 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
30 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
31 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PA_EINT0 */
32 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
33 SUNXI_FUNCTION(0x0, "gpio_in"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
35 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
36 SUNXI_FUNCTION(0x3, "jtag"), /* CKO */
37 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PA_EINT1 */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
39 SUNXI_FUNCTION(0x0, "gpio_in"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
42 SUNXI_FUNCTION(0x3, "jtag"), /* DOO */
43 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PA_EINT2 */
44 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
45 SUNXI_FUNCTION(0x0, "gpio_in"),
46 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
48 SUNXI_FUNCTION(0x3, "jtag"), /* DIO */
49 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PA_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
54 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PA_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
59 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PA_EINT5 */
60 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
61 SUNXI_FUNCTION(0x0, "gpio_in"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
64 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PA_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
69 SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PA_EINT7 */
70 /* Hole */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
75 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PB_EINT0 */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
80 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PB_EINT1 */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
85 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PB_EINT2 */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
90 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PB_EINT3 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
95 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PB_EINT4 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
100 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PB_EINT5 */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
105 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PB_EINT6 */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
110 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PB_EINT7 */
111 /* Hole */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
113 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out"),
115 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
116 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
121 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
123 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
126 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
131 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
140 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
141 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
142 SUNXI_FUNCTION(0x0, "gpio_in"),
143 SUNXI_FUNCTION(0x1, "gpio_out"),
144 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
145 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
154 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
159 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
164 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
165 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
166 SUNXI_FUNCTION(0x0, "gpio_in"),
167 SUNXI_FUNCTION(0x1, "gpio_out"),
168 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
169 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
170 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
171 SUNXI_FUNCTION(0x0, "gpio_in"),
172 SUNXI_FUNCTION(0x1, "gpio_out"),
173 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
174 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
179 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
184 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
185 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
186 SUNXI_FUNCTION(0x0, "gpio_in"),
187 SUNXI_FUNCTION(0x1, "gpio_out"),
188 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
189 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
194 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
203 /* Hole */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
216 SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
221 SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
226 SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
231 SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
233 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out"),
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
236 SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
241 SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
246 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
251 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
252 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
253 SUNXI_FUNCTION(0x0, "gpio_in"),
254 SUNXI_FUNCTION(0x1, "gpio_out"),
255 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
256 SUNXI_FUNCTION(0x3, "uart1")), /* TX */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
261 SUNXI_FUNCTION(0x3, "uart1")), /* RX */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
266 SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
271 SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
276 SUNXI_FUNCTION(0x3, "i2s1")), /* SYNC */
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
281 SUNXI_FUNCTION(0x3, "i2s1")), /* CLK */
282 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
283 SUNXI_FUNCTION(0x0, "gpio_in"),
284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
286 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
291 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
296 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
301 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out"),
305 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
306 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
307 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
308 SUNXI_FUNCTION(0x0, "gpio_in"),
309 SUNXI_FUNCTION(0x1, "gpio_out"),
310 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
311 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
316 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
321 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
326 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
331 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
336 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
341 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
342 /* Hole */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "csi")), /* D2 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "csi")), /* D3 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "csi")), /* D4 */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "csi")), /* D5 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "csi")), /* D6 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "csi")), /* D7 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
395 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
400 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
401 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
402 SUNXI_FUNCTION(0x0, "gpio_in"),
403 SUNXI_FUNCTION(0x1, "gpio_out")),
404 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
405 SUNXI_FUNCTION(0x0, "gpio_in"),
406 SUNXI_FUNCTION(0x1, "gpio_out")),
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out")),
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out")),
413 /* Hole */
414 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
415 SUNXI_FUNCTION(0x0, "gpio_in"),
416 SUNXI_FUNCTION(0x1, "gpio_out"),
417 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
418 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
419 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
420 SUNXI_FUNCTION(0x0, "gpio_in"),
421 SUNXI_FUNCTION(0x1, "gpio_out"),
422 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
423 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
424 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
425 SUNXI_FUNCTION(0x0, "gpio_in"),
426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
428 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
429 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
430 SUNXI_FUNCTION(0x0, "gpio_in"),
431 SUNXI_FUNCTION(0x1, "gpio_out"),
432 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
433 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
435 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
438 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
440 SUNXI_FUNCTION(0x0, "gpio_in"),
441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
443 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
444 /* Hole */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
449 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 0)), /* PG_EINT0 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
454 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 1)), /* PG_EINT1 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
459 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 2)), /* PG_EINT2 */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
464 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 3)), /* PG_EINT3 */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
469 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 4)), /* PG_EINT4 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
474 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 5)), /* PG_EINT5 */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
479 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 6)), /* PG_EINT6 */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
484 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 7)), /* PG_EINT7 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
489 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
494 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */
495 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
499 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 10)), /* PG_EINT10 */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
504 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 11)), /* PG_EINT11 */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
509 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 12)), /* PG_EINT12 */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
514 SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 13)), /* PG_EINT13 */
515 /* Hole */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "pwm0")),
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
521 SUNXI_FUNCTION(0x0, "gpio_in"),
522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "pwm1")),
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
528 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
529 SUNXI_FUNCTION(0x0, "gpio_in"),
530 SUNXI_FUNCTION(0x1, "gpio_out"),
531 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
536 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
537 SUNXI_FUNCTION(0x0, "gpio_in"),
538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out"),
543 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
544 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
549 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
554 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
559 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
560};
561
562static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = {
563 .pins = sun8i_a23_pins,
564 .npins = ARRAY_SIZE(sun8i_a23_pins),
565 .irq_banks = 3,
566};
567
568static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
569{
570 return sunxi_pinctrl_init(pdev,
571 &sun8i_a23_pinctrl_data);
572}
573
574static struct of_device_id sun8i_a23_pinctrl_match[] = {
575 { .compatible = "allwinner,sun8i-a23-pinctrl", },
576 {}
577};
578MODULE_DEVICE_TABLE(of, sun8i_a23_pinctrl_match);
579
580static struct platform_driver sun8i_a23_pinctrl_driver = {
581 .probe = sun8i_a23_pinctrl_probe,
582 .driver = {
583 .name = "sun8i-a23-pinctrl",
584 .owner = THIS_MODULE,
585 .of_match_table = sun8i_a23_pinctrl_match,
586 },
587};
588module_platform_driver(sun8i_a23_pinctrl_driver);
589
590MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
591MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
592MODULE_DESCRIPTION("Allwinner A23 pinctrl driver");
593MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 08:28:07 -0400