Merge tag 'tegra-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra into tegra/dt

Device tree updates for tegra. Various development, including a handful
of additions to the tegra30 device trees.

* tag 'tegra-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra:
  ASoC: DT: Add digital microphone binding to PAZ00 board.
  ARM: dt: Add ARM PMU to tegra*.dtsi
  ARM: dt: Add SD controller configuration to Tegra Cardhu
  ARM: dt: tegra: Enable headset autodetection on PAZ00 board.
  ARM: dt: tegra: Enable device tree audio codec on PAZ00 board.
  ARM: dt: Add binding for Tegra PMC
  ARM: dt: tegra: Enable audio on WM8903 boards, disable others
  ARM: dt: tegra: Add labels for I2S controllers
  ARM: dt: tegra: Modify I2S nodes to match binding
  ARM: dt: tegra: Add Tegra APB DMA device tree binding
  ARM: dt: tegra30.dtsi: Add extra GPIO interrupt
  ARM: dt: tegra30.dtsi: Reformat gpio's interrupts property
  dt: tegra gpio: Flesh out binding documentation
  ARM: tegra: seaboard: add EMC table to device tree
  ARM: tegra: emc: device tree bindings

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

12 files changed, 484 insertions, 15 deletions

diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt b/Documentation/devicetree/bindings/arm/tegra/emc.txt
new file mode 100644
index 000000000000..09335f8eee00
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/emc.txt
@@ -0,0 +1,100 @@
+Embedded Memory Controller
+
+Properties:
+- name : Should be emc
+- #address-cells : Should be 1
+- #size-cells : Should be 0
+- compatible : Should contain "nvidia,tegra20-emc".
+- reg : Offset and length of the register set for the device
+- nvidia,use-ram-code : If present, the sub-nodes will be addressed
+  and chosen using the ramcode board selector. If omitted, only one
+  set of tables can be present and said tables will be used
+  irrespective of ram-code configuration.
+
+Child device nodes describe the memory settings for different configurations and clock rates.
+
+Example:
+
+        emc@7000f400 {
+                #address-cells = < 1 >;
+                #size-cells = < 0 >;
+                compatible = "nvidia,tegra20-emc";
+                reg = <0x7000f4000 0x200>;
+        }
+
+
+Embedded Memory Controller ram-code table
+
+If the emc node has the nvidia,use-ram-code property present, then the
+next level of nodes below the emc table are used to specify which settings
+apply for which ram-code settings.
+
+If the emc node lacks the nvidia,use-ram-code property, this level is omitted
+and the tables are stored directly under the emc node (see below).
+
+Properties:
+
+- name : Should be emc-tables
+- nvidia,ram-code : the binary representation of the ram-code board strappings
+  for which this node (and children) are valid.
+
+
+
+Embedded Memory Controller configuration table
+
+This is a table containing the EMC register settings for the various
+operating speeds of the memory controller. They are always located as
+subnodes of the emc controller node.
+
+There are two ways of specifying which tables to use:
+
+* The simplest is if there is just one set of tables in the device tree,
+  and they will always be used (based on which frequency is used).
+  This is the preferred method, especially when firmware can fill in
+  this information based on the specific system information and just
+  pass it on to the kernel.
+
+* The slightly more complex one is when more than one memory configuration
+  might exist on the system.  The Tegra20 platform handles this during
+  early boot by selecting one out of possible 4 memory settings based
+  on a 2-pin "ram code" bootstrap setting on the board. The values of
+  these strappings can be read through a register in the SoC, and thus
+  used to select which tables to use.
+
+Properties:
+- name : Should be emc-table
+- compatible : Should contain "nvidia,tegra20-emc-table".
+- reg : either an opaque enumerator to tell different tables apart, or
+  the valid frequency for which the table should be used (in kHz).
+- clock-frequency : the clock frequency for the EMC at which this
+  table should be used (in kHz).
+- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
+  for operation at the 'clock-frequency' setting.
+  The order and contents of the registers are:
+    RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
+    WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
+    PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
+    TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
+    ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
+    ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
+    CFG_CLKTRIM_1, CFG_CLKTRIM_2
+
+                emc-table@166000 {
+                        reg = <166000>;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 166000 >;
+                        nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+                                                 0 0 0 0 >;
+                };
+
+                emc-table@333000 {
+                        reg = <333000>;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 333000 >;
+                        nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+                                                 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+                                                 0 0 0 0 >;
+                };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
new file mode 100644
index 000000000000..b5846e21cc2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -0,0 +1,19 @@
+NVIDIA Tegra Power Management Controller (PMC)
+
+Properties:
+- name : Should be pmc
+- compatible : Should contain "nvidia,tegra<chip>-pmc".
+- reg : Offset and length of the register set for the device
+- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
+  The PMU is an external Power Management Unit, whose interrupt output
+  signal is fed into the PMC. This signal is optionally inverted, and then
+  fed into the ARM GIC. The PMC is not involved in the detection or
+  handling of this interrupt signal, merely its inversion.
+
+Example:
+
+pmc@7000f400 {
+        compatible = "nvidia,tegra20-pmc";
+        reg = <0x7000e400 0x400>;
+        nvidia,invert-interrupt;
+};
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
new file mode 100644
index 000000000000..90fa7da525b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -0,0 +1,30 @@
+* NVIDIA Tegra APB DMA controller
+
+Required properties:
+- compatible: Should be "nvidia,<chip>-apbdma"
+- reg: Should contain DMA registers location and length. This shuld include
+  all of the per-channel registers.
+- interrupts: Should contain all of the per-channel DMA interrupts.
+
+Examples:
+
+apbdma: dma@6000a000 {
+        compatible = "nvidia,tegra20-apbdma";
+        reg = <0x6000a000 0x1200>;
+        interrupts = < 0 136 0x04
+                       0 137 0x04
+                       0 138 0x04
+                       0 139 0x04
+                       0 140 0x04
+                       0 141 0x04
+                       0 142 0x04
+                       0 143 0x04
+                       0 144 0x04
+                       0 145 0x04
+                       0 146 0x04
+                       0 147 0x04
+                       0 148 0x04
+                       0 149 0x04
+                       0 150 0x04
+                       0 151 0x04 >;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt b/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt
index eb4b530d64e1..50b363c5b884 100644
--- a/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt
@@ -2,7 +2,25 @@ NVIDIA Tegra 2 GPIO controller
 
 Required properties:
 - compatible : "nvidia,tegra20-gpio"
+- reg : Physical base address and length of the controller's registers.
+- interrupts : The interrupt outputs from the controller.
 - #gpio-cells : Should be two. The first cell is the pin number and the
   second cell is used to specify optional parameters:
   - bit 0 specifies polarity (0 for normal, 1 for inverted)
 - gpio-controller : Marks the device node as a GPIO controller.
+
+Example:
+
+gpio: gpio@6000d000 {
+        compatible = "nvidia,tegra20-gpio";
+        reg = < 0x6000d000 0x1000 >;
+        interrupts = < 0 32 0x04
+                       0 33 0x04
+                       0 34 0x04
+                       0 35 0x04
+                       0 55 0x04
+                       0 87 0x04
+                       0 89 0x04 >;
+        #gpio-cells = <2>;
+        gpio-controller;
+};
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 70c41fc897d7..73263501f581 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -33,4 +33,22 @@
         i2c@7000d000 {
                 clock-frequency = <100000>;
         };
+
+        sdhci@78000000 {
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+        };
+
+        sdhci@78000200 {
+                status = "disable";
+        };
+
+        sdhci@78000400 {
+                status = "disable";
+        };
+
+        sdhci@78000400 {
+                support-8bit;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 80afa1b70b80..6e8447dc0202 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,19 +10,25 @@
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        pmc@7000f400 {
+                nvidia,invert-interrupt;
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
 
-                codec: wm8903@1a {
+                wm8903: wm8903@1a {
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
-                        interrupts = < 347 >;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
 
                         gpio-controller;
                         #gpio-cells = <2>;
 
-                        /* 0x8000 = Not configured */
-                        gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >;
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
                 };
         };
 
@@ -38,13 +44,32 @@
                 clock-frequency = <400000>;
         };
 
-        sound {
-                compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903";
+        i2s@70002a00 {
+                status = "disable";
+        };
 
-                spkr-en-gpios = <&codec 2 0>;
-                hp-det-gpios = <&gpio 178 0>;
-                int-mic-en-gpios = <&gpio 184 0>;
-                ext-mic-en-gpios = <&gpio 185 0>;
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-harmony",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Harmony";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
         };
 
         serial@70006000 {
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 825d2957da0b..3c1ff5a43fb7 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -12,6 +12,13 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                alc5632: alc5632@1e {
+                        compatible = "realtek,alc5632";
+                        reg = <0x1e>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
         };
 
         i2c@7000c400 {
@@ -37,6 +44,30 @@
                 clock-frequency = <400000>;
         };
 
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-alc5632-paz00",
+                        "nvidia,tegra-audio-alc5632";
+
+                nvidia,model = "Compal PAZ00";
+
+                nvidia,audio-routing =
+                        "Int Spk", "SPKOUT",
+                        "Int Spk", "SPKOUTN",
+                        "Headset Mic", "MICBIAS1",
+                        "MIC1", "Headset Mic",
+                        "Headset Stereophone", "HPR",
+                        "Headset Stereophone", "HPL",
+                        "DMICDAT", "Digital Mic";
+
+                nvidia,audio-codec = <&alc5632>;
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+
         serial@70006000 {
                 clock-frequency = <216000000>;
         };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index b55a02e34ba7..876d5c92ce36 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -13,6 +13,20 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
+                };
         };
 
         i2c@7000c400 {
@@ -32,6 +46,32 @@
                 };
         };
 
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-seaboard",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Seaboard";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1R", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+        };
+
         serial@70006000 {
                 status = "disable";
         };
@@ -93,4 +133,42 @@
                         gpio-key,wakeup;
                 };
         };
+
+        emc@7000f400 {
+                emc-table@190000 {
+                        reg = < 190000 >;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 190000 >;
+                        nvidia,emc-registers = < 0x0000000c 0x00000026
+                                0x00000009 0x00000003 0x00000004 0x00000004
+                                0x00000002 0x0000000c 0x00000003 0x00000003
+                                0x00000002 0x00000001 0x00000004 0x00000005
+                                0x00000004 0x00000009 0x0000000d 0x0000059f
+                                0x00000000 0x00000003 0x00000003 0x00000003
+                                0x00000003 0x00000001 0x0000000b 0x000000c8
+                                0x00000003 0x00000007 0x00000004 0x0000000f
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0xa06204ae
+                                0x007dc010 0x00000000 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000 >;
+                };
+
+                emc-table@380000 {
+                        reg = < 380000 >;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 380000 >;
+                        nvidia,emc-registers = < 0x00000017 0x0000004b
+                                0x00000012 0x00000006 0x00000004 0x00000005
+                                0x00000003 0x0000000c 0x00000006 0x00000006
+                                0x00000003 0x00000001 0x00000004 0x00000005
+                                0x00000004 0x00000009 0x0000000d 0x00000b5f
+                                0x00000000 0x00000003 0x00000003 0x00000006
+                                0x00000006 0x00000001 0x00000011 0x000000c8
+                                0x00000003 0x0000000e 0x00000007 0x0000000f
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0xe044048b
+                                0x007d8010 0x00000000 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000 >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 3b3ee7db99f3..252476867b54 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -26,6 +26,18 @@
                 status = "disable";
         };
 
+        i2s@70002800 {
+                status = "disable";
+        };
+
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        das@70000c00 {
+                status = "disable";
+        };
+
         serial@70006000 {
                 clock-frequency = < 216000000 >;
         };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index c7d3b87f29df..2dcff8728e90 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -12,6 +12,20 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
+                };
         };
 
         i2c@7000c400 {
@@ -26,6 +40,34 @@
                 clock-frequency = <400000>;
         };
 
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-ventana",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Ventana";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+        };
+
         serial@70006000 {
                 status = "disable";
         };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3da7afd45322..d2bc7e7ad06d 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,11 @@
         compatible = "nvidia,tegra20";
         interrupt-parent = <&intc>;
 
+        pmc@7000f400 {
+                compatible = "nvidia,tegra20-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+
         intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -12,6 +17,33 @@
                       < 0x50040100 0x0100 >;
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 56 0x04
+                              0 57 0x04>;
+        };
+
+        apbdma: dma@6000a000 {
+                compatible = "nvidia,tegra20-apbdma";
+                reg = <0x6000a000 0x1200>;
+                interrupts = < 0 104 0x04
+                               0 105 0x04
+                               0 106 0x04
+                               0 107 0x04
+                               0 108 0x04
+                               0 109 0x04
+                               0 110 0x04
+                               0 111 0x04
+                               0 112 0x04
+                               0 113 0x04
+                               0 114 0x04
+                               0 115 0x04
+                               0 116 0x04
+                               0 117 0x04
+                               0 118 0x04
+                               0 119 0x04 >;
+        };
+
         i2c@7000c000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -44,18 +76,18 @@
                 interrupts = < 0 53 0x04 >;
         };
 
-        i2s@70002800 {
+        tegra_i2s1: i2s@70002800 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
                 interrupts = < 0 13 0x04 >;
-                dma-channel = < 2 >;
+                nvidia,dma-request-selector = < &apbdma 2 >;
         };
 
-        i2s@70002a00 {
+        tegra_i2s2: i2s@70002a00 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
                 interrupts = < 0 3 0x04 >;
-                dma-channel = < 1 >;
+                nvidia,dma-request-selector = < &apbdma 1 >;
         };
 
         das@70000c00 {
@@ -120,6 +152,13 @@
                 interrupts = < 0 91 0x04 >;
         };
 
+        emc@7000f400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-emc";
+                reg = <0x7000f400 0x200>;
+        };
+
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ee7db9892e02..e957051f8645 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,11 @@
         compatible = "nvidia,tegra30";
         interrupt-parent = <&intc>;
 
+        pmc@7000f400 {
+                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+
         intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -12,6 +17,51 @@
                       < 0x50040100 0x0100 >;
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 144 0x04
+                              0 145 0x04
+                              0 146 0x04
+                              0 147 0x04>;
+        };
+
+        apbdma: dma@6000a000 {
+                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+                reg = <0x6000a000 0x1400>;
+                interrupts = < 0 104 0x04
+                               0 105 0x04
+                               0 106 0x04
+                               0 107 0x04
+                               0 108 0x04
+                               0 109 0x04
+                               0 110 0x04
+                               0 111 0x04
+                               0 112 0x04
+                               0 113 0x04
+                               0 114 0x04
+                               0 115 0x04
+                               0 116 0x04
+                               0 117 0x04
+                               0 118 0x04
+                               0 119 0x04
+                               0 128 0x04
+                               0 129 0x04
+                               0 130 0x04
+                               0 131 0x04
+                               0 132 0x04
+                               0 133 0x04
+                               0 134 0x04
+                               0 135 0x04
+                               0 136 0x04
+                               0 137 0x04
+                               0 138 0x04
+                               0 139 0x04
+                               0 140 0x04
+                               0 141 0x04
+                               0 142 0x04
+                               0 143 0x04 >;
+        };
+
         i2c@7000c000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -55,7 +105,14 @@
         gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
                 reg = < 0x6000d000 0x1000 >;
-                interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
+                interrupts = < 0 32 0x04
+                               0 33 0x04
+                               0 34 0x04
+                               0 35 0x04
+                               0 55 0x04
+                               0 87 0x04
+                               0 89 0x04
+                               0 125 0x04 >;
                 #gpio-cells = <2>;
                 gpio-controller;
         };