Merge tag 'arc-v3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC fixes from Vineet Gupta:

 - Fallouts/wreckage of Cache Flush optimizations / aliasing dcache
   support

 - Fix for an interesting bug where piped input to grep was getting
   mysteriously clobbered

* tag 'arc-v3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: lazy dcache flush broke gdb in non-aliasing configs
  ARC: Use enough bits for determining page's cache color
  ARC: Brown paper bag bug in macro for checking cache color
  ARC: copy_(to|from)_user() to honor usermode-access permissions
  ARC: [mm] Prevent stray dcache lines after__sync_icache_dcach()
  ARC: [TB10x] Remove redundant abilis,simple-pinctrl mechanism

11 files changed, 41 insertions, 70 deletions

diff --git a/arch/arc/boot/dts/abilis_tb100_dvk.dts b/arch/arc/boot/dts/abilis_tb100_dvk.dts
index c0fd3623c393..0fa0d4abe795 100644
--- a/arch/arc/boot/dts/abilis_tb100_dvk.dts
+++ b/arch/arc/boot/dts/abilis_tb100_dvk.dts
@@ -37,7 +37,7 @@
 
         soc100 {
                 uart@FF100000 {
-                        pinctrl-names = "abilis,simple-default";
+                        pinctrl-names = "default";
                         pinctrl-0 = <&pctl_uart0>;
                 };
                 ethernet@FE100000 {
diff --git a/arch/arc/boot/dts/abilis_tb101_dvk.dts b/arch/arc/boot/dts/abilis_tb101_dvk.dts
index 6f8c381f6268..a4d80ce283ae 100644
--- a/arch/arc/boot/dts/abilis_tb101_dvk.dts
+++ b/arch/arc/boot/dts/abilis_tb101_dvk.dts
@@ -37,7 +37,7 @@
 
         soc100 {
                 uart@FF100000 {
-                        pinctrl-names = "abilis,simple-default";
+                        pinctrl-names = "default";
                         pinctrl-0 = <&pctl_uart0>;
                 };
                 ethernet@FE100000 {
diff --git a/arch/arc/boot/dts/abilis_tb10x.dtsi b/arch/arc/boot/dts/abilis_tb10x.dtsi
index a6139fc5aaa3..b97e3051ba4b 100644
--- a/arch/arc/boot/dts/abilis_tb10x.dtsi
+++ b/arch/arc/boot/dts/abilis_tb10x.dtsi
@@ -88,8 +88,7 @@
                 };
 
                 uart@FF100000 {
-                        compatible = "snps,dw-apb-uart",
-                                        "abilis,simple-pinctrl";
+                        compatible = "snps,dw-apb-uart";
                         reg = <0xFF100000 0x100>;
                         clock-frequency = <166666666>;
                         interrupts = <25 1>;
@@ -184,8 +183,7 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         cell-index = <1>;
-                        compatible = "abilis,tb100-spi",
-                                        "abilis,simple-pinctrl";
+                        compatible = "abilis,tb100-spi";
                         num-cs = <2>;
                         reg = <0xFE011000 0x20>;
                         interrupt-parent = <&tb10x_ictl>;
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index 9f841af41092..ef62682e8d95 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -93,14 +93,16 @@ static inline int cache_is_vipt_aliasing(void)
 #endif
 }
 
-#define CACHE_COLOR(addr)       (((unsigned long)(addr) >> (PAGE_SHIFT)) & 3)
+#define CACHE_COLOR(addr)       (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)
 
 /*
  * checks if two addresses (after page aligning) index into same cache set
  */
 #define addr_not_cache_congruent(addr1, addr2)                          \
+({                                                                      \
         cache_is_vipt_aliasing() ?                                      \
-                (CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0          \
+                (CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0;         \
+})
 
 #define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
 do {                                                                    \
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 374a35514116..ab84bf131fe1 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -19,13 +19,6 @@
 #define clear_page(paddr)               memset((paddr), 0, PAGE_SIZE)
 #define copy_page(to, from)             memcpy((to), (from), PAGE_SIZE)
 
-#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
-
-#define clear_user_page(addr, vaddr, pg)        clear_page(addr)
-#define copy_user_page(vto, vfrom, vaddr, pg)   copy_page(vto, vfrom)
-
-#else   /* VIPT aliasing dcache */
-
 struct vm_area_struct;
 struct page;
 
@@ -35,8 +28,6 @@ void copy_user_highpage(struct page *to, struct page *from,
                         unsigned long u_vaddr, struct vm_area_struct *vma);
 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page);
 
-#endif  /* CONFIG_ARC_CACHE_VIPT_ALIASING */
-
 #undef STRICT_MM_TYPECHECKS
 
 #ifdef STRICT_MM_TYPECHECKS
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 1cc4720faccb..95b1522212a7 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -57,9 +57,9 @@
 
 #define _PAGE_ACCESSED      (1<<1)      /* Page is accessed (S) */
 #define _PAGE_CACHEABLE     (1<<2)      /* Page is cached (H) */
-#define _PAGE_EXECUTE       (1<<3)      /* Page has user execute perm (H) */
-#define _PAGE_WRITE         (1<<4)      /* Page has user write perm (H) */
-#define _PAGE_READ          (1<<5)      /* Page has user read perm (H) */
+#define _PAGE_U_EXECUTE     (1<<3)      /* Page has user execute perm (H) */
+#define _PAGE_U_WRITE       (1<<4)      /* Page has user write perm (H) */
+#define _PAGE_U_READ        (1<<5)      /* Page has user read perm (H) */
 #define _PAGE_K_EXECUTE     (1<<6)      /* Page has kernel execute perm (H) */
 #define _PAGE_K_WRITE       (1<<7)      /* Page has kernel write perm (H) */
 #define _PAGE_K_READ        (1<<8)      /* Page has kernel perm (H) */
@@ -72,9 +72,9 @@
 
 /* PD1 */
 #define _PAGE_CACHEABLE     (1<<0)      /* Page is cached (H) */
-#define _PAGE_EXECUTE       (1<<1)      /* Page has user execute perm (H) */
-#define _PAGE_WRITE         (1<<2)      /* Page has user write perm (H) */
-#define _PAGE_READ          (1<<3)      /* Page has user read perm (H) */
+#define _PAGE_U_EXECUTE     (1<<1)      /* Page has user execute perm (H) */
+#define _PAGE_U_WRITE       (1<<2)      /* Page has user write perm (H) */
+#define _PAGE_U_READ        (1<<3)      /* Page has user read perm (H) */
 #define _PAGE_K_EXECUTE     (1<<4)      /* Page has kernel execute perm (H) */
 #define _PAGE_K_WRITE       (1<<5)      /* Page has kernel write perm (H) */
 #define _PAGE_K_READ        (1<<6)      /* Page has kernel perm (H) */
@@ -93,7 +93,8 @@
 #endif
 
 /* Kernel allowed all permissions for all pages */
-#define _K_PAGE_PERMS  (_PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
+#define _K_PAGE_PERMS  (_PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ | \
+                        _PAGE_GLOBAL | _PAGE_PRESENT)
 
 #ifdef CONFIG_ARC_CACHE_PAGES
 #define _PAGE_DEF_CACHEABLE _PAGE_CACHEABLE
@@ -106,7 +107,11 @@
  * -by default cached, unless config otherwise
  * -present in memory
  */
-#define ___DEF (_PAGE_PRESENT | _K_PAGE_PERMS | _PAGE_DEF_CACHEABLE)
+#define ___DEF (_PAGE_PRESENT | _PAGE_DEF_CACHEABLE)
+
+#define _PAGE_READ      (_PAGE_U_READ    | _PAGE_K_READ)
+#define _PAGE_WRITE     (_PAGE_U_WRITE   | _PAGE_K_WRITE)
+#define _PAGE_EXECUTE   (_PAGE_U_EXECUTE | _PAGE_K_EXECUTE)
 
 /* Set of bits not changed in pte_modify */
 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
@@ -125,11 +130,10 @@
  * kernel vaddr space - visible in all addr spaces, but kernel mode only
  * Thus Global, all-kernel-access, no-user-access, cached
  */
-#define PAGE_KERNEL          __pgprot(___DEF | _PAGE_GLOBAL)
+#define PAGE_KERNEL          __pgprot(_K_PAGE_PERMS | _PAGE_DEF_CACHEABLE)
 
 /* ioremap */
-#define PAGE_KERNEL_NO_CACHE __pgprot(_PAGE_PRESENT | _K_PAGE_PERMS | \
-                                                     _PAGE_GLOBAL)
+#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
 
 /**************************************************************************
  * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
diff --git a/arch/arc/include/asm/tlb.h b/arch/arc/include/asm/tlb.h
index 85b6df839bd7..cb0c708ca665 100644
--- a/arch/arc/include/asm/tlb.h
+++ b/arch/arc/include/asm/tlb.h
@@ -16,7 +16,7 @@
 /* Masks for actual TLB "PD"s */
 #define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
 #define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \
-                         _PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ | \
+                         _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
                          _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
 
 #ifndef __ASSEMBLY__
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 2f12bca8aef3..aedce1905441 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -610,7 +610,7 @@ void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
 
         local_irq_save(flags);
         __ic_line_inv_vaddr(paddr, vaddr, len);
-        __dc_line_op(paddr, vaddr, len, OP_FLUSH);
+        __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
         local_irq_restore(flags);
 }
 
@@ -676,6 +676,17 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
         flush_cache_all();
 }
 
+void flush_anon_page(struct vm_area_struct *vma, struct page *page,
+                     unsigned long u_vaddr)
+{
+        /* TBD: do we really need to clear the kernel mapping */
+        __flush_dcache_page(page_address(page), u_vaddr);
+        __flush_dcache_page(page_address(page), page_address(page));
+
+}
+
+#endif
+
 void copy_user_highpage(struct page *to, struct page *from,
         unsigned long u_vaddr, struct vm_area_struct *vma)
 {
@@ -725,16 +736,6 @@ void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
         set_bit(PG_arch_1, &page->flags);
 }
 
-void flush_anon_page(struct vm_area_struct *vma, struct page *page,
-                     unsigned long u_vaddr)
-{
-        /* TBD: do we really need to clear the kernel mapping */
-        __flush_dcache_page(page_address(page), u_vaddr);
-        __flush_dcache_page(page_address(page), page_address(page));
-
-}
-
-#endif
 
 /**********************************************************************
  * Explicit Cache flush request from user space via syscall
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 066145b5f348..fe1c5a073afe 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -444,7 +444,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
          *             so userspace sees the right data.
          *  (Avoids the flush for Non-exec + congruent mapping case)
          */
-        if (vma->vm_flags & VM_EXEC || addr_not_cache_congruent(paddr, vaddr)) {
+        if ((vma->vm_flags & VM_EXEC) ||
+             addr_not_cache_congruent(paddr, vaddr)) {
                 struct page *page = pfn_to_page(pte_pfn(*ptep));
 
                 int dirty = test_and_clear_bit(PG_arch_1, &page->flags);
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 9df765dc7c3a..3357d26ffe54 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -277,7 +277,7 @@ ARC_ENTRY EV_TLBMissI
         ;----------------------------------------------------------------
         ; VERIFY_PTE: Check if PTE permissions approp for executing code
         cmp_s   r2, VMALLOC_START
-        mov.lo  r2, (_PAGE_PRESENT | _PAGE_READ | _PAGE_EXECUTE)
+        mov.lo  r2, (_PAGE_PRESENT | _PAGE_U_READ | _PAGE_U_EXECUTE)
         mov.hs  r2, (_PAGE_PRESENT | _PAGE_K_READ | _PAGE_K_EXECUTE)
 
         and     r3, r0, r2  ; Mask out NON Flag bits from PTE
@@ -320,9 +320,9 @@ ARC_ENTRY EV_TLBMissD
         mov_s   r2, 0
         lr      r3, [ecr]
         btst_s  r3, ECR_C_BIT_DTLB_LD_MISS      ; Read Access
-        or.nz   r2, r2, _PAGE_READ              ; chk for Read flag in PTE
+        or.nz   r2, r2, _PAGE_U_READ            ; chk for Read flag in PTE
         btst_s  r3, ECR_C_BIT_DTLB_ST_MISS      ; Write Access
-        or.nz   r2, r2, _PAGE_WRITE             ; chk for Write flag in PTE
+        or.nz   r2, r2, _PAGE_U_WRITE           ; chk for Write flag in PTE
         ; Above laddering takes care of XCHG access
         ;   which is both Read and Write
 
diff --git a/arch/arc/plat-tb10x/tb10x.c b/arch/arc/plat-tb10x/tb10x.c
index d3567691c7e1..06cb30929460 100644
--- a/arch/arc/plat-tb10x/tb10x.c
+++ b/arch/arc/plat-tb10x/tb10x.c
@@ -34,31 +34,6 @@ static void __init tb10x_platform_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static void __init tb10x_platform_late_init(void)
-{
-        struct device_node *dn;
-
-        /*
-         * Pinctrl documentation recommends setting up the iomux here for
-         * all modules which don't require control over the pins themselves.
-         * Modules which need this kind of assistance are compatible with
-         * "abilis,simple-pinctrl", i.e. we can easily iterate over them.
-         * TODO: Does this recommended method work cleanly with pins required
-         * by modules?
-         */
-        for_each_compatible_node(dn, NULL, "abilis,simple-pinctrl") {
-                struct platform_device *pd = of_find_device_by_node(dn);
-                struct pinctrl *pctl;
-
-                pctl = pinctrl_get_select(&pd->dev, "abilis,simple-default");
-                if (IS_ERR(pctl)) {
-                        int ret = PTR_ERR(pctl);
-                        dev_err(&pd->dev, "Could not set up pinctrl: %d\n",
-                                ret);
-                }
-        }
-}
-
 static const char *tb10x_compat[] __initdata = {
         "abilis,arc-tb10x",
         NULL,
@@ -67,5 +42,4 @@ static const char *tb10x_compat[] __initdata = {
 MACHINE_START(TB10x, "tb10x")
         .dt_compat      = tb10x_compat,
         .init_machine   = tb10x_platform_init,
-        .init_late      = tb10x_platform_late_init,
 MACHINE_END