diff options
author | Shawn Guo <shawn.guo@linaro.org> | 2013-05-02 23:06:46 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2013-06-17 03:45:11 -0400 |
commit | 45fe6810347b0a83561a13d9ee656c899a309fc0 (patch) | |
tree | 814f2fa01f53482a3063484943ac7f3dbbe0e7de | |
parent | c1e31d126b4db6a3a8d96883fae40fe22d5eba65 (diff) |
ARM: imx: add clock support for imx6sl
Add clock support for i.MX6 SoloLite. It uses the dtc marco support to
define all clock IDs in imx6sl-clock.h, which will be included by both
clock driver and device tree sources, so that the data will stay sync
all the time between kernel and DT.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r-- | Documentation/devicetree/bindings/clock/imx6sl-clock.txt | 10 | ||||
-rw-r--r-- | arch/arm/mach-imx/clk-imx6sl.c | 270 | ||||
-rw-r--r-- | include/dt-bindings/clock/imx6sl-clock.h | 148 |
3 files changed, 428 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt new file mode 100644 index 000000000000..15e40bdf147d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt | |||
@@ -0,0 +1,10 @@ | |||
1 | * Clock bindings for Freescale i.MX6 SoloLite | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,imx6sl-ccm" | ||
5 | - reg: Address and length of the register set | ||
6 | - #clock-cells: Should be <1> | ||
7 | |||
8 | The clock consumer should specify the desired clock by having the clock | ||
9 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h | ||
10 | for the full list of i.MX6 SoloLite clock IDs. | ||
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c new file mode 100644 index 000000000000..76835a731db2 --- /dev/null +++ b/arch/arm/mach-imx/clk-imx6sl.c | |||
@@ -0,0 +1,270 @@ | |||
1 | /* | ||
2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | #include <linux/clk.h> | ||
11 | #include <linux/clkdev.h> | ||
12 | #include <linux/err.h> | ||
13 | #include <linux/of.h> | ||
14 | #include <linux/of_address.h> | ||
15 | #include <linux/of_irq.h> | ||
16 | #include <dt-bindings/clock/imx6sl-clock.h> | ||
17 | |||
18 | #include "clk.h" | ||
19 | #include "common.h" | ||
20 | |||
21 | static const char const *step_sels[] = { "osc", "pll2_pfd2", }; | ||
22 | static const char const *pll1_sw_sels[] = { "pll1_sys", "step", }; | ||
23 | static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; | ||
24 | static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", }; | ||
25 | static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; | ||
26 | static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; | ||
27 | static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; | ||
28 | static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; | ||
29 | static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; | ||
30 | static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; | ||
31 | static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; | ||
32 | static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", }; | ||
33 | static const char const *perclk_sels[] = { "ipg", "osc", }; | ||
34 | static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; | ||
35 | static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; | ||
36 | static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; | ||
37 | static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; | ||
38 | static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; | ||
39 | static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; | ||
40 | static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; | ||
41 | static const char const *uart_sels[] = { "pll3_80m", "osc", }; | ||
42 | |||
43 | static struct clk_div_table clk_enet_ref_table[] = { | ||
44 | { .val = 0, .div = 20, }, | ||
45 | { .val = 1, .div = 10, }, | ||
46 | { .val = 2, .div = 5, }, | ||
47 | { .val = 3, .div = 4, }, | ||
48 | { } | ||
49 | }; | ||
50 | |||
51 | static struct clk_div_table post_div_table[] = { | ||
52 | { .val = 2, .div = 1, }, | ||
53 | { .val = 1, .div = 2, }, | ||
54 | { .val = 0, .div = 4, }, | ||
55 | { } | ||
56 | }; | ||
57 | |||
58 | static struct clk_div_table video_div_table[] = { | ||
59 | { .val = 0, .div = 1, }, | ||
60 | { .val = 1, .div = 2, }, | ||
61 | { .val = 2, .div = 1, }, | ||
62 | { .val = 3, .div = 4, }, | ||
63 | { } | ||
64 | }; | ||
65 | |||
66 | static struct clk *clks[IMX6SL_CLK_CLK_END]; | ||
67 | static struct clk_onecell_data clk_data; | ||
68 | |||
69 | int __init imx6sl_clocks_init(void) | ||
70 | { | ||
71 | struct device_node *np; | ||
72 | void __iomem *base; | ||
73 | int irq; | ||
74 | int i; | ||
75 | |||
76 | of_clk_init(NULL); | ||
77 | |||
78 | clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); | ||
79 | clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); | ||
80 | clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); | ||
81 | |||
82 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); | ||
83 | base = of_iomap(np, 0); | ||
84 | WARN_ON(!base); | ||
85 | |||
86 | /* type name parent base div_mask */ | ||
87 | clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); | ||
88 | clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); | ||
89 | clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); | ||
90 | clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); | ||
91 | clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); | ||
92 | clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); | ||
93 | clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); | ||
94 | |||
95 | /* | ||
96 | * usbphy1 and usbphy2 are implemented as dummy gates using reserve | ||
97 | * bit 20. They are used by phy driver to keep the refcount of | ||
98 | * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be | ||
99 | * turned on during boot, and software will not need to control it | ||
100 | * anymore after that. | ||
101 | */ | ||
102 | clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); | ||
103 | clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | ||
104 | clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); | ||
105 | clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); | ||
106 | |||
107 | /* dev name parent_name flags reg shift width div: flags, div_table lock */ | ||
108 | clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); | ||
109 | clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); | ||
110 | clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | ||
111 | clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); | ||
112 | |||
113 | /* name parent_name reg idx */ | ||
114 | clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); | ||
115 | clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); | ||
116 | clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); | ||
117 | clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); | ||
118 | clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); | ||
119 | clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); | ||
120 | clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); | ||
121 | |||
122 | /* name parent_name mult div */ | ||
123 | clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2); | ||
124 | clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | ||
125 | clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | ||
126 | clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | ||
127 | |||
128 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ccm"); | ||
129 | base = of_iomap(np, 0); | ||
130 | WARN_ON(!base); | ||
131 | |||
132 | /* name reg shift width parent_names num_parents */ | ||
133 | clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | ||
134 | clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | ||
135 | clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); | ||
136 | clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); | ||
137 | clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); | ||
138 | clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); | ||
139 | clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); | ||
140 | clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | ||
141 | clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); | ||
142 | clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); | ||
143 | clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | ||
144 | clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | ||
145 | clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | ||
146 | clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | ||
147 | clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | ||
148 | clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | ||
149 | clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | ||
150 | clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); | ||
151 | clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); | ||
152 | clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); | ||
153 | clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); | ||
154 | clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); | ||
155 | clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); | ||
156 | clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); | ||
157 | clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | ||
158 | clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | ||
159 | clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | ||
160 | clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); | ||
161 | clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); | ||
162 | |||
163 | /* name reg shift width busy: reg, shift parent_names num_parents */ | ||
164 | clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | ||
165 | clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | ||
166 | |||
167 | /* name parent_name reg shift width */ | ||
168 | clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); | ||
169 | clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); | ||
170 | clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); | ||
171 | clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | ||
172 | clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); | ||
173 | clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); | ||
174 | clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); | ||
175 | clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | ||
176 | clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | ||
177 | clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | ||
178 | clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | ||
179 | clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | ||
180 | clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | ||
181 | clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | ||
182 | clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | ||
183 | clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | ||
184 | clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); | ||
185 | clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); | ||
186 | clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); | ||
187 | clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); | ||
188 | clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); | ||
189 | clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); | ||
190 | clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); | ||
191 | clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3); | ||
192 | clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); | ||
193 | clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); | ||
194 | clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); | ||
195 | clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); | ||
196 | clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); | ||
197 | clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); | ||
198 | clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); | ||
199 | clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); | ||
200 | clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6); | ||
201 | |||
202 | /* name parent_name reg shift width busy: reg, shift */ | ||
203 | clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | ||
204 | clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); | ||
205 | clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); | ||
206 | |||
207 | /* name parent_name reg shift */ | ||
208 | clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | ||
209 | clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | ||
210 | clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | ||
211 | clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | ||
212 | clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); | ||
213 | clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); | ||
214 | clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); | ||
215 | clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20); | ||
216 | clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); | ||
217 | clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); | ||
218 | clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); | ||
219 | clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); | ||
220 | clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); | ||
221 | clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); | ||
222 | clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0); | ||
223 | clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); | ||
224 | clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); | ||
225 | clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); | ||
226 | clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); | ||
227 | clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); | ||
228 | clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); | ||
229 | clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); | ||
230 | clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); | ||
231 | clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); | ||
232 | clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); | ||
233 | clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); | ||
234 | clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); | ||
235 | clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); | ||
236 | clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); | ||
237 | clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); | ||
238 | clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); | ||
239 | clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); | ||
240 | clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); | ||
241 | clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | ||
242 | clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | ||
243 | clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | ||
244 | clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | ||
245 | |||
246 | for (i = 0; i < ARRAY_SIZE(clks); i++) | ||
247 | if (IS_ERR(clks[i])) | ||
248 | pr_err("i.MX6SL clk %d: register failed with %ld\n", | ||
249 | i, PTR_ERR(clks[i])); | ||
250 | |||
251 | clk_data.clks = clks; | ||
252 | clk_data.clk_num = ARRAY_SIZE(clks); | ||
253 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | ||
254 | |||
255 | clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0"); | ||
256 | clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); | ||
257 | |||
258 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { | ||
259 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); | ||
260 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); | ||
261 | } | ||
262 | |||
263 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); | ||
264 | base = of_iomap(np, 0); | ||
265 | WARN_ON(!base); | ||
266 | irq = irq_of_parse_and_map(np, 0); | ||
267 | mxc_timer_init(base, irq); | ||
268 | |||
269 | return 0; | ||
270 | } | ||
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h new file mode 100644 index 000000000000..7fcdf90879f2 --- /dev/null +++ b/include/dt-bindings/clock/imx6sl-clock.h | |||
@@ -0,0 +1,148 @@ | |||
1 | /* | ||
2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | * | ||
8 | */ | ||
9 | |||
10 | #ifndef __DT_BINDINGS_CLOCK_IMX6SL_H | ||
11 | #define __DT_BINDINGS_CLOCK_IMX6SL_H | ||
12 | |||
13 | #define IMX6SL_CLK_DUMMY 0 | ||
14 | #define IMX6SL_CLK_CKIL 1 | ||
15 | #define IMX6SL_CLK_OSC 2 | ||
16 | #define IMX6SL_CLK_PLL1_SYS 3 | ||
17 | #define IMX6SL_CLK_PLL2_BUS 4 | ||
18 | #define IMX6SL_CLK_PLL3_USB_OTG 5 | ||
19 | #define IMX6SL_CLK_PLL4_AUDIO 6 | ||
20 | #define IMX6SL_CLK_PLL5_VIDEO 7 | ||
21 | #define IMX6SL_CLK_PLL6_ENET 8 | ||
22 | #define IMX6SL_CLK_PLL7_USB_HOST 9 | ||
23 | #define IMX6SL_CLK_USBPHY1 10 | ||
24 | #define IMX6SL_CLK_USBPHY2 11 | ||
25 | #define IMX6SL_CLK_USBPHY1_GATE 12 | ||
26 | #define IMX6SL_CLK_USBPHY2_GATE 13 | ||
27 | #define IMX6SL_CLK_PLL4_POST_DIV 14 | ||
28 | #define IMX6SL_CLK_PLL5_POST_DIV 15 | ||
29 | #define IMX6SL_CLK_PLL5_VIDEO_DIV 16 | ||
30 | #define IMX6SL_CLK_ENET_REF 17 | ||
31 | #define IMX6SL_CLK_PLL2_PFD0 18 | ||
32 | #define IMX6SL_CLK_PLL2_PFD1 19 | ||
33 | #define IMX6SL_CLK_PLL2_PFD2 20 | ||
34 | #define IMX6SL_CLK_PLL3_PFD0 21 | ||
35 | #define IMX6SL_CLK_PLL3_PFD1 22 | ||
36 | #define IMX6SL_CLK_PLL3_PFD2 23 | ||
37 | #define IMX6SL_CLK_PLL3_PFD3 24 | ||
38 | #define IMX6SL_CLK_PLL2_198M 25 | ||
39 | #define IMX6SL_CLK_PLL3_120M 26 | ||
40 | #define IMX6SL_CLK_PLL3_80M 27 | ||
41 | #define IMX6SL_CLK_PLL3_60M 28 | ||
42 | #define IMX6SL_CLK_STEP 29 | ||
43 | #define IMX6SL_CLK_PLL1_SW 30 | ||
44 | #define IMX6SL_CLK_OCRAM_ALT_SEL 31 | ||
45 | #define IMX6SL_CLK_OCRAM_SEL 32 | ||
46 | #define IMX6SL_CLK_PRE_PERIPH2_SEL 33 | ||
47 | #define IMX6SL_CLK_PRE_PERIPH_SEL 34 | ||
48 | #define IMX6SL_CLK_PERIPH2_CLK2_SEL 35 | ||
49 | #define IMX6SL_CLK_PERIPH_CLK2_SEL 36 | ||
50 | #define IMX6SL_CLK_CSI_SEL 37 | ||
51 | #define IMX6SL_CLK_LCDIF_AXI_SEL 38 | ||
52 | #define IMX6SL_CLK_USDHC1_SEL 39 | ||
53 | #define IMX6SL_CLK_USDHC2_SEL 40 | ||
54 | #define IMX6SL_CLK_USDHC3_SEL 41 | ||
55 | #define IMX6SL_CLK_USDHC4_SEL 42 | ||
56 | #define IMX6SL_CLK_SSI1_SEL 43 | ||
57 | #define IMX6SL_CLK_SSI2_SEL 44 | ||
58 | #define IMX6SL_CLK_SSI3_SEL 45 | ||
59 | #define IMX6SL_CLK_PERCLK_SEL 46 | ||
60 | #define IMX6SL_CLK_PXP_AXI_SEL 47 | ||
61 | #define IMX6SL_CLK_EPDC_AXI_SEL 48 | ||
62 | #define IMX6SL_CLK_GPU2D_OVG_SEL 49 | ||
63 | #define IMX6SL_CLK_GPU2D_SEL 50 | ||
64 | #define IMX6SL_CLK_LCDIF_PIX_SEL 51 | ||
65 | #define IMX6SL_CLK_EPDC_PIX_SEL 52 | ||
66 | #define IMX6SL_CLK_SPDIF0_SEL 53 | ||
67 | #define IMX6SL_CLK_SPDIF1_SEL 54 | ||
68 | #define IMX6SL_CLK_EXTERN_AUDIO_SEL 55 | ||
69 | #define IMX6SL_CLK_ECSPI_SEL 56 | ||
70 | #define IMX6SL_CLK_UART_SEL 57 | ||
71 | #define IMX6SL_CLK_PERIPH 58 | ||
72 | #define IMX6SL_CLK_PERIPH2 59 | ||
73 | #define IMX6SL_CLK_OCRAM_PODF 60 | ||
74 | #define IMX6SL_CLK_PERIPH_CLK2_PODF 61 | ||
75 | #define IMX6SL_CLK_PERIPH2_CLK2_PODF 62 | ||
76 | #define IMX6SL_CLK_IPG 63 | ||
77 | #define IMX6SL_CLK_CSI_PODF 64 | ||
78 | #define IMX6SL_CLK_LCDIF_AXI_PODF 65 | ||
79 | #define IMX6SL_CLK_USDHC1_PODF 66 | ||
80 | #define IMX6SL_CLK_USDHC2_PODF 67 | ||
81 | #define IMX6SL_CLK_USDHC3_PODF 68 | ||
82 | #define IMX6SL_CLK_USDHC4_PODF 69 | ||
83 | #define IMX6SL_CLK_SSI1_PRED 70 | ||
84 | #define IMX6SL_CLK_SSI1_PODF 71 | ||
85 | #define IMX6SL_CLK_SSI2_PRED 72 | ||
86 | #define IMX6SL_CLK_SSI2_PODF 73 | ||
87 | #define IMX6SL_CLK_SSI3_PRED 74 | ||
88 | #define IMX6SL_CLK_SSI3_PODF 75 | ||
89 | #define IMX6SL_CLK_PERCLK 76 | ||
90 | #define IMX6SL_CLK_PXP_AXI_PODF 77 | ||
91 | #define IMX6SL_CLK_EPDC_AXI_PODF 78 | ||
92 | #define IMX6SL_CLK_GPU2D_OVG_PODF 79 | ||
93 | #define IMX6SL_CLK_GPU2D_PODF 80 | ||
94 | #define IMX6SL_CLK_LCDIF_PIX_PRED 81 | ||
95 | #define IMX6SL_CLK_EPDC_PIX_PRED 82 | ||
96 | #define IMX6SL_CLK_LCDIF_PIX_PODF 83 | ||
97 | #define IMX6SL_CLK_EPDC_PIX_PODF 84 | ||
98 | #define IMX6SL_CLK_SPDIF0_PRED 85 | ||
99 | #define IMX6SL_CLK_SPDIF0_PODF 86 | ||
100 | #define IMX6SL_CLK_SPDIF1_PRED 87 | ||
101 | #define IMX6SL_CLK_SPDIF1_PODF 88 | ||
102 | #define IMX6SL_CLK_EXTERN_AUDIO_PRED 89 | ||
103 | #define IMX6SL_CLK_EXTERN_AUDIO_PODF 90 | ||
104 | #define IMX6SL_CLK_ECSPI_ROOT 91 | ||
105 | #define IMX6SL_CLK_UART_ROOT 92 | ||
106 | #define IMX6SL_CLK_AHB 93 | ||
107 | #define IMX6SL_CLK_MMDC_ROOT 94 | ||
108 | #define IMX6SL_CLK_ARM 95 | ||
109 | #define IMX6SL_CLK_ECSPI1 96 | ||
110 | #define IMX6SL_CLK_ECSPI2 97 | ||
111 | #define IMX6SL_CLK_ECSPI3 98 | ||
112 | #define IMX6SL_CLK_ECSPI4 99 | ||
113 | #define IMX6SL_CLK_EPIT1 100 | ||
114 | #define IMX6SL_CLK_EPIT2 101 | ||
115 | #define IMX6SL_CLK_EXTERN_AUDIO 102 | ||
116 | #define IMX6SL_CLK_GPT 103 | ||
117 | #define IMX6SL_CLK_GPT_SERIAL 104 | ||
118 | #define IMX6SL_CLK_GPU2D_OVG 105 | ||
119 | #define IMX6SL_CLK_I2C1 106 | ||
120 | #define IMX6SL_CLK_I2C2 107 | ||
121 | #define IMX6SL_CLK_I2C3 108 | ||
122 | #define IMX6SL_CLK_OCOTP 109 | ||
123 | #define IMX6SL_CLK_CSI 110 | ||
124 | #define IMX6SL_CLK_PXP_AXI 111 | ||
125 | #define IMX6SL_CLK_EPDC_AXI 112 | ||
126 | #define IMX6SL_CLK_LCDIF_AXI 113 | ||
127 | #define IMX6SL_CLK_LCDIF_PIX 114 | ||
128 | #define IMX6SL_CLK_EPDC_PIX 115 | ||
129 | #define IMX6SL_CLK_OCRAM 116 | ||
130 | #define IMX6SL_CLK_PWM1 117 | ||
131 | #define IMX6SL_CLK_PWM2 118 | ||
132 | #define IMX6SL_CLK_PWM3 119 | ||
133 | #define IMX6SL_CLK_PWM4 120 | ||
134 | #define IMX6SL_CLK_SDMA 121 | ||
135 | #define IMX6SL_CLK_SPDIF 122 | ||
136 | #define IMX6SL_CLK_SSI1 123 | ||
137 | #define IMX6SL_CLK_SSI2 124 | ||
138 | #define IMX6SL_CLK_SSI3 125 | ||
139 | #define IMX6SL_CLK_UART 126 | ||
140 | #define IMX6SL_CLK_UART_SERIAL 127 | ||
141 | #define IMX6SL_CLK_USBOH3 128 | ||
142 | #define IMX6SL_CLK_USDHC1 129 | ||
143 | #define IMX6SL_CLK_USDHC2 130 | ||
144 | #define IMX6SL_CLK_USDHC3 131 | ||
145 | #define IMX6SL_CLK_USDHC4 132 | ||
146 | #define IMX6SL_CLK_CLK_END 133 | ||
147 | |||
148 | #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ | ||