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authorBenoit Cousson <b-cousson@ti.com>2011-02-15 16:39:48 -0500
committerBenoit Cousson <b-cousson@ti.com>2011-02-17 12:25:37 -0500
commit407a6888f7362cb3dabe69ea6d9dcf3c750dc56a (patch)
tree7ad2a6e0fdb29a024883d3347b3ccce1c9ae5176
parent4ddff4932b31b8f21d1c57155ca5d4088693ce4b (diff)
OMAP4: hwmod data: Add AESS, McPDM, bandgap, counter_32k, MMC, KBD, ISS & IPU
Add more hwmod structures but keep them commented out for the moment until the driver adaptation to hwmod / omap_device is done. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c1009
1 files changed, 993 insertions, 16 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f108614f02f6..989bc9670436 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -40,11 +40,15 @@
40#define OMAP44XX_DMA_REQ_START 1 40#define OMAP44XX_DMA_REQ_START 1
41 41
42/* Backward references (IPs with Bus Master capability) */ 42/* Backward references (IPs with Bus Master capability) */
43static struct omap_hwmod omap44xx_aess_hwmod;
43static struct omap_hwmod omap44xx_dma_system_hwmod; 44static struct omap_hwmod omap44xx_dma_system_hwmod;
44static struct omap_hwmod omap44xx_dmm_hwmod; 45static struct omap_hwmod omap44xx_dmm_hwmod;
45static struct omap_hwmod omap44xx_dsp_hwmod; 46static struct omap_hwmod omap44xx_dsp_hwmod;
46static struct omap_hwmod omap44xx_dss_hwmod; 47static struct omap_hwmod omap44xx_dss_hwmod;
47static struct omap_hwmod omap44xx_emif_fw_hwmod; 48static struct omap_hwmod omap44xx_emif_fw_hwmod;
49static struct omap_hwmod omap44xx_hsi_hwmod;
50static struct omap_hwmod omap44xx_ipu_hwmod;
51static struct omap_hwmod omap44xx_iss_hwmod;
48static struct omap_hwmod omap44xx_iva_hwmod; 52static struct omap_hwmod omap44xx_iva_hwmod;
49static struct omap_hwmod omap44xx_l3_instr_hwmod; 53static struct omap_hwmod omap44xx_l3_instr_hwmod;
50static struct omap_hwmod omap44xx_l3_main_1_hwmod; 54static struct omap_hwmod omap44xx_l3_main_1_hwmod;
@@ -54,6 +58,8 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod;
54static struct omap_hwmod omap44xx_l4_cfg_hwmod; 58static struct omap_hwmod omap44xx_l4_cfg_hwmod;
55static struct omap_hwmod omap44xx_l4_per_hwmod; 59static struct omap_hwmod omap44xx_l4_per_hwmod;
56static struct omap_hwmod omap44xx_l4_wkup_hwmod; 60static struct omap_hwmod omap44xx_l4_wkup_hwmod;
61static struct omap_hwmod omap44xx_mmc1_hwmod;
62static struct omap_hwmod omap44xx_mmc2_hwmod;
57static struct omap_hwmod omap44xx_mpu_hwmod; 63static struct omap_hwmod omap44xx_mpu_hwmod;
58static struct omap_hwmod omap44xx_mpu_private_hwmod; 64static struct omap_hwmod omap44xx_mpu_private_hwmod;
59 65
@@ -238,6 +244,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
238 .user = OCP_USER_MPU | OCP_USER_SDMA, 244 .user = OCP_USER_MPU | OCP_USER_SDMA,
239}; 245};
240 246
247/* mmc1 -> l3_main_1 */
248static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
249 .master = &omap44xx_mmc1_hwmod,
250 .slave = &omap44xx_l3_main_1_hwmod,
251 .clk = "l3_div_ck",
252 .user = OCP_USER_MPU | OCP_USER_SDMA,
253};
254
255/* mmc2 -> l3_main_1 */
256static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
257 .master = &omap44xx_mmc2_hwmod,
258 .slave = &omap44xx_l3_main_1_hwmod,
259 .clk = "l3_div_ck",
260 .user = OCP_USER_MPU | OCP_USER_SDMA,
261};
262
241/* mpu -> l3_main_1 */ 263/* mpu -> l3_main_1 */
242static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 264static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
243 .master = &omap44xx_mpu_hwmod, 265 .master = &omap44xx_mpu_hwmod,
@@ -252,6 +274,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
252 &omap44xx_dss__l3_main_1, 274 &omap44xx_dss__l3_main_1,
253 &omap44xx_l3_main_2__l3_main_1, 275 &omap44xx_l3_main_2__l3_main_1,
254 &omap44xx_l4_cfg__l3_main_1, 276 &omap44xx_l4_cfg__l3_main_1,
277 &omap44xx_mmc1__l3_main_1,
278 &omap44xx_mmc2__l3_main_1,
255 &omap44xx_mpu__l3_main_1, 279 &omap44xx_mpu__l3_main_1,
256}; 280};
257 281
@@ -272,6 +296,30 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
272 .user = OCP_USER_MPU | OCP_USER_SDMA, 296 .user = OCP_USER_MPU | OCP_USER_SDMA,
273}; 297};
274 298
299/* hsi -> l3_main_2 */
300static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
301 .master = &omap44xx_hsi_hwmod,
302 .slave = &omap44xx_l3_main_2_hwmod,
303 .clk = "l3_div_ck",
304 .user = OCP_USER_MPU | OCP_USER_SDMA,
305};
306
307/* ipu -> l3_main_2 */
308static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
309 .master = &omap44xx_ipu_hwmod,
310 .slave = &omap44xx_l3_main_2_hwmod,
311 .clk = "l3_div_ck",
312 .user = OCP_USER_MPU | OCP_USER_SDMA,
313};
314
315/* iss -> l3_main_2 */
316static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
317 .master = &omap44xx_iss_hwmod,
318 .slave = &omap44xx_l3_main_2_hwmod,
319 .clk = "l3_div_ck",
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321};
322
275/* iva -> l3_main_2 */ 323/* iva -> l3_main_2 */
276static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { 324static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
277 .master = &omap44xx_iva_hwmod, 325 .master = &omap44xx_iva_hwmod,
@@ -299,6 +347,9 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
299/* l3_main_2 slave ports */ 347/* l3_main_2 slave ports */
300static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { 348static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
301 &omap44xx_dma_system__l3_main_2, 349 &omap44xx_dma_system__l3_main_2,
350 &omap44xx_hsi__l3_main_2,
351 &omap44xx_ipu__l3_main_2,
352 &omap44xx_iss__l3_main_2,
302 &omap44xx_iva__l3_main_2, 353 &omap44xx_iva__l3_main_2,
303 &omap44xx_l3_main_1__l3_main_2, 354 &omap44xx_l3_main_1__l3_main_2,
304 &omap44xx_l4_cfg__l3_main_2, 355 &omap44xx_l4_cfg__l3_main_2,
@@ -361,6 +412,14 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
361}; 412};
362 413
363/* l4_abe interface data */ 414/* l4_abe interface data */
415/* aess -> l4_abe */
416static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
417 .master = &omap44xx_aess_hwmod,
418 .slave = &omap44xx_l4_abe_hwmod,
419 .clk = "ocp_abe_iclk",
420 .user = OCP_USER_MPU | OCP_USER_SDMA,
421};
422
364/* dsp -> l4_abe */ 423/* dsp -> l4_abe */
365static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { 424static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
366 .master = &omap44xx_dsp_hwmod, 425 .master = &omap44xx_dsp_hwmod,
@@ -387,6 +446,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
387 446
388/* l4_abe slave ports */ 447/* l4_abe slave ports */
389static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { 448static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
449 &omap44xx_aess__l4_abe,
390 &omap44xx_dsp__l4_abe, 450 &omap44xx_dsp__l4_abe,
391 &omap44xx_l3_main_1__l4_abe, 451 &omap44xx_l3_main_1__l4_abe,
392 &omap44xx_mpu__l4_abe, 452 &omap44xx_mpu__l4_abe,
@@ -504,13 +564,10 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
504 * - They still need to be validated with the driver 564 * - They still need to be validated with the driver
505 * properly adapted to omap_hwmod / omap_device 565 * properly adapted to omap_hwmod / omap_device
506 * 566 *
507 * aess
508 * bandgap
509 * c2c 567 * c2c
510 * c2c_target_fw 568 * c2c_target_fw
511 * cm_core 569 * cm_core
512 * cm_core_aon 570 * cm_core_aon
513 * counter_32k
514 * ctrl_module_core 571 * ctrl_module_core
515 * ctrl_module_pad_core 572 * ctrl_module_pad_core
516 * ctrl_module_pad_wkup 573 * ctrl_module_pad_wkup
@@ -526,22 +583,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
526 * gpu 583 * gpu
527 * hdq1w 584 * hdq1w
528 * hsi 585 * hsi
529 * ipu
530 * iss
531 * kbd
532 * mcasp
533 * mcpdm
534 * mmc1
535 * mmc2
536 * mmc3
537 * mmc4
538 * mmc5
539 * mpu_c0
540 * mpu_c1
541 * ocmc_ram 586 * ocmc_ram
542 * ocp2scp_usb_phy 587 * ocp2scp_usb_phy
543 * ocp_wp_noc 588 * ocp_wp_noc
544 * prcm
545 * prcm_mpu 589 * prcm_mpu
546 * prm 590 * prm
547 * scrm 591 * scrm
@@ -557,6 +601,194 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
557 */ 601 */
558 602
559/* 603/*
604 * 'aess' class
605 * audio engine sub system
606 */
607
608static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
609 .rev_offs = 0x0000,
610 .sysc_offs = 0x0010,
611 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
613 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
614 .sysc_fields = &omap_hwmod_sysc_type2,
615};
616
617static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
618 .name = "aess",
619 .sysc = &omap44xx_aess_sysc,
620};
621
622/* aess */
623static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
624 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
625};
626
627static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
628 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
629 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
630 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
631 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
632 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
633 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
634 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
635 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
636};
637
638/* aess master ports */
639static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
640 &omap44xx_aess__l4_abe,
641};
642
643static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
644 {
645 .pa_start = 0x401f1000,
646 .pa_end = 0x401f13ff,
647 .flags = ADDR_TYPE_RT
648 },
649};
650
651/* l4_abe -> aess */
652static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
653 .master = &omap44xx_l4_abe_hwmod,
654 .slave = &omap44xx_aess_hwmod,
655 .clk = "ocp_abe_iclk",
656 .addr = omap44xx_aess_addrs,
657 .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
658 .user = OCP_USER_MPU,
659};
660
661static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
662 {
663 .pa_start = 0x490f1000,
664 .pa_end = 0x490f13ff,
665 .flags = ADDR_TYPE_RT
666 },
667};
668
669/* l4_abe -> aess (dma) */
670static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
671 .master = &omap44xx_l4_abe_hwmod,
672 .slave = &omap44xx_aess_hwmod,
673 .clk = "ocp_abe_iclk",
674 .addr = omap44xx_aess_dma_addrs,
675 .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
676 .user = OCP_USER_SDMA,
677};
678
679/* aess slave ports */
680static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
681 &omap44xx_l4_abe__aess,
682 &omap44xx_l4_abe__aess_dma,
683};
684
685static struct omap_hwmod omap44xx_aess_hwmod = {
686 .name = "aess",
687 .class = &omap44xx_aess_hwmod_class,
688 .mpu_irqs = omap44xx_aess_irqs,
689 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
690 .sdma_reqs = omap44xx_aess_sdma_reqs,
691 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
692 .main_clk = "aess_fck",
693 .prcm = {
694 .omap4 = {
695 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
696 },
697 },
698 .slaves = omap44xx_aess_slaves,
699 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
700 .masters = omap44xx_aess_masters,
701 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
702 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
703};
704
705/*
706 * 'bandgap' class
707 * bangap reference for ldo regulators
708 */
709
710static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
711 .name = "bandgap",
712};
713
714/* bandgap */
715static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
716 { .role = "fclk", .clk = "bandgap_fclk" },
717};
718
719static struct omap_hwmod omap44xx_bandgap_hwmod = {
720 .name = "bandgap",
721 .class = &omap44xx_bandgap_hwmod_class,
722 .prcm = {
723 .omap4 = {
724 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
725 },
726 },
727 .opt_clks = bandgap_opt_clks,
728 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
729 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
730};
731
732/*
733 * 'counter' class
734 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
735 */
736
737static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
738 .rev_offs = 0x0000,
739 .sysc_offs = 0x0004,
740 .sysc_flags = SYSC_HAS_SIDLEMODE,
741 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
742 SIDLE_SMART_WKUP),
743 .sysc_fields = &omap_hwmod_sysc_type1,
744};
745
746static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
747 .name = "counter",
748 .sysc = &omap44xx_counter_sysc,
749};
750
751/* counter_32k */
752static struct omap_hwmod omap44xx_counter_32k_hwmod;
753static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
754 {
755 .pa_start = 0x4a304000,
756 .pa_end = 0x4a30401f,
757 .flags = ADDR_TYPE_RT
758 },
759};
760
761/* l4_wkup -> counter_32k */
762static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
763 .master = &omap44xx_l4_wkup_hwmod,
764 .slave = &omap44xx_counter_32k_hwmod,
765 .clk = "l4_wkup_clk_mux_ck",
766 .addr = omap44xx_counter_32k_addrs,
767 .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
768 .user = OCP_USER_MPU | OCP_USER_SDMA,
769};
770
771/* counter_32k slave ports */
772static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
773 &omap44xx_l4_wkup__counter_32k,
774};
775
776static struct omap_hwmod omap44xx_counter_32k_hwmod = {
777 .name = "counter_32k",
778 .class = &omap44xx_counter_hwmod_class,
779 .flags = HWMOD_SWSUP_SIDLE,
780 .main_clk = "sys_32k_ck",
781 .prcm = {
782 .omap4 = {
783 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
784 },
785 },
786 .slaves = omap44xx_counter_32k_slaves,
787 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
788 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
789};
790
791/*
560 * 'dma' class 792 * 'dma' class
561 * dma controller for data exchange between memory to memory (i.e. internal or 793 * dma controller for data exchange between memory to memory (i.e. internal or
562 * external memory) and gp peripherals to memory or memory to gp peripherals 794 * external memory) and gp peripherals to memory or memory to gp peripherals
@@ -1748,6 +1980,83 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
1748}; 1980};
1749 1981
1750/* 1982/*
1983 * 'hsi' class
1984 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1985 * serial if)
1986 */
1987
1988static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1989 .rev_offs = 0x0000,
1990 .sysc_offs = 0x0010,
1991 .syss_offs = 0x0014,
1992 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1993 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1994 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1995 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1996 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1997 MSTANDBY_SMART),
1998 .sysc_fields = &omap_hwmod_sysc_type1,
1999};
2000
2001static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2002 .name = "hsi",
2003 .sysc = &omap44xx_hsi_sysc,
2004};
2005
2006/* hsi */
2007static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2008 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2009 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2010 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2011};
2012
2013/* hsi master ports */
2014static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2015 &omap44xx_hsi__l3_main_2,
2016};
2017
2018static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2019 {
2020 .pa_start = 0x4a058000,
2021 .pa_end = 0x4a05bfff,
2022 .flags = ADDR_TYPE_RT
2023 },
2024};
2025
2026/* l4_cfg -> hsi */
2027static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2028 .master = &omap44xx_l4_cfg_hwmod,
2029 .slave = &omap44xx_hsi_hwmod,
2030 .clk = "l4_div_ck",
2031 .addr = omap44xx_hsi_addrs,
2032 .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
2033 .user = OCP_USER_MPU | OCP_USER_SDMA,
2034};
2035
2036/* hsi slave ports */
2037static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2038 &omap44xx_l4_cfg__hsi,
2039};
2040
2041static struct omap_hwmod omap44xx_hsi_hwmod = {
2042 .name = "hsi",
2043 .class = &omap44xx_hsi_hwmod_class,
2044 .mpu_irqs = omap44xx_hsi_irqs,
2045 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
2046 .main_clk = "hsi_fck",
2047 .prcm = {
2048 .omap4 = {
2049 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2050 },
2051 },
2052 .slaves = omap44xx_hsi_slaves,
2053 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2054 .masters = omap44xx_hsi_masters,
2055 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2056 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2057};
2058
2059/*
1751 * 'i2c' class 2060 * 'i2c' class
1752 * multimaster high-speed i2c controller 2061 * multimaster high-speed i2c controller
1753 */ 2062 */
@@ -1981,6 +2290,188 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
1981}; 2290};
1982 2291
1983/* 2292/*
2293 * 'ipu' class
2294 * imaging processor unit
2295 */
2296
2297static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2298 .name = "ipu",
2299};
2300
2301/* ipu */
2302static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2303 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2304};
2305
2306static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2307 { .name = "cpu0", .rst_shift = 0 },
2308};
2309
2310static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2311 { .name = "cpu1", .rst_shift = 1 },
2312};
2313
2314static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2315 { .name = "mmu_cache", .rst_shift = 2 },
2316};
2317
2318/* ipu master ports */
2319static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2320 &omap44xx_ipu__l3_main_2,
2321};
2322
2323/* l3_main_2 -> ipu */
2324static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2325 .master = &omap44xx_l3_main_2_hwmod,
2326 .slave = &omap44xx_ipu_hwmod,
2327 .clk = "l3_div_ck",
2328 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329};
2330
2331/* ipu slave ports */
2332static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2333 &omap44xx_l3_main_2__ipu,
2334};
2335
2336/* Pseudo hwmod for reset control purpose only */
2337static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2338 .name = "ipu_c0",
2339 .class = &omap44xx_ipu_hwmod_class,
2340 .flags = HWMOD_INIT_NO_RESET,
2341 .rst_lines = omap44xx_ipu_c0_resets,
2342 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2343 .prcm = {
2344 .omap4 = {
2345 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2346 },
2347 },
2348 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2349};
2350
2351/* Pseudo hwmod for reset control purpose only */
2352static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2353 .name = "ipu_c1",
2354 .class = &omap44xx_ipu_hwmod_class,
2355 .flags = HWMOD_INIT_NO_RESET,
2356 .rst_lines = omap44xx_ipu_c1_resets,
2357 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2358 .prcm = {
2359 .omap4 = {
2360 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2361 },
2362 },
2363 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2364};
2365
2366static struct omap_hwmod omap44xx_ipu_hwmod = {
2367 .name = "ipu",
2368 .class = &omap44xx_ipu_hwmod_class,
2369 .mpu_irqs = omap44xx_ipu_irqs,
2370 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
2371 .rst_lines = omap44xx_ipu_resets,
2372 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2373 .main_clk = "ipu_fck",
2374 .prcm = {
2375 .omap4 = {
2376 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2377 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2378 },
2379 },
2380 .slaves = omap44xx_ipu_slaves,
2381 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2382 .masters = omap44xx_ipu_masters,
2383 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2384 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2385};
2386
2387/*
2388 * 'iss' class
2389 * external images sensor pixel data processor
2390 */
2391
2392static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2393 .rev_offs = 0x0000,
2394 .sysc_offs = 0x0010,
2395 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2396 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2398 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2399 MSTANDBY_SMART),
2400 .sysc_fields = &omap_hwmod_sysc_type2,
2401};
2402
2403static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2404 .name = "iss",
2405 .sysc = &omap44xx_iss_sysc,
2406};
2407
2408/* iss */
2409static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2410 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2411};
2412
2413static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2414 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2415 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2416 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2417 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2418};
2419
2420/* iss master ports */
2421static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2422 &omap44xx_iss__l3_main_2,
2423};
2424
2425static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2426 {
2427 .pa_start = 0x52000000,
2428 .pa_end = 0x520000ff,
2429 .flags = ADDR_TYPE_RT
2430 },
2431};
2432
2433/* l3_main_2 -> iss */
2434static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2435 .master = &omap44xx_l3_main_2_hwmod,
2436 .slave = &omap44xx_iss_hwmod,
2437 .clk = "l3_div_ck",
2438 .addr = omap44xx_iss_addrs,
2439 .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
2440 .user = OCP_USER_MPU | OCP_USER_SDMA,
2441};
2442
2443/* iss slave ports */
2444static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2445 &omap44xx_l3_main_2__iss,
2446};
2447
2448static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2449 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2450};
2451
2452static struct omap_hwmod omap44xx_iss_hwmod = {
2453 .name = "iss",
2454 .class = &omap44xx_iss_hwmod_class,
2455 .mpu_irqs = omap44xx_iss_irqs,
2456 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
2457 .sdma_reqs = omap44xx_iss_sdma_reqs,
2458 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2459 .main_clk = "iss_fck",
2460 .prcm = {
2461 .omap4 = {
2462 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2463 },
2464 },
2465 .opt_clks = iss_opt_clks,
2466 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2467 .slaves = omap44xx_iss_slaves,
2468 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2469 .masters = omap44xx_iss_masters,
2470 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2472};
2473
2474/*
1984 * 'iva' class 2475 * 'iva' class
1985 * multi-standard video encoder/decoder hardware accelerator 2476 * multi-standard video encoder/decoder hardware accelerator
1986 */ 2477 */
@@ -2090,6 +2581,73 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
2090}; 2581};
2091 2582
2092/* 2583/*
2584 * 'kbd' class
2585 * keyboard controller
2586 */
2587
2588static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2589 .rev_offs = 0x0000,
2590 .sysc_offs = 0x0010,
2591 .syss_offs = 0x0014,
2592 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2593 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2594 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2595 SYSS_HAS_RESET_STATUS),
2596 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2597 .sysc_fields = &omap_hwmod_sysc_type1,
2598};
2599
2600static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2601 .name = "kbd",
2602 .sysc = &omap44xx_kbd_sysc,
2603};
2604
2605/* kbd */
2606static struct omap_hwmod omap44xx_kbd_hwmod;
2607static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2608 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2609};
2610
2611static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2612 {
2613 .pa_start = 0x4a31c000,
2614 .pa_end = 0x4a31c07f,
2615 .flags = ADDR_TYPE_RT
2616 },
2617};
2618
2619/* l4_wkup -> kbd */
2620static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2621 .master = &omap44xx_l4_wkup_hwmod,
2622 .slave = &omap44xx_kbd_hwmod,
2623 .clk = "l4_wkup_clk_mux_ck",
2624 .addr = omap44xx_kbd_addrs,
2625 .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
2626 .user = OCP_USER_MPU | OCP_USER_SDMA,
2627};
2628
2629/* kbd slave ports */
2630static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2631 &omap44xx_l4_wkup__kbd,
2632};
2633
2634static struct omap_hwmod omap44xx_kbd_hwmod = {
2635 .name = "kbd",
2636 .class = &omap44xx_kbd_hwmod_class,
2637 .mpu_irqs = omap44xx_kbd_irqs,
2638 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
2639 .main_clk = "kbd_fck",
2640 .prcm = {
2641 .omap4 = {
2642 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2643 },
2644 },
2645 .slaves = omap44xx_kbd_slaves,
2646 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2647 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2648};
2649
2650/*
2093 * 'mailbox' class 2651 * 'mailbox' class
2094 * mailbox module allowing communication between the on-chip processors using a 2652 * mailbox module allowing communication between the on-chip processors using a
2095 * queued mailbox-interrupt mechanism. 2653 * queued mailbox-interrupt mechanism.
@@ -2437,6 +2995,98 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2437}; 2995};
2438 2996
2439/* 2997/*
2998 * 'mcpdm' class
2999 * multi channel pdm controller (proprietary interface with phoenix power
3000 * ic)
3001 */
3002
3003static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3004 .rev_offs = 0x0000,
3005 .sysc_offs = 0x0010,
3006 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3007 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3009 SIDLE_SMART_WKUP),
3010 .sysc_fields = &omap_hwmod_sysc_type2,
3011};
3012
3013static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3014 .name = "mcpdm",
3015 .sysc = &omap44xx_mcpdm_sysc,
3016};
3017
3018/* mcpdm */
3019static struct omap_hwmod omap44xx_mcpdm_hwmod;
3020static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3021 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3022};
3023
3024static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3025 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3026 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3027};
3028
3029static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3030 {
3031 .pa_start = 0x40132000,
3032 .pa_end = 0x4013207f,
3033 .flags = ADDR_TYPE_RT
3034 },
3035};
3036
3037/* l4_abe -> mcpdm */
3038static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3039 .master = &omap44xx_l4_abe_hwmod,
3040 .slave = &omap44xx_mcpdm_hwmod,
3041 .clk = "ocp_abe_iclk",
3042 .addr = omap44xx_mcpdm_addrs,
3043 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3044 .user = OCP_USER_MPU,
3045};
3046
3047static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3048 {
3049 .pa_start = 0x49032000,
3050 .pa_end = 0x4903207f,
3051 .flags = ADDR_TYPE_RT
3052 },
3053};
3054
3055/* l4_abe -> mcpdm (dma) */
3056static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3057 .master = &omap44xx_l4_abe_hwmod,
3058 .slave = &omap44xx_mcpdm_hwmod,
3059 .clk = "ocp_abe_iclk",
3060 .addr = omap44xx_mcpdm_dma_addrs,
3061 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3062 .user = OCP_USER_SDMA,
3063};
3064
3065/* mcpdm slave ports */
3066static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3067 &omap44xx_l4_abe__mcpdm,
3068 &omap44xx_l4_abe__mcpdm_dma,
3069};
3070
3071static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3072 .name = "mcpdm",
3073 .class = &omap44xx_mcpdm_hwmod_class,
3074 .mpu_irqs = omap44xx_mcpdm_irqs,
3075 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3076 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3077 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3078 .main_clk = "mcpdm_fck",
3079 .prcm = {
3080 .omap4 = {
3081 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3082 },
3083 },
3084 .slaves = omap44xx_mcpdm_slaves,
3085 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3086 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3087};
3088
3089/*
2440 * 'mcspi' class 3090 * 'mcspi' class
2441 * multichannel serial port interface (mcspi) / master/slave synchronous serial 3091 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2442 * bus 3092 * bus
@@ -2676,6 +3326,300 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2676}; 3326};
2677 3327
2678/* 3328/*
3329 * 'mmc' class
3330 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3331 */
3332
3333static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3334 .rev_offs = 0x0000,
3335 .sysc_offs = 0x0010,
3336 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3337 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3338 SYSC_HAS_SOFTRESET),
3339 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3340 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3341 MSTANDBY_SMART),
3342 .sysc_fields = &omap_hwmod_sysc_type2,
3343};
3344
3345static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3346 .name = "mmc",
3347 .sysc = &omap44xx_mmc_sysc,
3348};
3349
3350/* mmc1 */
3351static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3352 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3353};
3354
3355static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3356 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3357 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3358};
3359
3360/* mmc1 master ports */
3361static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3362 &omap44xx_mmc1__l3_main_1,
3363};
3364
3365static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3366 {
3367 .pa_start = 0x4809c000,
3368 .pa_end = 0x4809c3ff,
3369 .flags = ADDR_TYPE_RT
3370 },
3371};
3372
3373/* l4_per -> mmc1 */
3374static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3375 .master = &omap44xx_l4_per_hwmod,
3376 .slave = &omap44xx_mmc1_hwmod,
3377 .clk = "l4_div_ck",
3378 .addr = omap44xx_mmc1_addrs,
3379 .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
3380 .user = OCP_USER_MPU | OCP_USER_SDMA,
3381};
3382
3383/* mmc1 slave ports */
3384static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3385 &omap44xx_l4_per__mmc1,
3386};
3387
3388static struct omap_hwmod omap44xx_mmc1_hwmod = {
3389 .name = "mmc1",
3390 .class = &omap44xx_mmc_hwmod_class,
3391 .mpu_irqs = omap44xx_mmc1_irqs,
3392 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
3393 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3394 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3395 .main_clk = "mmc1_fck",
3396 .prcm = {
3397 .omap4 = {
3398 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3399 },
3400 },
3401 .slaves = omap44xx_mmc1_slaves,
3402 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3403 .masters = omap44xx_mmc1_masters,
3404 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3405 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3406};
3407
3408/* mmc2 */
3409static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3410 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3411};
3412
3413static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3414 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3415 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3416};
3417
3418/* mmc2 master ports */
3419static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3420 &omap44xx_mmc2__l3_main_1,
3421};
3422
3423static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3424 {
3425 .pa_start = 0x480b4000,
3426 .pa_end = 0x480b43ff,
3427 .flags = ADDR_TYPE_RT
3428 },
3429};
3430
3431/* l4_per -> mmc2 */
3432static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3433 .master = &omap44xx_l4_per_hwmod,
3434 .slave = &omap44xx_mmc2_hwmod,
3435 .clk = "l4_div_ck",
3436 .addr = omap44xx_mmc2_addrs,
3437 .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
3438 .user = OCP_USER_MPU | OCP_USER_SDMA,
3439};
3440
3441/* mmc2 slave ports */
3442static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3443 &omap44xx_l4_per__mmc2,
3444};
3445
3446static struct omap_hwmod omap44xx_mmc2_hwmod = {
3447 .name = "mmc2",
3448 .class = &omap44xx_mmc_hwmod_class,
3449 .mpu_irqs = omap44xx_mmc2_irqs,
3450 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
3451 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3452 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3453 .main_clk = "mmc2_fck",
3454 .prcm = {
3455 .omap4 = {
3456 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3457 },
3458 },
3459 .slaves = omap44xx_mmc2_slaves,
3460 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3461 .masters = omap44xx_mmc2_masters,
3462 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3463 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3464};
3465
3466/* mmc3 */
3467static struct omap_hwmod omap44xx_mmc3_hwmod;
3468static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3469 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3470};
3471
3472static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3473 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3474 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3475};
3476
3477static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3478 {
3479 .pa_start = 0x480ad000,
3480 .pa_end = 0x480ad3ff,
3481 .flags = ADDR_TYPE_RT
3482 },
3483};
3484
3485/* l4_per -> mmc3 */
3486static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3487 .master = &omap44xx_l4_per_hwmod,
3488 .slave = &omap44xx_mmc3_hwmod,
3489 .clk = "l4_div_ck",
3490 .addr = omap44xx_mmc3_addrs,
3491 .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
3492 .user = OCP_USER_MPU | OCP_USER_SDMA,
3493};
3494
3495/* mmc3 slave ports */
3496static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3497 &omap44xx_l4_per__mmc3,
3498};
3499
3500static struct omap_hwmod omap44xx_mmc3_hwmod = {
3501 .name = "mmc3",
3502 .class = &omap44xx_mmc_hwmod_class,
3503 .mpu_irqs = omap44xx_mmc3_irqs,
3504 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
3505 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3506 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3507 .main_clk = "mmc3_fck",
3508 .prcm = {
3509 .omap4 = {
3510 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3511 },
3512 },
3513 .slaves = omap44xx_mmc3_slaves,
3514 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3515 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3516};
3517
3518/* mmc4 */
3519static struct omap_hwmod omap44xx_mmc4_hwmod;
3520static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3521 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3522};
3523
3524static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3525 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3526 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3527};
3528
3529static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3530 {
3531 .pa_start = 0x480d1000,
3532 .pa_end = 0x480d13ff,
3533 .flags = ADDR_TYPE_RT
3534 },
3535};
3536
3537/* l4_per -> mmc4 */
3538static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3539 .master = &omap44xx_l4_per_hwmod,
3540 .slave = &omap44xx_mmc4_hwmod,
3541 .clk = "l4_div_ck",
3542 .addr = omap44xx_mmc4_addrs,
3543 .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
3544 .user = OCP_USER_MPU | OCP_USER_SDMA,
3545};
3546
3547/* mmc4 slave ports */
3548static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3549 &omap44xx_l4_per__mmc4,
3550};
3551
3552static struct omap_hwmod omap44xx_mmc4_hwmod = {
3553 .name = "mmc4",
3554 .class = &omap44xx_mmc_hwmod_class,
3555 .mpu_irqs = omap44xx_mmc4_irqs,
3556 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
3557 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3558 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3559 .main_clk = "mmc4_fck",
3560 .prcm = {
3561 .omap4 = {
3562 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3563 },
3564 },
3565 .slaves = omap44xx_mmc4_slaves,
3566 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3568};
3569
3570/* mmc5 */
3571static struct omap_hwmod omap44xx_mmc5_hwmod;
3572static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3573 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3574};
3575
3576static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3577 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3578 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3579};
3580
3581static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3582 {
3583 .pa_start = 0x480d5000,
3584 .pa_end = 0x480d53ff,
3585 .flags = ADDR_TYPE_RT
3586 },
3587};
3588
3589/* l4_per -> mmc5 */
3590static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3591 .master = &omap44xx_l4_per_hwmod,
3592 .slave = &omap44xx_mmc5_hwmod,
3593 .clk = "l4_div_ck",
3594 .addr = omap44xx_mmc5_addrs,
3595 .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
3596 .user = OCP_USER_MPU | OCP_USER_SDMA,
3597};
3598
3599/* mmc5 slave ports */
3600static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3601 &omap44xx_l4_per__mmc5,
3602};
3603
3604static struct omap_hwmod omap44xx_mmc5_hwmod = {
3605 .name = "mmc5",
3606 .class = &omap44xx_mmc_hwmod_class,
3607 .mpu_irqs = omap44xx_mmc5_irqs,
3608 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
3609 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3610 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3611 .main_clk = "mmc5_fck",
3612 .prcm = {
3613 .omap4 = {
3614 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3615 },
3616 },
3617 .slaves = omap44xx_mmc5_slaves,
3618 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3619 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3620};
3621
3622/*
2679 * 'mpu' class 3623 * 'mpu' class
2680 * mpu sub-system 3624 * mpu sub-system
2681 */ 3625 */
@@ -3935,6 +4879,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
3935 /* mpu_bus class */ 4879 /* mpu_bus class */
3936 &omap44xx_mpu_private_hwmod, 4880 &omap44xx_mpu_private_hwmod,
3937 4881
4882 /* aess class */
4883/* &omap44xx_aess_hwmod, */
4884
4885 /* bandgap class */
4886 &omap44xx_bandgap_hwmod,
4887
4888 /* counter class */
4889/* &omap44xx_counter_32k_hwmod, */
4890
3938 /* dma class */ 4891 /* dma class */
3939 &omap44xx_dma_system_hwmod, 4892 &omap44xx_dma_system_hwmod,
3940 4893
@@ -3962,17 +4915,31 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
3962 &omap44xx_gpio5_hwmod, 4915 &omap44xx_gpio5_hwmod,
3963 &omap44xx_gpio6_hwmod, 4916 &omap44xx_gpio6_hwmod,
3964 4917
4918 /* hsi class */
4919/* &omap44xx_hsi_hwmod, */
4920
3965 /* i2c class */ 4921 /* i2c class */
3966 &omap44xx_i2c1_hwmod, 4922 &omap44xx_i2c1_hwmod,
3967 &omap44xx_i2c2_hwmod, 4923 &omap44xx_i2c2_hwmod,
3968 &omap44xx_i2c3_hwmod, 4924 &omap44xx_i2c3_hwmod,
3969 &omap44xx_i2c4_hwmod, 4925 &omap44xx_i2c4_hwmod,
3970 4926
4927 /* ipu class */
4928 &omap44xx_ipu_hwmod,
4929 &omap44xx_ipu_c0_hwmod,
4930 &omap44xx_ipu_c1_hwmod,
4931
4932 /* iss class */
4933/* &omap44xx_iss_hwmod, */
4934
3971 /* iva class */ 4935 /* iva class */
3972 &omap44xx_iva_hwmod, 4936 &omap44xx_iva_hwmod,
3973 &omap44xx_iva_seq0_hwmod, 4937 &omap44xx_iva_seq0_hwmod,
3974 &omap44xx_iva_seq1_hwmod, 4938 &omap44xx_iva_seq1_hwmod,
3975 4939
4940 /* kbd class */
4941/* &omap44xx_kbd_hwmod, */
4942
3976 /* mailbox class */ 4943 /* mailbox class */
3977 &omap44xx_mailbox_hwmod, 4944 &omap44xx_mailbox_hwmod,
3978 4945
@@ -3982,12 +4949,22 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
3982 &omap44xx_mcbsp3_hwmod, 4949 &omap44xx_mcbsp3_hwmod,
3983 &omap44xx_mcbsp4_hwmod, 4950 &omap44xx_mcbsp4_hwmod,
3984 4951
4952 /* mcpdm class */
4953/* &omap44xx_mcpdm_hwmod, */
4954
3985 /* mcspi class */ 4955 /* mcspi class */
3986 &omap44xx_mcspi1_hwmod, 4956 &omap44xx_mcspi1_hwmod,
3987 &omap44xx_mcspi2_hwmod, 4957 &omap44xx_mcspi2_hwmod,
3988 &omap44xx_mcspi3_hwmod, 4958 &omap44xx_mcspi3_hwmod,
3989 &omap44xx_mcspi4_hwmod, 4959 &omap44xx_mcspi4_hwmod,
3990 4960
4961 /* mmc class */
4962/* &omap44xx_mmc1_hwmod, */
4963/* &omap44xx_mmc2_hwmod, */
4964/* &omap44xx_mmc3_hwmod, */
4965/* &omap44xx_mmc4_hwmod, */
4966/* &omap44xx_mmc5_hwmod, */
4967
3991 /* mpu class */ 4968 /* mpu class */
3992 &omap44xx_mpu_hwmod, 4969 &omap44xx_mpu_hwmod,
3993 4970
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 09:55:22 -0500