diff options
author | Borislav Petkov <bp@suse.de> | 2014-01-14 18:07:11 -0500 |
---|---|---|
committer | H. Peter Anvin <hpa@linux.intel.com> | 2014-01-14 19:39:07 -0500 |
commit | 3b56496865f9f7d9bcb2f93b44c63f274f08e3b6 (patch) | |
tree | cb431f67bb7b87610a3ead2bf0b12ffdb8b9541e | |
parent | a6da83f98267bc8ee4e34aa899169991eb0ceb93 (diff) |
x86, cpu, amd: Add workaround for family 16h, erratum 793
This adds the workaround for erratum 793 as a precaution in case not
every BIOS implements it. This addresses CVE-2013-6885.
Erratum text:
[Revision Guide for AMD Family 16h Models 00h-0Fh Processors,
document 51810 Rev. 3.04 November 2013]
793 Specific Combination of Writes to Write Combined Memory Types and
Locked Instructions May Cause Core Hang
Description
Under a highly specific and detailed set of internal timing
conditions, a locked instruction may trigger a timing sequence whereby
the write to a write combined memory type is not flushed, causing the
locked instruction to stall indefinitely.
Potential Effect on System
Processor core hang.
Suggested Workaround
BIOS should set MSR
C001_1020[15] = 1b.
Fix Planned
No fix planned
[ hpa: updated description, fixed typo in MSR name ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/20140114230711.GS29865@pd.tnic
Tested-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
-rw-r--r-- | arch/x86/include/uapi/asm/msr-index.h | 1 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/amd.c | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 37813b5ddc37..59cea185ad1d 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h | |||
@@ -184,6 +184,7 @@ | |||
184 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 | 184 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
185 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 | 185 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
186 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 | 186 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
187 | #define MSR_AMD64_LS_CFG 0xc0011020 | ||
187 | #define MSR_AMD64_DC_CFG 0xc0011022 | 188 | #define MSR_AMD64_DC_CFG 0xc0011022 |
188 | #define MSR_AMD64_BU_CFG2 0xc001102a | 189 | #define MSR_AMD64_BU_CFG2 0xc001102a |
189 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 | 190 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bca023bdd6b2..59bfebc8c805 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c | |||
@@ -508,6 +508,16 @@ static void early_init_amd(struct cpuinfo_x86 *c) | |||
508 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | 508 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
509 | } | 509 | } |
510 | #endif | 510 | #endif |
511 | |||
512 | /* F16h erratum 793, CVE-2013-6885 */ | ||
513 | if (c->x86 == 0x16 && c->x86_model <= 0xf) { | ||
514 | u64 val; | ||
515 | |||
516 | rdmsrl(MSR_AMD64_LS_CFG, val); | ||
517 | if (!(val & BIT(15))) | ||
518 | wrmsrl(MSR_AMD64_LS_CFG, val | BIT(15)); | ||
519 | } | ||
520 | |||
511 | } | 521 | } |
512 | 522 | ||
513 | static const int amd_erratum_383[]; | 523 | static const int amd_erratum_383[]; |