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authorArnd Bergmann <arnd@arndb.de>2014-11-19 11:25:59 -0500
committerArnd Bergmann <arnd@arndb.de>2014-11-19 11:25:59 -0500
commit3410d4247cdbadfd08b455adf9217404e0eb71ba (patch)
treee7cf62a2e48afef76be7d3000ec514b39a386025
parent1b6166e5bac2d36ecf83ded7e5c863b087862441 (diff)
parentb89ff7c3c2dee189489a5f45eb8d72e106179299 (diff)
Merge tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
Pull "Renesas ARM Based SoC DT Fixes for v3.18" from Simon Horman: * Correct IIC0 parent clock on r8a7740 * Correct SD3CKCR address to device tree on r8a7790 * tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi2
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi4
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d46c213a17ad..eed697a6bd6b 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -433,7 +433,7 @@
433 clocks = <&cpg_clocks R8A7740_CLK_S>, 433 clocks = <&cpg_clocks R8A7740_CLK_S>,
434 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, 434 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
435 <&cpg_clocks R8A7740_CLK_B>, 435 <&cpg_clocks R8A7740_CLK_B>,
436 <&sub_clk>, <&sub_clk>, 436 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
437 <&cpg_clocks R8A7740_CLK_B>; 437 <&cpg_clocks R8A7740_CLK_B>;
438 #clock-cells = <1>; 438 #clock-cells = <1>;
439 renesas,clock-indices = < 439 renesas,clock-indices = <
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d0e17733dc1a..e20affe156c1 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -666,9 +666,9 @@
666 #clock-cells = <0>; 666 #clock-cells = <0>;
667 clock-output-names = "sd2"; 667 clock-output-names = "sd2";
668 }; 668 };
669 sd3_clk: sd3_clk@e615007c { 669 sd3_clk: sd3_clk@e615026c {
670 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; 670 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
671 reg = <0 0xe615007c 0 4>; 671 reg = <0 0xe615026c 0 4>;
672 clocks = <&pll1_div2_clk>; 672 clocks = <&pll1_div2_clk>;
673 #clock-cells = <0>; 673 #clock-cells = <0>;
674 clock-output-names = "sd3"; 674 clock-output-names = "sd3";