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authorAlex Deucher <alexdeucher@gmail.com>2010-03-24 13:33:47 -0400
committerDave Airlie <airlied@redhat.com>2010-04-08 20:16:00 -0400
commit32fcdbf4084544c3d8fa413004d57e5dc6f2eefe (patch)
tree179aaa9296f8ad63028d7274d0eed8039d428dce
parent747943ea187e5acceb7ffc762ff2c84cb3449745 (diff)
drm/radeon/kms/evergreen: implement gfx init
This initializes the gfx engine so accel can eventually be used. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c556
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h105
-rw-r--r--drivers/gpu/drm/radeon/radeon.h25
3 files changed, 668 insertions, 18 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a6130a494c56..26b219bb1388 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -434,24 +434,572 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
434 434
435 return 0; 435 return 0;
436} 436}
437 437#endif
438 438
439/* 439/*
440 * Core functions 440 * Core functions
441 */ 441 */
442static u32 evergreen_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 442static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
443 u32 num_tile_pipes,
443 u32 num_backends, 444 u32 num_backends,
444 u32 backend_disable_mask) 445 u32 backend_disable_mask)
445{ 446{
446 u32 backend_map = 0; 447 u32 backend_map = 0;
448 u32 enabled_backends_mask = 0;
449 u32 enabled_backends_count = 0;
450 u32 cur_pipe;
451 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
452 u32 cur_backend = 0;
453 u32 i;
454 bool force_no_swizzle;
455
456 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
457 num_tile_pipes = EVERGREEN_MAX_PIPES;
458 if (num_tile_pipes < 1)
459 num_tile_pipes = 1;
460 if (num_backends > EVERGREEN_MAX_BACKENDS)
461 num_backends = EVERGREEN_MAX_BACKENDS;
462 if (num_backends < 1)
463 num_backends = 1;
464
465 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
466 if (((backend_disable_mask >> i) & 1) == 0) {
467 enabled_backends_mask |= (1 << i);
468 ++enabled_backends_count;
469 }
470 if (enabled_backends_count == num_backends)
471 break;
472 }
473
474 if (enabled_backends_count == 0) {
475 enabled_backends_mask = 1;
476 enabled_backends_count = 1;
477 }
478
479 if (enabled_backends_count != num_backends)
480 num_backends = enabled_backends_count;
481
482 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
483 switch (rdev->family) {
484 case CHIP_CEDAR:
485 case CHIP_REDWOOD:
486 force_no_swizzle = false;
487 break;
488 case CHIP_CYPRESS:
489 case CHIP_HEMLOCK:
490 case CHIP_JUNIPER:
491 default:
492 force_no_swizzle = true;
493 break;
494 }
495 if (force_no_swizzle) {
496 bool last_backend_enabled = false;
497
498 force_no_swizzle = false;
499 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
500 if (((enabled_backends_mask >> i) & 1) == 1) {
501 if (last_backend_enabled)
502 force_no_swizzle = true;
503 last_backend_enabled = true;
504 } else
505 last_backend_enabled = false;
506 }
507 }
508
509 switch (num_tile_pipes) {
510 case 1:
511 case 3:
512 case 5:
513 case 7:
514 DRM_ERROR("odd number of pipes!\n");
515 break;
516 case 2:
517 swizzle_pipe[0] = 0;
518 swizzle_pipe[1] = 1;
519 break;
520 case 4:
521 if (force_no_swizzle) {
522 swizzle_pipe[0] = 0;
523 swizzle_pipe[1] = 1;
524 swizzle_pipe[2] = 2;
525 swizzle_pipe[3] = 3;
526 } else {
527 swizzle_pipe[0] = 0;
528 swizzle_pipe[1] = 2;
529 swizzle_pipe[2] = 1;
530 swizzle_pipe[3] = 3;
531 }
532 break;
533 case 6:
534 if (force_no_swizzle) {
535 swizzle_pipe[0] = 0;
536 swizzle_pipe[1] = 1;
537 swizzle_pipe[2] = 2;
538 swizzle_pipe[3] = 3;
539 swizzle_pipe[4] = 4;
540 swizzle_pipe[5] = 5;
541 } else {
542 swizzle_pipe[0] = 0;
543 swizzle_pipe[1] = 2;
544 swizzle_pipe[2] = 4;
545 swizzle_pipe[3] = 1;
546 swizzle_pipe[4] = 3;
547 swizzle_pipe[5] = 5;
548 }
549 break;
550 case 8:
551 if (force_no_swizzle) {
552 swizzle_pipe[0] = 0;
553 swizzle_pipe[1] = 1;
554 swizzle_pipe[2] = 2;
555 swizzle_pipe[3] = 3;
556 swizzle_pipe[4] = 4;
557 swizzle_pipe[5] = 5;
558 swizzle_pipe[6] = 6;
559 swizzle_pipe[7] = 7;
560 } else {
561 swizzle_pipe[0] = 0;
562 swizzle_pipe[1] = 2;
563 swizzle_pipe[2] = 4;
564 swizzle_pipe[3] = 6;
565 swizzle_pipe[4] = 1;
566 swizzle_pipe[5] = 3;
567 swizzle_pipe[6] = 5;
568 swizzle_pipe[7] = 7;
569 }
570 break;
571 }
572
573 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
574 while (((1 << cur_backend) & enabled_backends_mask) == 0)
575 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
576
577 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
578
579 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
580 }
447 581
448 return backend_map; 582 return backend_map;
449} 583}
450#endif
451 584
452static void evergreen_gpu_init(struct radeon_device *rdev) 585static void evergreen_gpu_init(struct radeon_device *rdev)
453{ 586{
454 /* XXX */ 587 u32 cc_rb_backend_disable = 0;
588 u32 cc_gc_shader_pipe_config;
589 u32 gb_addr_config = 0;
590 u32 mc_shared_chmap, mc_arb_ramcfg;
591 u32 gb_backend_map;
592 u32 grbm_gfx_index;
593 u32 sx_debug_1;
594 u32 smx_dc_ctl0;
595 u32 sq_config;
596 u32 sq_lds_resource_mgmt;
597 u32 sq_gpr_resource_mgmt_1;
598 u32 sq_gpr_resource_mgmt_2;
599 u32 sq_gpr_resource_mgmt_3;
600 u32 sq_thread_resource_mgmt;
601 u32 sq_thread_resource_mgmt_2;
602 u32 sq_stack_resource_mgmt_1;
603 u32 sq_stack_resource_mgmt_2;
604 u32 sq_stack_resource_mgmt_3;
605 u32 vgt_cache_invalidation;
606 u32 hdp_host_path_cntl;
607 int i, j, num_shader_engines, ps_thread_count;
608
609 switch (rdev->family) {
610 case CHIP_CYPRESS:
611 case CHIP_HEMLOCK:
612 rdev->config.evergreen.num_ses = 2;
613 rdev->config.evergreen.max_pipes = 4;
614 rdev->config.evergreen.max_tile_pipes = 8;
615 rdev->config.evergreen.max_simds = 10;
616 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
617 rdev->config.evergreen.max_gprs = 256;
618 rdev->config.evergreen.max_threads = 248;
619 rdev->config.evergreen.max_gs_threads = 32;
620 rdev->config.evergreen.max_stack_entries = 512;
621 rdev->config.evergreen.sx_num_of_sets = 4;
622 rdev->config.evergreen.sx_max_export_size = 256;
623 rdev->config.evergreen.sx_max_export_pos_size = 64;
624 rdev->config.evergreen.sx_max_export_smx_size = 192;
625 rdev->config.evergreen.max_hw_contexts = 8;
626 rdev->config.evergreen.sq_num_cf_insts = 2;
627
628 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
629 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
630 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
631 break;
632 case CHIP_JUNIPER:
633 rdev->config.evergreen.num_ses = 1;
634 rdev->config.evergreen.max_pipes = 4;
635 rdev->config.evergreen.max_tile_pipes = 4;
636 rdev->config.evergreen.max_simds = 10;
637 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
638 rdev->config.evergreen.max_gprs = 256;
639 rdev->config.evergreen.max_threads = 248;
640 rdev->config.evergreen.max_gs_threads = 32;
641 rdev->config.evergreen.max_stack_entries = 512;
642 rdev->config.evergreen.sx_num_of_sets = 4;
643 rdev->config.evergreen.sx_max_export_size = 256;
644 rdev->config.evergreen.sx_max_export_pos_size = 64;
645 rdev->config.evergreen.sx_max_export_smx_size = 192;
646 rdev->config.evergreen.max_hw_contexts = 8;
647 rdev->config.evergreen.sq_num_cf_insts = 2;
648
649 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
650 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
651 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
652 break;
653 case CHIP_REDWOOD:
654 rdev->config.evergreen.num_ses = 1;
655 rdev->config.evergreen.max_pipes = 4;
656 rdev->config.evergreen.max_tile_pipes = 4;
657 rdev->config.evergreen.max_simds = 5;
658 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
659 rdev->config.evergreen.max_gprs = 256;
660 rdev->config.evergreen.max_threads = 248;
661 rdev->config.evergreen.max_gs_threads = 32;
662 rdev->config.evergreen.max_stack_entries = 256;
663 rdev->config.evergreen.sx_num_of_sets = 4;
664 rdev->config.evergreen.sx_max_export_size = 256;
665 rdev->config.evergreen.sx_max_export_pos_size = 64;
666 rdev->config.evergreen.sx_max_export_smx_size = 192;
667 rdev->config.evergreen.max_hw_contexts = 8;
668 rdev->config.evergreen.sq_num_cf_insts = 2;
669
670 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
671 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
672 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
673 break;
674 case CHIP_CEDAR:
675 default:
676 rdev->config.evergreen.num_ses = 1;
677 rdev->config.evergreen.max_pipes = 2;
678 rdev->config.evergreen.max_tile_pipes = 2;
679 rdev->config.evergreen.max_simds = 2;
680 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
681 rdev->config.evergreen.max_gprs = 256;
682 rdev->config.evergreen.max_threads = 192;
683 rdev->config.evergreen.max_gs_threads = 16;
684 rdev->config.evergreen.max_stack_entries = 256;
685 rdev->config.evergreen.sx_num_of_sets = 4;
686 rdev->config.evergreen.sx_max_export_size = 128;
687 rdev->config.evergreen.sx_max_export_pos_size = 32;
688 rdev->config.evergreen.sx_max_export_smx_size = 96;
689 rdev->config.evergreen.max_hw_contexts = 4;
690 rdev->config.evergreen.sq_num_cf_insts = 1;
691
692 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
693 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
694 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
695 break;
696 }
697
698 /* Initialize HDP */
699 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
700 WREG32((0x2c14 + j), 0x00000000);
701 WREG32((0x2c18 + j), 0x00000000);
702 WREG32((0x2c1c + j), 0x00000000);
703 WREG32((0x2c20 + j), 0x00000000);
704 WREG32((0x2c24 + j), 0x00000000);
705 }
706
707 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
708
709 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
710
711 cc_gc_shader_pipe_config |=
712 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
713 & EVERGREEN_MAX_PIPES_MASK);
714 cc_gc_shader_pipe_config |=
715 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
716 & EVERGREEN_MAX_SIMDS_MASK);
717
718 cc_rb_backend_disable =
719 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
720 & EVERGREEN_MAX_BACKENDS_MASK);
721
722
723 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
724 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
725
726 switch (rdev->config.evergreen.max_tile_pipes) {
727 case 1:
728 default:
729 gb_addr_config |= NUM_PIPES(0);
730 break;
731 case 2:
732 gb_addr_config |= NUM_PIPES(1);
733 break;
734 case 4:
735 gb_addr_config |= NUM_PIPES(2);
736 break;
737 case 8:
738 gb_addr_config |= NUM_PIPES(3);
739 break;
740 }
741
742 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
743 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
744 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
745 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
746 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
747 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
748
749 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
750 gb_addr_config |= ROW_SIZE(2);
751 else
752 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
753
754 if (rdev->ddev->pdev->device == 0x689e) {
755 u32 efuse_straps_4;
756 u32 efuse_straps_3;
757 u8 efuse_box_bit_131_124;
758
759 WREG32(RCU_IND_INDEX, 0x204);
760 efuse_straps_4 = RREG32(RCU_IND_DATA);
761 WREG32(RCU_IND_INDEX, 0x203);
762 efuse_straps_3 = RREG32(RCU_IND_DATA);
763 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
764
765 switch(efuse_box_bit_131_124) {
766 case 0x00:
767 gb_backend_map = 0x76543210;
768 break;
769 case 0x55:
770 gb_backend_map = 0x77553311;
771 break;
772 case 0x56:
773 gb_backend_map = 0x77553300;
774 break;
775 case 0x59:
776 gb_backend_map = 0x77552211;
777 break;
778 case 0x66:
779 gb_backend_map = 0x77443300;
780 break;
781 case 0x99:
782 gb_backend_map = 0x66552211;
783 break;
784 case 0x5a:
785 gb_backend_map = 0x77552200;
786 break;
787 case 0xaa:
788 gb_backend_map = 0x66442200;
789 break;
790 case 0x95:
791 gb_backend_map = 0x66553311;
792 break;
793 default:
794 DRM_ERROR("bad backend map, using default\n");
795 gb_backend_map =
796 evergreen_get_tile_pipe_to_backend_map(rdev,
797 rdev->config.evergreen.max_tile_pipes,
798 rdev->config.evergreen.max_backends,
799 ((EVERGREEN_MAX_BACKENDS_MASK <<
800 rdev->config.evergreen.max_backends) &
801 EVERGREEN_MAX_BACKENDS_MASK));
802 break;
803 }
804 } else if (rdev->ddev->pdev->device == 0x68b9) {
805 u32 efuse_straps_3;
806 u8 efuse_box_bit_127_124;
807
808 WREG32(RCU_IND_INDEX, 0x203);
809 efuse_straps_3 = RREG32(RCU_IND_DATA);
810 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28;
811
812 switch(efuse_box_bit_127_124) {
813 case 0x0:
814 gb_backend_map = 0x00003210;
815 break;
816 case 0x5:
817 case 0x6:
818 case 0x9:
819 case 0xa:
820 gb_backend_map = 0x00003311;
821 break;
822 default:
823 DRM_ERROR("bad backend map, using default\n");
824 gb_backend_map =
825 evergreen_get_tile_pipe_to_backend_map(rdev,
826 rdev->config.evergreen.max_tile_pipes,
827 rdev->config.evergreen.max_backends,
828 ((EVERGREEN_MAX_BACKENDS_MASK <<
829 rdev->config.evergreen.max_backends) &
830 EVERGREEN_MAX_BACKENDS_MASK));
831 break;
832 }
833 } else
834 gb_backend_map =
835 evergreen_get_tile_pipe_to_backend_map(rdev,
836 rdev->config.evergreen.max_tile_pipes,
837 rdev->config.evergreen.max_backends,
838 ((EVERGREEN_MAX_BACKENDS_MASK <<
839 rdev->config.evergreen.max_backends) &
840 EVERGREEN_MAX_BACKENDS_MASK));
841
842 WREG32(GB_BACKEND_MAP, gb_backend_map);
843 WREG32(GB_ADDR_CONFIG, gb_addr_config);
844 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
845 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
846
847 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
848 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
849
850 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
851 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
852 u32 sp = cc_gc_shader_pipe_config;
853 u32 gfx = grbm_gfx_index | SE_INDEX(i);
854
855 if (i == num_shader_engines) {
856 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
857 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
858 }
859
860 WREG32(GRBM_GFX_INDEX, gfx);
861 WREG32(RLC_GFX_INDEX, gfx);
862
863 WREG32(CC_RB_BACKEND_DISABLE, rb);
864 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
865 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
866 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
867 }
868
869 grbm_gfx_index |= SE_BROADCAST_WRITES;
870 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
871 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
872
873 WREG32(CGTS_SYS_TCC_DISABLE, 0);
874 WREG32(CGTS_TCC_DISABLE, 0);
875 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
876 WREG32(CGTS_USER_TCC_DISABLE, 0);
877
878 /* set HW defaults for 3D engine */
879 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
880 ROQ_IB2_START(0x2b)));
881
882 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
883
884 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
885 SYNC_GRADIENT |
886 SYNC_WALKER |
887 SYNC_ALIGNER));
888
889 sx_debug_1 = RREG32(SX_DEBUG_1);
890 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
891 WREG32(SX_DEBUG_1, sx_debug_1);
892
893
894 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
895 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
896 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
897 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
898
899 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
900 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
901 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
902
903 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
904 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
905 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
906
907 WREG32(VGT_NUM_INSTANCES, 1);
908 WREG32(SPI_CONFIG_CNTL, 0);
909 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
910 WREG32(CP_PERFMON_CNTL, 0);
911
912 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
913 FETCH_FIFO_HIWATER(0x4) |
914 DONE_FIFO_HIWATER(0xe0) |
915 ALU_UPDATE_FIFO_HIWATER(0x8)));
916
917 sq_config = RREG32(SQ_CONFIG);
918 sq_config &= ~(PS_PRIO(3) |
919 VS_PRIO(3) |
920 GS_PRIO(3) |
921 ES_PRIO(3));
922 sq_config |= (VC_ENABLE |
923 EXPORT_SRC_C |
924 PS_PRIO(0) |
925 VS_PRIO(1) |
926 GS_PRIO(2) |
927 ES_PRIO(3));
928
929 if (rdev->family == CHIP_CEDAR)
930 /* no vertex cache */
931 sq_config &= ~VC_ENABLE;
932
933 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
934
935 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
936 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
937 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
938 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
939 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
940 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
941 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
942
943 if (rdev->family == CHIP_CEDAR)
944 ps_thread_count = 96;
945 else
946 ps_thread_count = 128;
947
948 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
949 sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
950 sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
951 sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
952 sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
953 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
954
955 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
956 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
957 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
958 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
959 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
960 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
961
962 WREG32(SQ_CONFIG, sq_config);
963 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
964 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
965 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
966 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
967 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
968 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
969 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
970 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
971 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
972 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
973
974 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
975 FORCE_EOV_MAX_REZ_CNT(255)));
976
977 if (rdev->family == CHIP_CEDAR)
978 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
979 else
980 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
981 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
982 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
983
984 WREG32(VGT_GS_VERTEX_REUSE, 16);
985 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
986
987 WREG32(CB_PERF_CTR0_SEL_0, 0);
988 WREG32(CB_PERF_CTR0_SEL_1, 0);
989 WREG32(CB_PERF_CTR1_SEL_0, 0);
990 WREG32(CB_PERF_CTR1_SEL_1, 0);
991 WREG32(CB_PERF_CTR2_SEL_0, 0);
992 WREG32(CB_PERF_CTR2_SEL_1, 0);
993 WREG32(CB_PERF_CTR3_SEL_0, 0);
994 WREG32(CB_PERF_CTR3_SEL_1, 0);
995
996 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
997 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
998
999 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1000
1001 udelay(50);
1002
455} 1003}
456 1004
457int evergreen_mc_init(struct radeon_device *rdev) 1005int evergreen_mc_init(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 7c290a6dd0e3..effe335356c7 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -24,12 +24,49 @@
24#ifndef EVERGREEND_H 24#ifndef EVERGREEND_H
25#define EVERGREEND_H 25#define EVERGREEND_H
26 26
27#define EVERGREEN_MAX_SH_GPRS 256
28#define EVERGREEN_MAX_TEMP_GPRS 16
29#define EVERGREEN_MAX_SH_THREADS 256
30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31#define EVERGREEN_MAX_FRC_EOV_CNT 16384
32#define EVERGREEN_MAX_BACKENDS 8
33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34#define EVERGREEN_MAX_SIMDS 16
35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36#define EVERGREEN_MAX_PIPES 8
37#define EVERGREEN_MAX_PIPES_MASK 0xFF
38#define EVERGREEN_MAX_LDS_NUM 0xFFFF
39
27/* Registers */ 40/* Registers */
28 41
29#define CC_GC_SHADER_PIPE_CONFIG 0x8950 42#define RCU_IND_INDEX 0x100
30#define CC_RB_BACKEND_DISABLE 0x98F4 43#define RCU_IND_DATA 0x104
31#define BACKEND_DISABLE(x) ((x) << 16) 44
45#define GRBM_GFX_INDEX 0x802C
46#define INSTANCE_INDEX(x) ((x) << 0)
47#define SE_INDEX(x) ((x) << 16)
48#define INSTANCE_BROADCAST_WRITES (1 << 30)
49#define SE_BROADCAST_WRITES (1 << 31)
50#define RLC_GFX_INDEX 0x3fC4
51#define CC_GC_SHADER_PIPE_CONFIG 0x8950
52#define WRITE_DIS (1 << 0)
53#define CC_RB_BACKEND_DISABLE 0x98F4
54#define BACKEND_DISABLE(x) ((x) << 16)
55#define GB_ADDR_CONFIG 0x98F8
56#define NUM_PIPES(x) ((x) << 0)
57#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
58#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
59#define NUM_SHADER_ENGINES(x) ((x) << 12)
60#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
61#define NUM_GPUS(x) ((x) << 20)
62#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
63#define ROW_SIZE(x) ((x) << 28)
64#define GB_BACKEND_MAP 0x98FC
65#define DMIF_ADDR_CONFIG 0xBD4
66#define HDP_ADDR_CONFIG 0x2F48
67
32#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 68#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
69#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
33 70
34#define CGTS_SYS_TCC_DISABLE 0x3F90 71#define CGTS_SYS_TCC_DISABLE 0x3F90
35#define CGTS_TCC_DISABLE 0x9148 72#define CGTS_TCC_DISABLE 0x9148
@@ -38,9 +75,9 @@
38 75
39#define CONFIG_MEMSIZE 0x5428 76#define CONFIG_MEMSIZE 0x5428
40 77
41#define CP_ME_CNTL 0x86D8 78#define CP_ME_CNTL 0x86D8
42#define CP_ME_HALT (1<<28) 79#define CP_ME_HALT (1 << 28)
43#define CP_PFP_HALT (1<<26) 80#define CP_PFP_HALT (1 << 26)
44#define CP_ME_RAM_DATA 0xC160 81#define CP_ME_RAM_DATA 0xC160
45#define CP_ME_RAM_RADDR 0xC158 82#define CP_ME_RAM_RADDR 0xC158
46#define CP_ME_RAM_WADDR 0xC15C 83#define CP_ME_RAM_WADDR 0xC15C
@@ -53,10 +90,10 @@
53#define ROQ_IB1_START(x) ((x) << 0) 90#define ROQ_IB1_START(x) ((x) << 0)
54#define ROQ_IB2_START(x) ((x) << 8) 91#define ROQ_IB2_START(x) ((x) << 8)
55#define CP_RB_CNTL 0xC104 92#define CP_RB_CNTL 0xC104
56#define RB_BUFSZ(x) ((x)<<0) 93#define RB_BUFSZ(x) ((x) << 0)
57#define RB_BLKSZ(x) ((x)<<8) 94#define RB_BLKSZ(x) ((x) << 8)
58#define RB_NO_UPDATE (1<<27) 95#define RB_NO_UPDATE (1 << 27)
59#define RB_RPTR_WR_ENA (1<<31) 96#define RB_RPTR_WR_ENA (1 << 31)
60#define BUF_SWAP_32BIT (2 << 16) 97#define BUF_SWAP_32BIT (2 << 16)
61#define CP_RB_RPTR 0x8700 98#define CP_RB_RPTR 0x8700
62#define CP_RB_RPTR_ADDR 0xC10C 99#define CP_RB_RPTR_ADDR 0xC10C
@@ -184,9 +221,10 @@
184#define PA_SC_FIFO_SIZE 0x8BCC 221#define PA_SC_FIFO_SIZE 0x8BCC
185#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 222#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
186#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 223#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
224#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
187#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 225#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
188#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 226#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
189#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 227#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
190#define PA_SC_LINE_STIPPLE 0x28A0C 228#define PA_SC_LINE_STIPPLE 0x28A0C
191#define PA_SC_LINE_STIPPLE_STATE 0x8B10 229#define PA_SC_LINE_STIPPLE_STATE 0x8B10
192 230
@@ -203,7 +241,7 @@
203 241
204#define SMX_DC_CTL0 0xA020 242#define SMX_DC_CTL0 0xA020
205#define USE_HASH_FUNCTION (1 << 0) 243#define USE_HASH_FUNCTION (1 << 0)
206#define CACHE_DEPTH(x) ((x) << 1) 244#define NUMBER_OF_SETS(x) ((x) << 1)
207#define FLUSH_ALL_ON_EVENT (1 << 10) 245#define FLUSH_ALL_ON_EVENT (1 << 10)
208#define STALL_ON_EVENT (1 << 11) 246#define STALL_ON_EVENT (1 << 11)
209#define SMX_EVENT_CTL 0xA02C 247#define SMX_EVENT_CTL 0xA02C
@@ -234,6 +272,13 @@
234#define SQ_CONFIG 0x8C00 272#define SQ_CONFIG 0x8C00
235#define VC_ENABLE (1 << 0) 273#define VC_ENABLE (1 << 0)
236#define EXPORT_SRC_C (1 << 1) 274#define EXPORT_SRC_C (1 << 1)
275#define CS_PRIO(x) ((x) << 18)
276#define LS_PRIO(x) ((x) << 20)
277#define HS_PRIO(x) ((x) << 22)
278#define PS_PRIO(x) ((x) << 24)
279#define VS_PRIO(x) ((x) << 26)
280#define GS_PRIO(x) ((x) << 28)
281#define ES_PRIO(x) ((x) << 30)
237#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 282#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
238#define NUM_PS_GPRS(x) ((x) << 0) 283#define NUM_PS_GPRS(x) ((x) << 0)
239#define NUM_VS_GPRS(x) ((x) << 16) 284#define NUM_VS_GPRS(x) ((x) << 16)
@@ -241,6 +286,29 @@
241#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 286#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
242#define NUM_GS_GPRS(x) ((x) << 0) 287#define NUM_GS_GPRS(x) ((x) << 0)
243#define NUM_ES_GPRS(x) ((x) << 16) 288#define NUM_ES_GPRS(x) ((x) << 16)
289#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
290#define NUM_HS_GPRS(x) ((x) << 0)
291#define NUM_LS_GPRS(x) ((x) << 16)
292#define SQ_THREAD_RESOURCE_MGMT 0x8C18
293#define NUM_PS_THREADS(x) ((x) << 0)
294#define NUM_VS_THREADS(x) ((x) << 8)
295#define NUM_GS_THREADS(x) ((x) << 16)
296#define NUM_ES_THREADS(x) ((x) << 24)
297#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
298#define NUM_HS_THREADS(x) ((x) << 0)
299#define NUM_LS_THREADS(x) ((x) << 8)
300#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
301#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
302#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
303#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
304#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
305#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
306#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
307#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
308#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
309#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
310#define SQ_LDS_RESOURCE_MGMT 0x8E2C
311
244#define SQ_MS_FIFO_SIZES 0x8CF0 312#define SQ_MS_FIFO_SIZES 0x8CF0
245#define CACHE_FIFO_SIZE(x) ((x) << 0) 313#define CACHE_FIFO_SIZE(x) ((x) << 0)
246#define FETCH_FIFO_HIWATER(x) ((x) << 8) 314#define FETCH_FIFO_HIWATER(x) ((x) << 8)
@@ -255,6 +323,15 @@
255#define SMX_BUFFER_SIZE(x) ((x) << 16) 323#define SMX_BUFFER_SIZE(x) ((x) << 16)
256#define SX_MISC 0x28350 324#define SX_MISC 0x28350
257 325
326#define CB_PERF_CTR0_SEL_0 0x9A20
327#define CB_PERF_CTR0_SEL_1 0x9A24
328#define CB_PERF_CTR1_SEL_0 0x9A28
329#define CB_PERF_CTR1_SEL_1 0x9A2C
330#define CB_PERF_CTR2_SEL_0 0x9A30
331#define CB_PERF_CTR2_SEL_1 0x9A34
332#define CB_PERF_CTR3_SEL_0 0x9A38
333#define CB_PERF_CTR3_SEL_1 0x9A3C
334
258#define TA_CNTL_AUX 0x9508 335#define TA_CNTL_AUX 0x9508
259#define DISABLE_CUBE_WRAP (1 << 0) 336#define DISABLE_CUBE_WRAP (1 << 0)
260#define DISABLE_CUBE_ANISO (1 << 1) 337#define DISABLE_CUBE_ANISO (1 << 1)
@@ -263,7 +340,7 @@
263#define SYNC_ALIGNER (1 << 26) 340#define SYNC_ALIGNER (1 << 26)
264 341
265#define VGT_CACHE_INVALIDATION 0x88C4 342#define VGT_CACHE_INVALIDATION 0x88C4
266#define CACHE_INVALIDATION(x) ((x)<<0) 343#define CACHE_INVALIDATION(x) ((x) << 0)
267#define VC_ONLY 0 344#define VC_ONLY 0
268#define TC_ONLY 1 345#define TC_ONLY 1
269#define VC_AND_TC 2 346#define VC_AND_TC 2
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4ac97ab28947..a77a86203996 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -870,11 +870,36 @@ struct rv770_asic {
870 struct r100_gpu_lockup lockup; 870 struct r100_gpu_lockup lockup;
871}; 871};
872 872
873struct evergreen_asic {
874 unsigned num_ses;
875 unsigned max_pipes;
876 unsigned max_tile_pipes;
877 unsigned max_simds;
878 unsigned max_backends;
879 unsigned max_gprs;
880 unsigned max_threads;
881 unsigned max_stack_entries;
882 unsigned max_hw_contexts;
883 unsigned max_gs_threads;
884 unsigned sx_max_export_size;
885 unsigned sx_max_export_pos_size;
886 unsigned sx_max_export_smx_size;
887 unsigned sq_num_cf_insts;
888 unsigned sx_num_of_sets;
889 unsigned sc_prim_fifo_size;
890 unsigned sc_hiz_tile_fifo_size;
891 unsigned sc_earlyz_tile_fifo_size;
892 unsigned tiling_nbanks;
893 unsigned tiling_npipes;
894 unsigned tiling_group_size;
895};
896
873union radeon_asic_config { 897union radeon_asic_config {
874 struct r300_asic r300; 898 struct r300_asic r300;
875 struct r100_asic r100; 899 struct r100_asic r100;
876 struct r600_asic r600; 900 struct r600_asic r600;
877 struct rv770_asic rv770; 901 struct rv770_asic rv770;
902 struct evergreen_asic evergreen;
878}; 903};
879 904
880/* 905/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 12:36:26 -0500