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authorJamie Iles <jamie@jamieiles.com>2011-08-01 12:25:19 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2011-08-10 07:00:26 -0400
commit30343ef1de348cd21cd7d0cebde3c0175b730e0b (patch)
treef70c2ba846c1f664a7be2e1f2d9b39d4c83c6996
parent4efae8c9363e28892eaaf2a6463f2f5f255e6fb0 (diff)
crypto: picoxcell - support for device tree matching
Allow the crypto engines to be matched from device tree bindings. Cc: devicetree-discuss@lists.ozlabs.org Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r--Documentation/devicetree/bindings/crypto/picochip-spacc.txt23
-rw-r--r--drivers/crypto/picoxcell_crypto.c36
2 files changed, 53 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
new file mode 100644
index 000000000000..d8609ece1f4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
@@ -0,0 +1,23 @@
1Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
2
3Picochip picoXcell devices contain crypto offload engines that may be used for
4IPSEC and femtocell layer 2 ciphering.
5
6Required properties:
7 - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
8 "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
9 - reg : Offset and length of the register set for this device
10 - interrupt-parent : The interrupt controller that controls the SPAcc
11 interrupt.
12 - interrupts : The interrupt line from the SPAcc.
13 - ref-clock : The input clock that drives the SPAcc.
14
15Example SPAcc node:
16
17spacc@10000 {
18 compatible = "picochip,spacc-ipsec";
19 reg = <0x100000 0x10000>;
20 interrupt-parent = <&vic0>;
21 interrupts = <24>;
22 ref-clock = <&ipsec_clk>, "ref";
23};
diff --git a/drivers/crypto/picoxcell_crypto.c b/drivers/crypto/picoxcell_crypto.c
index d119e0e32f23..017340c3b715 100644
--- a/drivers/crypto/picoxcell_crypto.c
+++ b/drivers/crypto/picoxcell_crypto.c
@@ -34,6 +34,7 @@
34#include <linux/io.h> 34#include <linux/io.h>
35#include <linux/list.h> 35#include <linux/list.h>
36#include <linux/module.h> 36#include <linux/module.h>
37#include <linux/of.h>
37#include <linux/platform_device.h> 38#include <linux/platform_device.h>
38#include <linux/pm.h> 39#include <linux/pm.h>
39#include <linux/rtnetlink.h> 40#include <linux/rtnetlink.h>
@@ -1657,27 +1658,49 @@ static struct spacc_alg l2_engine_algs[] = {
1657 }, 1658 },
1658}; 1659};
1659 1660
1661#ifdef CONFIG_OF
1662static const struct of_device_id spacc_of_id_table[] = {
1663 { .compatible = "picochip,spacc-ipsec" },
1664 { .compatible = "picochip,spacc-l2" },
1665 {}
1666};
1667#else /* CONFIG_OF */
1668#define spacc_of_id_table NULL
1669#endif /* CONFIG_OF */
1670
1671static bool spacc_is_compatible(struct platform_device *pdev,
1672 const char *spacc_type)
1673{
1674 const struct platform_device_id *platid = platform_get_device_id(pdev);
1675
1676 if (platid && !strcmp(platid->name, spacc_type))
1677 return true;
1678
1679#ifdef CONFIG_OF
1680 if (of_device_is_compatible(pdev->dev.of_node, spacc_type))
1681 return true;
1682#endif /* CONFIG_OF */
1683
1684 return false;
1685}
1686
1660static int __devinit spacc_probe(struct platform_device *pdev) 1687static int __devinit spacc_probe(struct platform_device *pdev)
1661{ 1688{
1662 int i, err, ret = -EINVAL; 1689 int i, err, ret = -EINVAL;
1663 struct resource *mem, *irq; 1690 struct resource *mem, *irq;
1664 const struct platform_device_id *platid = platform_get_device_id(pdev);
1665 struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine), 1691 struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine),
1666 GFP_KERNEL); 1692 GFP_KERNEL);
1667 if (!engine) 1693 if (!engine)
1668 return -ENOMEM; 1694 return -ENOMEM;
1669 1695
1670 if (!platid) 1696 if (spacc_is_compatible(pdev, "picochip,spacc-ipsec")) {
1671 return -EINVAL;
1672
1673 if (!strcmp(platid->name, "picoxcell-ipsec")) {
1674 engine->max_ctxs = SPACC_CRYPTO_IPSEC_MAX_CTXS; 1697 engine->max_ctxs = SPACC_CRYPTO_IPSEC_MAX_CTXS;
1675 engine->cipher_pg_sz = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ; 1698 engine->cipher_pg_sz = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ;
1676 engine->hash_pg_sz = SPACC_CRYPTO_IPSEC_HASH_PG_SZ; 1699 engine->hash_pg_sz = SPACC_CRYPTO_IPSEC_HASH_PG_SZ;
1677 engine->fifo_sz = SPACC_CRYPTO_IPSEC_FIFO_SZ; 1700 engine->fifo_sz = SPACC_CRYPTO_IPSEC_FIFO_SZ;
1678 engine->algs = ipsec_engine_algs; 1701 engine->algs = ipsec_engine_algs;
1679 engine->num_algs = ARRAY_SIZE(ipsec_engine_algs); 1702 engine->num_algs = ARRAY_SIZE(ipsec_engine_algs);
1680 } else if (!strcmp(platid->name, "picoxcell-l2")) { 1703 } else if (spacc_is_compatible(pdev, "picochip,spacc-l2")) {
1681 engine->max_ctxs = SPACC_CRYPTO_L2_MAX_CTXS; 1704 engine->max_ctxs = SPACC_CRYPTO_L2_MAX_CTXS;
1682 engine->cipher_pg_sz = SPACC_CRYPTO_L2_CIPHER_PG_SZ; 1705 engine->cipher_pg_sz = SPACC_CRYPTO_L2_CIPHER_PG_SZ;
1683 engine->hash_pg_sz = SPACC_CRYPTO_L2_HASH_PG_SZ; 1706 engine->hash_pg_sz = SPACC_CRYPTO_L2_HASH_PG_SZ;
@@ -1826,6 +1849,7 @@ static struct platform_driver spacc_driver = {
1826#ifdef CONFIG_PM 1849#ifdef CONFIG_PM
1827 .pm = &spacc_pm_ops, 1850 .pm = &spacc_pm_ops,
1828#endif /* CONFIG_PM */ 1851#endif /* CONFIG_PM */
1852 .of_match_table = spacc_of_id_table,
1829 }, 1853 },
1830 .id_table = spacc_id_table, 1854 .id_table = spacc_id_table,
1831}; 1855};