ARM: add Armada 1500 and Sony NSZ-GS7 device tree files

This adds very basic device tree files for the Marvell Armada 1500 SoC
(Berlin BG2) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
device comprising the Armada 1500 SoC above.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>

4 files changed, 282 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
new file mode 100644
index 000000000000..737afa5f8148
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -0,0 +1,24 @@
+Marvell Berlin SoC Family Device Tree Bindings
+---------------------------------------------------------------
+
+Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
+shall have the following properties:
+
+* Required root node properties:
+compatible: must contain "marvell,berlin"
+
+In addition, the above compatible shall be extended with the specific
+SoC and board used. Currently known SoC compatibles are:
+    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
+    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
+    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
+    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)
+
+* Example:
+
+/ {
+        model = "Sony NSZ-GS7";
+        compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+        ...
+}
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a65b24f..7d06d64e2953 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -45,6 +45,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
         bcm28155-ap.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BERLIN) += \
+        berlin2-sony-nsz-gs7.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
         da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
new file mode 100644
index 000000000000..c72bfd468d10
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -0,0 +1,29 @@
+/*
+ * Device Tree file for Sony NSZ-GS7
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "berlin2.dtsi"
+
+/ {
+        model = "Sony NSZ-GS7";
+        compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>; /* 1 GB */
+        };
+};
+
+&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
new file mode 100644
index 000000000000..56a1af2f1052
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -0,0 +1,227 @@
+/*
+ * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
+ *
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ *  (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        model = "Marvell Armada 1500 (BG2) SoC";
+        compatible = "marvell,berlin2", "marvell,berlin";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "marvell,pj4b";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "marvell,pj4b";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <1>;
+                };
+        };
+
+        clocks {
+                smclk: sysmgr-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+
+                cfgclk: cfg-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <100000000>;
+                };
+
+                sysclk: system-clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <400000000>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&gic>;
+
+                ranges = <0 0xf7000000 0x1000000>;
+
+                l2: l2-cache-controller@ac0000 {
+                        compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+                        reg = <0xac0000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                gic: interrupt-controller@ad1000 {
+                        compatible = "arm,cortex-a9-gic";
+                        reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                };
+
+                local-timer@ad0600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xad0600 0x20>;
+                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&sysclk>;
+                };
+
+                apb@e80000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        ranges = <0 0xe80000 0x10000>;
+                        interrupt-parent = <&aic>;
+
+                        timer0: timer@2c00 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c00 0x14>;
+                                interrupts = <8>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "okay";
+                        };
+
+                        timer1: timer@2c14 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c14 0x14>;
+                                interrupts = <9>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "okay";
+                        };
+
+                        timer2: timer@2c28 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c28 0x14>;
+                                interrupts = <10>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer3: timer@2c3c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c3c 0x14>;
+                                interrupts = <11>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer4: timer@2c50 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c50 0x14>;
+                                interrupts = <12>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer5: timer@2c64 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c64 0x14>;
+                                interrupts = <13>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer6: timer@2c78 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c78 0x14>;
+                                interrupts = <14>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        timer7: timer@2c8c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c8c 0x14>;
+                                interrupts = <15>;
+                                clocks = <&cfgclk>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+
+                        aic: interrupt-controller@3000 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0x3000 0xc00>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                apb@fc0000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        ranges = <0 0xfc0000 0x10000>;
+                        interrupt-parent = <&sic>;
+
+                        uart0: serial@9000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x9000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <8>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        uart1: serial@a000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0xa000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <9>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        uart2: serial@b000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0xb000 0x100>;
+                                reg-shift = <2>;
+                                reg-io-width = <1>;
+                                interrupts = <10>;
+                                clocks = <&smclk>;
+                                status = "disabled";
+                        };
+
+                        sic: interrupt-controller@e000 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0xe000 0x400>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+        };
+};