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authorRafał Miłecki <zajec5@gmail.com>2012-09-25 04:17:22 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-09-28 13:54:02 -0400
commit1fd41a65f19bdabb31549af00ce23d4c5c14781a (patch)
tree7fcb424f7ca6c58aa886062ba4ea3a81f6efde54
parentf1b98bb367f672ee78800fa62880b522bef86eed (diff)
bcma: change delays to follow timers-howto guide
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/bcma/core.c2
-rw-r--r--drivers/bcma/driver_chipcommon_pmu.c5
-rw-r--r--drivers/bcma/driver_pci.c6
-rw-r--r--drivers/bcma/driver_pci_host.c8
4 files changed, 12 insertions, 9 deletions
diff --git a/drivers/bcma/core.c b/drivers/bcma/core.c
index 63c8b470536f..03bbe104338f 100644
--- a/drivers/bcma/core.c
+++ b/drivers/bcma/core.c
@@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma_device *core,
65 switch (clkmode) { 65 switch (clkmode) {
66 case BCMA_CLKMODE_FAST: 66 case BCMA_CLKMODE_FAST:
67 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); 67 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
68 udelay(64); 68 usleep_range(64, 300);
69 for (i = 0; i < 1500; i++) { 69 for (i = 0; i < 1500; i++) {
70 if (bcma_read32(core, BCMA_CLKCTLST) & 70 if (bcma_read32(core, BCMA_CLKCTLST) &
71 BCMA_CLKCTLST_HAVEHT) { 71 BCMA_CLKCTLST_HAVEHT) {
diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c
index 8b8f2f3862a2..201faf106b3f 100644
--- a/drivers/bcma/driver_chipcommon_pmu.c
+++ b/drivers/bcma/driver_chipcommon_pmu.c
@@ -76,7 +76,10 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
76 if (max_msk) 76 if (max_msk)
77 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); 77 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
78 78
79 /* Add some delay; allow resources to come up and settle. */ 79 /*
80 * Add some delay; allow resources to come up and settle.
81 * Delay is required for SoC (early init).
82 */
80 mdelay(2); 83 mdelay(2);
81} 84}
82 85
diff --git a/drivers/bcma/driver_pci.c b/drivers/bcma/driver_pci.c
index c32ebd537abe..c39ee6d45850 100644
--- a/drivers/bcma/driver_pci.c
+++ b/drivers/bcma/driver_pci.c
@@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
51 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); 51 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
52 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) 52 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
53 break; 53 break;
54 msleep(1); 54 usleep_range(1000, 2000);
55 } 55 }
56} 56}
57 57
@@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
92 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); 92 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
93 break; 93 break;
94 } 94 }
95 msleep(1); 95 usleep_range(1000, 2000);
96 } 96 }
97 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); 97 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
98 return ret; 98 return ret;
@@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
132 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); 132 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
133 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) 133 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
134 break; 134 break;
135 msleep(1); 135 usleep_range(1000, 2000);
136 } 136 }
137 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); 137 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
138} 138}
diff --git a/drivers/bcma/driver_pci_host.c b/drivers/bcma/driver_pci_host.c
index cbae2c231336..9baf886e82df 100644
--- a/drivers/bcma/driver_pci_host.c
+++ b/drivers/bcma/driver_pci_host.c
@@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
425 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; 425 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
426 426
427 /* Reset RC */ 427 /* Reset RC */
428 udelay(3000); 428 usleep_range(3000, 5000);
429 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); 429 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
430 udelay(1000); 430 usleep_range(1000, 2000);
431 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | 431 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
432 BCMA_CORE_PCI_CTL_RST_OE); 432 BCMA_CORE_PCI_CTL_RST_OE);
433 433
@@ -481,7 +481,7 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
481 * before issuing configuration requests to PCI Express 481 * before issuing configuration requests to PCI Express
482 * devices. 482 * devices.
483 */ 483 */
484 udelay(100000); 484 msleep(100);
485 485
486 bcma_core_pci_enable_crs(pc); 486 bcma_core_pci_enable_crs(pc);
487 487
@@ -501,7 +501,7 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
501 set_io_port_base(pc_host->pci_controller.io_map_base); 501 set_io_port_base(pc_host->pci_controller.io_map_base);
502 /* Give some time to the PCI controller to configure itself with the new 502 /* Give some time to the PCI controller to configure itself with the new
503 * values. Not waiting at this point causes crashes of the machine. */ 503 * values. Not waiting at this point causes crashes of the machine. */
504 mdelay(10); 504 usleep_range(10000, 15000);
505 register_pci_controller(&pc_host->pci_controller); 505 register_pci_controller(&pc_host->pci_controller);
506 return; 506 return;
507} 507}