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authorNick Hoath <nicholas.hoath@intel.com>2015-02-05 05:47:19 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-13 17:28:08 -0500
commit1de4582f98db7eafd12695139aed7df6a0a0ff3a (patch)
tree37583e5d8685dbc35c51989814b226555148e817
parentab0dfafefd85b0abf61f0efad769803bee8e49fb (diff)
drm/i915/gen9: Implement WaDisableDgMirrorFixInHalfSliceChicken5
Move WaDisableDgMirrorFixInHalfSliceChicken5 to gen9_init_workarounds v2: Added stepping check v3: Removed unused register bitmap Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> [danvet: Bikesheds.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c8
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c10
2 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bebefe79f7ce..2b89aacdda90 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -63,14 +63,6 @@ static void gen9_init_clock_gating(struct drm_device *dev)
63 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 63 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
64 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 64 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
65 65
66 /*
67 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
68 * This is a pre-production w/a.
69 */
70 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
71 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
72 ~GEN9_DG_MIRROR_FIX_ENABLE);
73
74 /* Wa4x4STCOptimizationDisable:skl */ 66 /* Wa4x4STCOptimizationDisable:skl */
75 I915_WRITE(CACHE_MODE_1, 67 I915_WRITE(CACHE_MODE_1,
76 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); 68 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b869f1c68753..248db5157e02 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -882,6 +882,16 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
882 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 882 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
883 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 883 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
884 884
885 if (INTEL_REVID(dev) == SKL_REVID_A0) {
886 /*
887 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
888 * This is a pre-production w/a.
889 */
890 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
891 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
892 ~GEN9_DG_MIRROR_FIX_ENABLE);
893 }
894
885 return 0; 895 return 0;
886} 896}
887 897