aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:30:30 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-21 15:30:30 -0500
commit18a8d49973667aa016e68826eeb374788b7c63b0 (patch)
treed7f90fcf05087ce50ee931b596e60e4c3c082a29
parentc189cb8ef62832f33b6cf757350a0270532a1ad8 (diff)
parentec02ace8ca0a50eef430d3676de5c5fa978b0e29 (diff)
Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
Diffstat
-rw-r--r--Documentation/clk.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos7-clock.txt15
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt10
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,lcc.txt21
-rw-r--r--Documentation/devicetree/bindings/clock/qoriq-clock.txt5
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt33
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt12
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt43
-rw-r--r--Documentation/devicetree/bindings/clock/ti,cdce706.txt42
-rw-r--r--Documentation/devicetree/bindings/clock/ti/fapll.txt33
-rw-r--r--Documentation/devicetree/bindings/mmc/sunxi-mmc.txt8
-rw-r--r--MAINTAINERS5
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi72
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi54
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi44
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi86
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi72
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi96
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c3688
-rw-r--r--arch/arm/mach-omap2/clock.c16
-rw-r--r--arch/arm/mach-omap2/clock.h14
-rw-r--r--arch/arm/mach-omap2/clock_common_data.c11
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c13
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c2
-rw-r--r--arch/arm/mach-omap2/io.c26
-rw-r--r--arch/arm/mach-omap2/prm.h1
-rw-r--r--arch/arm/mach-omap2/prm_common.c11
-rw-r--r--arch/arm/mach-tegra/tegra.c2
-rw-r--r--arch/mips/alchemy/common/clock.c6
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig1
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig1
-rw-r--r--arch/powerpc/kernel/time.c5
-rw-r--r--arch/powerpc/platforms/512x/clock-commonclk.c11
-rw-r--r--drivers/clk/Kconfig18
-rw-r--r--drivers/clk/Makefile4
-rw-r--r--drivers/clk/at91/clk-programmable.c2
-rw-r--r--drivers/clk/bcm/clk-kona.c2
-rw-r--r--drivers/clk/clk-asm9260.c348
-rw-r--r--drivers/clk/clk-cdce706.c700
-rw-r--r--drivers/clk/clk-composite.c29
-rw-r--r--drivers/clk/clk-divider.c228
-rw-r--r--drivers/clk/clk-gate.c18
-rw-r--r--drivers/clk/clk-mux.c16
-rw-r--r--drivers/clk/clk-qoriq.c (renamed from drivers/clk/clk-ppc-corenet.c)178
-rw-r--r--drivers/clk/clk.c1009
-rw-r--r--drivers/clk/clk.h24
-rw-r--r--drivers/clk/clkdev.c110
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c2
-rw-r--r--drivers/clk/mmp/clk-mix.c2
-rw-r--r--drivers/clk/pxa/Makefile1
-rw-r--r--drivers/clk/pxa/clk-pxa.c2
-rw-r--r--drivers/clk/pxa/clk-pxa3xx.c364
-rw-r--r--drivers/clk/qcom/Kconfig18
-rw-r--r--drivers/clk/qcom/Makefile4
-rw-r--r--drivers/clk/qcom/clk-pll.c1
-rw-r--r--drivers/clk/qcom/clk-rcg.c10
-rw-r--r--drivers/clk/qcom/clk-rcg2.c6
-rw-r--r--drivers/clk/qcom/clk-regmap-divider.c70
-rw-r--r--drivers/clk/qcom/clk-regmap-divider.h29
-rw-r--r--drivers/clk/qcom/clk-regmap-mux.c59
-rw-r--r--drivers/clk/qcom/clk-regmap-mux.h29
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c12
-rw-r--r--drivers/clk/qcom/lcc-ipq806x.c473
-rw-r--r--drivers/clk/qcom/lcc-msm8960.c585
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c48
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c32
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c217
-rw-r--r--drivers/clk/samsung/clk-exynos4.c10
-rw-r--r--drivers/clk/samsung/clk-exynos4415.c216
-rw-r--r--drivers/clk/samsung/clk-exynos7.c408
-rw-r--r--drivers/clk/samsung/clk.c13
-rw-r--r--drivers/clk/samsung/clk.h3
-rw-r--r--drivers/clk/shmobile/Makefile2
-rw-r--r--drivers/clk/shmobile/clk-div6.c18
-rw-r--r--drivers/clk/shmobile/clk-r8a73a4.c241
-rw-r--r--drivers/clk/shmobile/clk-rcar-gen2.c88
-rw-r--r--drivers/clk/st/clk-flexgen.c39
-rw-r--r--drivers/clk/st/clkgen-mux.c14
-rw-r--r--drivers/clk/sunxi/Makefile1
-rw-r--r--drivers/clk/sunxi/clk-factors.c12
-rw-r--r--drivers/clk/sunxi/clk-factors.h7
-rw-r--r--drivers/clk/sunxi/clk-mod0.c224
-rw-r--r--drivers/clk/sunxi/clk-sun6i-ar100.c2
-rw-r--r--drivers/clk/sunxi/clk-sun8i-mbus.c13
-rw-r--r--drivers/clk/sunxi/clk-sun9i-core.c119
-rw-r--r--drivers/clk/sunxi/clk-sun9i-mmc.c219
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c262
-rw-r--r--drivers/clk/tegra/Makefile1
-rw-r--r--drivers/clk/tegra/clk-id.h2
-rw-r--r--drivers/clk/tegra/clk-periph.c14
-rw-r--r--drivers/clk/tegra/clk-pll.c18
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c18
-rw-r--r--drivers/clk/tegra/clk-tegra114.c10
-rw-r--r--drivers/clk/tegra/clk-tegra124.c168
-rw-r--r--drivers/clk/tegra/clk.c7
-rw-r--r--drivers/clk/ti/Makefile8
-rw-r--r--drivers/clk/ti/clk-3xxx-legacy.c4653
-rw-r--r--drivers/clk/ti/clk-3xxx.c8
-rw-r--r--drivers/clk/ti/clk-44xx.c2
-rw-r--r--drivers/clk/ti/clk-54xx.c2
-rw-r--r--drivers/clk/ti/clk-7xx.c2
-rw-r--r--drivers/clk/ti/clk-816x.c53
-rw-r--r--drivers/clk/ti/clk.c127
-rw-r--r--drivers/clk/ti/clock.h172
-rw-r--r--drivers/clk/ti/composite.c48
-rw-r--r--drivers/clk/ti/divider.c132
-rw-r--r--drivers/clk/ti/dpll.c121
-rw-r--r--drivers/clk/ti/fapll.c410
-rw-r--r--drivers/clk/ti/gate.c163
-rw-r--r--drivers/clk/ti/interface.c98
-rw-r--r--drivers/clk/ti/mux.c70
-rw-r--r--drivers/clk/ux500/clk-prcc.c1
-rw-r--r--drivers/clk/ux500/clk-prcmu.c1
-rw-r--r--drivers/clk/zynq/clkc.c1
-rw-r--r--drivers/cpufreq/Kconfig.powerpc2
-rw-r--r--drivers/mmc/host/sunxi-mmc.c63
-rw-r--r--include/dt-bindings/clock/alphascale,asm9260.h97
-rw-r--r--include/dt-bindings/clock/exynos4.h7
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h88
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq806x.h1
-rw-r--r--include/dt-bindings/clock/qcom,lcc-ipq806x.h30
-rw-r--r--include/dt-bindings/clock/qcom,lcc-msm8960.h50
-rw-r--r--include/dt-bindings/clock/tegra124-car-common.h345
-rw-r--r--include/dt-bindings/clock/tegra124-car.h345
-rw-r--r--include/linux/clk-private.h220
-rw-r--r--include/linux/clk-provider.h58
-rw-r--r--include/linux/clk.h45
-rw-r--r--include/linux/clk/sunxi.h22
-rw-r--r--include/linux/clk/tegra.h2
-rw-r--r--include/linux/clk/ti.h25
132 files changed, 13039 insertions, 5696 deletions
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 4ff84623d5e1..0e4f90aa1c13 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -73,6 +73,8 @@ the operations defined in clk.h:
73 unsigned long *parent_rate); 73 unsigned long *parent_rate);
74 long (*determine_rate)(struct clk_hw *hw, 74 long (*determine_rate)(struct clk_hw *hw,
75 unsigned long rate, 75 unsigned long rate,
76 unsigned long min_rate,
77 unsigned long max_rate,
76 unsigned long *best_parent_rate, 78 unsigned long *best_parent_rate,
77 struct clk_hw **best_parent_clk); 79 struct clk_hw **best_parent_clk);
78 int (*set_parent)(struct clk_hw *hw, u8 index); 80 int (*set_parent)(struct clk_hw *hw, u8 index);
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f80c1c3..6bf1e7493f61 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -34,6 +34,8 @@ Required Properties for Clock Controller:
34 - "samsung,exynos7-clock-peris" 34 - "samsung,exynos7-clock-peris"
35 - "samsung,exynos7-clock-fsys0" 35 - "samsung,exynos7-clock-fsys0"
36 - "samsung,exynos7-clock-fsys1" 36 - "samsung,exynos7-clock-fsys1"
37 - "samsung,exynos7-clock-mscl"
38 - "samsung,exynos7-clock-aud"
37 39
38 - reg: physical base address of the controller and the length of 40 - reg: physical base address of the controller and the length of
39 memory mapped region. 41 memory mapped region.
@@ -53,6 +55,7 @@ Input clocks for top0 clock controller:
53 - dout_sclk_bus1_pll 55 - dout_sclk_bus1_pll
54 - dout_sclk_cc_pll 56 - dout_sclk_cc_pll
55 - dout_sclk_mfc_pll 57 - dout_sclk_mfc_pll
58 - dout_sclk_aud_pll
56 59
57Input clocks for top1 clock controller: 60Input clocks for top1 clock controller:
58 - fin_pll 61 - fin_pll
@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller:
76 - sclk_uart1 79 - sclk_uart1
77 - sclk_uart2 80 - sclk_uart2
78 - sclk_uart3 81 - sclk_uart3
82 - sclk_spi0
83 - sclk_spi1
84 - sclk_spi2
85 - sclk_spi3
86 - sclk_spi4
87 - sclk_i2s1
88 - sclk_pcm1
89 - sclk_spdif
79 90
80Input clocks for peris clock controller: 91Input clocks for peris clock controller:
81 - fin_pll 92 - fin_pll
@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller:
91 - dout_aclk_fsys1_200 102 - dout_aclk_fsys1_200
92 - dout_sclk_mmc0 103 - dout_sclk_mmc0
93 - dout_sclk_mmc1 104 - dout_sclk_mmc1
105
106Input clocks for aud clock controller:
107 - fin_pll
108 - fout_aud_pll
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
index ded5d6212c84..c6620bc96703 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
@@ -1,4 +1,4 @@
1NVIDIA Tegra124 Clock And Reset Controller 1NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
2 2
3This binding uses the common clock binding: 3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt 4Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -7,14 +7,16 @@ The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates. 7for muxing and gating Tegra's clocks, and setting their rates.
8 8
9Required properties : 9Required properties :
10- compatible : Should be "nvidia,tegra124-car" 10- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11- reg : Should contain CAR registers location and length 11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks: 12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc". 13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1. 14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the 15 In clock consumers, this cell represents the clock ID exposed by the
16 CAR. The assignments may be found in header file 16 CAR. The assignments may be found in the header files
17 <dt-bindings/clock/tegra124-car.h>. 17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
18- #reset-cells : Should be 1. 20- #reset-cells : Should be 1.
19 In clock consumers, this cell represents the bit number in the CAR's 21 In clock consumers, this cell represents the bit number in the CAR's
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. 22 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.txt b/Documentation/devicetree/bindings/clock/qcom,lcc.txt
new file mode 100644
index 000000000000..dd755be63a01
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,lcc.txt
@@ -0,0 +1,21 @@
1Qualcomm LPASS Clock & Reset Controller Binding
2------------------------------------------------
3
4Required properties :
5- compatible : shall contain only one of the following:
6
7 "qcom,lcc-msm8960"
8 "qcom,lcc-apq8064"
9 "qcom,lcc-ipq8064"
10
11- reg : shall contain base register location and length
12- #clock-cells : shall contain 1
13- #reset-cells : shall contain 1
14
15Example:
16 clock-controller@28000000 {
17 compatible = "qcom,lcc-ipq8064";
18 reg = <0x28000000 0x1000>;
19 #clock-cells = <1>;
20 #reset-cells = <1>;
21 };
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 266ff9d23229..df4a259a6898 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -1,6 +1,6 @@
1* Clock Block on Freescale CoreNet Platforms 1* Clock Block on Freescale QorIQ Platforms
2 2
3Freescale CoreNet chips take primary clocking input from the external 3Freescale qoriq chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using 4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies 5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including 6which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties:
29 * "fsl,t4240-clockgen" 29 * "fsl,t4240-clockgen"
30 * "fsl,b4420-clockgen" 30 * "fsl,b4420-clockgen"
31 * "fsl,b4860-clockgen" 31 * "fsl,b4860-clockgen"
32 * "fsl,ls1021a-clockgen"
32 Chassis clock strings include: 33 Chassis clock strings include:
33 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks 34 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
34 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks 35 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 2e18676bd4b5..0a80fa70ca26 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -11,6 +11,7 @@ Required Properties:
11 11
12 - compatible: Must be one of the following 12 - compatible: Must be one of the following
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks 13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
14 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks 15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
15 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks 16 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
16 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks 17 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
new file mode 100644
index 000000000000..ece92393e80d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
@@ -0,0 +1,33 @@
1* Renesas R8A73A4 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
4and several fixed ratio dividers.
5
6Required Properties:
7
8 - compatible: Must be "renesas,r8a73a4-cpg-clocks"
9
10 - reg: Base address and length of the memory resource used by the CPG
11
12 - clocks: Reference to the parent clocks ("extal1" and "extal2")
13
14 - #clock-cells: Must be 1
15
16 - clock-output-names: The names of the clocks. Supported clocks are "main",
17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
18 "m1", "m2", "zx", "zs", and "hp".
19
20
21Example
22-------
23
24 cpg_clocks: cpg_clocks@e6150000 {
25 compatible = "renesas,r8a73a4-cpg-clocks";
26 reg = <0 0xe6150000 0 0x10000>;
27 clocks = <&extal1_clk>, <&extal2_clk>;
28 #clock-cells = <1>;
29 clock-output-names = "main", "pll0", "pll1", "pll2",
30 "pll2s", "pll2h", "z", "z2",
31 "i", "m3", "b", "m1", "m2",
32 "zx", "zs", "hp";
33 };
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index e6ad35b894f9..b02944fba9de 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -8,15 +8,18 @@ Required Properties:
8 - compatible: Must be one of 8 - compatible: Must be one of
9 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG 9 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
10 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG 10 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
11 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
11 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG 12 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
12 - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG 13 - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
13 14
14 - reg: Base address and length of the memory resource used by the CPG 15 - reg: Base address and length of the memory resource used by the CPG
15 16
16 - clocks: Reference to the parent clock 17 - clocks: References to the parent clocks: first to the EXTAL clock, second
18 to the USB_EXTAL clock
17 - #clock-cells: Must be 1 19 - #clock-cells: Must be 1
18 - clock-output-names: The names of the clocks. Supported clocks are "main", 20 - clock-output-names: The names of the clocks. Supported clocks are "main",
19 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z" 21 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
22 "adsp"
20 23
21 24
22Example 25Example
@@ -26,8 +29,9 @@ Example
26 compatible = "renesas,r8a7790-cpg-clocks", 29 compatible = "renesas,r8a7790-cpg-clocks",
27 "renesas,rcar-gen2-cpg-clocks"; 30 "renesas,rcar-gen2-cpg-clocks";
28 reg = <0 0xe6150000 0 0x1000>; 31 reg = <0 0xe6150000 0 0x1000>;
29 clocks = <&extal_clk>; 32 clocks = <&extal_clk &usb_extal_clk>;
30 #clock-cells = <1>; 33 #clock-cells = <1>;
31 clock-output-names = "main", "pll0, "pll1", "pll3", 34 clock-output-names = "main", "pll0, "pll1", "pll3",
32 "lb", "qspi", "sdh", "sd0", "sd1", "z"; 35 "lb", "qspi", "sdh", "sd0", "sd1", "z",
36 "rcan", "adsp";
33 }; 37 };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 67b2b99f2b33..60b44285250d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -26,7 +26,7 @@ Required properties:
26 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s 26 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
27 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 27 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
28 "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 28 "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
29 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 29 "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
30 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 30 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
31 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 31 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
32 "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 32 "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
@@ -55,9 +55,11 @@ Required properties:
55 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 55 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
56 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 56 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
57 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 57 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
58 "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 58 "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
59 "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 59 "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
60 "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
60 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks 61 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
62 "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
61 "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 63 "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
62 "allwinner,sun7i-a20-out-clk" - for the external output clocks 64 "allwinner,sun7i-a20-out-clk" - for the external output clocks
63 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 65 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
@@ -73,7 +75,9 @@ Required properties for all clocks:
73- #clock-cells : from common clock binding; shall be set to 0 except for 75- #clock-cells : from common clock binding; shall be set to 0 except for
74 the following compatibles where it shall be set to 1: 76 the following compatibles where it shall be set to 1:
75 "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", 77 "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
76 "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk" 78 "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
79 "allwinner,*-usb-clk", "allwinner,*-mmc-clk",
80 "allwinner,*-mmc-config-clk"
77- clock-output-names : shall be the corresponding names of the outputs. 81- clock-output-names : shall be the corresponding names of the outputs.
78 If the clock module only has one output, the name shall be the 82 If the clock module only has one output, the name shall be the
79 module name. 83 module name.
@@ -81,6 +85,10 @@ Required properties for all clocks:
81And "allwinner,*-usb-clk" clocks also require: 85And "allwinner,*-usb-clk" clocks also require:
82- reset-cells : shall be set to 1 86- reset-cells : shall be set to 1
83 87
88The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
89- #reset-cells : shall be set to 1
90- resets : shall be the reset control phandle for the mmc block.
91
84For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate 92For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
85dummy clocks at 25 MHz and 125 MHz, respectively. See example. 93dummy clocks at 25 MHz and 125 MHz, respectively. See example.
86 94
@@ -95,6 +103,14 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
95is the normal PLL6 output, or "pll6". The second output is rate doubled 103is the normal PLL6 output, or "pll6". The second output is rate doubled
96PLL6, or "pll6x2". 104PLL6, or "pll6x2".
97 105
106The "allwinner,*-mmc-clk" clocks have three different outputs: the
107main clock, with the ID 0, and the output and sample clocks, with the
108IDs 1 and 2, respectively.
109
110The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
111per mmc controller. The number of outputs is determined by the size of
112the address block, which is related to the overall mmc block.
113
98For example: 114For example:
99 115
100osc24M: clk@01c20050 { 116osc24M: clk@01c20050 {
@@ -138,11 +154,11 @@ cpu: cpu@01c20054 {
138}; 154};
139 155
140mmc0_clk: clk@01c20088 { 156mmc0_clk: clk@01c20088 {
141 #clock-cells = <0>; 157 #clock-cells = <1>;
142 compatible = "allwinner,sun4i-mod0-clk"; 158 compatible = "allwinner,sun4i-a10-mmc-clk";
143 reg = <0x01c20088 0x4>; 159 reg = <0x01c20088 0x4>;
144 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 160 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
145 clock-output-names = "mmc0"; 161 clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
146}; 162};
147 163
148mii_phy_tx_clk: clk@2 { 164mii_phy_tx_clk: clk@2 {
@@ -170,3 +186,16 @@ gmac_clk: clk@01c20164 {
170 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 186 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
171 clock-output-names = "gmac"; 187 clock-output-names = "gmac";
172}; 188};
189
190mmc_config_clk: clk@01c13000 {
191 compatible = "allwinner,sun9i-a80-mmc-config-clk";
192 reg = <0x01c13000 0x10>;
193 clocks = <&ahb0_gates 8>;
194 clock-names = "ahb";
195 resets = <&ahb0_resets 8>;
196 reset-names = "ahb";
197 #clock-cells = <1>;
198 #reset-cells = <1>;
199 clock-output-names = "mmc0_config", "mmc1_config",
200 "mmc2_config", "mmc3_config";
201};
diff --git a/Documentation/devicetree/bindings/clock/ti,cdce706.txt b/Documentation/devicetree/bindings/clock/ti,cdce706.txt
new file mode 100644
index 000000000000..616836e7e1e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti,cdce706.txt
@@ -0,0 +1,42 @@
1Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
2synthesizer/multiplier/divider.
3
4Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf
5
6I2C device node required properties:
7- compatible: shall be "ti,cdce706".
8- reg: i2c device address, shall be in range [0x68...0x6b].
9- #clock-cells: from common clock binding; shall be set to 1.
10- clocks: from common clock binding; list of parent clock
11 handles, shall be reference clock(s) connected to CLK_IN0
12 and CLK_IN1 pins.
13- clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
14 in case of crystal oscillator or differential signal input
15 configuration. Use clk_in0 and clk_in1 in case of independent
16 single-ended LVCMOS inputs configuration.
17
18Example:
19
20 clocks {
21 clk54: clk54 {
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <54000000>;
25 };
26 };
27 ...
28 i2c0: i2c-master@0d090000 {
29 ...
30 cdce706: clock-synth@69 {
31 compatible = "ti,cdce706";
32 #clock-cells = <1>;
33 reg = <0x69>;
34 clocks = <&clk54>;
35 clock-names = "clk_in0";
36 };
37 };
38 ...
39 simple-audio-card,codec {
40 ...
41 clocks = <&cdce706 4>;
42 };
diff --git a/Documentation/devicetree/bindings/clock/ti/fapll.txt b/Documentation/devicetree/bindings/clock/ti/fapll.txt
new file mode 100644
index 000000000000..c19b3f253b8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fapll.txt
@@ -0,0 +1,33 @@
1Binding for Texas Instruments FAPLL clock.
2
3Binding status: Unstable - ABI compatibility may be broken in the future
4
5This binding uses the common clock binding[1]. It assumes a
6register-mapped FAPLL with usually two selectable input clocks
7(reference clock and bypass clock), and one or more child
8syntesizers.
9
10[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11
12Required properties:
13- compatible : shall be "ti,dm816-fapll-clock"
14- #clock-cells : from common clock binding; shall be set to 0.
15- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
16- reg : address and length of the register set for controlling the FAPLL.
17
18Examples:
19 main_fapll: main_fapll {
20 #clock-cells = <1>;
21 compatible = "ti,dm816-fapll-clock";
22 reg = <0x400 0x40>;
23 clocks = <&sys_clkin_ck &sys_clkin_ck>;
24 clock-indices = <1>, <2>, <3>, <4>, <5>,
25 <6>, <7>;
26 clock-output-names = "main_pll_clk1",
27 "main_pll_clk2",
28 "main_pll_clk3",
29 "main_pll_clk4",
30 "main_pll_clk5",
31 "main_pll_clk6",
32 "main_pll_clk7";
33 };
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 91b3a3467150..4bf41d833804 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -10,8 +10,8 @@ Absolute maximum transfer rate is 200MB/s
10Required properties: 10Required properties:
11 - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc" 11 - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"
12 - reg : mmc controller base registers 12 - reg : mmc controller base registers
13 - clocks : a list with 2 phandle + clock specifier pairs 13 - clocks : a list with 4 phandle + clock specifier pairs
14 - clock-names : must contain "ahb" and "mmc" 14 - clock-names : must contain "ahb", "mmc", "output" and "sample"
15 - interrupts : mmc controller interrupt 15 - interrupts : mmc controller interrupt
16 16
17Optional properties: 17Optional properties:
@@ -25,8 +25,8 @@ Examples:
25 mmc0: mmc@01c0f000 { 25 mmc0: mmc@01c0f000 {
26 compatible = "allwinner,sun5i-a13-mmc"; 26 compatible = "allwinner,sun5i-a13-mmc";
27 reg = <0x01c0f000 0x1000>; 27 reg = <0x01c0f000 0x1000>;
28 clocks = <&ahb_gates 8>, <&mmc0_clk>; 28 clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>;
29 clock-names = "ahb", "mod"; 29 clock-names = "ahb", "mod", "output", "sample";
30 interrupts = <0 32 4>; 30 interrupts = <0 32 4>;
31 status = "disabled"; 31 status = "disabled";
32 }; 32 };
diff --git a/MAINTAINERS b/MAINTAINERS
index 7cfcee4e2bea..574321803958 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9719,6 +9719,11 @@ L: linux-omap@vger.kernel.org
9719S: Maintained 9719S: Maintained
9720F: drivers/thermal/ti-soc-thermal/ 9720F: drivers/thermal/ti-soc-thermal/
9721 9721
9722TI CDCE706 CLOCK DRIVER
9723M: Max Filippov <jcmvbkbc@gmail.com>
9724S: Maintained
9725F: drivers/clk/clk-cdce706.c
9726
9722TI CLOCK DRIVER 9727TI CLOCK DRIVER
9723M: Tero Kristo <t-kristo@ti.com> 9728M: Tero Kristo <t-kristo@ti.com>
9724L: linux-omap@vger.kernel.org 9729L: linux-omap@vger.kernel.org
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 8ca3c1a2063d..5c2925831f20 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -294,35 +294,43 @@
294 }; 294 };
295 295
296 mmc0_clk: clk@01c20088 { 296 mmc0_clk: clk@01c20088 {
297 #clock-cells = <0>; 297 #clock-cells = <1>;
298 compatible = "allwinner,sun4i-a10-mod0-clk"; 298 compatible = "allwinner,sun4i-a10-mmc-clk";
299 reg = <0x01c20088 0x4>; 299 reg = <0x01c20088 0x4>;
300 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 300 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
301 clock-output-names = "mmc0"; 301 clock-output-names = "mmc0",
302 "mmc0_output",
303 "mmc0_sample";
302 }; 304 };
303 305
304 mmc1_clk: clk@01c2008c { 306 mmc1_clk: clk@01c2008c {
305 #clock-cells = <0>; 307 #clock-cells = <1>;
306 compatible = "allwinner,sun4i-a10-mod0-clk"; 308 compatible = "allwinner,sun4i-a10-mmc-clk";
307 reg = <0x01c2008c 0x4>; 309 reg = <0x01c2008c 0x4>;
308 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 310 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
309 clock-output-names = "mmc1"; 311 clock-output-names = "mmc1",
312 "mmc1_output",
313 "mmc1_sample";
310 }; 314 };
311 315
312 mmc2_clk: clk@01c20090 { 316 mmc2_clk: clk@01c20090 {
313 #clock-cells = <0>; 317 #clock-cells = <1>;
314 compatible = "allwinner,sun4i-a10-mod0-clk"; 318 compatible = "allwinner,sun4i-a10-mmc-clk";
315 reg = <0x01c20090 0x4>; 319 reg = <0x01c20090 0x4>;
316 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 320 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
317 clock-output-names = "mmc2"; 321 clock-output-names = "mmc2",
322 "mmc2_output",
323 "mmc2_sample";
318 }; 324 };
319 325
320 mmc3_clk: clk@01c20094 { 326 mmc3_clk: clk@01c20094 {
321 #clock-cells = <0>; 327 #clock-cells = <1>;
322 compatible = "allwinner,sun4i-a10-mod0-clk"; 328 compatible = "allwinner,sun4i-a10-mmc-clk";
323 reg = <0x01c20094 0x4>; 329 reg = <0x01c20094 0x4>;
324 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 330 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
325 clock-output-names = "mmc3"; 331 clock-output-names = "mmc3",
332 "mmc3_output",
333 "mmc3_sample";
326 }; 334 };
327 335
328 ts_clk: clk@01c20098 { 336 ts_clk: clk@01c20098 {
@@ -468,8 +476,14 @@
468 mmc0: mmc@01c0f000 { 476 mmc0: mmc@01c0f000 {
469 compatible = "allwinner,sun4i-a10-mmc"; 477 compatible = "allwinner,sun4i-a10-mmc";
470 reg = <0x01c0f000 0x1000>; 478 reg = <0x01c0f000 0x1000>;
471 clocks = <&ahb_gates 8>, <&mmc0_clk>; 479 clocks = <&ahb_gates 8>,
472 clock-names = "ahb", "mmc"; 480 <&mmc0_clk 0>,
481 <&mmc0_clk 1>,
482 <&mmc0_clk 2>;
483 clock-names = "ahb",
484 "mmc",
485 "output",
486 "sample";
473 interrupts = <32>; 487 interrupts = <32>;
474 status = "disabled"; 488 status = "disabled";
475 }; 489 };
@@ -477,8 +491,14 @@
477 mmc1: mmc@01c10000 { 491 mmc1: mmc@01c10000 {
478 compatible = "allwinner,sun4i-a10-mmc"; 492 compatible = "allwinner,sun4i-a10-mmc";
479 reg = <0x01c10000 0x1000>; 493 reg = <0x01c10000 0x1000>;
480 clocks = <&ahb_gates 9>, <&mmc1_clk>; 494 clocks = <&ahb_gates 9>,
481 clock-names = "ahb", "mmc"; 495 <&mmc1_clk 0>,
496 <&mmc1_clk 1>,
497 <&mmc1_clk 2>;
498 clock-names = "ahb",
499 "mmc",
500 "output",
501 "sample";
482 interrupts = <33>; 502 interrupts = <33>;
483 status = "disabled"; 503 status = "disabled";
484 }; 504 };
@@ -486,8 +506,14 @@
486 mmc2: mmc@01c11000 { 506 mmc2: mmc@01c11000 {
487 compatible = "allwinner,sun4i-a10-mmc"; 507 compatible = "allwinner,sun4i-a10-mmc";
488 reg = <0x01c11000 0x1000>; 508 reg = <0x01c11000 0x1000>;
489 clocks = <&ahb_gates 10>, <&mmc2_clk>; 509 clocks = <&ahb_gates 10>,
490 clock-names = "ahb", "mmc"; 510 <&mmc2_clk 0>,
511 <&mmc2_clk 1>,
512 <&mmc2_clk 2>;
513 clock-names = "ahb",
514 "mmc",
515 "output",
516 "sample";
491 interrupts = <34>; 517 interrupts = <34>;
492 status = "disabled"; 518 status = "disabled";
493 }; 519 };
@@ -495,8 +521,14 @@
495 mmc3: mmc@01c12000 { 521 mmc3: mmc@01c12000 {
496 compatible = "allwinner,sun4i-a10-mmc"; 522 compatible = "allwinner,sun4i-a10-mmc";
497 reg = <0x01c12000 0x1000>; 523 reg = <0x01c12000 0x1000>;
498 clocks = <&ahb_gates 11>, <&mmc3_clk>; 524 clocks = <&ahb_gates 11>,
499 clock-names = "ahb", "mmc"; 525 <&mmc3_clk 0>,
526 <&mmc3_clk 1>,
527 <&mmc3_clk 2>;
528 clock-names = "ahb",
529 "mmc",
530 "output",
531 "sample";
500 interrupts = <35>; 532 interrupts = <35>;
501 status = "disabled"; 533 status = "disabled";
502 }; 534 };
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 905f84d141f0..2fd8988f310c 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -218,27 +218,33 @@
218 }; 218 };
219 219
220 mmc0_clk: clk@01c20088 { 220 mmc0_clk: clk@01c20088 {
221 #clock-cells = <0>; 221 #clock-cells = <1>;
222 compatible = "allwinner,sun4i-a10-mod0-clk"; 222 compatible = "allwinner,sun4i-a10-mmc-clk";
223 reg = <0x01c20088 0x4>; 223 reg = <0x01c20088 0x4>;
224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 224 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
225 clock-output-names = "mmc0"; 225 clock-output-names = "mmc0",
226 "mmc0_output",
227 "mmc0_sample";
226 }; 228 };
227 229
228 mmc1_clk: clk@01c2008c { 230 mmc1_clk: clk@01c2008c {
229 #clock-cells = <0>; 231 #clock-cells = <1>;
230 compatible = "allwinner,sun4i-a10-mod0-clk"; 232 compatible = "allwinner,sun4i-a10-mmc-clk";
231 reg = <0x01c2008c 0x4>; 233 reg = <0x01c2008c 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc1"; 235 clock-output-names = "mmc1",
236 "mmc1_output",
237 "mmc1_sample";
234 }; 238 };
235 239
236 mmc2_clk: clk@01c20090 { 240 mmc2_clk: clk@01c20090 {
237 #clock-cells = <0>; 241 #clock-cells = <1>;
238 compatible = "allwinner,sun4i-a10-mod0-clk"; 242 compatible = "allwinner,sun4i-a10-mmc-clk";
239 reg = <0x01c20090 0x4>; 243 reg = <0x01c20090 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 244 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc2"; 245 clock-output-names = "mmc2",
246 "mmc2_output",
247 "mmc2_sample";
242 }; 248 };
243 249
244 ts_clk: clk@01c20098 { 250 ts_clk: clk@01c20098 {
@@ -368,8 +374,14 @@
368 mmc0: mmc@01c0f000 { 374 mmc0: mmc@01c0f000 {
369 compatible = "allwinner,sun5i-a13-mmc"; 375 compatible = "allwinner,sun5i-a13-mmc";
370 reg = <0x01c0f000 0x1000>; 376 reg = <0x01c0f000 0x1000>;
371 clocks = <&ahb_gates 8>, <&mmc0_clk>; 377 clocks = <&ahb_gates 8>,
372 clock-names = "ahb", "mmc"; 378 <&mmc0_clk 0>,
379 <&mmc0_clk 1>,
380 <&mmc0_clk 2>;
381 clock-names = "ahb",
382 "mmc",
383 "output",
384 "sample";
373 interrupts = <32>; 385 interrupts = <32>;
374 status = "disabled"; 386 status = "disabled";
375 }; 387 };
@@ -377,8 +389,14 @@
377 mmc1: mmc@01c10000 { 389 mmc1: mmc@01c10000 {
378 compatible = "allwinner,sun5i-a13-mmc"; 390 compatible = "allwinner,sun5i-a13-mmc";
379 reg = <0x01c10000 0x1000>; 391 reg = <0x01c10000 0x1000>;
380 clocks = <&ahb_gates 9>, <&mmc1_clk>; 392 clocks = <&ahb_gates 9>,
381 clock-names = "ahb", "mmc"; 393 <&mmc1_clk 0>,
394 <&mmc1_clk 1>,
395 <&mmc1_clk 2>;
396 clock-names = "ahb",
397 "mmc",
398 "output",
399 "sample";
382 interrupts = <33>; 400 interrupts = <33>;
383 status = "disabled"; 401 status = "disabled";
384 }; 402 };
@@ -386,8 +404,14 @@
386 mmc2: mmc@01c11000 { 404 mmc2: mmc@01c11000 {
387 compatible = "allwinner,sun5i-a13-mmc"; 405 compatible = "allwinner,sun5i-a13-mmc";
388 reg = <0x01c11000 0x1000>; 406 reg = <0x01c11000 0x1000>;
389 clocks = <&ahb_gates 10>, <&mmc2_clk>; 407 clocks = <&ahb_gates 10>,
390 clock-names = "ahb", "mmc"; 408 <&mmc2_clk 0>,
409 <&mmc2_clk 1>,
410 <&mmc2_clk 2>;
411 clock-names = "ahb",
412 "mmc",
413 "output",
414 "sample";
391 interrupts = <34>; 415 interrupts = <34>;
392 status = "disabled"; 416 status = "disabled";
393 }; 417 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 4910393d1b09..f8818f1edbbe 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -257,27 +257,33 @@
257 }; 257 };
258 258
259 mmc0_clk: clk@01c20088 { 259 mmc0_clk: clk@01c20088 {
260 #clock-cells = <0>; 260 #clock-cells = <1>;
261 compatible = "allwinner,sun4i-a10-mod0-clk"; 261 compatible = "allwinner,sun4i-a10-mmc-clk";
262 reg = <0x01c20088 0x4>; 262 reg = <0x01c20088 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "mmc0"; 264 clock-output-names = "mmc0",
265 "mmc0_output",
266 "mmc0_sample";
265 }; 267 };
266 268
267 mmc1_clk: clk@01c2008c { 269 mmc1_clk: clk@01c2008c {
268 #clock-cells = <0>; 270 #clock-cells = <1>;
269 compatible = "allwinner,sun4i-a10-mod0-clk"; 271 compatible = "allwinner,sun4i-a10-mmc-clk";
270 reg = <0x01c2008c 0x4>; 272 reg = <0x01c2008c 0x4>;
271 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
272 clock-output-names = "mmc1"; 274 clock-output-names = "mmc1",
275 "mmc1_output",
276 "mmc1_sample";
273 }; 277 };
274 278
275 mmc2_clk: clk@01c20090 { 279 mmc2_clk: clk@01c20090 {
276 #clock-cells = <0>; 280 #clock-cells = <1>;
277 compatible = "allwinner,sun4i-a10-mod0-clk"; 281 compatible = "allwinner,sun4i-a10-mmc-clk";
278 reg = <0x01c20090 0x4>; 282 reg = <0x01c20090 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 283 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "mmc2"; 284 clock-output-names = "mmc2",
285 "mmc2_output",
286 "mmc2_sample";
281 }; 287 };
282 288
283 ts_clk: clk@01c20098 { 289 ts_clk: clk@01c20098 {
@@ -391,8 +397,14 @@
391 mmc0: mmc@01c0f000 { 397 mmc0: mmc@01c0f000 {
392 compatible = "allwinner,sun5i-a13-mmc"; 398 compatible = "allwinner,sun5i-a13-mmc";
393 reg = <0x01c0f000 0x1000>; 399 reg = <0x01c0f000 0x1000>;
394 clocks = <&ahb_gates 8>, <&mmc0_clk>; 400 clocks = <&ahb_gates 8>,
395 clock-names = "ahb", "mmc"; 401 <&mmc0_clk 0>,
402 <&mmc0_clk 1>,
403 <&mmc0_clk 2>;
404 clock-names = "ahb",
405 "mmc",
406 "output",
407 "sample";
396 interrupts = <32>; 408 interrupts = <32>;
397 status = "disabled"; 409 status = "disabled";
398 }; 410 };
@@ -400,8 +412,14 @@
400 mmc2: mmc@01c11000 { 412 mmc2: mmc@01c11000 {
401 compatible = "allwinner,sun5i-a13-mmc"; 413 compatible = "allwinner,sun5i-a13-mmc";
402 reg = <0x01c11000 0x1000>; 414 reg = <0x01c11000 0x1000>;
403 clocks = <&ahb_gates 10>, <&mmc2_clk>; 415 clocks = <&ahb_gates 10>,
404 clock-names = "ahb", "mmc"; 416 <&mmc2_clk 0>,
417 <&mmc2_clk 1>,
418 <&mmc2_clk 2>;
419 clock-names = "ahb",
420 "mmc",
421 "output",
422 "sample";
405 interrupts = <34>; 423 interrupts = <34>;
406 status = "disabled"; 424 status = "disabled";
407 }; 425 };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 47e557656993..fa2f403ccf28 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -190,19 +190,11 @@
190 clock-output-names = "axi"; 190 clock-output-names = "axi";
191 }; 191 };
192 192
193 ahb1_mux: ahb1_mux@01c20054 {
194 #clock-cells = <0>;
195 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
196 reg = <0x01c20054 0x4>;
197 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
198 clock-output-names = "ahb1_mux";
199 };
200
201 ahb1: ahb1@01c20054 { 193 ahb1: ahb1@01c20054 {
202 #clock-cells = <0>; 194 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-a10-ahb-clk"; 195 compatible = "allwinner,sun6i-a31-ahb1-clk";
204 reg = <0x01c20054 0x4>; 196 reg = <0x01c20054 0x4>;
205 clocks = <&ahb1_mux>; 197 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
206 clock-output-names = "ahb1"; 198 clock-output-names = "ahb1";
207 }; 199 };
208 200
@@ -265,35 +257,43 @@
265 }; 257 };
266 258
267 mmc0_clk: clk@01c20088 { 259 mmc0_clk: clk@01c20088 {
268 #clock-cells = <0>; 260 #clock-cells = <1>;
269 compatible = "allwinner,sun4i-a10-mod0-clk"; 261 compatible = "allwinner,sun4i-a10-mmc-clk";
270 reg = <0x01c20088 0x4>; 262 reg = <0x01c20088 0x4>;
271 clocks = <&osc24M>, <&pll6 0>; 263 clocks = <&osc24M>, <&pll6 0>;
272 clock-output-names = "mmc0"; 264 clock-output-names = "mmc0",
265 "mmc0_output",
266 "mmc0_sample";
273 }; 267 };
274 268
275 mmc1_clk: clk@01c2008c { 269 mmc1_clk: clk@01c2008c {
276 #clock-cells = <0>; 270 #clock-cells = <1>;
277 compatible = "allwinner,sun4i-a10-mod0-clk"; 271 compatible = "allwinner,sun4i-a10-mmc-clk";
278 reg = <0x01c2008c 0x4>; 272 reg = <0x01c2008c 0x4>;
279 clocks = <&osc24M>, <&pll6 0>; 273 clocks = <&osc24M>, <&pll6 0>;
280 clock-output-names = "mmc1"; 274 clock-output-names = "mmc1",
275 "mmc1_output",
276 "mmc1_sample";
281 }; 277 };
282 278
283 mmc2_clk: clk@01c20090 { 279 mmc2_clk: clk@01c20090 {
284 #clock-cells = <0>; 280 #clock-cells = <1>;
285 compatible = "allwinner,sun4i-a10-mod0-clk"; 281 compatible = "allwinner,sun4i-a10-mmc-clk";
286 reg = <0x01c20090 0x4>; 282 reg = <0x01c20090 0x4>;
287 clocks = <&osc24M>, <&pll6 0>; 283 clocks = <&osc24M>, <&pll6 0>;
288 clock-output-names = "mmc2"; 284 clock-output-names = "mmc2",
285 "mmc2_output",
286 "mmc2_sample";
289 }; 287 };
290 288
291 mmc3_clk: clk@01c20094 { 289 mmc3_clk: clk@01c20094 {
292 #clock-cells = <0>; 290 #clock-cells = <1>;
293 compatible = "allwinner,sun4i-a10-mod0-clk"; 291 compatible = "allwinner,sun4i-a10-mmc-clk";
294 reg = <0x01c20094 0x4>; 292 reg = <0x01c20094 0x4>;
295 clocks = <&osc24M>, <&pll6 0>; 293 clocks = <&osc24M>, <&pll6 0>;
296 clock-output-names = "mmc3"; 294 clock-output-names = "mmc3",
295 "mmc3_output",
296 "mmc3_sample";
297 }; 297 };
298 298
299 spi0_clk: clk@01c200a0 { 299 spi0_clk: clk@01c200a0 {
@@ -383,15 +383,21 @@
383 #dma-cells = <1>; 383 #dma-cells = <1>;
384 384
385 /* DMA controller requires AHB1 clocked from PLL6 */ 385 /* DMA controller requires AHB1 clocked from PLL6 */
386 assigned-clocks = <&ahb1_mux>; 386 assigned-clocks = <&ahb1>;
387 assigned-clock-parents = <&pll6 0>; 387 assigned-clock-parents = <&pll6 0>;
388 }; 388 };
389 389
390 mmc0: mmc@01c0f000 { 390 mmc0: mmc@01c0f000 {
391 compatible = "allwinner,sun5i-a13-mmc"; 391 compatible = "allwinner,sun5i-a13-mmc";
392 reg = <0x01c0f000 0x1000>; 392 reg = <0x01c0f000 0x1000>;
393 clocks = <&ahb1_gates 8>, <&mmc0_clk>; 393 clocks = <&ahb1_gates 8>,
394 clock-names = "ahb", "mmc"; 394 <&mmc0_clk 0>,
395 <&mmc0_clk 1>,
396 <&mmc0_clk 2>;
397 clock-names = "ahb",
398 "mmc",
399 "output",
400 "sample";
395 resets = <&ahb1_rst 8>; 401 resets = <&ahb1_rst 8>;
396 reset-names = "ahb"; 402 reset-names = "ahb";
397 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -401,8 +407,14 @@
401 mmc1: mmc@01c10000 { 407 mmc1: mmc@01c10000 {
402 compatible = "allwinner,sun5i-a13-mmc"; 408 compatible = "allwinner,sun5i-a13-mmc";
403 reg = <0x01c10000 0x1000>; 409 reg = <0x01c10000 0x1000>;
404 clocks = <&ahb1_gates 9>, <&mmc1_clk>; 410 clocks = <&ahb1_gates 9>,
405 clock-names = "ahb", "mmc"; 411 <&mmc1_clk 0>,
412 <&mmc1_clk 1>,
413 <&mmc1_clk 2>;
414 clock-names = "ahb",
415 "mmc",
416 "output",
417 "sample";
406 resets = <&ahb1_rst 9>; 418 resets = <&ahb1_rst 9>;
407 reset-names = "ahb"; 419 reset-names = "ahb";
408 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 420 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -412,8 +424,14 @@
412 mmc2: mmc@01c11000 { 424 mmc2: mmc@01c11000 {
413 compatible = "allwinner,sun5i-a13-mmc"; 425 compatible = "allwinner,sun5i-a13-mmc";
414 reg = <0x01c11000 0x1000>; 426 reg = <0x01c11000 0x1000>;
415 clocks = <&ahb1_gates 10>, <&mmc2_clk>; 427 clocks = <&ahb1_gates 10>,
416 clock-names = "ahb", "mmc"; 428 <&mmc2_clk 0>,
429 <&mmc2_clk 1>,
430 <&mmc2_clk 2>;
431 clock-names = "ahb",
432 "mmc",
433 "output",
434 "sample";
417 resets = <&ahb1_rst 10>; 435 resets = <&ahb1_rst 10>;
418 reset-names = "ahb"; 436 reset-names = "ahb";
419 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 437 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -423,8 +441,14 @@
423 mmc3: mmc@01c12000 { 441 mmc3: mmc@01c12000 {
424 compatible = "allwinner,sun5i-a13-mmc"; 442 compatible = "allwinner,sun5i-a13-mmc";
425 reg = <0x01c12000 0x1000>; 443 reg = <0x01c12000 0x1000>;
426 clocks = <&ahb1_gates 11>, <&mmc3_clk>; 444 clocks = <&ahb1_gates 11>,
427 clock-names = "ahb", "mmc"; 445 <&mmc3_clk 0>,
446 <&mmc3_clk 1>,
447 <&mmc3_clk 2>;
448 clock-names = "ahb",
449 "mmc",
450 "output",
451 "sample";
428 resets = <&ahb1_rst 11>; 452 resets = <&ahb1_rst 11>;
429 reset-names = "ahb"; 453 reset-names = "ahb";
430 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 454 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 786d491542ac..3a8530b79f1c 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -337,35 +337,43 @@
337 }; 337 };
338 338
339 mmc0_clk: clk@01c20088 { 339 mmc0_clk: clk@01c20088 {
340 #clock-cells = <0>; 340 #clock-cells = <1>;
341 compatible = "allwinner,sun4i-a10-mod0-clk"; 341 compatible = "allwinner,sun4i-a10-mmc-clk";
342 reg = <0x01c20088 0x4>; 342 reg = <0x01c20088 0x4>;
343 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 343 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
344 clock-output-names = "mmc0"; 344 clock-output-names = "mmc0",
345 "mmc0_output",
346 "mmc0_sample";
345 }; 347 };
346 348
347 mmc1_clk: clk@01c2008c { 349 mmc1_clk: clk@01c2008c {
348 #clock-cells = <0>; 350 #clock-cells = <1>;
349 compatible = "allwinner,sun4i-a10-mod0-clk"; 351 compatible = "allwinner,sun4i-a10-mmc-clk";
350 reg = <0x01c2008c 0x4>; 352 reg = <0x01c2008c 0x4>;
351 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 353 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
352 clock-output-names = "mmc1"; 354 clock-output-names = "mmc1",
355 "mmc1_output",
356 "mmc1_sample";
353 }; 357 };
354 358
355 mmc2_clk: clk@01c20090 { 359 mmc2_clk: clk@01c20090 {
356 #clock-cells = <0>; 360 #clock-cells = <1>;
357 compatible = "allwinner,sun4i-a10-mod0-clk"; 361 compatible = "allwinner,sun4i-a10-mmc-clk";
358 reg = <0x01c20090 0x4>; 362 reg = <0x01c20090 0x4>;
359 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 363 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
360 clock-output-names = "mmc2"; 364 clock-output-names = "mmc2",
365 "mmc2_output",
366 "mmc2_sample";
361 }; 367 };
362 368
363 mmc3_clk: clk@01c20094 { 369 mmc3_clk: clk@01c20094 {
364 #clock-cells = <0>; 370 #clock-cells = <1>;
365 compatible = "allwinner,sun4i-a10-mod0-clk"; 371 compatible = "allwinner,sun4i-a10-mmc-clk";
366 reg = <0x01c20094 0x4>; 372 reg = <0x01c20094 0x4>;
367 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 373 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
368 clock-output-names = "mmc3"; 374 clock-output-names = "mmc3",
375 "mmc3_output",
376 "mmc3_sample";
369 }; 377 };
370 378
371 ts_clk: clk@01c20098 { 379 ts_clk: clk@01c20098 {
@@ -583,8 +591,14 @@
583 mmc0: mmc@01c0f000 { 591 mmc0: mmc@01c0f000 {
584 compatible = "allwinner,sun5i-a13-mmc"; 592 compatible = "allwinner,sun5i-a13-mmc";
585 reg = <0x01c0f000 0x1000>; 593 reg = <0x01c0f000 0x1000>;
586 clocks = <&ahb_gates 8>, <&mmc0_clk>; 594 clocks = <&ahb_gates 8>,
587 clock-names = "ahb", "mmc"; 595 <&mmc0_clk 0>,
596 <&mmc0_clk 1>,
597 <&mmc0_clk 2>;
598 clock-names = "ahb",
599 "mmc",
600 "output",
601 "sample";
588 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 602 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
589 status = "disabled"; 603 status = "disabled";
590 }; 604 };
@@ -592,8 +606,14 @@
592 mmc1: mmc@01c10000 { 606 mmc1: mmc@01c10000 {
593 compatible = "allwinner,sun5i-a13-mmc"; 607 compatible = "allwinner,sun5i-a13-mmc";
594 reg = <0x01c10000 0x1000>; 608 reg = <0x01c10000 0x1000>;
595 clocks = <&ahb_gates 9>, <&mmc1_clk>; 609 clocks = <&ahb_gates 9>,
596 clock-names = "ahb", "mmc"; 610 <&mmc1_clk 0>,
611 <&mmc1_clk 1>,
612 <&mmc1_clk 2>;
613 clock-names = "ahb",
614 "mmc",
615 "output",
616 "sample";
597 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 617 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
598 status = "disabled"; 618 status = "disabled";
599 }; 619 };
@@ -601,8 +621,14 @@
601 mmc2: mmc@01c11000 { 621 mmc2: mmc@01c11000 {
602 compatible = "allwinner,sun5i-a13-mmc"; 622 compatible = "allwinner,sun5i-a13-mmc";
603 reg = <0x01c11000 0x1000>; 623 reg = <0x01c11000 0x1000>;
604 clocks = <&ahb_gates 10>, <&mmc2_clk>; 624 clocks = <&ahb_gates 10>,
605 clock-names = "ahb", "mmc"; 625 <&mmc2_clk 0>,
626 <&mmc2_clk 1>,
627 <&mmc2_clk 2>;
628 clock-names = "ahb",
629 "mmc",
630 "output",
631 "sample";
606 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 632 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
607 status = "disabled"; 633 status = "disabled";
608 }; 634 };
@@ -610,8 +636,14 @@
610 mmc3: mmc@01c12000 { 636 mmc3: mmc@01c12000 {
611 compatible = "allwinner,sun5i-a13-mmc"; 637 compatible = "allwinner,sun5i-a13-mmc";
612 reg = <0x01c12000 0x1000>; 638 reg = <0x01c12000 0x1000>;
613 clocks = <&ahb_gates 11>, <&mmc3_clk>; 639 clocks = <&ahb_gates 11>,
614 clock-names = "ahb", "mmc"; 640 <&mmc3_clk 0>,
641 <&mmc3_clk 1>,
642 <&mmc3_clk 2>;
643 clock-names = "ahb",
644 "mmc",
645 "output",
646 "sample";
615 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 647 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
616 status = "disabled"; 648 status = "disabled";
617 }; 649 };
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index dd34527293e4..382ebd137ee4 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -119,11 +119,19 @@
119 }; 119 };
120 120
121 /* dummy clock until actually implemented */ 121 /* dummy clock until actually implemented */
122 pll6: pll6_clk { 122 pll5: pll5_clk {
123 #clock-cells = <0>; 123 #clock-cells = <0>;
124 compatible = "fixed-clock"; 124 compatible = "fixed-clock";
125 clock-frequency = <600000000>; 125 clock-frequency = <0>;
126 clock-output-names = "pll6"; 126 clock-output-names = "pll5";
127 };
128
129 pll6: clk@01c20028 {
130 #clock-cells = <1>;
131 compatible = "allwinner,sun6i-a31-pll6-clk";
132 reg = <0x01c20028 0x4>;
133 clocks = <&osc24M>;
134 clock-output-names = "pll6", "pll6x2";
127 }; 135 };
128 136
129 cpu: cpu_clk@01c20050 { 137 cpu: cpu_clk@01c20050 {
@@ -149,19 +157,11 @@
149 clock-output-names = "axi"; 157 clock-output-names = "axi";
150 }; 158 };
151 159
152 ahb1_mux: ahb1_mux_clk@01c20054 {
153 #clock-cells = <0>;
154 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
155 reg = <0x01c20054 0x4>;
156 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
157 clock-output-names = "ahb1_mux";
158 };
159
160 ahb1: ahb1_clk@01c20054 { 160 ahb1: ahb1_clk@01c20054 {
161 #clock-cells = <0>; 161 #clock-cells = <0>;
162 compatible = "allwinner,sun4i-a10-ahb-clk"; 162 compatible = "allwinner,sun6i-a31-ahb1-clk";
163 reg = <0x01c20054 0x4>; 163 reg = <0x01c20054 0x4>;
164 clocks = <&ahb1_mux>; 164 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
165 clock-output-names = "ahb1"; 165 clock-output-names = "ahb1";
166 }; 166 };
167 167
@@ -202,7 +202,7 @@
202 #clock-cells = <0>; 202 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-a10-apb1-clk"; 203 compatible = "allwinner,sun4i-a10-apb1-clk";
204 reg = <0x01c20058 0x4>; 204 reg = <0x01c20058 0x4>;
205 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 205 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
206 clock-output-names = "apb2"; 206 clock-output-names = "apb2";
207 }; 207 };
208 208
@@ -218,27 +218,41 @@
218 }; 218 };
219 219
220 mmc0_clk: clk@01c20088 { 220 mmc0_clk: clk@01c20088 {
221 #clock-cells = <0>; 221 #clock-cells = <1>;
222 compatible = "allwinner,sun4i-a10-mod0-clk"; 222 compatible = "allwinner,sun4i-a10-mmc-clk";
223 reg = <0x01c20088 0x4>; 223 reg = <0x01c20088 0x4>;
224 clocks = <&osc24M>, <&pll6>; 224 clocks = <&osc24M>, <&pll6 0>;
225 clock-output-names = "mmc0"; 225 clock-output-names = "mmc0",
226 "mmc0_output",
227 "mmc0_sample";
226 }; 228 };
227 229
228 mmc1_clk: clk@01c2008c { 230 mmc1_clk: clk@01c2008c {
229 #clock-cells = <0>; 231 #clock-cells = <1>;
230 compatible = "allwinner,sun4i-a10-mod0-clk"; 232 compatible = "allwinner,sun4i-a10-mmc-clk";
231 reg = <0x01c2008c 0x4>; 233 reg = <0x01c2008c 0x4>;
232 clocks = <&osc24M>, <&pll6>; 234 clocks = <&osc24M>, <&pll6 0>;
233 clock-output-names = "mmc1"; 235 clock-output-names = "mmc1",
236 "mmc1_output",
237 "mmc1_sample";
234 }; 238 };
235 239
236 mmc2_clk: clk@01c20090 { 240 mmc2_clk: clk@01c20090 {
237 #clock-cells = <0>; 241 #clock-cells = <1>;
238 compatible = "allwinner,sun4i-a10-mod0-clk"; 242 compatible = "allwinner,sun4i-a10-mmc-clk";
239 reg = <0x01c20090 0x4>; 243 reg = <0x01c20090 0x4>;
240 clocks = <&osc24M>, <&pll6>; 244 clocks = <&osc24M>, <&pll6 0>;
241 clock-output-names = "mmc2"; 245 clock-output-names = "mmc2",
246 "mmc2_output",
247 "mmc2_sample";
248 };
249
250 mbus_clk: clk@01c2015c {
251 #clock-cells = <0>;
252 compatible = "allwinner,sun8i-a23-mbus-clk";
253 reg = <0x01c2015c 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
255 clock-output-names = "mbus";
242 }; 256 };
243 }; 257 };
244 258
@@ -260,8 +274,14 @@
260 mmc0: mmc@01c0f000 { 274 mmc0: mmc@01c0f000 {
261 compatible = "allwinner,sun5i-a13-mmc"; 275 compatible = "allwinner,sun5i-a13-mmc";
262 reg = <0x01c0f000 0x1000>; 276 reg = <0x01c0f000 0x1000>;
263 clocks = <&ahb1_gates 8>, <&mmc0_clk>; 277 clocks = <&ahb1_gates 8>,
264 clock-names = "ahb", "mmc"; 278 <&mmc0_clk 0>,
279 <&mmc0_clk 1>,
280 <&mmc0_clk 2>;
281 clock-names = "ahb",
282 "mmc",
283 "output",
284 "sample";
265 resets = <&ahb1_rst 8>; 285 resets = <&ahb1_rst 8>;
266 reset-names = "ahb"; 286 reset-names = "ahb";
267 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 287 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -271,8 +291,14 @@
271 mmc1: mmc@01c10000 { 291 mmc1: mmc@01c10000 {
272 compatible = "allwinner,sun5i-a13-mmc"; 292 compatible = "allwinner,sun5i-a13-mmc";
273 reg = <0x01c10000 0x1000>; 293 reg = <0x01c10000 0x1000>;
274 clocks = <&ahb1_gates 9>, <&mmc1_clk>; 294 clocks = <&ahb1_gates 9>,
275 clock-names = "ahb", "mmc"; 295 <&mmc1_clk 0>,
296 <&mmc1_clk 1>,
297 <&mmc1_clk 2>;
298 clock-names = "ahb",
299 "mmc",
300 "output",
301 "sample";
276 resets = <&ahb1_rst 9>; 302 resets = <&ahb1_rst 9>;
277 reset-names = "ahb"; 303 reset-names = "ahb";
278 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 304 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -282,8 +308,14 @@
282 mmc2: mmc@01c11000 { 308 mmc2: mmc@01c11000 {
283 compatible = "allwinner,sun5i-a13-mmc"; 309 compatible = "allwinner,sun5i-a13-mmc";
284 reg = <0x01c11000 0x1000>; 310 reg = <0x01c11000 0x1000>;
285 clocks = <&ahb1_gates 10>, <&mmc2_clk>; 311 clocks = <&ahb1_gates 10>,
286 clock-names = "ahb", "mmc"; 312 <&mmc2_clk 0>,
313 <&mmc2_clk 1>,
314 <&mmc2_clk 2>;
315 clock-names = "ahb",
316 "mmc",
317 "output",
318 "sample";
287 resets = <&ahb1_rst 10>; 319 resets = <&ahb1_rst 10>;
288 reset-names = "ahb"; 320 reset-names = "ahb";
289 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 00d5d8f9f150..b83f18fcec9b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -190,7 +190,7 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
190obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 190obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
191obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 191obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
192obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 192obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
193obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o 193obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
194obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o 194obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
195obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) 195obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
196obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 196obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
deleted file mode 100644
index e79c80bbc755..000000000000
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ /dev/null
@@ -1,3688 +0,0 @@
1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
11 *
12 */
13
14/*
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clk-private.h>
23#include <linux/list.h>
24#include <linux/io.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "clock.h"
29#include "clock3xxx.h"
30#include "clock34xx.h"
31#include "clock36xx.h"
32#include "clock3517.h"
33#include "cm3xxx.h"
34#include "cm-regbits-34xx.h"
35#include "prm3xxx.h"
36#include "prm-regbits-34xx.h"
37#include "control.h"
38
39/*
40 * clocks
41 */
42
43#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
44
45/* Maximum DPLL multiplier, divider values for OMAP3 */
46#define OMAP3_MAX_DPLL_MULT 2047
47#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48#define OMAP3_MAX_DPLL_DIV 128
49
50DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
51
52DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
53
54DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
57
58DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
59
60DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
61
62DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
63
64DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
67
68DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
69
70DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
71
72DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
75
76static const char *osc_sys_ck_parent_names[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
79};
80
81DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
82 OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
84
85DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
87 OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
88
89static struct dpll_data dpll3_dd = {
90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
91 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
92 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
93 .clk_bypass = &sys_ck,
94 .clk_ref = &sys_ck,
95 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
98 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
99 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
100 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
102 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
104 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
105 .max_multiplier = OMAP3_MAX_DPLL_MULT,
106 .min_divider = 1,
107 .max_divider = OMAP3_MAX_DPLL_DIV,
108};
109
110static struct clk dpll3_ck;
111
112static const char *dpll3_ck_parent_names[] = {
113 "sys_ck",
114 "sys_ck",
115};
116
117static const struct clk_ops dpll3_ck_ops = {
118 .init = &omap2_init_clk_clkdm,
119 .get_parent = &omap2_init_dpll_parent,
120 .recalc_rate = &omap3_dpll_recalc,
121 .round_rate = &omap2_dpll_round_rate,
122};
123
124static struct clk_hw_omap dpll3_ck_hw = {
125 .hw = {
126 .clk = &dpll3_ck,
127 },
128 .ops = &clkhwops_omap3_dpll,
129 .dpll_data = &dpll3_dd,
130 .clkdm_name = "dpll3_clkdm",
131};
132
133DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
134
135DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
136 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
138 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
139 CLK_DIVIDER_ONE_BASED, NULL);
140
141static struct clk core_ck;
142
143static const char *core_ck_parent_names[] = {
144 "dpll3_m2_ck",
145};
146
147static const struct clk_ops core_ck_ops = {};
148
149DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
150DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
151
152DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
153 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
154 OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
155 CLK_DIVIDER_ONE_BASED, NULL);
156
157DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
158 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
159 OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
160 CLK_DIVIDER_ONE_BASED, NULL);
161
162static struct clk security_l4_ick2;
163
164static const char *security_l4_ick2_parent_names[] = {
165 "l4_ick",
166};
167
168DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
169DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
170
171static struct clk aes1_ick;
172
173static const char *aes1_ick_parent_names[] = {
174 "security_l4_ick2",
175};
176
177static const struct clk_ops aes1_ick_ops = {
178 .enable = &omap2_dflt_clk_enable,
179 .disable = &omap2_dflt_clk_disable,
180 .is_enabled = &omap2_dflt_clk_is_enabled,
181};
182
183static struct clk_hw_omap aes1_ick_hw = {
184 .hw = {
185 .clk = &aes1_ick,
186 },
187 .ops = &clkhwops_iclk_wait,
188 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
189 .enable_bit = OMAP3430_EN_AES1_SHIFT,
190};
191
192DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
193
194static struct clk core_l4_ick;
195
196static const struct clk_ops core_l4_ick_ops = {
197 .init = &omap2_init_clk_clkdm,
198};
199
200DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
201DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
202
203static struct clk aes2_ick;
204
205static const char *aes2_ick_parent_names[] = {
206 "core_l4_ick",
207};
208
209static const struct clk_ops aes2_ick_ops = {
210 .init = &omap2_init_clk_clkdm,
211 .enable = &omap2_dflt_clk_enable,
212 .disable = &omap2_dflt_clk_disable,
213 .is_enabled = &omap2_dflt_clk_is_enabled,
214};
215
216static struct clk_hw_omap aes2_ick_hw = {
217 .hw = {
218 .clk = &aes2_ick,
219 },
220 .ops = &clkhwops_iclk_wait,
221 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
222 .enable_bit = OMAP3430_EN_AES2_SHIFT,
223 .clkdm_name = "core_l4_clkdm",
224};
225
226DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
227
228static struct clk dpll1_fck;
229
230static struct dpll_data dpll1_dd = {
231 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
232 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
233 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
234 .clk_bypass = &dpll1_fck,
235 .clk_ref = &sys_ck,
236 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
237 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
238 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
239 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
240 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
241 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
242 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
243 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
244 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
245 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
246 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
247 .max_multiplier = OMAP3_MAX_DPLL_MULT,
248 .min_divider = 1,
249 .max_divider = OMAP3_MAX_DPLL_DIV,
250};
251
252static struct clk dpll1_ck;
253
254static const struct clk_ops dpll1_ck_ops = {
255 .init = &omap2_init_clk_clkdm,
256 .enable = &omap3_noncore_dpll_enable,
257 .disable = &omap3_noncore_dpll_disable,
258 .get_parent = &omap2_init_dpll_parent,
259 .recalc_rate = &omap3_dpll_recalc,
260 .set_rate = &omap3_noncore_dpll_set_rate,
261 .set_parent = &omap3_noncore_dpll_set_parent,
262 .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent,
263 .determine_rate = &omap3_noncore_dpll_determine_rate,
264 .round_rate = &omap2_dpll_round_rate,
265};
266
267static struct clk_hw_omap dpll1_ck_hw = {
268 .hw = {
269 .clk = &dpll1_ck,
270 },
271 .ops = &clkhwops_omap3_dpll,
272 .dpll_data = &dpll1_dd,
273 .clkdm_name = "dpll1_clkdm",
274};
275
276DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
277
278DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
279
280DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
281 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
282 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
283 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
284 CLK_DIVIDER_ONE_BASED, NULL);
285
286static struct clk mpu_ck;
287
288static const char *mpu_ck_parent_names[] = {
289 "dpll1_x2m2_ck",
290};
291
292DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
293DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
294
295DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
296 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
297 OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
298 0x0, NULL);
299
300static struct clk cam_ick;
301
302static struct clk_hw_omap cam_ick_hw = {
303 .hw = {
304 .clk = &cam_ick,
305 },
306 .ops = &clkhwops_iclk,
307 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
308 .enable_bit = OMAP3430_EN_CAM_SHIFT,
309 .clkdm_name = "cam_clkdm",
310};
311
312DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
313
314/* DPLL4 */
315/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
316/* Type: DPLL */
317static struct dpll_data dpll4_dd;
318
319static struct dpll_data dpll4_dd_34xx __initdata = {
320 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
321 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
322 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
323 .clk_bypass = &sys_ck,
324 .clk_ref = &sys_ck,
325 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
326 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
327 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
329 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
330 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
331 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
332 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
333 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
334 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
335 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
336 .max_multiplier = OMAP3_MAX_DPLL_MULT,
337 .min_divider = 1,
338 .max_divider = OMAP3_MAX_DPLL_DIV,
339};
340
341static struct dpll_data dpll4_dd_3630 __initdata = {
342 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
343 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
344 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
345 .clk_bypass = &sys_ck,
346 .clk_ref = &sys_ck,
347 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
348 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
349 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
350 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
353 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
354 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
355 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
356 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
357 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
358 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
359 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
360 .min_divider = 1,
361 .max_divider = OMAP3_MAX_DPLL_DIV,
362 .flags = DPLL_J_TYPE
363};
364
365static struct clk dpll4_ck;
366
367static const struct clk_ops dpll4_ck_ops = {
368 .init = &omap2_init_clk_clkdm,
369 .enable = &omap3_noncore_dpll_enable,
370 .disable = &omap3_noncore_dpll_disable,
371 .get_parent = &omap2_init_dpll_parent,
372 .recalc_rate = &omap3_dpll_recalc,
373 .set_rate = &omap3_dpll4_set_rate,
374 .set_parent = &omap3_noncore_dpll_set_parent,
375 .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent,
376 .determine_rate = &omap3_noncore_dpll_determine_rate,
377 .round_rate = &omap2_dpll_round_rate,
378};
379
380static struct clk_hw_omap dpll4_ck_hw = {
381 .hw = {
382 .clk = &dpll4_ck,
383 },
384 .dpll_data = &dpll4_dd,
385 .ops = &clkhwops_omap3_dpll,
386 .clkdm_name = "dpll4_clkdm",
387};
388
389DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
390
391static const struct clk_div_table dpll4_mx_ck_div_table[] = {
392 { .div = 1, .val = 1 },
393 { .div = 2, .val = 2 },
394 { .div = 3, .val = 3 },
395 { .div = 4, .val = 4 },
396 { .div = 5, .val = 5 },
397 { .div = 6, .val = 6 },
398 { .div = 7, .val = 7 },
399 { .div = 8, .val = 8 },
400 { .div = 9, .val = 9 },
401 { .div = 10, .val = 10 },
402 { .div = 11, .val = 11 },
403 { .div = 12, .val = 12 },
404 { .div = 13, .val = 13 },
405 { .div = 14, .val = 14 },
406 { .div = 15, .val = 15 },
407 { .div = 16, .val = 16 },
408 { .div = 17, .val = 17 },
409 { .div = 18, .val = 18 },
410 { .div = 19, .val = 19 },
411 { .div = 20, .val = 20 },
412 { .div = 21, .val = 21 },
413 { .div = 22, .val = 22 },
414 { .div = 23, .val = 23 },
415 { .div = 24, .val = 24 },
416 { .div = 25, .val = 25 },
417 { .div = 26, .val = 26 },
418 { .div = 27, .val = 27 },
419 { .div = 28, .val = 28 },
420 { .div = 29, .val = 29 },
421 { .div = 30, .val = 30 },
422 { .div = 31, .val = 31 },
423 { .div = 32, .val = 32 },
424 { .div = 0 },
425};
426
427DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
428 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
429 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
430 CLK_DIVIDER_ONE_BASED, NULL);
431
432static struct clk dpll4_m5x2_ck;
433
434static const char *dpll4_m5x2_ck_parent_names[] = {
435 "dpll4_m5_ck",
436};
437
438static const struct clk_ops dpll4_m5x2_ck_ops = {
439 .init = &omap2_init_clk_clkdm,
440 .enable = &omap2_dflt_clk_enable,
441 .disable = &omap2_dflt_clk_disable,
442 .is_enabled = &omap2_dflt_clk_is_enabled,
443 .set_rate = &omap3_clkoutx2_set_rate,
444 .recalc_rate = &omap3_clkoutx2_recalc,
445 .round_rate = &omap3_clkoutx2_round_rate,
446};
447
448static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
449 .init = &omap2_init_clk_clkdm,
450 .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
451 .disable = &omap2_dflt_clk_disable,
452 .recalc_rate = &omap3_clkoutx2_recalc,
453};
454
455static struct clk_hw_omap dpll4_m5x2_ck_hw = {
456 .hw = {
457 .clk = &dpll4_m5x2_ck,
458 },
459 .ops = &clkhwops_wait,
460 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
461 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
462 .flags = INVERT_ENABLE,
463 .clkdm_name = "dpll4_clkdm",
464};
465
466DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
467 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
468
469static struct clk dpll4_m5x2_ck_3630 = {
470 .name = "dpll4_m5x2_ck",
471 .hw = &dpll4_m5x2_ck_hw.hw,
472 .parent_names = dpll4_m5x2_ck_parent_names,
473 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
474 .ops = &dpll4_m5x2_ck_3630_ops,
475 .flags = CLK_SET_RATE_PARENT,
476};
477
478static struct clk cam_mclk;
479
480static const char *cam_mclk_parent_names[] = {
481 "dpll4_m5x2_ck",
482};
483
484static struct clk_hw_omap cam_mclk_hw = {
485 .hw = {
486 .clk = &cam_mclk,
487 },
488 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
489 .enable_bit = OMAP3430_EN_CAM_SHIFT,
490 .clkdm_name = "cam_clkdm",
491};
492
493static struct clk cam_mclk = {
494 .name = "cam_mclk",
495 .hw = &cam_mclk_hw.hw,
496 .parent_names = cam_mclk_parent_names,
497 .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
498 .ops = &aes2_ick_ops,
499 .flags = CLK_SET_RATE_PARENT,
500};
501
502static const struct clksel_rate clkout2_src_core_rates[] = {
503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
504 { .div = 0 }
505};
506
507static const struct clksel_rate clkout2_src_sys_rates[] = {
508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
509 { .div = 0 }
510};
511
512static const struct clksel_rate clkout2_src_96m_rates[] = {
513 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
514 { .div = 0 }
515};
516
517DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
518 OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
519 OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
520 CLK_DIVIDER_ONE_BASED, NULL);
521
522static struct clk dpll4_m2x2_ck;
523
524static const char *dpll4_m2x2_ck_parent_names[] = {
525 "dpll4_m2_ck",
526};
527
528static struct clk_hw_omap dpll4_m2x2_ck_hw = {
529 .hw = {
530 .clk = &dpll4_m2x2_ck,
531 },
532 .ops = &clkhwops_wait,
533 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
534 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
535 .flags = INVERT_ENABLE,
536 .clkdm_name = "dpll4_clkdm",
537};
538
539DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
540
541static struct clk dpll4_m2x2_ck_3630 = {
542 .name = "dpll4_m2x2_ck",
543 .hw = &dpll4_m2x2_ck_hw.hw,
544 .parent_names = dpll4_m2x2_ck_parent_names,
545 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
546 .ops = &dpll4_m5x2_ck_3630_ops,
547};
548
549static struct clk omap_96m_alwon_fck;
550
551static const char *omap_96m_alwon_fck_parent_names[] = {
552 "dpll4_m2x2_ck",
553};
554
555DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
556DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
557 core_ck_ops);
558
559static struct clk cm_96m_fck;
560
561static const char *cm_96m_fck_parent_names[] = {
562 "omap_96m_alwon_fck",
563};
564
565DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
566DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
567
568static const struct clksel_rate clkout2_src_54m_rates[] = {
569 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
570 { .div = 0 }
571};
572
573DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
574 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
575 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
576 0, dpll4_mx_ck_div_table, NULL);
577
578static struct clk dpll4_m3x2_ck;
579
580static const char *dpll4_m3x2_ck_parent_names[] = {
581 "dpll4_m3_ck",
582};
583
584static struct clk_hw_omap dpll4_m3x2_ck_hw = {
585 .hw = {
586 .clk = &dpll4_m3x2_ck,
587 },
588 .ops = &clkhwops_wait,
589 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
590 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
591 .flags = INVERT_ENABLE,
592 .clkdm_name = "dpll4_clkdm",
593};
594
595DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
596
597static struct clk dpll4_m3x2_ck_3630 = {
598 .name = "dpll4_m3x2_ck",
599 .hw = &dpll4_m3x2_ck_hw.hw,
600 .parent_names = dpll4_m3x2_ck_parent_names,
601 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
602 .ops = &dpll4_m5x2_ck_3630_ops,
603};
604
605static const char *omap_54m_fck_parent_names[] = {
606 "dpll4_m3x2_ck", "sys_altclk",
607};
608
609DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
610 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
611 OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
612
613static const struct clksel clkout2_src_clksel[] = {
614 { .parent = &core_ck, .rates = clkout2_src_core_rates },
615 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
616 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
617 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
618 { .parent = NULL },
619};
620
621static const char *clkout2_src_ck_parent_names[] = {
622 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
623};
624
625static const struct clk_ops clkout2_src_ck_ops = {
626 .init = &omap2_init_clk_clkdm,
627 .enable = &omap2_dflt_clk_enable,
628 .disable = &omap2_dflt_clk_disable,
629 .is_enabled = &omap2_dflt_clk_is_enabled,
630 .recalc_rate = &omap2_clksel_recalc,
631 .get_parent = &omap2_clksel_find_parent_index,
632 .set_parent = &omap2_clksel_set_parent,
633};
634
635DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
636 clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
637 OMAP3430_CLKOUT2SOURCE_MASK,
638 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
639 NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
640
641static const struct clksel_rate omap_48m_cm96m_rates[] = {
642 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
643 { .div = 0 }
644};
645
646static const struct clksel_rate omap_48m_alt_rates[] = {
647 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
648 { .div = 0 }
649};
650
651static const struct clksel omap_48m_clksel[] = {
652 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
653 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
654 { .parent = NULL },
655};
656
657static const char *omap_48m_fck_parent_names[] = {
658 "cm_96m_fck", "sys_altclk",
659};
660
661static struct clk omap_48m_fck;
662
663static const struct clk_ops omap_48m_fck_ops = {
664 .recalc_rate = &omap2_clksel_recalc,
665 .get_parent = &omap2_clksel_find_parent_index,
666 .set_parent = &omap2_clksel_set_parent,
667};
668
669static struct clk_hw_omap omap_48m_fck_hw = {
670 .hw = {
671 .clk = &omap_48m_fck,
672 },
673 .clksel = omap_48m_clksel,
674 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
675 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
676};
677
678DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
679
680DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
681
682static struct clk core_12m_fck;
683
684static const char *core_12m_fck_parent_names[] = {
685 "omap_12m_fck",
686};
687
688DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
689DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
690
691static struct clk core_48m_fck;
692
693static const char *core_48m_fck_parent_names[] = {
694 "omap_48m_fck",
695};
696
697DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
698DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
699
700static const char *omap_96m_fck_parent_names[] = {
701 "cm_96m_fck", "sys_ck",
702};
703
704DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
705 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
706 OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
707
708static struct clk core_96m_fck;
709
710static const char *core_96m_fck_parent_names[] = {
711 "omap_96m_fck",
712};
713
714DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
715DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
716
717static struct clk core_l3_ick;
718
719static const char *core_l3_ick_parent_names[] = {
720 "l3_ick",
721};
722
723DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
724DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
725
726DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
727
728static struct clk corex2_fck;
729
730static const char *corex2_fck_parent_names[] = {
731 "dpll3_m2x2_ck",
732};
733
734DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
735DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
736
737static const char *cpefuse_fck_parent_names[] = {
738 "sys_ck",
739};
740
741static struct clk cpefuse_fck;
742
743static struct clk_hw_omap cpefuse_fck_hw = {
744 .hw = {
745 .clk = &cpefuse_fck,
746 },
747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
748 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
749 .clkdm_name = "core_l4_clkdm",
750};
751
752DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
753
754static struct clk csi2_96m_fck;
755
756static const char *csi2_96m_fck_parent_names[] = {
757 "core_96m_fck",
758};
759
760static struct clk_hw_omap csi2_96m_fck_hw = {
761 .hw = {
762 .clk = &csi2_96m_fck,
763 },
764 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
765 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
766 .clkdm_name = "cam_clkdm",
767};
768
769DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
770
771static struct clk d2d_26m_fck;
772
773static struct clk_hw_omap d2d_26m_fck_hw = {
774 .hw = {
775 .clk = &d2d_26m_fck,
776 },
777 .ops = &clkhwops_wait,
778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
779 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
780 .clkdm_name = "d2d_clkdm",
781};
782
783DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
784
785static struct clk des1_ick;
786
787static struct clk_hw_omap des1_ick_hw = {
788 .hw = {
789 .clk = &des1_ick,
790 },
791 .ops = &clkhwops_iclk_wait,
792 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
793 .enable_bit = OMAP3430_EN_DES1_SHIFT,
794};
795
796DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
797
798static struct clk des2_ick;
799
800static struct clk_hw_omap des2_ick_hw = {
801 .hw = {
802 .clk = &des2_ick,
803 },
804 .ops = &clkhwops_iclk_wait,
805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
806 .enable_bit = OMAP3430_EN_DES2_SHIFT,
807 .clkdm_name = "core_l4_clkdm",
808};
809
810DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
811
812DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
813 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
814 OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
815 CLK_DIVIDER_ONE_BASED, NULL);
816
817static struct clk dpll2_fck;
818
819static struct dpll_data dpll2_dd = {
820 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
821 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
822 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
823 .clk_bypass = &dpll2_fck,
824 .clk_ref = &sys_ck,
825 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
826 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
827 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
828 .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
829 (1 << DPLL_LOW_POWER_BYPASS)),
830 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
831 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
832 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
833 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
834 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
835 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
836 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
837 .max_multiplier = OMAP3_MAX_DPLL_MULT,
838 .min_divider = 1,
839 .max_divider = OMAP3_MAX_DPLL_DIV,
840};
841
842static struct clk dpll2_ck;
843
844static struct clk_hw_omap dpll2_ck_hw = {
845 .hw = {
846 .clk = &dpll2_ck,
847 },
848 .ops = &clkhwops_omap3_dpll,
849 .dpll_data = &dpll2_dd,
850 .clkdm_name = "dpll2_clkdm",
851};
852
853DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
854
855DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
856 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
857 OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
858 CLK_DIVIDER_ONE_BASED, NULL);
859
860DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
861 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
862 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
863 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
864 CLK_DIVIDER_ONE_BASED, NULL);
865
866DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
867 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
868 OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
869 CLK_DIVIDER_ONE_BASED, NULL);
870
871static struct clk dpll3_m3x2_ck;
872
873static const char *dpll3_m3x2_ck_parent_names[] = {
874 "dpll3_m3_ck",
875};
876
877static struct clk_hw_omap dpll3_m3x2_ck_hw = {
878 .hw = {
879 .clk = &dpll3_m3x2_ck,
880 },
881 .ops = &clkhwops_wait,
882 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
883 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
884 .flags = INVERT_ENABLE,
885 .clkdm_name = "dpll3_clkdm",
886};
887
888DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
889
890static struct clk dpll3_m3x2_ck_3630 = {
891 .name = "dpll3_m3x2_ck",
892 .hw = &dpll3_m3x2_ck_hw.hw,
893 .parent_names = dpll3_m3x2_ck_parent_names,
894 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
895 .ops = &dpll4_m5x2_ck_3630_ops,
896};
897
898DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
899
900DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
901 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
902 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
903 0, dpll4_mx_ck_div_table, NULL);
904
905static struct clk dpll4_m4x2_ck;
906
907static const char *dpll4_m4x2_ck_parent_names[] = {
908 "dpll4_m4_ck",
909};
910
911static struct clk_hw_omap dpll4_m4x2_ck_hw = {
912 .hw = {
913 .clk = &dpll4_m4x2_ck,
914 },
915 .ops = &clkhwops_wait,
916 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
917 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
918 .flags = INVERT_ENABLE,
919 .clkdm_name = "dpll4_clkdm",
920};
921
922DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
923 dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
924
925static struct clk dpll4_m4x2_ck_3630 = {
926 .name = "dpll4_m4x2_ck",
927 .hw = &dpll4_m4x2_ck_hw.hw,
928 .parent_names = dpll4_m4x2_ck_parent_names,
929 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
930 .ops = &dpll4_m5x2_ck_3630_ops,
931 .flags = CLK_SET_RATE_PARENT,
932};
933
934DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
935 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
936 OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
937 CLK_DIVIDER_ONE_BASED, NULL);
938
939static struct clk dpll4_m6x2_ck;
940
941static const char *dpll4_m6x2_ck_parent_names[] = {
942 "dpll4_m6_ck",
943};
944
945static struct clk_hw_omap dpll4_m6x2_ck_hw = {
946 .hw = {
947 .clk = &dpll4_m6x2_ck,
948 },
949 .ops = &clkhwops_wait,
950 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
951 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
952 .flags = INVERT_ENABLE,
953 .clkdm_name = "dpll4_clkdm",
954};
955
956DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
957
958static struct clk dpll4_m6x2_ck_3630 = {
959 .name = "dpll4_m6x2_ck",
960 .hw = &dpll4_m6x2_ck_hw.hw,
961 .parent_names = dpll4_m6x2_ck_parent_names,
962 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
963 .ops = &dpll4_m5x2_ck_3630_ops,
964};
965
966DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
967
968static struct dpll_data dpll5_dd = {
969 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
970 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
971 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
972 .clk_bypass = &sys_ck,
973 .clk_ref = &sys_ck,
974 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
975 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
976 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
977 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
978 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
979 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
980 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
981 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
982 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
983 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
984 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
985 .max_multiplier = OMAP3_MAX_DPLL_MULT,
986 .min_divider = 1,
987 .max_divider = OMAP3_MAX_DPLL_DIV,
988};
989
990static struct clk dpll5_ck;
991
992static struct clk_hw_omap dpll5_ck_hw = {
993 .hw = {
994 .clk = &dpll5_ck,
995 },
996 .ops = &clkhwops_omap3_dpll,
997 .dpll_data = &dpll5_dd,
998 .clkdm_name = "dpll5_clkdm",
999};
1000
1001DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
1002
1003DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
1004 OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1005 OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
1006 CLK_DIVIDER_ONE_BASED, NULL);
1007
1008static struct clk dss1_alwon_fck_3430es1;
1009
1010static const char *dss1_alwon_fck_3430es1_parent_names[] = {
1011 "dpll4_m4x2_ck",
1012};
1013
1014static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
1015 .hw = {
1016 .clk = &dss1_alwon_fck_3430es1,
1017 },
1018 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1019 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1020 .clkdm_name = "dss_clkdm",
1021};
1022
1023DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
1024 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1025 CLK_SET_RATE_PARENT);
1026
1027static struct clk dss1_alwon_fck_3430es2;
1028
1029static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
1030 .hw = {
1031 .clk = &dss1_alwon_fck_3430es2,
1032 },
1033 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
1034 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1035 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1036 .clkdm_name = "dss_clkdm",
1037};
1038
1039DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
1040 dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
1041 CLK_SET_RATE_PARENT);
1042
1043static struct clk dss2_alwon_fck;
1044
1045static struct clk_hw_omap dss2_alwon_fck_hw = {
1046 .hw = {
1047 .clk = &dss2_alwon_fck,
1048 },
1049 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1050 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
1051 .clkdm_name = "dss_clkdm",
1052};
1053
1054DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
1055
1056static struct clk dss_96m_fck;
1057
1058static struct clk_hw_omap dss_96m_fck_hw = {
1059 .hw = {
1060 .clk = &dss_96m_fck,
1061 },
1062 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1063 .enable_bit = OMAP3430_EN_TV_SHIFT,
1064 .clkdm_name = "dss_clkdm",
1065};
1066
1067DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1068
1069static struct clk dss_ick_3430es1;
1070
1071static struct clk_hw_omap dss_ick_3430es1_hw = {
1072 .hw = {
1073 .clk = &dss_ick_3430es1,
1074 },
1075 .ops = &clkhwops_iclk,
1076 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1077 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1078 .clkdm_name = "dss_clkdm",
1079};
1080
1081DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1082
1083static struct clk dss_ick_3430es2;
1084
1085static struct clk_hw_omap dss_ick_3430es2_hw = {
1086 .hw = {
1087 .clk = &dss_ick_3430es2,
1088 },
1089 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1090 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1091 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1092 .clkdm_name = "dss_clkdm",
1093};
1094
1095DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1096
1097static struct clk dss_tv_fck;
1098
1099static const char *dss_tv_fck_parent_names[] = {
1100 "omap_54m_fck",
1101};
1102
1103static struct clk_hw_omap dss_tv_fck_hw = {
1104 .hw = {
1105 .clk = &dss_tv_fck,
1106 },
1107 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1108 .enable_bit = OMAP3430_EN_TV_SHIFT,
1109 .clkdm_name = "dss_clkdm",
1110};
1111
1112DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1113
1114static struct clk emac_fck;
1115
1116static const char *emac_fck_parent_names[] = {
1117 "rmii_ck",
1118};
1119
1120static struct clk_hw_omap emac_fck_hw = {
1121 .hw = {
1122 .clk = &emac_fck,
1123 },
1124 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1125 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
1126};
1127
1128DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1129
1130static struct clk ipss_ick;
1131
1132static const char *ipss_ick_parent_names[] = {
1133 "core_l3_ick",
1134};
1135
1136static struct clk_hw_omap ipss_ick_hw = {
1137 .hw = {
1138 .clk = &ipss_ick,
1139 },
1140 .ops = &clkhwops_am35xx_ipss_wait,
1141 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1142 .enable_bit = AM35XX_EN_IPSS_SHIFT,
1143 .clkdm_name = "core_l3_clkdm",
1144};
1145
1146DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1147
1148static struct clk emac_ick;
1149
1150static const char *emac_ick_parent_names[] = {
1151 "ipss_ick",
1152};
1153
1154static struct clk_hw_omap emac_ick_hw = {
1155 .hw = {
1156 .clk = &emac_ick,
1157 },
1158 .ops = &clkhwops_am35xx_ipss_module_wait,
1159 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1160 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1161 .clkdm_name = "core_l3_clkdm",
1162};
1163
1164DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1165
1166static struct clk emu_core_alwon_ck;
1167
1168static const char *emu_core_alwon_ck_parent_names[] = {
1169 "dpll3_m3x2_ck",
1170};
1171
1172DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1173DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1174 core_l4_ick_ops);
1175
1176static struct clk emu_mpu_alwon_ck;
1177
1178static const char *emu_mpu_alwon_ck_parent_names[] = {
1179 "mpu_ck",
1180};
1181
1182DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1183DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1184
1185static struct clk emu_per_alwon_ck;
1186
1187static const char *emu_per_alwon_ck_parent_names[] = {
1188 "dpll4_m6x2_ck",
1189};
1190
1191DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1192DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1193 core_l4_ick_ops);
1194
1195static const char *emu_src_ck_parent_names[] = {
1196 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1197};
1198
1199static const struct clksel_rate emu_src_sys_rates[] = {
1200 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1201 { .div = 0 },
1202};
1203
1204static const struct clksel_rate emu_src_core_rates[] = {
1205 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1206 { .div = 0 },
1207};
1208
1209static const struct clksel_rate emu_src_per_rates[] = {
1210 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1211 { .div = 0 },
1212};
1213
1214static const struct clksel_rate emu_src_mpu_rates[] = {
1215 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1216 { .div = 0 },
1217};
1218
1219static const struct clksel emu_src_clksel[] = {
1220 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1221 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1222 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1223 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
1224 { .parent = NULL },
1225};
1226
1227static const struct clk_ops emu_src_ck_ops = {
1228 .init = &omap2_init_clk_clkdm,
1229 .recalc_rate = &omap2_clksel_recalc,
1230 .get_parent = &omap2_clksel_find_parent_index,
1231 .set_parent = &omap2_clksel_set_parent,
1232 .enable = &omap2_clkops_enable_clkdm,
1233 .disable = &omap2_clkops_disable_clkdm,
1234};
1235
1236static struct clk emu_src_ck;
1237
1238static struct clk_hw_omap emu_src_ck_hw = {
1239 .hw = {
1240 .clk = &emu_src_ck,
1241 },
1242 .clksel = emu_src_clksel,
1243 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1244 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
1245 .clkdm_name = "emu_clkdm",
1246};
1247
1248DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1249
1250DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1251 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1252 OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1253 CLK_DIVIDER_ONE_BASED, NULL);
1254
1255static struct clk fac_ick;
1256
1257static struct clk_hw_omap fac_ick_hw = {
1258 .hw = {
1259 .clk = &fac_ick,
1260 },
1261 .ops = &clkhwops_iclk_wait,
1262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1263 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1264 .clkdm_name = "core_l4_clkdm",
1265};
1266
1267DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1268
1269static struct clk fshostusb_fck;
1270
1271static const char *fshostusb_fck_parent_names[] = {
1272 "core_48m_fck",
1273};
1274
1275static struct clk_hw_omap fshostusb_fck_hw = {
1276 .hw = {
1277 .clk = &fshostusb_fck,
1278 },
1279 .ops = &clkhwops_wait,
1280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1281 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1282 .clkdm_name = "core_l4_clkdm",
1283};
1284
1285DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1286
1287static struct clk gfx_l3_ck;
1288
1289static struct clk_hw_omap gfx_l3_ck_hw = {
1290 .hw = {
1291 .clk = &gfx_l3_ck,
1292 },
1293 .ops = &clkhwops_wait,
1294 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1295 .enable_bit = OMAP_EN_GFX_SHIFT,
1296 .clkdm_name = "gfx_3430es1_clkdm",
1297};
1298
1299DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1300
1301DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1302 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1303 OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1304 CLK_DIVIDER_ONE_BASED, NULL);
1305
1306static struct clk gfx_cg1_ck;
1307
1308static const char *gfx_cg1_ck_parent_names[] = {
1309 "gfx_l3_fck",
1310};
1311
1312static struct clk_hw_omap gfx_cg1_ck_hw = {
1313 .hw = {
1314 .clk = &gfx_cg1_ck,
1315 },
1316 .ops = &clkhwops_wait,
1317 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1318 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1319 .clkdm_name = "gfx_3430es1_clkdm",
1320};
1321
1322DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1323
1324static struct clk gfx_cg2_ck;
1325
1326static struct clk_hw_omap gfx_cg2_ck_hw = {
1327 .hw = {
1328 .clk = &gfx_cg2_ck,
1329 },
1330 .ops = &clkhwops_wait,
1331 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1332 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1333 .clkdm_name = "gfx_3430es1_clkdm",
1334};
1335
1336DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1337
1338static struct clk gfx_l3_ick;
1339
1340static const char *gfx_l3_ick_parent_names[] = {
1341 "gfx_l3_ck",
1342};
1343
1344DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1345DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1346
1347static struct clk wkup_32k_fck;
1348
1349static const char *wkup_32k_fck_parent_names[] = {
1350 "omap_32k_fck",
1351};
1352
1353DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1354DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1355
1356static struct clk gpio1_dbck;
1357
1358static const char *gpio1_dbck_parent_names[] = {
1359 "wkup_32k_fck",
1360};
1361
1362static struct clk_hw_omap gpio1_dbck_hw = {
1363 .hw = {
1364 .clk = &gpio1_dbck,
1365 },
1366 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1367 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1368 .clkdm_name = "wkup_clkdm",
1369};
1370
1371DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1372
1373static struct clk wkup_l4_ick;
1374
1375DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1376DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
1377
1378static struct clk gpio1_ick;
1379
1380static const char *gpio1_ick_parent_names[] = {
1381 "wkup_l4_ick",
1382};
1383
1384static struct clk_hw_omap gpio1_ick_hw = {
1385 .hw = {
1386 .clk = &gpio1_ick,
1387 },
1388 .ops = &clkhwops_iclk_wait,
1389 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1390 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1391 .clkdm_name = "wkup_clkdm",
1392};
1393
1394DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1395
1396static struct clk per_32k_alwon_fck;
1397
1398DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1399DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1400 core_l4_ick_ops);
1401
1402static struct clk gpio2_dbck;
1403
1404static const char *gpio2_dbck_parent_names[] = {
1405 "per_32k_alwon_fck",
1406};
1407
1408static struct clk_hw_omap gpio2_dbck_hw = {
1409 .hw = {
1410 .clk = &gpio2_dbck,
1411 },
1412 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1413 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1414 .clkdm_name = "per_clkdm",
1415};
1416
1417DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1418
1419static struct clk per_l4_ick;
1420
1421DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1422DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1423
1424static struct clk gpio2_ick;
1425
1426static const char *gpio2_ick_parent_names[] = {
1427 "per_l4_ick",
1428};
1429
1430static struct clk_hw_omap gpio2_ick_hw = {
1431 .hw = {
1432 .clk = &gpio2_ick,
1433 },
1434 .ops = &clkhwops_iclk_wait,
1435 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1436 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1437 .clkdm_name = "per_clkdm",
1438};
1439
1440DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1441
1442static struct clk gpio3_dbck;
1443
1444static struct clk_hw_omap gpio3_dbck_hw = {
1445 .hw = {
1446 .clk = &gpio3_dbck,
1447 },
1448 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1449 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1450 .clkdm_name = "per_clkdm",
1451};
1452
1453DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1454
1455static struct clk gpio3_ick;
1456
1457static struct clk_hw_omap gpio3_ick_hw = {
1458 .hw = {
1459 .clk = &gpio3_ick,
1460 },
1461 .ops = &clkhwops_iclk_wait,
1462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1463 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1464 .clkdm_name = "per_clkdm",
1465};
1466
1467DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1468
1469static struct clk gpio4_dbck;
1470
1471static struct clk_hw_omap gpio4_dbck_hw = {
1472 .hw = {
1473 .clk = &gpio4_dbck,
1474 },
1475 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1476 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1477 .clkdm_name = "per_clkdm",
1478};
1479
1480DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1481
1482static struct clk gpio4_ick;
1483
1484static struct clk_hw_omap gpio4_ick_hw = {
1485 .hw = {
1486 .clk = &gpio4_ick,
1487 },
1488 .ops = &clkhwops_iclk_wait,
1489 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1490 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1491 .clkdm_name = "per_clkdm",
1492};
1493
1494DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1495
1496static struct clk gpio5_dbck;
1497
1498static struct clk_hw_omap gpio5_dbck_hw = {
1499 .hw = {
1500 .clk = &gpio5_dbck,
1501 },
1502 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1503 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1504 .clkdm_name = "per_clkdm",
1505};
1506
1507DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1508
1509static struct clk gpio5_ick;
1510
1511static struct clk_hw_omap gpio5_ick_hw = {
1512 .hw = {
1513 .clk = &gpio5_ick,
1514 },
1515 .ops = &clkhwops_iclk_wait,
1516 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1517 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1518 .clkdm_name = "per_clkdm",
1519};
1520
1521DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1522
1523static struct clk gpio6_dbck;
1524
1525static struct clk_hw_omap gpio6_dbck_hw = {
1526 .hw = {
1527 .clk = &gpio6_dbck,
1528 },
1529 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1530 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1531 .clkdm_name = "per_clkdm",
1532};
1533
1534DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1535
1536static struct clk gpio6_ick;
1537
1538static struct clk_hw_omap gpio6_ick_hw = {
1539 .hw = {
1540 .clk = &gpio6_ick,
1541 },
1542 .ops = &clkhwops_iclk_wait,
1543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1544 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1545 .clkdm_name = "per_clkdm",
1546};
1547
1548DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1549
1550static struct clk gpmc_fck;
1551
1552static struct clk_hw_omap gpmc_fck_hw = {
1553 .hw = {
1554 .clk = &gpmc_fck,
1555 },
1556 .flags = ENABLE_ON_INIT,
1557 .clkdm_name = "core_l3_clkdm",
1558};
1559
1560DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1561
1562static const struct clksel omap343x_gpt_clksel[] = {
1563 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1564 { .parent = &sys_ck, .rates = gpt_sys_rates },
1565 { .parent = NULL },
1566};
1567
1568static const char *gpt10_fck_parent_names[] = {
1569 "omap_32k_fck", "sys_ck",
1570};
1571
1572DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1573 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1574 OMAP3430_CLKSEL_GPT10_MASK,
1575 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1576 OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1577 gpt10_fck_parent_names, clkout2_src_ck_ops);
1578
1579static struct clk gpt10_ick;
1580
1581static struct clk_hw_omap gpt10_ick_hw = {
1582 .hw = {
1583 .clk = &gpt10_ick,
1584 },
1585 .ops = &clkhwops_iclk_wait,
1586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1587 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1588 .clkdm_name = "core_l4_clkdm",
1589};
1590
1591DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1592
1593DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1594 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1595 OMAP3430_CLKSEL_GPT11_MASK,
1596 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1597 OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1598 gpt10_fck_parent_names, clkout2_src_ck_ops);
1599
1600static struct clk gpt11_ick;
1601
1602static struct clk_hw_omap gpt11_ick_hw = {
1603 .hw = {
1604 .clk = &gpt11_ick,
1605 },
1606 .ops = &clkhwops_iclk_wait,
1607 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1608 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1609 .clkdm_name = "core_l4_clkdm",
1610};
1611
1612DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1613
1614static struct clk gpt12_fck;
1615
1616static const char *gpt12_fck_parent_names[] = {
1617 "secure_32k_fck",
1618};
1619
1620DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1621DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1622
1623static struct clk gpt12_ick;
1624
1625static struct clk_hw_omap gpt12_ick_hw = {
1626 .hw = {
1627 .clk = &gpt12_ick,
1628 },
1629 .ops = &clkhwops_iclk_wait,
1630 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1631 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1632 .clkdm_name = "wkup_clkdm",
1633};
1634
1635DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1636
1637DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1638 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1639 OMAP3430_CLKSEL_GPT1_MASK,
1640 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1641 OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1642 gpt10_fck_parent_names, clkout2_src_ck_ops);
1643
1644static struct clk gpt1_ick;
1645
1646static struct clk_hw_omap gpt1_ick_hw = {
1647 .hw = {
1648 .clk = &gpt1_ick,
1649 },
1650 .ops = &clkhwops_iclk_wait,
1651 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1652 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1653 .clkdm_name = "wkup_clkdm",
1654};
1655
1656DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1657
1658DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1659 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1660 OMAP3430_CLKSEL_GPT2_MASK,
1661 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1662 OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1663 gpt10_fck_parent_names, clkout2_src_ck_ops);
1664
1665static struct clk gpt2_ick;
1666
1667static struct clk_hw_omap gpt2_ick_hw = {
1668 .hw = {
1669 .clk = &gpt2_ick,
1670 },
1671 .ops = &clkhwops_iclk_wait,
1672 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1673 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1674 .clkdm_name = "per_clkdm",
1675};
1676
1677DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1678
1679DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1680 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1681 OMAP3430_CLKSEL_GPT3_MASK,
1682 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1683 OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1684 gpt10_fck_parent_names, clkout2_src_ck_ops);
1685
1686static struct clk gpt3_ick;
1687
1688static struct clk_hw_omap gpt3_ick_hw = {
1689 .hw = {
1690 .clk = &gpt3_ick,
1691 },
1692 .ops = &clkhwops_iclk_wait,
1693 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1694 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1695 .clkdm_name = "per_clkdm",
1696};
1697
1698DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1699
1700DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1701 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1702 OMAP3430_CLKSEL_GPT4_MASK,
1703 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1704 OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1705 gpt10_fck_parent_names, clkout2_src_ck_ops);
1706
1707static struct clk gpt4_ick;
1708
1709static struct clk_hw_omap gpt4_ick_hw = {
1710 .hw = {
1711 .clk = &gpt4_ick,
1712 },
1713 .ops = &clkhwops_iclk_wait,
1714 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1715 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1716 .clkdm_name = "per_clkdm",
1717};
1718
1719DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1720
1721DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1722 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1723 OMAP3430_CLKSEL_GPT5_MASK,
1724 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1725 OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1726 gpt10_fck_parent_names, clkout2_src_ck_ops);
1727
1728static struct clk gpt5_ick;
1729
1730static struct clk_hw_omap gpt5_ick_hw = {
1731 .hw = {
1732 .clk = &gpt5_ick,
1733 },
1734 .ops = &clkhwops_iclk_wait,
1735 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1736 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1737 .clkdm_name = "per_clkdm",
1738};
1739
1740DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1741
1742DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1743 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1744 OMAP3430_CLKSEL_GPT6_MASK,
1745 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1746 OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1747 gpt10_fck_parent_names, clkout2_src_ck_ops);
1748
1749static struct clk gpt6_ick;
1750
1751static struct clk_hw_omap gpt6_ick_hw = {
1752 .hw = {
1753 .clk = &gpt6_ick,
1754 },
1755 .ops = &clkhwops_iclk_wait,
1756 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1757 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1758 .clkdm_name = "per_clkdm",
1759};
1760
1761DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1762
1763DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1764 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1765 OMAP3430_CLKSEL_GPT7_MASK,
1766 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1767 OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1768 gpt10_fck_parent_names, clkout2_src_ck_ops);
1769
1770static struct clk gpt7_ick;
1771
1772static struct clk_hw_omap gpt7_ick_hw = {
1773 .hw = {
1774 .clk = &gpt7_ick,
1775 },
1776 .ops = &clkhwops_iclk_wait,
1777 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1778 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1779 .clkdm_name = "per_clkdm",
1780};
1781
1782DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1783
1784DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1785 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1786 OMAP3430_CLKSEL_GPT8_MASK,
1787 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1788 OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1789 gpt10_fck_parent_names, clkout2_src_ck_ops);
1790
1791static struct clk gpt8_ick;
1792
1793static struct clk_hw_omap gpt8_ick_hw = {
1794 .hw = {
1795 .clk = &gpt8_ick,
1796 },
1797 .ops = &clkhwops_iclk_wait,
1798 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1799 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1800 .clkdm_name = "per_clkdm",
1801};
1802
1803DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1804
1805DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1806 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1807 OMAP3430_CLKSEL_GPT9_MASK,
1808 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1809 OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1810 gpt10_fck_parent_names, clkout2_src_ck_ops);
1811
1812static struct clk gpt9_ick;
1813
1814static struct clk_hw_omap gpt9_ick_hw = {
1815 .hw = {
1816 .clk = &gpt9_ick,
1817 },
1818 .ops = &clkhwops_iclk_wait,
1819 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1820 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1821 .clkdm_name = "per_clkdm",
1822};
1823
1824DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1825
1826static struct clk hdq_fck;
1827
1828static const char *hdq_fck_parent_names[] = {
1829 "core_12m_fck",
1830};
1831
1832static struct clk_hw_omap hdq_fck_hw = {
1833 .hw = {
1834 .clk = &hdq_fck,
1835 },
1836 .ops = &clkhwops_wait,
1837 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1838 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1839 .clkdm_name = "core_l4_clkdm",
1840};
1841
1842DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1843
1844static struct clk hdq_ick;
1845
1846static struct clk_hw_omap hdq_ick_hw = {
1847 .hw = {
1848 .clk = &hdq_ick,
1849 },
1850 .ops = &clkhwops_iclk_wait,
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1852 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1853 .clkdm_name = "core_l4_clkdm",
1854};
1855
1856DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1857
1858static struct clk hecc_ck;
1859
1860static struct clk_hw_omap hecc_ck_hw = {
1861 .hw = {
1862 .clk = &hecc_ck,
1863 },
1864 .ops = &clkhwops_am35xx_ipss_module_wait,
1865 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1866 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
1867 .clkdm_name = "core_l3_clkdm",
1868};
1869
1870DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
1871
1872static struct clk hsotgusb_fck_am35xx;
1873
1874static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1875 .hw = {
1876 .clk = &hsotgusb_fck_am35xx,
1877 },
1878 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1879 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
1880 .clkdm_name = "core_l3_clkdm",
1881};
1882
1883DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
1884
1885static struct clk hsotgusb_ick_3430es1;
1886
1887static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1888 .hw = {
1889 .clk = &hsotgusb_ick_3430es1,
1890 },
1891 .ops = &clkhwops_iclk,
1892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1893 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1894 .clkdm_name = "core_l3_clkdm",
1895};
1896
1897DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1898
1899static struct clk hsotgusb_ick_3430es2;
1900
1901static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1902 .hw = {
1903 .clk = &hsotgusb_ick_3430es2,
1904 },
1905 .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1908 .clkdm_name = "core_l3_clkdm",
1909};
1910
1911DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1912
1913static struct clk hsotgusb_ick_am35xx;
1914
1915static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1916 .hw = {
1917 .clk = &hsotgusb_ick_am35xx,
1918 },
1919 .ops = &clkhwops_am35xx_ipss_module_wait,
1920 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1921 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1922 .clkdm_name = "core_l3_clkdm",
1923};
1924
1925DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1926
1927static struct clk i2c1_fck;
1928
1929static struct clk_hw_omap i2c1_fck_hw = {
1930 .hw = {
1931 .clk = &i2c1_fck,
1932 },
1933 .ops = &clkhwops_wait,
1934 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1935 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1936 .clkdm_name = "core_l4_clkdm",
1937};
1938
1939DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1940
1941static struct clk i2c1_ick;
1942
1943static struct clk_hw_omap i2c1_ick_hw = {
1944 .hw = {
1945 .clk = &i2c1_ick,
1946 },
1947 .ops = &clkhwops_iclk_wait,
1948 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1949 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1950 .clkdm_name = "core_l4_clkdm",
1951};
1952
1953DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1954
1955static struct clk i2c2_fck;
1956
1957static struct clk_hw_omap i2c2_fck_hw = {
1958 .hw = {
1959 .clk = &i2c2_fck,
1960 },
1961 .ops = &clkhwops_wait,
1962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1963 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1964 .clkdm_name = "core_l4_clkdm",
1965};
1966
1967DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1968
1969static struct clk i2c2_ick;
1970
1971static struct clk_hw_omap i2c2_ick_hw = {
1972 .hw = {
1973 .clk = &i2c2_ick,
1974 },
1975 .ops = &clkhwops_iclk_wait,
1976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1978 .clkdm_name = "core_l4_clkdm",
1979};
1980
1981DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1982
1983static struct clk i2c3_fck;
1984
1985static struct clk_hw_omap i2c3_fck_hw = {
1986 .hw = {
1987 .clk = &i2c3_fck,
1988 },
1989 .ops = &clkhwops_wait,
1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1991 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1992 .clkdm_name = "core_l4_clkdm",
1993};
1994
1995DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1996
1997static struct clk i2c3_ick;
1998
1999static struct clk_hw_omap i2c3_ick_hw = {
2000 .hw = {
2001 .clk = &i2c3_ick,
2002 },
2003 .ops = &clkhwops_iclk_wait,
2004 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2005 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
2006 .clkdm_name = "core_l4_clkdm",
2007};
2008
2009DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
2010
2011static struct clk icr_ick;
2012
2013static struct clk_hw_omap icr_ick_hw = {
2014 .hw = {
2015 .clk = &icr_ick,
2016 },
2017 .ops = &clkhwops_iclk_wait,
2018 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019 .enable_bit = OMAP3430_EN_ICR_SHIFT,
2020 .clkdm_name = "core_l4_clkdm",
2021};
2022
2023DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
2024
2025static struct clk iva2_ck;
2026
2027static const char *iva2_ck_parent_names[] = {
2028 "dpll2_m2_ck",
2029};
2030
2031static struct clk_hw_omap iva2_ck_hw = {
2032 .hw = {
2033 .clk = &iva2_ck,
2034 },
2035 .ops = &clkhwops_wait,
2036 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
2037 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
2038 .clkdm_name = "iva2_clkdm",
2039};
2040
2041DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
2042
2043static struct clk mad2d_ick;
2044
2045static struct clk_hw_omap mad2d_ick_hw = {
2046 .hw = {
2047 .clk = &mad2d_ick,
2048 },
2049 .ops = &clkhwops_iclk_wait,
2050 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2051 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
2052 .clkdm_name = "d2d_clkdm",
2053};
2054
2055DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2056
2057static struct clk mailboxes_ick;
2058
2059static struct clk_hw_omap mailboxes_ick_hw = {
2060 .hw = {
2061 .clk = &mailboxes_ick,
2062 },
2063 .ops = &clkhwops_iclk_wait,
2064 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2065 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2066 .clkdm_name = "core_l4_clkdm",
2067};
2068
2069DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2070
2071static const struct clksel_rate common_mcbsp_96m_rates[] = {
2072 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2073 { .div = 0 }
2074};
2075
2076static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2077 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2078 { .div = 0 }
2079};
2080
2081static const struct clksel mcbsp_15_clksel[] = {
2082 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2083 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2084 { .parent = NULL },
2085};
2086
2087static const char *mcbsp1_fck_parent_names[] = {
2088 "core_96m_fck", "mcbsp_clks",
2089};
2090
2091DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2092 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2093 OMAP2_MCBSP1_CLKS_MASK,
2094 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2095 OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2096 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2097
2098static struct clk mcbsp1_ick;
2099
2100static struct clk_hw_omap mcbsp1_ick_hw = {
2101 .hw = {
2102 .clk = &mcbsp1_ick,
2103 },
2104 .ops = &clkhwops_iclk_wait,
2105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2106 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2107 .clkdm_name = "core_l4_clkdm",
2108};
2109
2110DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2111
2112static struct clk per_96m_fck;
2113
2114DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2115DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2116
2117static const struct clksel mcbsp_234_clksel[] = {
2118 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2119 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2120 { .parent = NULL },
2121};
2122
2123static const char *mcbsp2_fck_parent_names[] = {
2124 "per_96m_fck", "mcbsp_clks",
2125};
2126
2127DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2128 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2129 OMAP2_MCBSP2_CLKS_MASK,
2130 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2131 OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2132 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2133
2134static struct clk mcbsp2_ick;
2135
2136static struct clk_hw_omap mcbsp2_ick_hw = {
2137 .hw = {
2138 .clk = &mcbsp2_ick,
2139 },
2140 .ops = &clkhwops_iclk_wait,
2141 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2142 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2143 .clkdm_name = "per_clkdm",
2144};
2145
2146DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2147
2148DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2149 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2150 OMAP2_MCBSP3_CLKS_MASK,
2151 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2152 OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2153 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2154
2155static struct clk mcbsp3_ick;
2156
2157static struct clk_hw_omap mcbsp3_ick_hw = {
2158 .hw = {
2159 .clk = &mcbsp3_ick,
2160 },
2161 .ops = &clkhwops_iclk_wait,
2162 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2163 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2164 .clkdm_name = "per_clkdm",
2165};
2166
2167DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2168
2169DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2170 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2171 OMAP2_MCBSP4_CLKS_MASK,
2172 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2173 OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2174 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2175
2176static struct clk mcbsp4_ick;
2177
2178static struct clk_hw_omap mcbsp4_ick_hw = {
2179 .hw = {
2180 .clk = &mcbsp4_ick,
2181 },
2182 .ops = &clkhwops_iclk_wait,
2183 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2184 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2185 .clkdm_name = "per_clkdm",
2186};
2187
2188DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2189
2190DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2191 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2192 OMAP2_MCBSP5_CLKS_MASK,
2193 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2194 OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2195 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2196
2197static struct clk mcbsp5_ick;
2198
2199static struct clk_hw_omap mcbsp5_ick_hw = {
2200 .hw = {
2201 .clk = &mcbsp5_ick,
2202 },
2203 .ops = &clkhwops_iclk_wait,
2204 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2205 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2206 .clkdm_name = "core_l4_clkdm",
2207};
2208
2209DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2210
2211static struct clk mcspi1_fck;
2212
2213static struct clk_hw_omap mcspi1_fck_hw = {
2214 .hw = {
2215 .clk = &mcspi1_fck,
2216 },
2217 .ops = &clkhwops_wait,
2218 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2219 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2220 .clkdm_name = "core_l4_clkdm",
2221};
2222
2223DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2224
2225static struct clk mcspi1_ick;
2226
2227static struct clk_hw_omap mcspi1_ick_hw = {
2228 .hw = {
2229 .clk = &mcspi1_ick,
2230 },
2231 .ops = &clkhwops_iclk_wait,
2232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2233 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2234 .clkdm_name = "core_l4_clkdm",
2235};
2236
2237DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2238
2239static struct clk mcspi2_fck;
2240
2241static struct clk_hw_omap mcspi2_fck_hw = {
2242 .hw = {
2243 .clk = &mcspi2_fck,
2244 },
2245 .ops = &clkhwops_wait,
2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2247 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2248 .clkdm_name = "core_l4_clkdm",
2249};
2250
2251DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2252
2253static struct clk mcspi2_ick;
2254
2255static struct clk_hw_omap mcspi2_ick_hw = {
2256 .hw = {
2257 .clk = &mcspi2_ick,
2258 },
2259 .ops = &clkhwops_iclk_wait,
2260 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2261 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2262 .clkdm_name = "core_l4_clkdm",
2263};
2264
2265DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2266
2267static struct clk mcspi3_fck;
2268
2269static struct clk_hw_omap mcspi3_fck_hw = {
2270 .hw = {
2271 .clk = &mcspi3_fck,
2272 },
2273 .ops = &clkhwops_wait,
2274 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2275 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2276 .clkdm_name = "core_l4_clkdm",
2277};
2278
2279DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2280
2281static struct clk mcspi3_ick;
2282
2283static struct clk_hw_omap mcspi3_ick_hw = {
2284 .hw = {
2285 .clk = &mcspi3_ick,
2286 },
2287 .ops = &clkhwops_iclk_wait,
2288 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2289 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2290 .clkdm_name = "core_l4_clkdm",
2291};
2292
2293DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2294
2295static struct clk mcspi4_fck;
2296
2297static struct clk_hw_omap mcspi4_fck_hw = {
2298 .hw = {
2299 .clk = &mcspi4_fck,
2300 },
2301 .ops = &clkhwops_wait,
2302 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2303 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2304 .clkdm_name = "core_l4_clkdm",
2305};
2306
2307DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2308
2309static struct clk mcspi4_ick;
2310
2311static struct clk_hw_omap mcspi4_ick_hw = {
2312 .hw = {
2313 .clk = &mcspi4_ick,
2314 },
2315 .ops = &clkhwops_iclk_wait,
2316 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2317 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2318 .clkdm_name = "core_l4_clkdm",
2319};
2320
2321DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2322
2323static struct clk mmchs1_fck;
2324
2325static struct clk_hw_omap mmchs1_fck_hw = {
2326 .hw = {
2327 .clk = &mmchs1_fck,
2328 },
2329 .ops = &clkhwops_wait,
2330 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2331 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2332 .clkdm_name = "core_l4_clkdm",
2333};
2334
2335DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2336
2337static struct clk mmchs1_ick;
2338
2339static struct clk_hw_omap mmchs1_ick_hw = {
2340 .hw = {
2341 .clk = &mmchs1_ick,
2342 },
2343 .ops = &clkhwops_iclk_wait,
2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2345 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2346 .clkdm_name = "core_l4_clkdm",
2347};
2348
2349DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2350
2351static struct clk mmchs2_fck;
2352
2353static struct clk_hw_omap mmchs2_fck_hw = {
2354 .hw = {
2355 .clk = &mmchs2_fck,
2356 },
2357 .ops = &clkhwops_wait,
2358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2359 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2360 .clkdm_name = "core_l4_clkdm",
2361};
2362
2363DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2364
2365static struct clk mmchs2_ick;
2366
2367static struct clk_hw_omap mmchs2_ick_hw = {
2368 .hw = {
2369 .clk = &mmchs2_ick,
2370 },
2371 .ops = &clkhwops_iclk_wait,
2372 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2373 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2374 .clkdm_name = "core_l4_clkdm",
2375};
2376
2377DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2378
2379static struct clk mmchs3_fck;
2380
2381static struct clk_hw_omap mmchs3_fck_hw = {
2382 .hw = {
2383 .clk = &mmchs3_fck,
2384 },
2385 .ops = &clkhwops_wait,
2386 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2387 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2388 .clkdm_name = "core_l4_clkdm",
2389};
2390
2391DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2392
2393static struct clk mmchs3_ick;
2394
2395static struct clk_hw_omap mmchs3_ick_hw = {
2396 .hw = {
2397 .clk = &mmchs3_ick,
2398 },
2399 .ops = &clkhwops_iclk_wait,
2400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2401 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2402 .clkdm_name = "core_l4_clkdm",
2403};
2404
2405DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2406
2407static struct clk modem_fck;
2408
2409static struct clk_hw_omap modem_fck_hw = {
2410 .hw = {
2411 .clk = &modem_fck,
2412 },
2413 .ops = &clkhwops_iclk_wait,
2414 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2415 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
2416 .clkdm_name = "d2d_clkdm",
2417};
2418
2419DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2420
2421static struct clk mspro_fck;
2422
2423static struct clk_hw_omap mspro_fck_hw = {
2424 .hw = {
2425 .clk = &mspro_fck,
2426 },
2427 .ops = &clkhwops_wait,
2428 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2429 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2430 .clkdm_name = "core_l4_clkdm",
2431};
2432
2433DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2434
2435static struct clk mspro_ick;
2436
2437static struct clk_hw_omap mspro_ick_hw = {
2438 .hw = {
2439 .clk = &mspro_ick,
2440 },
2441 .ops = &clkhwops_iclk_wait,
2442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2443 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2444 .clkdm_name = "core_l4_clkdm",
2445};
2446
2447DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2448
2449static struct clk omap_192m_alwon_fck;
2450
2451DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2452DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2453 core_ck_ops);
2454
2455static struct clk omap_32ksync_ick;
2456
2457static struct clk_hw_omap omap_32ksync_ick_hw = {
2458 .hw = {
2459 .clk = &omap_32ksync_ick,
2460 },
2461 .ops = &clkhwops_iclk_wait,
2462 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2463 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2464 .clkdm_name = "wkup_clkdm",
2465};
2466
2467DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2468
2469static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2470 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2471 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2472 { .div = 0 }
2473};
2474
2475static const struct clksel omap_96m_alwon_fck_clksel[] = {
2476 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2477 { .parent = NULL }
2478};
2479
2480static struct clk omap_96m_alwon_fck_3630;
2481
2482static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2483 "omap_192m_alwon_fck",
2484};
2485
2486static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2487 .set_rate = &omap2_clksel_set_rate,
2488 .recalc_rate = &omap2_clksel_recalc,
2489 .round_rate = &omap2_clksel_round_rate,
2490};
2491
2492static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2493 .hw = {
2494 .clk = &omap_96m_alwon_fck_3630,
2495 },
2496 .clksel = omap_96m_alwon_fck_clksel,
2497 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2498 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
2499};
2500
2501static struct clk omap_96m_alwon_fck_3630 = {
2502 .name = "omap_96m_alwon_fck",
2503 .hw = &omap_96m_alwon_fck_3630_hw.hw,
2504 .parent_names = omap_96m_alwon_fck_3630_parent_names,
2505 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2506 .ops = &omap_96m_alwon_fck_3630_ops,
2507};
2508
2509static struct clk omapctrl_ick;
2510
2511static struct clk_hw_omap omapctrl_ick_hw = {
2512 .hw = {
2513 .clk = &omapctrl_ick,
2514 },
2515 .ops = &clkhwops_iclk_wait,
2516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2517 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2518 .flags = ENABLE_ON_INIT,
2519 .clkdm_name = "core_l4_clkdm",
2520};
2521
2522DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2523
2524DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2525 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2526 OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2527 CLK_DIVIDER_ONE_BASED, NULL);
2528
2529DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2530 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2531 OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2532 CLK_DIVIDER_ONE_BASED, NULL);
2533
2534static struct clk per_48m_fck;
2535
2536DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2537DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2538
2539static struct clk security_l3_ick;
2540
2541DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2542DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2543
2544static struct clk pka_ick;
2545
2546static const char *pka_ick_parent_names[] = {
2547 "security_l3_ick",
2548};
2549
2550static struct clk_hw_omap pka_ick_hw = {
2551 .hw = {
2552 .clk = &pka_ick,
2553 },
2554 .ops = &clkhwops_iclk_wait,
2555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2556 .enable_bit = OMAP3430_EN_PKA_SHIFT,
2557};
2558
2559DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2560
2561DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2562 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2563 OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2564 CLK_DIVIDER_ONE_BASED, NULL);
2565
2566static struct clk rng_ick;
2567
2568static struct clk_hw_omap rng_ick_hw = {
2569 .hw = {
2570 .clk = &rng_ick,
2571 },
2572 .ops = &clkhwops_iclk_wait,
2573 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2574 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2575};
2576
2577DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2578
2579static struct clk sad2d_ick;
2580
2581static struct clk_hw_omap sad2d_ick_hw = {
2582 .hw = {
2583 .clk = &sad2d_ick,
2584 },
2585 .ops = &clkhwops_iclk_wait,
2586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2587 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
2588 .clkdm_name = "d2d_clkdm",
2589};
2590
2591DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2592
2593static struct clk sdrc_ick;
2594
2595static struct clk_hw_omap sdrc_ick_hw = {
2596 .hw = {
2597 .clk = &sdrc_ick,
2598 },
2599 .ops = &clkhwops_wait,
2600 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2601 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
2602 .flags = ENABLE_ON_INIT,
2603 .clkdm_name = "core_l3_clkdm",
2604};
2605
2606DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2607
2608static const struct clksel_rate sgx_core_rates[] = {
2609 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2610 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2611 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2612 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2613 { .div = 0 }
2614};
2615
2616static const struct clksel_rate sgx_96m_rates[] = {
2617 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2618 { .div = 0 }
2619};
2620
2621static const struct clksel_rate sgx_192m_rates[] = {
2622 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2623 { .div = 0 }
2624};
2625
2626static const struct clksel_rate sgx_corex2_rates[] = {
2627 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2628 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2629 { .div = 0 }
2630};
2631
2632static const struct clksel sgx_clksel[] = {
2633 { .parent = &core_ck, .rates = sgx_core_rates },
2634 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2635 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2636 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2637 { .parent = NULL },
2638};
2639
2640static const char *sgx_fck_parent_names[] = {
2641 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2642};
2643
2644static struct clk sgx_fck;
2645
2646static const struct clk_ops sgx_fck_ops = {
2647 .init = &omap2_init_clk_clkdm,
2648 .enable = &omap2_dflt_clk_enable,
2649 .disable = &omap2_dflt_clk_disable,
2650 .is_enabled = &omap2_dflt_clk_is_enabled,
2651 .recalc_rate = &omap2_clksel_recalc,
2652 .set_rate = &omap2_clksel_set_rate,
2653 .round_rate = &omap2_clksel_round_rate,
2654 .get_parent = &omap2_clksel_find_parent_index,
2655 .set_parent = &omap2_clksel_set_parent,
2656};
2657
2658DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2659 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2660 OMAP3430ES2_CLKSEL_SGX_MASK,
2661 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2662 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2663 &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2664
2665static struct clk sgx_ick;
2666
2667static struct clk_hw_omap sgx_ick_hw = {
2668 .hw = {
2669 .clk = &sgx_ick,
2670 },
2671 .ops = &clkhwops_wait,
2672 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2673 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2674 .clkdm_name = "sgx_clkdm",
2675};
2676
2677DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2678
2679static struct clk sha11_ick;
2680
2681static struct clk_hw_omap sha11_ick_hw = {
2682 .hw = {
2683 .clk = &sha11_ick,
2684 },
2685 .ops = &clkhwops_iclk_wait,
2686 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2687 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2688};
2689
2690DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2691
2692static struct clk sha12_ick;
2693
2694static struct clk_hw_omap sha12_ick_hw = {
2695 .hw = {
2696 .clk = &sha12_ick,
2697 },
2698 .ops = &clkhwops_iclk_wait,
2699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2700 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
2701 .clkdm_name = "core_l4_clkdm",
2702};
2703
2704DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2705
2706static struct clk sr1_fck;
2707
2708static struct clk_hw_omap sr1_fck_hw = {
2709 .hw = {
2710 .clk = &sr1_fck,
2711 },
2712 .ops = &clkhwops_wait,
2713 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2714 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2715 .clkdm_name = "wkup_clkdm",
2716};
2717
2718DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2719
2720static struct clk sr2_fck;
2721
2722static struct clk_hw_omap sr2_fck_hw = {
2723 .hw = {
2724 .clk = &sr2_fck,
2725 },
2726 .ops = &clkhwops_wait,
2727 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2728 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2729 .clkdm_name = "wkup_clkdm",
2730};
2731
2732DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2733
2734static struct clk sr_l4_ick;
2735
2736DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2737DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2738
2739static struct clk ssi_l4_ick;
2740
2741DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2742DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2743
2744static struct clk ssi_ick_3430es1;
2745
2746static const char *ssi_ick_3430es1_parent_names[] = {
2747 "ssi_l4_ick",
2748};
2749
2750static struct clk_hw_omap ssi_ick_3430es1_hw = {
2751 .hw = {
2752 .clk = &ssi_ick_3430es1,
2753 },
2754 .ops = &clkhwops_iclk,
2755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2756 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2757 .clkdm_name = "core_l4_clkdm",
2758};
2759
2760DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2761
2762static struct clk ssi_ick_3430es2;
2763
2764static struct clk_hw_omap ssi_ick_3430es2_hw = {
2765 .hw = {
2766 .clk = &ssi_ick_3430es2,
2767 },
2768 .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
2769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2770 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2771 .clkdm_name = "core_l4_clkdm",
2772};
2773
2774DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2775
2776static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2777 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2778 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2779 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2780 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2781 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2782 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2783 { .div = 0 }
2784};
2785
2786static const struct clksel ssi_ssr_clksel[] = {
2787 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2788 { .parent = NULL },
2789};
2790
2791static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2792 "corex2_fck",
2793};
2794
2795static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2796 .init = &omap2_init_clk_clkdm,
2797 .enable = &omap2_dflt_clk_enable,
2798 .disable = &omap2_dflt_clk_disable,
2799 .is_enabled = &omap2_dflt_clk_is_enabled,
2800 .recalc_rate = &omap2_clksel_recalc,
2801 .set_rate = &omap2_clksel_set_rate,
2802 .round_rate = &omap2_clksel_round_rate,
2803};
2804
2805DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2806 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2807 OMAP3430_CLKSEL_SSI_MASK,
2808 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2809 OMAP3430_EN_SSI_SHIFT,
2810 NULL, ssi_ssr_fck_3430es1_parent_names,
2811 ssi_ssr_fck_3430es1_ops);
2812
2813DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2814 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2815 OMAP3430_CLKSEL_SSI_MASK,
2816 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2817 OMAP3430_EN_SSI_SHIFT,
2818 NULL, ssi_ssr_fck_3430es1_parent_names,
2819 ssi_ssr_fck_3430es1_ops);
2820
2821DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2822 &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2823
2824DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2825 &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2826
2827static struct clk sys_clkout1;
2828
2829static const char *sys_clkout1_parent_names[] = {
2830 "osc_sys_ck",
2831};
2832
2833static struct clk_hw_omap sys_clkout1_hw = {
2834 .hw = {
2835 .clk = &sys_clkout1,
2836 },
2837 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
2838 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
2839};
2840
2841DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2842
2843DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2844 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2845 OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2846
2847DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2848 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2849 OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2850 0x0, NULL);
2851
2852DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2853 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2854 OMAP3430_CLKSEL_TRACECLK_SHIFT,
2855 OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2856
2857static struct clk ts_fck;
2858
2859static struct clk_hw_omap ts_fck_hw = {
2860 .hw = {
2861 .clk = &ts_fck,
2862 },
2863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2864 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
2865 .clkdm_name = "core_l4_clkdm",
2866};
2867
2868DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2869
2870static struct clk uart1_fck;
2871
2872static struct clk_hw_omap uart1_fck_hw = {
2873 .hw = {
2874 .clk = &uart1_fck,
2875 },
2876 .ops = &clkhwops_wait,
2877 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2878 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2879 .clkdm_name = "core_l4_clkdm",
2880};
2881
2882DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2883
2884static struct clk uart1_ick;
2885
2886static struct clk_hw_omap uart1_ick_hw = {
2887 .hw = {
2888 .clk = &uart1_ick,
2889 },
2890 .ops = &clkhwops_iclk_wait,
2891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2892 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2893 .clkdm_name = "core_l4_clkdm",
2894};
2895
2896DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2897
2898static struct clk uart2_fck;
2899
2900static struct clk_hw_omap uart2_fck_hw = {
2901 .hw = {
2902 .clk = &uart2_fck,
2903 },
2904 .ops = &clkhwops_wait,
2905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2906 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2907 .clkdm_name = "core_l4_clkdm",
2908};
2909
2910DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2911
2912static struct clk uart2_ick;
2913
2914static struct clk_hw_omap uart2_ick_hw = {
2915 .hw = {
2916 .clk = &uart2_ick,
2917 },
2918 .ops = &clkhwops_iclk_wait,
2919 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2920 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2921 .clkdm_name = "core_l4_clkdm",
2922};
2923
2924DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2925
2926static struct clk uart3_fck;
2927
2928static const char *uart3_fck_parent_names[] = {
2929 "per_48m_fck",
2930};
2931
2932static struct clk_hw_omap uart3_fck_hw = {
2933 .hw = {
2934 .clk = &uart3_fck,
2935 },
2936 .ops = &clkhwops_wait,
2937 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2938 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2939 .clkdm_name = "per_clkdm",
2940};
2941
2942DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2943
2944static struct clk uart3_ick;
2945
2946static struct clk_hw_omap uart3_ick_hw = {
2947 .hw = {
2948 .clk = &uart3_ick,
2949 },
2950 .ops = &clkhwops_iclk_wait,
2951 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2952 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2953 .clkdm_name = "per_clkdm",
2954};
2955
2956DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2957
2958static struct clk uart4_fck;
2959
2960static struct clk_hw_omap uart4_fck_hw = {
2961 .hw = {
2962 .clk = &uart4_fck,
2963 },
2964 .ops = &clkhwops_wait,
2965 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2966 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2967 .clkdm_name = "per_clkdm",
2968};
2969
2970DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2971
2972static struct clk uart4_fck_am35xx;
2973
2974static struct clk_hw_omap uart4_fck_am35xx_hw = {
2975 .hw = {
2976 .clk = &uart4_fck_am35xx,
2977 },
2978 .ops = &clkhwops_wait,
2979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2980 .enable_bit = AM35XX_EN_UART4_SHIFT,
2981 .clkdm_name = "core_l4_clkdm",
2982};
2983
2984DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2985
2986static struct clk uart4_ick;
2987
2988static struct clk_hw_omap uart4_ick_hw = {
2989 .hw = {
2990 .clk = &uart4_ick,
2991 },
2992 .ops = &clkhwops_iclk_wait,
2993 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2994 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2995 .clkdm_name = "per_clkdm",
2996};
2997
2998DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2999
3000static struct clk uart4_ick_am35xx;
3001
3002static struct clk_hw_omap uart4_ick_am35xx_hw = {
3003 .hw = {
3004 .clk = &uart4_ick_am35xx,
3005 },
3006 .ops = &clkhwops_iclk_wait,
3007 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3008 .enable_bit = AM35XX_EN_UART4_SHIFT,
3009 .clkdm_name = "core_l4_clkdm",
3010};
3011
3012DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
3013
3014static const struct clksel_rate div2_rates[] = {
3015 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3016 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3017 { .div = 0 }
3018};
3019
3020static const struct clksel usb_l4_clksel[] = {
3021 { .parent = &l4_ick, .rates = div2_rates },
3022 { .parent = NULL },
3023};
3024
3025static const char *usb_l4_ick_parent_names[] = {
3026 "l4_ick",
3027};
3028
3029DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
3030 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
3031 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
3032 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3033 OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
3034 &clkhwops_iclk_wait, usb_l4_ick_parent_names,
3035 ssi_ssr_fck_3430es1_ops);
3036
3037static struct clk usbhost_120m_fck;
3038
3039static const char *usbhost_120m_fck_parent_names[] = {
3040 "dpll5_m2_ck",
3041};
3042
3043static struct clk_hw_omap usbhost_120m_fck_hw = {
3044 .hw = {
3045 .clk = &usbhost_120m_fck,
3046 },
3047 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3048 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
3049 .clkdm_name = "usbhost_clkdm",
3050};
3051
3052DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
3053 aes2_ick_ops);
3054
3055static struct clk usbhost_48m_fck;
3056
3057static struct clk_hw_omap usbhost_48m_fck_hw = {
3058 .hw = {
3059 .clk = &usbhost_48m_fck,
3060 },
3061 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
3062 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
3063 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3064 .clkdm_name = "usbhost_clkdm",
3065};
3066
3067DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3068
3069static struct clk usbhost_ick;
3070
3071static struct clk_hw_omap usbhost_ick_hw = {
3072 .hw = {
3073 .clk = &usbhost_ick,
3074 },
3075 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3076 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3077 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
3078 .clkdm_name = "usbhost_clkdm",
3079};
3080
3081DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3082
3083static struct clk usbtll_fck;
3084
3085static struct clk_hw_omap usbtll_fck_hw = {
3086 .hw = {
3087 .clk = &usbtll_fck,
3088 },
3089 .ops = &clkhwops_wait,
3090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3091 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3092 .clkdm_name = "core_l4_clkdm",
3093};
3094
3095DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3096
3097static struct clk usbtll_ick;
3098
3099static struct clk_hw_omap usbtll_ick_hw = {
3100 .hw = {
3101 .clk = &usbtll_ick,
3102 },
3103 .ops = &clkhwops_iclk_wait,
3104 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3105 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3106 .clkdm_name = "core_l4_clkdm",
3107};
3108
3109DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3110
3111static const struct clksel_rate usim_96m_rates[] = {
3112 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3113 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3114 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3115 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3116 { .div = 0 }
3117};
3118
3119static const struct clksel_rate usim_120m_rates[] = {
3120 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3121 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3122 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3123 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3124 { .div = 0 }
3125};
3126
3127static const struct clksel usim_clksel[] = {
3128 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3129 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3130 { .parent = &sys_ck, .rates = div2_rates },
3131 { .parent = NULL },
3132};
3133
3134static const char *usim_fck_parent_names[] = {
3135 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3136};
3137
3138static struct clk usim_fck;
3139
3140static const struct clk_ops usim_fck_ops = {
3141 .enable = &omap2_dflt_clk_enable,
3142 .disable = &omap2_dflt_clk_disable,
3143 .is_enabled = &omap2_dflt_clk_is_enabled,
3144 .recalc_rate = &omap2_clksel_recalc,
3145 .get_parent = &omap2_clksel_find_parent_index,
3146 .set_parent = &omap2_clksel_set_parent,
3147};
3148
3149DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3150 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3151 OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3152 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3153 OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3154 usim_fck_parent_names, usim_fck_ops);
3155
3156static struct clk usim_ick;
3157
3158static struct clk_hw_omap usim_ick_hw = {
3159 .hw = {
3160 .clk = &usim_ick,
3161 },
3162 .ops = &clkhwops_iclk_wait,
3163 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3164 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
3165 .clkdm_name = "wkup_clkdm",
3166};
3167
3168DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3169
3170static struct clk vpfe_fck;
3171
3172static const char *vpfe_fck_parent_names[] = {
3173 "pclk_ck",
3174};
3175
3176static struct clk_hw_omap vpfe_fck_hw = {
3177 .hw = {
3178 .clk = &vpfe_fck,
3179 },
3180 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3181 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3182};
3183
3184DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3185
3186static struct clk vpfe_ick;
3187
3188static struct clk_hw_omap vpfe_ick_hw = {
3189 .hw = {
3190 .clk = &vpfe_ick,
3191 },
3192 .ops = &clkhwops_am35xx_ipss_module_wait,
3193 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3194 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3195 .clkdm_name = "core_l3_clkdm",
3196};
3197
3198DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3199
3200static struct clk wdt1_fck;
3201
3202DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3203DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3204
3205static struct clk wdt1_ick;
3206
3207static struct clk_hw_omap wdt1_ick_hw = {
3208 .hw = {
3209 .clk = &wdt1_ick,
3210 },
3211 .ops = &clkhwops_iclk_wait,
3212 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3213 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
3214 .clkdm_name = "wkup_clkdm",
3215};
3216
3217DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3218
3219static struct clk wdt2_fck;
3220
3221static struct clk_hw_omap wdt2_fck_hw = {
3222 .hw = {
3223 .clk = &wdt2_fck,
3224 },
3225 .ops = &clkhwops_wait,
3226 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3227 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3228 .clkdm_name = "wkup_clkdm",
3229};
3230
3231DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3232
3233static struct clk wdt2_ick;
3234
3235static struct clk_hw_omap wdt2_ick_hw = {
3236 .hw = {
3237 .clk = &wdt2_ick,
3238 },
3239 .ops = &clkhwops_iclk_wait,
3240 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3241 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3242 .clkdm_name = "wkup_clkdm",
3243};
3244
3245DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3246
3247static struct clk wdt3_fck;
3248
3249static struct clk_hw_omap wdt3_fck_hw = {
3250 .hw = {
3251 .clk = &wdt3_fck,
3252 },
3253 .ops = &clkhwops_wait,
3254 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3255 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3256 .clkdm_name = "per_clkdm",
3257};
3258
3259DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3260
3261static struct clk wdt3_ick;
3262
3263static struct clk_hw_omap wdt3_ick_hw = {
3264 .hw = {
3265 .clk = &wdt3_ick,
3266 },
3267 .ops = &clkhwops_iclk_wait,
3268 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3269 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3270 .clkdm_name = "per_clkdm",
3271};
3272
3273DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3274
3275/*
3276 * clocks specific to omap3430es1
3277 */
3278static struct omap_clk omap3430es1_clks[] = {
3279 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
3280 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
3281 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
3282 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
3283 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
3284 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
3285 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
3286 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
3287 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
3288 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
3289 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
3290 CLK(NULL, "fac_ick", &fac_ick),
3291 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
3292 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
3293 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
3294 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
3295 CLK(NULL, "dss_ick", &dss_ick_3430es1),
3296};
3297
3298/*
3299 * clocks specific to am35xx
3300 */
3301static struct omap_clk am35xx_clks[] = {
3302 CLK(NULL, "ipss_ick", &ipss_ick),
3303 CLK(NULL, "rmii_ck", &rmii_ck),
3304 CLK(NULL, "pclk_ck", &pclk_ck),
3305 CLK(NULL, "emac_ick", &emac_ick),
3306 CLK(NULL, "emac_fck", &emac_fck),
3307 CLK("davinci_emac.0", NULL, &emac_ick),
3308 CLK("davinci_mdio.0", NULL, &emac_fck),
3309 CLK("vpfe-capture", "master", &vpfe_ick),
3310 CLK("vpfe-capture", "slave", &vpfe_fck),
3311 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
3312 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
3313 CLK(NULL, "hecc_ck", &hecc_ck),
3314 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
3315 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
3316};
3317
3318/*
3319 * clocks specific to omap36xx
3320 */
3321static struct omap_clk omap36xx_clks[] = {
3322 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
3323 CLK(NULL, "uart4_fck", &uart4_fck),
3324};
3325
3326/*
3327 * clocks common to omap36xx omap34xx
3328 */
3329static struct omap_clk omap34xx_omap36xx_clks[] = {
3330 CLK(NULL, "aes1_ick", &aes1_ick),
3331 CLK("omap_rng", "ick", &rng_ick),
3332 CLK("omap3-rom-rng", "ick", &rng_ick),
3333 CLK(NULL, "sha11_ick", &sha11_ick),
3334 CLK(NULL, "des1_ick", &des1_ick),
3335 CLK(NULL, "cam_mclk", &cam_mclk),
3336 CLK(NULL, "cam_ick", &cam_ick),
3337 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
3338 CLK(NULL, "security_l3_ick", &security_l3_ick),
3339 CLK(NULL, "pka_ick", &pka_ick),
3340 CLK(NULL, "icr_ick", &icr_ick),
3341 CLK("omap-aes", "ick", &aes2_ick),
3342 CLK("omap-sham", "ick", &sha12_ick),
3343 CLK(NULL, "des2_ick", &des2_ick),
3344 CLK(NULL, "mspro_ick", &mspro_ick),
3345 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
3346 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
3347 CLK(NULL, "sr1_fck", &sr1_fck),
3348 CLK(NULL, "sr2_fck", &sr2_fck),
3349 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
3350 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
3351 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
3352 CLK(NULL, "dpll2_fck", &dpll2_fck),
3353 CLK(NULL, "iva2_ck", &iva2_ck),
3354 CLK(NULL, "modem_fck", &modem_fck),
3355 CLK(NULL, "sad2d_ick", &sad2d_ick),
3356 CLK(NULL, "mad2d_ick", &mad2d_ick),
3357 CLK(NULL, "mspro_fck", &mspro_fck),
3358 CLK(NULL, "dpll2_ck", &dpll2_ck),
3359 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
3360};
3361
3362/*
3363 * clocks common to omap36xx and omap3430es2plus
3364 */
3365static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
3366 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
3367 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
3368 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
3369 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
3370 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
3371 CLK(NULL, "usim_fck", &usim_fck),
3372 CLK(NULL, "usim_ick", &usim_ick),
3373};
3374
3375/*
3376 * clocks common to am35xx omap36xx and omap3430es2plus
3377 */
3378static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3379 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
3380 CLK(NULL, "dpll5_ck", &dpll5_ck),
3381 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
3382 CLK(NULL, "sgx_fck", &sgx_fck),
3383 CLK(NULL, "sgx_ick", &sgx_ick),
3384 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3385 CLK(NULL, "ts_fck", &ts_fck),
3386 CLK(NULL, "usbtll_fck", &usbtll_fck),
3387 CLK(NULL, "usbtll_ick", &usbtll_ick),
3388 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3389 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3390 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
3391 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
3392 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
3393 CLK(NULL, "dss_ick", &dss_ick_3430es2),
3394 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3395 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3396 CLK(NULL, "usbhost_ick", &usbhost_ick),
3397};
3398
3399/*
3400 * common clocks
3401 */
3402static struct omap_clk omap3xxx_clks[] = {
3403 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
3404 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
3405 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
3406 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
3407 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
3408 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
3409 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
3410 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
3411 CLK("twl", "fck", &osc_sys_ck),
3412 CLK(NULL, "sys_ck", &sys_ck),
3413 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
3414 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
3415 CLK(NULL, "sys_altclk", &sys_altclk),
3416 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
3417 CLK(NULL, "sys_clkout1", &sys_clkout1),
3418 CLK(NULL, "dpll1_ck", &dpll1_ck),
3419 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
3420 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
3421 CLK(NULL, "dpll3_ck", &dpll3_ck),
3422 CLK(NULL, "core_ck", &core_ck),
3423 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
3424 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
3425 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
3426 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
3427 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
3428 CLK(NULL, "dpll4_ck", &dpll4_ck),
3429 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
3430 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
3431 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
3432 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
3433 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
3434 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
3435 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
3436 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
3437 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
3438 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
3439 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
3440 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
3441 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
3442 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
3443 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
3444 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
3445 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
3446 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
3447 CLK(NULL, "sys_clkout2", &sys_clkout2),
3448 CLK(NULL, "corex2_fck", &corex2_fck),
3449 CLK(NULL, "dpll1_fck", &dpll1_fck),
3450 CLK(NULL, "mpu_ck", &mpu_ck),
3451 CLK(NULL, "arm_fck", &arm_fck),
3452 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
3453 CLK(NULL, "l3_ick", &l3_ick),
3454 CLK(NULL, "l4_ick", &l4_ick),
3455 CLK(NULL, "rm_ick", &rm_ick),
3456 CLK(NULL, "gpt10_fck", &gpt10_fck),
3457 CLK(NULL, "gpt11_fck", &gpt11_fck),
3458 CLK(NULL, "core_96m_fck", &core_96m_fck),
3459 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
3460 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
3461 CLK(NULL, "i2c3_fck", &i2c3_fck),
3462 CLK(NULL, "i2c2_fck", &i2c2_fck),
3463 CLK(NULL, "i2c1_fck", &i2c1_fck),
3464 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
3465 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
3466 CLK(NULL, "core_48m_fck", &core_48m_fck),
3467 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
3468 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
3469 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
3470 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
3471 CLK(NULL, "uart2_fck", &uart2_fck),
3472 CLK(NULL, "uart1_fck", &uart1_fck),
3473 CLK(NULL, "core_12m_fck", &core_12m_fck),
3474 CLK("omap_hdq.0", "fck", &hdq_fck),
3475 CLK(NULL, "hdq_fck", &hdq_fck),
3476 CLK(NULL, "core_l3_ick", &core_l3_ick),
3477 CLK(NULL, "sdrc_ick", &sdrc_ick),
3478 CLK(NULL, "gpmc_fck", &gpmc_fck),
3479 CLK(NULL, "core_l4_ick", &core_l4_ick),
3480 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
3481 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
3482 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
3483 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
3484 CLK("omap_hdq.0", "ick", &hdq_ick),
3485 CLK(NULL, "hdq_ick", &hdq_ick),
3486 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
3487 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
3488 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
3489 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
3490 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
3491 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
3492 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
3493 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
3494 CLK("omap_i2c.3", "ick", &i2c3_ick),
3495 CLK("omap_i2c.2", "ick", &i2c2_ick),
3496 CLK("omap_i2c.1", "ick", &i2c1_ick),
3497 CLK(NULL, "i2c3_ick", &i2c3_ick),
3498 CLK(NULL, "i2c2_ick", &i2c2_ick),
3499 CLK(NULL, "i2c1_ick", &i2c1_ick),
3500 CLK(NULL, "uart2_ick", &uart2_ick),
3501 CLK(NULL, "uart1_ick", &uart1_ick),
3502 CLK(NULL, "gpt11_ick", &gpt11_ick),
3503 CLK(NULL, "gpt10_ick", &gpt10_ick),
3504 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
3505 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
3506 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
3507 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
3508 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
3509 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
3510 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
3511 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
3512 CLK(NULL, "init_60m_fclk", &dummy_ck),
3513 CLK(NULL, "gpt1_fck", &gpt1_fck),
3514 CLK(NULL, "aes2_ick", &aes2_ick),
3515 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
3516 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
3517 CLK(NULL, "sha12_ick", &sha12_ick),
3518 CLK(NULL, "wdt2_fck", &wdt2_fck),
3519 CLK("omap_wdt", "ick", &wdt2_ick),
3520 CLK(NULL, "wdt2_ick", &wdt2_ick),
3521 CLK(NULL, "wdt1_ick", &wdt1_ick),
3522 CLK(NULL, "gpio1_ick", &gpio1_ick),
3523 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
3524 CLK(NULL, "gpt12_ick", &gpt12_ick),
3525 CLK(NULL, "gpt1_ick", &gpt1_ick),
3526 CLK(NULL, "per_96m_fck", &per_96m_fck),
3527 CLK(NULL, "per_48m_fck", &per_48m_fck),
3528 CLK(NULL, "uart3_fck", &uart3_fck),
3529 CLK(NULL, "gpt2_fck", &gpt2_fck),
3530 CLK(NULL, "gpt3_fck", &gpt3_fck),
3531 CLK(NULL, "gpt4_fck", &gpt4_fck),
3532 CLK(NULL, "gpt5_fck", &gpt5_fck),
3533 CLK(NULL, "gpt6_fck", &gpt6_fck),
3534 CLK(NULL, "gpt7_fck", &gpt7_fck),
3535 CLK(NULL, "gpt8_fck", &gpt8_fck),
3536 CLK(NULL, "gpt9_fck", &gpt9_fck),
3537 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
3538 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
3539 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
3540 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
3541 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
3542 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
3543 CLK(NULL, "wdt3_fck", &wdt3_fck),
3544 CLK(NULL, "per_l4_ick", &per_l4_ick),
3545 CLK(NULL, "gpio6_ick", &gpio6_ick),
3546 CLK(NULL, "gpio5_ick", &gpio5_ick),
3547 CLK(NULL, "gpio4_ick", &gpio4_ick),
3548 CLK(NULL, "gpio3_ick", &gpio3_ick),
3549 CLK(NULL, "gpio2_ick", &gpio2_ick),
3550 CLK(NULL, "wdt3_ick", &wdt3_ick),
3551 CLK(NULL, "uart3_ick", &uart3_ick),
3552 CLK(NULL, "uart4_ick", &uart4_ick),
3553 CLK(NULL, "gpt9_ick", &gpt9_ick),
3554 CLK(NULL, "gpt8_ick", &gpt8_ick),
3555 CLK(NULL, "gpt7_ick", &gpt7_ick),
3556 CLK(NULL, "gpt6_ick", &gpt6_ick),
3557 CLK(NULL, "gpt5_ick", &gpt5_ick),
3558 CLK(NULL, "gpt4_ick", &gpt4_ick),
3559 CLK(NULL, "gpt3_ick", &gpt3_ick),
3560 CLK(NULL, "gpt2_ick", &gpt2_ick),
3561 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
3562 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
3563 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
3564 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
3565 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
3566 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
3567 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
3568 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
3569 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
3570 CLK("etb", "emu_src_ck", &emu_src_ck),
3571 CLK(NULL, "emu_src_ck", &emu_src_ck),
3572 CLK(NULL, "pclk_fck", &pclk_fck),
3573 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
3574 CLK(NULL, "atclk_fck", &atclk_fck),
3575 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
3576 CLK(NULL, "traceclk_fck", &traceclk_fck),
3577 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
3578 CLK(NULL, "gpt12_fck", &gpt12_fck),
3579 CLK(NULL, "wdt1_fck", &wdt1_fck),
3580 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
3581 CLK(NULL, "timer_sys_ck", &sys_ck),
3582 CLK(NULL, "cpufreq_ck", &dpll1_ck),
3583};
3584
3585static const char *enable_init_clks[] = {
3586 "sdrc_ick",
3587 "gpmc_fck",
3588 "omapctrl_ick",
3589};
3590
3591int __init omap3xxx_clk_init(void)
3592{
3593 if (omap3_has_192mhz_clk())
3594 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3595
3596 if (cpu_is_omap3630()) {
3597 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3598 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3599 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3600 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3601 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3602 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3603 }
3604
3605 /*
3606 * XXX This type of dynamic rewriting of the clock tree is
3607 * deprecated and should be revised soon.
3608 */
3609 if (cpu_is_omap3630())
3610 dpll4_dd = dpll4_dd_3630;
3611 else
3612 dpll4_dd = dpll4_dd_34xx;
3613
3614
3615 /*
3616 * 3505 must be tested before 3517, since 3517 returns true
3617 * for both AM3517 chips and AM3517 family chips, which
3618 * includes 3505. Unfortunately there's no obvious family
3619 * test for 3517/3505 :-(
3620 */
3621 if (soc_is_am35xx()) {
3622 cpu_mask = RATE_IN_34XX;
3623 omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
3624 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3625 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3626 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3627 } else if (cpu_is_omap3630()) {
3628 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3629 omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
3630 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3631 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3632 omap_clocks_register(omap34xx_omap36xx_clks,
3633 ARRAY_SIZE(omap34xx_omap36xx_clks));
3634 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3635 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3636 omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
3637 } else if (cpu_is_omap34xx()) {
3638 if (omap_rev() == OMAP3430_REV_ES1_0) {
3639 cpu_mask = RATE_IN_3430ES1;
3640 omap_clocks_register(omap3430es1_clks,
3641 ARRAY_SIZE(omap3430es1_clks));
3642 omap_clocks_register(omap34xx_omap36xx_clks,
3643 ARRAY_SIZE(omap34xx_omap36xx_clks));
3644 omap_clocks_register(omap3xxx_clks,
3645 ARRAY_SIZE(omap3xxx_clks));
3646 } else {
3647 /*
3648 * Assume that anything that we haven't matched yet
3649 * has 3430ES2-type clocks.
3650 */
3651 cpu_mask = RATE_IN_3430ES2PLUS;
3652 omap_clocks_register(omap34xx_omap36xx_clks,
3653 ARRAY_SIZE(omap34xx_omap36xx_clks));
3654 omap_clocks_register(omap36xx_omap3430es2plus_clks,
3655 ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
3656 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
3657 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
3658 omap_clocks_register(omap3xxx_clks,
3659 ARRAY_SIZE(omap3xxx_clks));
3660 }
3661 } else {
3662 WARN(1, "clock: could not identify OMAP3 variant\n");
3663 }
3664
3665 omap2_clk_disable_autoidle_all();
3666
3667 omap2_clk_enable_init_clocks(enable_init_clks,
3668 ARRAY_SIZE(enable_init_clks));
3669
3670 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3671 (clk_get_rate(&osc_sys_ck) / 1000000),
3672 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3673 (clk_get_rate(&core_ck) / 1000000),
3674 (clk_get_rate(&arm_fck) / 1000000));
3675
3676 /*
3677 * Lock DPLL5 -- here only until other device init code can
3678 * handle this
3679 */
3680 if (omap_rev() >= OMAP3430_REV_ES2_0)
3681 omap3_clk_lock_dpll5();
3682
3683 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3684 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3685 arm_fck_p = clk_get(NULL, "arm_fck");
3686
3687 return 0;
3688}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4ae4ccebced2..6124db5c37ae 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,7 +23,6 @@
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26#include <linux/clk-private.h>
27#include <asm/cpu.h> 26#include <asm/cpu.h>
28 27
29#include <trace/events/power.h> 28#include <trace/events/power.h>
@@ -633,21 +632,6 @@ const struct clk_hw_omap_ops clkhwops_wait = {
633}; 632};
634 633
635/** 634/**
636 * omap_clocks_register - register an array of omap_clk
637 * @ocs: pointer to an array of omap_clk to register
638 */
639void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
640{
641 struct omap_clk *c;
642
643 for (c = oclks; c < oclks + cnt; c++) {
644 clkdev_add(&c->lk);
645 if (!__clk_init(NULL, c->lk.clk))
646 omap2_init_clk_hw_omap_clocks(c->lk.clk);
647 }
648}
649
650/**
651 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 635 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
652 * @mpurate_ck_name: clk name of the clock to change rate 636 * @mpurate_ck_name: clk name of the clock to change rate
653 * 637 *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1cf9dd85248a..a56742f96000 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -40,23 +40,29 @@ struct omap_clk {
40struct clockdomain; 40struct clockdomain;
41 41
42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ 42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
43 static struct clk _name = { \ 43 static struct clk_core _name##_core = { \
44 .name = #_name, \ 44 .name = #_name, \
45 .hw = &_name##_hw.hw, \ 45 .hw = &_name##_hw.hw, \
46 .parent_names = _parent_array_name, \ 46 .parent_names = _parent_array_name, \
47 .num_parents = ARRAY_SIZE(_parent_array_name), \ 47 .num_parents = ARRAY_SIZE(_parent_array_name), \
48 .ops = &_clkops_name, \ 48 .ops = &_clkops_name, \
49 }; \
50 static struct clk _name = { \
51 .core = &_name##_core, \
49 }; 52 };
50 53
51#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \ 54#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
52 _clkops_name, _flags) \ 55 _clkops_name, _flags) \
53 static struct clk _name = { \ 56 static struct clk_core _name##_core = { \
54 .name = #_name, \ 57 .name = #_name, \
55 .hw = &_name##_hw.hw, \ 58 .hw = &_name##_hw.hw, \
56 .parent_names = _parent_array_name, \ 59 .parent_names = _parent_array_name, \
57 .num_parents = ARRAY_SIZE(_parent_array_name), \ 60 .num_parents = ARRAY_SIZE(_parent_array_name), \
58 .ops = &_clkops_name, \ 61 .ops = &_clkops_name, \
59 .flags = _flags, \ 62 .flags = _flags, \
63 }; \
64 static struct clk _name = { \
65 .core = &_name##_core, \
60 }; 66 };
61 67
62#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ 68#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
@@ -238,7 +244,6 @@ struct ti_clk_features {
238extern struct ti_clk_features ti_clk_features; 244extern struct ti_clk_features ti_clk_features;
239 245
240extern const struct clkops clkops_omap2_dflt_wait; 246extern const struct clkops clkops_omap2_dflt_wait;
241extern const struct clkops clkops_dummy;
242extern const struct clkops clkops_omap2_dflt; 247extern const struct clkops clkops_omap2_dflt;
243 248
244extern struct clk_functions omap2_clk_functions; 249extern struct clk_functions omap2_clk_functions;
@@ -247,7 +252,6 @@ extern const struct clksel_rate gpt_32k_rates[];
247extern const struct clksel_rate gpt_sys_rates[]; 252extern const struct clksel_rate gpt_sys_rates[];
248extern const struct clksel_rate gfx_l3_rates[]; 253extern const struct clksel_rate gfx_l3_rates[];
249extern const struct clksel_rate dsp_ick_rates[]; 254extern const struct clksel_rate dsp_ick_rates[];
250extern struct clk dummy_ck;
251 255
252extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 256extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
253extern const struct clk_hw_omap_ops clkhwops_wait; 257extern const struct clk_hw_omap_ops clkhwops_wait;
@@ -272,7 +276,5 @@ extern void __iomem *clk_memmaps[];
272extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 276extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
273extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); 277extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
274 278
275extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
276
277void __init ti_clk_init_features(void); 279void __init ti_clk_init_features(void);
278#endif 280#endif
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index ef4d21bfb964..61b60dfb14ce 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -16,7 +16,6 @@
16 * OMAP3xxx clock definition files. 16 * OMAP3xxx clock definition files.
17 */ 17 */
18 18
19#include <linux/clk-private.h>
20#include "clock.h" 19#include "clock.h"
21 20
22/* clksel_rate data common to 24xx/343x */ 21/* clksel_rate data common to 24xx/343x */
@@ -114,13 +113,3 @@ const struct clksel_rate div31_1to31_rates[] = {
114 { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, 113 { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
115 { .div = 0 }, 114 { .div = 0 },
116}; 115};
117
118/* Clocks shared between various OMAP SoCs */
119
120static struct clk_ops dummy_ck_ops = {};
121
122struct clk dummy_ck = {
123 .name = "dummy_clk",
124 .ops = &dummy_ck_ops,
125 .flags = CLK_IS_BASIC,
126};
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index c2da2a0fe5ad..44e57ec225d4 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -410,7 +410,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
410 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 410 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
411 int r; 411 int r;
412 struct dpll_data *dd; 412 struct dpll_data *dd;
413 struct clk *parent; 413 struct clk_hw *parent;
414 414
415 dd = clk->dpll_data; 415 dd = clk->dpll_data;
416 if (!dd) 416 if (!dd)
@@ -427,13 +427,13 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
427 } 427 }
428 } 428 }
429 429
430 parent = __clk_get_parent(hw->clk); 430 parent = __clk_get_hw(__clk_get_parent(hw->clk));
431 431
432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { 432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
433 WARN_ON(parent != dd->clk_bypass); 433 WARN_ON(parent != __clk_get_hw(dd->clk_bypass));
434 r = _omap3_noncore_dpll_bypass(clk); 434 r = _omap3_noncore_dpll_bypass(clk);
435 } else { 435 } else {
436 WARN_ON(parent != dd->clk_ref); 436 WARN_ON(parent != __clk_get_hw(dd->clk_ref));
437 r = _omap3_noncore_dpll_lock(clk); 437 r = _omap3_noncore_dpll_lock(clk);
438 } 438 }
439 439
@@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
473 * in failure. 473 * in failure.
474 */ 474 */
475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, 475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476 unsigned long min_rate,
477 unsigned long max_rate,
476 unsigned long *best_parent_rate, 478 unsigned long *best_parent_rate,
477 struct clk_hw **best_parent_clk) 479 struct clk_hw **best_parent_clk)
478{ 480{
@@ -549,7 +551,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
549 if (!dd) 551 if (!dd)
550 return -EINVAL; 552 return -EINVAL;
551 553
552 if (__clk_get_parent(hw->clk) != dd->clk_ref) 554 if (__clk_get_hw(__clk_get_parent(hw->clk)) !=
555 __clk_get_hw(dd->clk_ref))
553 return -EINVAL; 556 return -EINVAL;
554 557
555 if (dd->last_rounded_rate == 0) 558 if (dd->last_rounded_rate == 0)
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index fc712240e5fd..f231be05b9a6 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -202,6 +202,8 @@ out:
202 * in failure. 202 * in failure.
203 */ 203 */
204long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, 204long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
205 unsigned long min_rate,
206 unsigned long max_rate,
205 unsigned long *best_parent_rate, 207 unsigned long *best_parent_rate,
206 struct clk_hw **best_parent_clk) 208 struct clk_hw **best_parent_clk)
207{ 209{
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index e60780f05374..c4871c55bd8b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -461,7 +461,17 @@ void __init omap3_init_early(void)
461 omap3xxx_clockdomains_init(); 461 omap3xxx_clockdomains_init();
462 omap3xxx_hwmod_init(); 462 omap3xxx_hwmod_init();
463 omap_hwmod_init_postsetup(); 463 omap_hwmod_init_postsetup();
464 omap_clk_soc_init = omap3xxx_clk_init; 464 if (!of_have_populated_dt()) {
465 omap3_prcm_legacy_iomaps_init();
466 if (soc_is_am35xx())
467 omap_clk_soc_init = am35xx_clk_legacy_init;
468 else if (cpu_is_omap3630())
469 omap_clk_soc_init = omap36xx_clk_legacy_init;
470 else if (omap_rev() == OMAP3430_REV_ES1_0)
471 omap_clk_soc_init = omap3430es1_clk_legacy_init;
472 else
473 omap_clk_soc_init = omap3430_clk_legacy_init;
474 }
465} 475}
466 476
467void __init omap3430_init_early(void) 477void __init omap3430_init_early(void)
@@ -753,15 +763,17 @@ int __init omap_clk_init(void)
753 763
754 ti_clk_init_features(); 764 ti_clk_init_features();
755 765
756 ret = of_prcm_init(); 766 if (of_have_populated_dt()) {
757 if (ret) 767 ret = of_prcm_init();
758 return ret; 768 if (ret)
769 return ret;
759 770
760 of_clk_init(NULL); 771 of_clk_init(NULL);
761 772
762 ti_dt_clk_init_retry_clks(); 773 ti_dt_clk_init_retry_clks();
763 774
764 ti_dt_clockdomains_setup(); 775 ti_dt_clockdomains_setup();
776 }
765 777
766 ret = omap_clk_soc_init(); 778 ret = omap_clk_soc_init();
767 779
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 77752e49d8d4..b9061a6a2db8 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -20,6 +20,7 @@ extern void __iomem *prm_base;
20extern u16 prm_features; 20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
22int of_prcm_init(void); 22int of_prcm_init(void);
23void omap3_prcm_legacy_iomaps_init(void);
23# endif 24# endif
24 25
25/* 26/*
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 264b5e29404d..bfaa7ba595cc 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -35,6 +35,8 @@
35#include "prm44xx.h" 35#include "prm44xx.h"
36#include "common.h" 36#include "common.h"
37#include "clock.h" 37#include "clock.h"
38#include "cm.h"
39#include "control.h"
38 40
39/* 41/*
40 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs 42 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -641,6 +643,15 @@ int __init of_prcm_init(void)
641 return 0; 643 return 0;
642} 644}
643 645
646void __init omap3_prcm_legacy_iomaps_init(void)
647{
648 ti_clk_ll_ops = &omap_clk_ll_ops;
649
650 clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
651 clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
652 clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
653}
654
644static int __init prm_late_init(void) 655static int __init prm_late_init(void)
645{ 656{
646 if (prm_ll_data->late_init) 657 if (prm_ll_data->late_init)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index ef016af1c9e7..914341bcef25 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -91,8 +91,6 @@ static void __init tegra_dt_init(void)
91 struct soc_device *soc_dev; 91 struct soc_device *soc_dev;
92 struct device *parent = NULL; 92 struct device *parent = NULL;
93 93
94 tegra_clocks_apply_init_table();
95
96 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 94 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
97 if (!soc_dev_attr) 95 if (!soc_dev_attr)
98 goto out; 96 goto out;
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 48a9dfc55b51..604b7d009d8d 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -546,6 +546,8 @@ static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
546} 546}
547 547
548static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate, 548static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
549 unsigned long min_rate,
550 unsigned long max_rate,
549 unsigned long *best_parent_rate, 551 unsigned long *best_parent_rate,
550 struct clk_hw **best_parent_clk) 552 struct clk_hw **best_parent_clk)
551{ 553{
@@ -678,6 +680,8 @@ static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
678} 680}
679 681
680static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate, 682static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
683 unsigned long min_rate,
684 unsigned long max_rate,
681 unsigned long *best_parent_rate, 685 unsigned long *best_parent_rate,
682 struct clk_hw **best_parent_clk) 686 struct clk_hw **best_parent_clk)
683{ 687{
@@ -897,6 +901,8 @@ static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
897} 901}
898 902
899static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate, 903static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
904 unsigned long min_rate,
905 unsigned long max_rate,
900 unsigned long *best_parent_rate, 906 unsigned long *best_parent_rate,
901 struct clk_hw **best_parent_clk) 907 struct clk_hw **best_parent_clk)
902{ 908{
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 51866f170684..ca7957b09a3c 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -142,6 +142,7 @@ CONFIG_VIRT_DRIVERS=y
142CONFIG_FSL_HV_MANAGER=y 142CONFIG_FSL_HV_MANAGER=y
143CONFIG_STAGING=y 143CONFIG_STAGING=y
144CONFIG_FSL_CORENET_CF=y 144CONFIG_FSL_CORENET_CF=y
145CONFIG_CLK_QORIQ=y
145CONFIG_EXT2_FS=y 146CONFIG_EXT2_FS=y
146CONFIG_EXT3_FS=y 147CONFIG_EXT3_FS=y
147# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 148# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index d6c0c8198952..04737aaa8b6b 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -122,6 +122,7 @@ CONFIG_DMADEVICES=y
122CONFIG_FSL_DMA=y 122CONFIG_FSL_DMA=y
123CONFIG_VIRT_DRIVERS=y 123CONFIG_VIRT_DRIVERS=y
124CONFIG_FSL_HV_MANAGER=y 124CONFIG_FSL_HV_MANAGER=y
125CONFIG_CLK_QORIQ=y
125CONFIG_FSL_CORENET_CF=y 126CONFIG_FSL_CORENET_CF=y
126CONFIG_EXT2_FS=y 127CONFIG_EXT2_FS=y
127CONFIG_EXT3_FS=y 128CONFIG_EXT3_FS=y
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 7316dd15278a..2d7b33fab953 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -54,6 +54,7 @@
54#include <linux/irq.h> 54#include <linux/irq.h>
55#include <linux/delay.h> 55#include <linux/delay.h>
56#include <linux/irq_work.h> 56#include <linux/irq_work.h>
57#include <linux/clk-provider.h>
57#include <asm/trace.h> 58#include <asm/trace.h>
58 59
59#include <asm/io.h> 60#include <asm/io.h>
@@ -975,6 +976,10 @@ void __init time_init(void)
975 976
976 init_decrementer_clockevent(); 977 init_decrementer_clockevent();
977 tick_setup_hrtimer_broadcast(); 978 tick_setup_hrtimer_broadcast();
979
980#ifdef CONFIG_COMMON_CLK
981 of_clk_init(NULL);
982#endif
978} 983}
979 984
980 985
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index 6eb614a271fb..f691bcabd710 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -1168,6 +1168,11 @@ static void mpc5121_clk_provide_backwards_compat(void)
1168 } 1168 }
1169} 1169}
1170 1170
1171/*
1172 * The "fixed-clock" nodes (which includes the oscillator node if the board's
1173 * DT provides one) has already been scanned by the of_clk_init() in
1174 * time_init().
1175 */
1171int __init mpc5121_clk_init(void) 1176int __init mpc5121_clk_init(void)
1172{ 1177{
1173 struct device_node *clk_np; 1178 struct device_node *clk_np;
@@ -1187,12 +1192,6 @@ int __init mpc5121_clk_init(void)
1187 mpc512x_clk_preset_data(); 1192 mpc512x_clk_preset_data();
1188 1193
1189 /* 1194 /*
1190 * have the device tree scanned for "fixed-clock" nodes (which
1191 * includes the oscillator node if the board's DT provides one)
1192 */
1193 of_clk_init(NULL);
1194
1195 /*
1196 * add a dummy clock for those situations where a clock spec is 1195 * add a dummy clock for those situations where a clock spec is
1197 * required yet no real clock is involved 1196 * required yet no real clock is involved
1198 */ 1197 */
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 91f86131bb7a..0b474a04730f 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -102,12 +102,12 @@ config COMMON_CLK_AXI_CLKGEN
102 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx 102 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
103 FPGAs. It is commonly used in Analog Devices' reference designs. 103 FPGAs. It is commonly used in Analog Devices' reference designs.
104 104
105config CLK_PPC_CORENET 105config CLK_QORIQ
106 bool "Clock driver for PowerPC corenet platforms" 106 bool "Clock driver for Freescale QorIQ platforms"
107 depends on PPC_E500MC && OF 107 depends on (PPC_E500MC || ARM) && OF
108 ---help--- 108 ---help---
109 This adds the clock driver support for Freescale PowerPC corenet 109 This adds the clock driver support for Freescale QorIQ platforms
110 platforms using common clock framework. 110 using common clock framework.
111 111
112config COMMON_CLK_XGENE 112config COMMON_CLK_XGENE
113 bool "Clock driver for APM XGene SoC" 113 bool "Clock driver for APM XGene SoC"
@@ -135,6 +135,14 @@ config COMMON_CLK_PXA
135 ---help--- 135 ---help---
136 Sypport for the Marvell PXA SoC. 136 Sypport for the Marvell PXA SoC.
137 137
138config COMMON_CLK_CDCE706
139 tristate "Clock driver for TI CDCE706 clock synthesizer"
140 depends on I2C
141 select REGMAP_I2C
142 select RATIONAL
143 ---help---
144 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
145
138source "drivers/clk/qcom/Kconfig" 146source "drivers/clk/qcom/Kconfig"
139 147
140endmenu 148endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5bc6e1b..d478ceb69c5f 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -16,9 +16,11 @@ endif
16 16
17# hardware specific clock types 17# hardware specific clock types
18# please keep this section sorted lexicographically by file/directory path name 18# please keep this section sorted lexicographically by file/directory path name
19obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
19obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o 20obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
20obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o 21obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
21obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o 22obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
23obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
22obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o 24obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
23obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 25obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
24obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 26obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
@@ -30,7 +32,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
30obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o 32obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
31obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o 33obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
32obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o 34obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
33obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o 35obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
34obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o 36obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
35obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o 37obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
36obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o 38obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index bbdb1b985c91..86c8a073dcc3 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -56,6 +56,8 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
56 56
57static long clk_programmable_determine_rate(struct clk_hw *hw, 57static long clk_programmable_determine_rate(struct clk_hw *hw,
58 unsigned long rate, 58 unsigned long rate,
59 unsigned long min_rate,
60 unsigned long max_rate,
59 unsigned long *best_parent_rate, 61 unsigned long *best_parent_rate,
60 struct clk_hw **best_parent_hw) 62 struct clk_hw **best_parent_hw)
61{ 63{
diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c
index 1c06f6f3a8c5..05abae89262e 100644
--- a/drivers/clk/bcm/clk-kona.c
+++ b/drivers/clk/bcm/clk-kona.c
@@ -1032,6 +1032,8 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1032} 1032}
1033 1033
1034static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, 1034static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
1035 unsigned long min_rate,
1036 unsigned long max_rate,
1035 unsigned long *best_parent_rate, struct clk_hw **best_parent) 1037 unsigned long *best_parent_rate, struct clk_hw **best_parent)
1036{ 1038{
1037 struct kona_clk *bcm_clk = to_kona_clk(hw); 1039 struct kona_clk *bcm_clk = to_kona_clk(hw);
diff --git a/drivers/clk/clk-asm9260.c b/drivers/clk/clk-asm9260.c
new file mode 100644
index 000000000000..88f4ff6916fe
--- /dev/null
+++ b/drivers/clk/clk-asm9260.c
@@ -0,0 +1,348 @@
1/*
2 * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18#include <linux/clkdev.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/clk-provider.h>
22#include <linux/spinlock.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <dt-bindings/clock/alphascale,asm9260.h>
26
27#define HW_AHBCLKCTRL0 0x0020
28#define HW_AHBCLKCTRL1 0x0030
29#define HW_SYSPLLCTRL 0x0100
30#define HW_MAINCLKSEL 0x0120
31#define HW_MAINCLKUEN 0x0124
32#define HW_UARTCLKSEL 0x0128
33#define HW_UARTCLKUEN 0x012c
34#define HW_I2S0CLKSEL 0x0130
35#define HW_I2S0CLKUEN 0x0134
36#define HW_I2S1CLKSEL 0x0138
37#define HW_I2S1CLKUEN 0x013c
38#define HW_WDTCLKSEL 0x0160
39#define HW_WDTCLKUEN 0x0164
40#define HW_CLKOUTCLKSEL 0x0170
41#define HW_CLKOUTCLKUEN 0x0174
42#define HW_CPUCLKDIV 0x017c
43#define HW_SYSAHBCLKDIV 0x0180
44#define HW_I2S0MCLKDIV 0x0190
45#define HW_I2S0SCLKDIV 0x0194
46#define HW_I2S1MCLKDIV 0x0188
47#define HW_I2S1SCLKDIV 0x018c
48#define HW_UART0CLKDIV 0x0198
49#define HW_UART1CLKDIV 0x019c
50#define HW_UART2CLKDIV 0x01a0
51#define HW_UART3CLKDIV 0x01a4
52#define HW_UART4CLKDIV 0x01a8
53#define HW_UART5CLKDIV 0x01ac
54#define HW_UART6CLKDIV 0x01b0
55#define HW_UART7CLKDIV 0x01b4
56#define HW_UART8CLKDIV 0x01b8
57#define HW_UART9CLKDIV 0x01bc
58#define HW_SPI0CLKDIV 0x01c0
59#define HW_SPI1CLKDIV 0x01c4
60#define HW_QUADSPICLKDIV 0x01c8
61#define HW_SSP0CLKDIV 0x01d0
62#define HW_NANDCLKDIV 0x01d4
63#define HW_TRACECLKDIV 0x01e0
64#define HW_CAMMCLKDIV 0x01e8
65#define HW_WDTCLKDIV 0x01ec
66#define HW_CLKOUTCLKDIV 0x01f4
67#define HW_MACCLKDIV 0x01f8
68#define HW_LCDCLKDIV 0x01fc
69#define HW_ADCANACLKDIV 0x0200
70
71static struct clk *clks[MAX_CLKS];
72static struct clk_onecell_data clk_data;
73static DEFINE_SPINLOCK(asm9260_clk_lock);
74
75struct asm9260_div_clk {
76 unsigned int idx;
77 const char *name;
78 const char *parent_name;
79 u32 reg;
80};
81
82struct asm9260_gate_data {
83 unsigned int idx;
84 const char *name;
85 const char *parent_name;
86 u32 reg;
87 u8 bit_idx;
88 unsigned long flags;
89};
90
91struct asm9260_mux_clock {
92 u8 mask;
93 u32 *table;
94 const char *name;
95 const char **parent_names;
96 u8 num_parents;
97 unsigned long offset;
98 unsigned long flags;
99};
100
101static void __iomem *base;
102
103static const struct asm9260_div_clk asm9260_div_clks[] __initconst = {
104 { CLKID_SYS_CPU, "cpu_div", "main_gate", HW_CPUCLKDIV },
105 { CLKID_SYS_AHB, "ahb_div", "cpu_div", HW_SYSAHBCLKDIV },
106
107 /* i2s has two deviders: one for only external mclk and internal
108 * devider for all clks. */
109 { CLKID_SYS_I2S0M, "i2s0m_div", "i2s0_mclk", HW_I2S0MCLKDIV },
110 { CLKID_SYS_I2S1M, "i2s1m_div", "i2s1_mclk", HW_I2S1MCLKDIV },
111 { CLKID_SYS_I2S0S, "i2s0s_div", "i2s0_gate", HW_I2S0SCLKDIV },
112 { CLKID_SYS_I2S1S, "i2s1s_div", "i2s0_gate", HW_I2S1SCLKDIV },
113
114 { CLKID_SYS_UART0, "uart0_div", "uart_gate", HW_UART0CLKDIV },
115 { CLKID_SYS_UART1, "uart1_div", "uart_gate", HW_UART1CLKDIV },
116 { CLKID_SYS_UART2, "uart2_div", "uart_gate", HW_UART2CLKDIV },
117 { CLKID_SYS_UART3, "uart3_div", "uart_gate", HW_UART3CLKDIV },
118 { CLKID_SYS_UART4, "uart4_div", "uart_gate", HW_UART4CLKDIV },
119 { CLKID_SYS_UART5, "uart5_div", "uart_gate", HW_UART5CLKDIV },
120 { CLKID_SYS_UART6, "uart6_div", "uart_gate", HW_UART6CLKDIV },
121 { CLKID_SYS_UART7, "uart7_div", "uart_gate", HW_UART7CLKDIV },
122 { CLKID_SYS_UART8, "uart8_div", "uart_gate", HW_UART8CLKDIV },
123 { CLKID_SYS_UART9, "uart9_div", "uart_gate", HW_UART9CLKDIV },
124
125 { CLKID_SYS_SPI0, "spi0_div", "main_gate", HW_SPI0CLKDIV },
126 { CLKID_SYS_SPI1, "spi1_div", "main_gate", HW_SPI1CLKDIV },
127 { CLKID_SYS_QUADSPI, "quadspi_div", "main_gate", HW_QUADSPICLKDIV },
128 { CLKID_SYS_SSP0, "ssp0_div", "main_gate", HW_SSP0CLKDIV },
129 { CLKID_SYS_NAND, "nand_div", "main_gate", HW_NANDCLKDIV },
130 { CLKID_SYS_TRACE, "trace_div", "main_gate", HW_TRACECLKDIV },
131 { CLKID_SYS_CAMM, "camm_div", "main_gate", HW_CAMMCLKDIV },
132 { CLKID_SYS_MAC, "mac_div", "main_gate", HW_MACCLKDIV },
133 { CLKID_SYS_LCD, "lcd_div", "main_gate", HW_LCDCLKDIV },
134 { CLKID_SYS_ADCANA, "adcana_div", "main_gate", HW_ADCANACLKDIV },
135
136 { CLKID_SYS_WDT, "wdt_div", "wdt_gate", HW_WDTCLKDIV },
137 { CLKID_SYS_CLKOUT, "clkout_div", "clkout_gate", HW_CLKOUTCLKDIV },
138};
139
140static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = {
141 { 0, "main_gate", "main_mux", HW_MAINCLKUEN, 0 },
142 { 0, "uart_gate", "uart_mux", HW_UARTCLKUEN, 0 },
143 { 0, "i2s0_gate", "i2s0_mux", HW_I2S0CLKUEN, 0 },
144 { 0, "i2s1_gate", "i2s1_mux", HW_I2S1CLKUEN, 0 },
145 { 0, "wdt_gate", "wdt_mux", HW_WDTCLKUEN, 0 },
146 { 0, "clkout_gate", "clkout_mux", HW_CLKOUTCLKUEN, 0 },
147};
148static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
149 /* ahb gates */
150 { CLKID_AHB_ROM, "rom", "ahb_div",
151 HW_AHBCLKCTRL0, 1, CLK_IGNORE_UNUSED},
152 { CLKID_AHB_RAM, "ram", "ahb_div",
153 HW_AHBCLKCTRL0, 2, CLK_IGNORE_UNUSED},
154 { CLKID_AHB_GPIO, "gpio", "ahb_div",
155 HW_AHBCLKCTRL0, 4 },
156 { CLKID_AHB_MAC, "mac", "ahb_div",
157 HW_AHBCLKCTRL0, 5 },
158 { CLKID_AHB_EMI, "emi", "ahb_div",
159 HW_AHBCLKCTRL0, 6, CLK_IGNORE_UNUSED},
160 { CLKID_AHB_USB0, "usb0", "ahb_div",
161 HW_AHBCLKCTRL0, 7 },
162 { CLKID_AHB_USB1, "usb1", "ahb_div",
163 HW_AHBCLKCTRL0, 8 },
164 { CLKID_AHB_DMA0, "dma0", "ahb_div",
165 HW_AHBCLKCTRL0, 9 },
166 { CLKID_AHB_DMA1, "dma1", "ahb_div",
167 HW_AHBCLKCTRL0, 10 },
168 { CLKID_AHB_UART0, "uart0", "ahb_div",
169 HW_AHBCLKCTRL0, 11 },
170 { CLKID_AHB_UART1, "uart1", "ahb_div",
171 HW_AHBCLKCTRL0, 12 },
172 { CLKID_AHB_UART2, "uart2", "ahb_div",
173 HW_AHBCLKCTRL0, 13 },
174 { CLKID_AHB_UART3, "uart3", "ahb_div",
175 HW_AHBCLKCTRL0, 14 },
176 { CLKID_AHB_UART4, "uart4", "ahb_div",
177 HW_AHBCLKCTRL0, 15 },
178 { CLKID_AHB_UART5, "uart5", "ahb_div",
179 HW_AHBCLKCTRL0, 16 },
180 { CLKID_AHB_UART6, "uart6", "ahb_div",
181 HW_AHBCLKCTRL0, 17 },
182 { CLKID_AHB_UART7, "uart7", "ahb_div",
183 HW_AHBCLKCTRL0, 18 },
184 { CLKID_AHB_UART8, "uart8", "ahb_div",
185 HW_AHBCLKCTRL0, 19 },
186 { CLKID_AHB_UART9, "uart9", "ahb_div",
187 HW_AHBCLKCTRL0, 20 },
188 { CLKID_AHB_I2S0, "i2s0", "ahb_div",
189 HW_AHBCLKCTRL0, 21 },
190 { CLKID_AHB_I2C0, "i2c0", "ahb_div",
191 HW_AHBCLKCTRL0, 22 },
192 { CLKID_AHB_I2C1, "i2c1", "ahb_div",
193 HW_AHBCLKCTRL0, 23 },
194 { CLKID_AHB_SSP0, "ssp0", "ahb_div",
195 HW_AHBCLKCTRL0, 24 },
196 { CLKID_AHB_IOCONFIG, "ioconf", "ahb_div",
197 HW_AHBCLKCTRL0, 25 },
198 { CLKID_AHB_WDT, "wdt", "ahb_div",
199 HW_AHBCLKCTRL0, 26 },
200 { CLKID_AHB_CAN0, "can0", "ahb_div",
201 HW_AHBCLKCTRL0, 27 },
202 { CLKID_AHB_CAN1, "can1", "ahb_div",
203 HW_AHBCLKCTRL0, 28 },
204 { CLKID_AHB_MPWM, "mpwm", "ahb_div",
205 HW_AHBCLKCTRL0, 29 },
206 { CLKID_AHB_SPI0, "spi0", "ahb_div",
207 HW_AHBCLKCTRL0, 30 },
208 { CLKID_AHB_SPI1, "spi1", "ahb_div",
209 HW_AHBCLKCTRL0, 31 },
210
211 { CLKID_AHB_QEI, "qei", "ahb_div",
212 HW_AHBCLKCTRL1, 0 },
213 { CLKID_AHB_QUADSPI0, "quadspi0", "ahb_div",
214 HW_AHBCLKCTRL1, 1 },
215 { CLKID_AHB_CAMIF, "capmif", "ahb_div",
216 HW_AHBCLKCTRL1, 2 },
217 { CLKID_AHB_LCDIF, "lcdif", "ahb_div",
218 HW_AHBCLKCTRL1, 3 },
219 { CLKID_AHB_TIMER0, "timer0", "ahb_div",
220 HW_AHBCLKCTRL1, 4 },
221 { CLKID_AHB_TIMER1, "timer1", "ahb_div",
222 HW_AHBCLKCTRL1, 5 },
223 { CLKID_AHB_TIMER2, "timer2", "ahb_div",
224 HW_AHBCLKCTRL1, 6 },
225 { CLKID_AHB_TIMER3, "timer3", "ahb_div",
226 HW_AHBCLKCTRL1, 7 },
227 { CLKID_AHB_IRQ, "irq", "ahb_div",
228 HW_AHBCLKCTRL1, 8, CLK_IGNORE_UNUSED},
229 { CLKID_AHB_RTC, "rtc", "ahb_div",
230 HW_AHBCLKCTRL1, 9 },
231 { CLKID_AHB_NAND, "nand", "ahb_div",
232 HW_AHBCLKCTRL1, 10 },
233 { CLKID_AHB_ADC0, "adc0", "ahb_div",
234 HW_AHBCLKCTRL1, 11 },
235 { CLKID_AHB_LED, "led", "ahb_div",
236 HW_AHBCLKCTRL1, 12 },
237 { CLKID_AHB_DAC0, "dac0", "ahb_div",
238 HW_AHBCLKCTRL1, 13 },
239 { CLKID_AHB_LCD, "lcd", "ahb_div",
240 HW_AHBCLKCTRL1, 14 },
241 { CLKID_AHB_I2S1, "i2s1", "ahb_div",
242 HW_AHBCLKCTRL1, 15 },
243 { CLKID_AHB_MAC1, "mac1", "ahb_div",
244 HW_AHBCLKCTRL1, 16 },
245};
246
247static const char __initdata *main_mux_p[] = { NULL, NULL };
248static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"};
249static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"};
250static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"};
251static u32 three_mux_table[] = {0, 1, 3};
252
253static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
254 { 1, three_mux_table, "main_mux", main_mux_p,
255 ARRAY_SIZE(main_mux_p), HW_MAINCLKSEL, },
256 { 1, three_mux_table, "uart_mux", main_mux_p,
257 ARRAY_SIZE(main_mux_p), HW_UARTCLKSEL, },
258 { 1, three_mux_table, "wdt_mux", main_mux_p,
259 ARRAY_SIZE(main_mux_p), HW_WDTCLKSEL, },
260 { 3, three_mux_table, "i2s0_mux", i2s0_mux_p,
261 ARRAY_SIZE(i2s0_mux_p), HW_I2S0CLKSEL, },
262 { 3, three_mux_table, "i2s1_mux", i2s1_mux_p,
263 ARRAY_SIZE(i2s1_mux_p), HW_I2S1CLKSEL, },
264 { 3, three_mux_table, "clkout_mux", clkout_mux_p,
265 ARRAY_SIZE(clkout_mux_p), HW_CLKOUTCLKSEL, },
266};
267
268static void __init asm9260_acc_init(struct device_node *np)
269{
270 struct clk *clk;
271 const char *ref_clk, *pll_clk = "pll";
272 u32 rate;
273 int n;
274 u32 accuracy = 0;
275
276 base = of_io_request_and_map(np, 0, np->name);
277 if (!base)
278 panic("%s: unable to map resource", np->name);
279
280 /* register pll */
281 rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
282
283 ref_clk = of_clk_get_parent_name(np, 0);
284 accuracy = clk_get_accuracy(__clk_lookup(ref_clk));
285 clk = clk_register_fixed_rate_with_accuracy(NULL, pll_clk,
286 ref_clk, 0, rate, accuracy);
287
288 if (IS_ERR(clk))
289 panic("%s: can't register REFCLK. Check DT!", np->name);
290
291 for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
292 const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
293
294 mc->parent_names[0] = ref_clk;
295 mc->parent_names[1] = pll_clk;
296 clk = clk_register_mux_table(NULL, mc->name, mc->parent_names,
297 mc->num_parents, mc->flags, base + mc->offset,
298 0, mc->mask, 0, mc->table, &asm9260_clk_lock);
299 }
300
301 /* clock mux gate cells */
302 for (n = 0; n < ARRAY_SIZE(asm9260_mux_gates); n++) {
303 const struct asm9260_gate_data *gd = &asm9260_mux_gates[n];
304
305 clk = clk_register_gate(NULL, gd->name,
306 gd->parent_name, gd->flags | CLK_SET_RATE_PARENT,
307 base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock);
308 }
309
310 /* clock div cells */
311 for (n = 0; n < ARRAY_SIZE(asm9260_div_clks); n++) {
312 const struct asm9260_div_clk *dc = &asm9260_div_clks[n];
313
314 clks[dc->idx] = clk_register_divider(NULL, dc->name,
315 dc->parent_name, CLK_SET_RATE_PARENT,
316 base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,
317 &asm9260_clk_lock);
318 }
319
320 /* clock ahb gate cells */
321 for (n = 0; n < ARRAY_SIZE(asm9260_ahb_gates); n++) {
322 const struct asm9260_gate_data *gd = &asm9260_ahb_gates[n];
323
324 clks[gd->idx] = clk_register_gate(NULL, gd->name,
325 gd->parent_name, gd->flags, base + gd->reg,
326 gd->bit_idx, 0, &asm9260_clk_lock);
327 }
328
329 /* check for errors on leaf clocks */
330 for (n = 0; n < MAX_CLKS; n++) {
331 if (!IS_ERR(clks[n]))
332 continue;
333
334 pr_err("%s: Unable to register leaf clock %d\n",
335 np->full_name, n);
336 goto fail;
337 }
338
339 /* register clk-provider */
340 clk_data.clks = clks;
341 clk_data.clk_num = MAX_CLKS;
342 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
343 return;
344fail:
345 iounmap(base);
346}
347CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller",
348 asm9260_acc_init);
diff --git a/drivers/clk/clk-cdce706.c b/drivers/clk/clk-cdce706.c
new file mode 100644
index 000000000000..c386ad25beb4
--- /dev/null
+++ b/drivers/clk/clk-cdce706.c
@@ -0,0 +1,700 @@
1/*
2 * TI CDCE706 programmable 3-PLL clock synthesizer driver
3 *
4 * Copyright (c) 2014 Cadence Design Systems Inc.
5 *
6 * Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/delay.h>
15#include <linux/i2c.h>
16#include <linux/interrupt.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/rational.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23
24#define CDCE706_CLKIN_CLOCK 10
25#define CDCE706_CLKIN_SOURCE 11
26#define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll))
27#define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll))
28#define CDCE706_PLL_HI(pll) (3 + 3 * (pll))
29#define CDCE706_PLL_MUX 3
30#define CDCE706_PLL_FVCO 6
31#define CDCE706_DIVIDER(div) (13 + (div))
32#define CDCE706_CLKOUT(out) (19 + (out))
33
34#define CDCE706_CLKIN_CLOCK_MASK 0x10
35#define CDCE706_CLKIN_SOURCE_SHIFT 6
36#define CDCE706_CLKIN_SOURCE_MASK 0xc0
37#define CDCE706_CLKIN_SOURCE_LVCMOS 0x40
38
39#define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll))
40#define CDCE706_PLL_LOW_M_MASK 0xff
41#define CDCE706_PLL_LOW_N_MASK 0xff
42#define CDCE706_PLL_HI_M_MASK 0x1
43#define CDCE706_PLL_HI_N_MASK 0x1e
44#define CDCE706_PLL_HI_N_SHIFT 1
45#define CDCE706_PLL_M_MAX 0x1ff
46#define CDCE706_PLL_N_MAX 0xfff
47#define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll))
48#define CDCE706_PLL_FREQ_MIN 80000000
49#define CDCE706_PLL_FREQ_MAX 300000000
50#define CDCE706_PLL_FREQ_HI 180000000
51
52#define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4))
53#define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1))
54#define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div))
55#define CDCE706_DIVIDER_DIVIDER_MASK 0x7f
56#define CDCE706_DIVIDER_DIVIDER_MAX 0x7f
57
58#define CDCE706_CLKOUT_DIVIDER_MASK 0x7
59#define CDCE706_CLKOUT_ENABLE_MASK 0x8
60
61static struct regmap_config cdce706_regmap_config = {
62 .reg_bits = 8,
63 .val_bits = 8,
64 .val_format_endian = REGMAP_ENDIAN_NATIVE,
65};
66
67#define to_hw_data(phw) (container_of((phw), struct cdce706_hw_data, hw))
68
69struct cdce706_hw_data {
70 struct cdce706_dev_data *dev_data;
71 unsigned idx;
72 unsigned parent;
73 struct clk *clk;
74 struct clk_hw hw;
75 unsigned div;
76 unsigned mul;
77 unsigned mux;
78};
79
80struct cdce706_dev_data {
81 struct i2c_client *client;
82 struct regmap *regmap;
83 struct clk_onecell_data onecell;
84 struct clk *clks[6];
85 struct clk *clkin_clk[2];
86 const char *clkin_name[2];
87 struct cdce706_hw_data clkin[1];
88 struct cdce706_hw_data pll[3];
89 struct cdce706_hw_data divider[6];
90 struct cdce706_hw_data clkout[6];
91};
92
93static const char * const cdce706_source_name[] = {
94 "clk_in0", "clk_in1",
95};
96
97static const char *cdce706_clkin_name[] = {
98 "clk_in",
99};
100
101static const char * const cdce706_pll_name[] = {
102 "pll1", "pll2", "pll3",
103};
104
105static const char *cdce706_divider_parent_name[] = {
106 "clk_in", "pll1", "pll2", "pll2", "pll3",
107};
108
109static const char *cdce706_divider_name[] = {
110 "p0", "p1", "p2", "p3", "p4", "p5",
111};
112
113static const char * const cdce706_clkout_name[] = {
114 "clk_out0", "clk_out1", "clk_out2", "clk_out3", "clk_out4", "clk_out5",
115};
116
117static int cdce706_reg_read(struct cdce706_dev_data *dev_data, unsigned reg,
118 unsigned *val)
119{
120 int rc = regmap_read(dev_data->regmap, reg | 0x80, val);
121
122 if (rc < 0)
123 dev_err(&dev_data->client->dev, "error reading reg %u", reg);
124 return rc;
125}
126
127static int cdce706_reg_write(struct cdce706_dev_data *dev_data, unsigned reg,
128 unsigned val)
129{
130 int rc = regmap_write(dev_data->regmap, reg | 0x80, val);
131
132 if (rc < 0)
133 dev_err(&dev_data->client->dev, "error writing reg %u", reg);
134 return rc;
135}
136
137static int cdce706_reg_update(struct cdce706_dev_data *dev_data, unsigned reg,
138 unsigned mask, unsigned val)
139{
140 int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val);
141
142 if (rc < 0)
143 dev_err(&dev_data->client->dev, "error updating reg %u", reg);
144 return rc;
145}
146
147static int cdce706_clkin_set_parent(struct clk_hw *hw, u8 index)
148{
149 struct cdce706_hw_data *hwd = to_hw_data(hw);
150
151 hwd->parent = index;
152 return 0;
153}
154
155static u8 cdce706_clkin_get_parent(struct clk_hw *hw)
156{
157 struct cdce706_hw_data *hwd = to_hw_data(hw);
158
159 return hwd->parent;
160}
161
162static const struct clk_ops cdce706_clkin_ops = {
163 .set_parent = cdce706_clkin_set_parent,
164 .get_parent = cdce706_clkin_get_parent,
165};
166
167static unsigned long cdce706_pll_recalc_rate(struct clk_hw *hw,
168 unsigned long parent_rate)
169{
170 struct cdce706_hw_data *hwd = to_hw_data(hw);
171
172 dev_dbg(&hwd->dev_data->client->dev,
173 "%s, pll: %d, mux: %d, mul: %u, div: %u\n",
174 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div);
175
176 if (!hwd->mux) {
177 if (hwd->div && hwd->mul) {
178 u64 res = (u64)parent_rate * hwd->mul;
179
180 do_div(res, hwd->div);
181 return res;
182 }
183 } else {
184 if (hwd->div)
185 return parent_rate / hwd->div;
186 }
187 return 0;
188}
189
190static long cdce706_pll_round_rate(struct clk_hw *hw, unsigned long rate,
191 unsigned long *parent_rate)
192{
193 struct cdce706_hw_data *hwd = to_hw_data(hw);
194 unsigned long mul, div;
195 u64 res;
196
197 dev_dbg(&hwd->dev_data->client->dev,
198 "%s, rate: %lu, parent_rate: %lu\n",
199 __func__, rate, *parent_rate);
200
201 rational_best_approximation(rate, *parent_rate,
202 CDCE706_PLL_N_MAX, CDCE706_PLL_M_MAX,
203 &mul, &div);
204 hwd->mul = mul;
205 hwd->div = div;
206
207 dev_dbg(&hwd->dev_data->client->dev,
208 "%s, pll: %d, mul: %lu, div: %lu\n",
209 __func__, hwd->idx, mul, div);
210
211 res = (u64)*parent_rate * hwd->mul;
212 do_div(res, hwd->div);
213 return res;
214}
215
216static int cdce706_pll_set_rate(struct clk_hw *hw, unsigned long rate,
217 unsigned long parent_rate)
218{
219 struct cdce706_hw_data *hwd = to_hw_data(hw);
220 unsigned long mul = hwd->mul, div = hwd->div;
221 int err;
222
223 dev_dbg(&hwd->dev_data->client->dev,
224 "%s, pll: %d, mul: %lu, div: %lu\n",
225 __func__, hwd->idx, mul, div);
226
227 err = cdce706_reg_update(hwd->dev_data,
228 CDCE706_PLL_HI(hwd->idx),
229 CDCE706_PLL_HI_M_MASK | CDCE706_PLL_HI_N_MASK,
230 ((div >> 8) & CDCE706_PLL_HI_M_MASK) |
231 ((mul >> (8 - CDCE706_PLL_HI_N_SHIFT)) &
232 CDCE706_PLL_HI_N_MASK));
233 if (err < 0)
234 return err;
235
236 err = cdce706_reg_write(hwd->dev_data,
237 CDCE706_PLL_M_LOW(hwd->idx),
238 div & CDCE706_PLL_LOW_M_MASK);
239 if (err < 0)
240 return err;
241
242 err = cdce706_reg_write(hwd->dev_data,
243 CDCE706_PLL_N_LOW(hwd->idx),
244 mul & CDCE706_PLL_LOW_N_MASK);
245 if (err < 0)
246 return err;
247
248 err = cdce706_reg_update(hwd->dev_data,
249 CDCE706_PLL_FVCO,
250 CDCE706_PLL_FVCO_MASK(hwd->idx),
251 rate > CDCE706_PLL_FREQ_HI ?
252 CDCE706_PLL_FVCO_MASK(hwd->idx) : 0);
253 return err;
254}
255
256static const struct clk_ops cdce706_pll_ops = {
257 .recalc_rate = cdce706_pll_recalc_rate,
258 .round_rate = cdce706_pll_round_rate,
259 .set_rate = cdce706_pll_set_rate,
260};
261
262static int cdce706_divider_set_parent(struct clk_hw *hw, u8 index)
263{
264 struct cdce706_hw_data *hwd = to_hw_data(hw);
265
266 if (hwd->parent == index)
267 return 0;
268 hwd->parent = index;
269 return cdce706_reg_update(hwd->dev_data,
270 CDCE706_DIVIDER_PLL(hwd->idx),
271 CDCE706_DIVIDER_PLL_MASK(hwd->idx),
272 index << CDCE706_DIVIDER_PLL_SHIFT(hwd->idx));
273}
274
275static u8 cdce706_divider_get_parent(struct clk_hw *hw)
276{
277 struct cdce706_hw_data *hwd = to_hw_data(hw);
278
279 return hwd->parent;
280}
281
282static unsigned long cdce706_divider_recalc_rate(struct clk_hw *hw,
283 unsigned long parent_rate)
284{
285 struct cdce706_hw_data *hwd = to_hw_data(hw);
286
287 dev_dbg(&hwd->dev_data->client->dev,
288 "%s, divider: %d, div: %u\n",
289 __func__, hwd->idx, hwd->div);
290 if (hwd->div)
291 return parent_rate / hwd->div;
292 return 0;
293}
294
295static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
296 unsigned long *parent_rate)
297{
298 struct cdce706_hw_data *hwd = to_hw_data(hw);
299 struct cdce706_dev_data *cdce = hwd->dev_data;
300 unsigned long mul, div;
301
302 dev_dbg(&hwd->dev_data->client->dev,
303 "%s, rate: %lu, parent_rate: %lu\n",
304 __func__, rate, *parent_rate);
305
306 rational_best_approximation(rate, *parent_rate,
307 1, CDCE706_DIVIDER_DIVIDER_MAX,
308 &mul, &div);
309 if (!mul)
310 div = CDCE706_DIVIDER_DIVIDER_MAX;
311
312 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
313 unsigned long best_diff = rate;
314 unsigned long best_div = 0;
315 struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
316 unsigned long gp_rate = gp_clk ? clk_get_rate(gp_clk) : 0;
317
318 for (div = CDCE706_PLL_FREQ_MIN / rate; best_diff &&
319 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) {
320 unsigned long n, m;
321 unsigned long diff;
322 unsigned long div_rate;
323 u64 div_rate64;
324
325 if (rate * div < CDCE706_PLL_FREQ_MIN)
326 continue;
327
328 rational_best_approximation(rate * div, gp_rate,
329 CDCE706_PLL_N_MAX,
330 CDCE706_PLL_M_MAX,
331 &n, &m);
332 div_rate64 = (u64)gp_rate * n;
333 do_div(div_rate64, m);
334 do_div(div_rate64, div);
335 div_rate = div_rate64;
336 diff = max(div_rate, rate) - min(div_rate, rate);
337
338 if (diff < best_diff) {
339 best_diff = diff;
340 best_div = div;
341 dev_dbg(&hwd->dev_data->client->dev,
342 "%s, %lu * %lu / %lu / %lu = %lu\n",
343 __func__, gp_rate, n, m, div, div_rate);
344 }
345 }
346
347 div = best_div;
348
349 dev_dbg(&hwd->dev_data->client->dev,
350 "%s, altering parent rate: %lu -> %lu\n",
351 __func__, *parent_rate, rate * div);
352 *parent_rate = rate * div;
353 }
354 hwd->div = div;
355
356 dev_dbg(&hwd->dev_data->client->dev,
357 "%s, divider: %d, div: %lu\n",
358 __func__, hwd->idx, div);
359
360 return *parent_rate / div;
361}
362
363static int cdce706_divider_set_rate(struct clk_hw *hw, unsigned long rate,
364 unsigned long parent_rate)
365{
366 struct cdce706_hw_data *hwd = to_hw_data(hw);
367
368 dev_dbg(&hwd->dev_data->client->dev,
369 "%s, divider: %d, div: %u\n",
370 __func__, hwd->idx, hwd->div);
371
372 return cdce706_reg_update(hwd->dev_data,
373 CDCE706_DIVIDER(hwd->idx),
374 CDCE706_DIVIDER_DIVIDER_MASK,
375 hwd->div);
376}
377
378static const struct clk_ops cdce706_divider_ops = {
379 .set_parent = cdce706_divider_set_parent,
380 .get_parent = cdce706_divider_get_parent,
381 .recalc_rate = cdce706_divider_recalc_rate,
382 .round_rate = cdce706_divider_round_rate,
383 .set_rate = cdce706_divider_set_rate,
384};
385
386static int cdce706_clkout_prepare(struct clk_hw *hw)
387{
388 struct cdce706_hw_data *hwd = to_hw_data(hw);
389
390 return cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx),
391 CDCE706_CLKOUT_ENABLE_MASK,
392 CDCE706_CLKOUT_ENABLE_MASK);
393}
394
395static void cdce706_clkout_unprepare(struct clk_hw *hw)
396{
397 struct cdce706_hw_data *hwd = to_hw_data(hw);
398
399 cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx),
400 CDCE706_CLKOUT_ENABLE_MASK, 0);
401}
402
403static int cdce706_clkout_set_parent(struct clk_hw *hw, u8 index)
404{
405 struct cdce706_hw_data *hwd = to_hw_data(hw);
406
407 if (hwd->parent == index)
408 return 0;
409 hwd->parent = index;
410 return cdce706_reg_update(hwd->dev_data,
411 CDCE706_CLKOUT(hwd->idx),
412 CDCE706_CLKOUT_ENABLE_MASK, index);
413}
414
415static u8 cdce706_clkout_get_parent(struct clk_hw *hw)
416{
417 struct cdce706_hw_data *hwd = to_hw_data(hw);
418
419 return hwd->parent;
420}
421
422static unsigned long cdce706_clkout_recalc_rate(struct clk_hw *hw,
423 unsigned long parent_rate)
424{
425 return parent_rate;
426}
427
428static long cdce706_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
429 unsigned long *parent_rate)
430{
431 *parent_rate = rate;
432 return rate;
433}
434
435static int cdce706_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
436 unsigned long parent_rate)
437{
438 return 0;
439}
440
441static const struct clk_ops cdce706_clkout_ops = {
442 .prepare = cdce706_clkout_prepare,
443 .unprepare = cdce706_clkout_unprepare,
444 .set_parent = cdce706_clkout_set_parent,
445 .get_parent = cdce706_clkout_get_parent,
446 .recalc_rate = cdce706_clkout_recalc_rate,
447 .round_rate = cdce706_clkout_round_rate,
448 .set_rate = cdce706_clkout_set_rate,
449};
450
451static int cdce706_register_hw(struct cdce706_dev_data *cdce,
452 struct cdce706_hw_data *hw, unsigned num_hw,
453 const char * const *clk_names,
454 struct clk_init_data *init)
455{
456 unsigned i;
457
458 for (i = 0; i < num_hw; ++i, ++hw) {
459 init->name = clk_names[i];
460 hw->dev_data = cdce;
461 hw->idx = i;
462 hw->hw.init = init;
463 hw->clk = devm_clk_register(&cdce->client->dev,
464 &hw->hw);
465 if (IS_ERR(hw->clk)) {
466 dev_err(&cdce->client->dev, "Failed to register %s\n",
467 clk_names[i]);
468 return PTR_ERR(hw->clk);
469 }
470 }
471 return 0;
472}
473
474static int cdce706_register_clkin(struct cdce706_dev_data *cdce)
475{
476 struct clk_init_data init = {
477 .ops = &cdce706_clkin_ops,
478 .parent_names = cdce->clkin_name,
479 .num_parents = ARRAY_SIZE(cdce->clkin_name),
480 };
481 unsigned i;
482 int ret;
483 unsigned clock, source;
484
485 for (i = 0; i < ARRAY_SIZE(cdce->clkin_name); ++i) {
486 struct clk *parent = devm_clk_get(&cdce->client->dev,
487 cdce706_source_name[i]);
488
489 if (IS_ERR(parent)) {
490 cdce->clkin_name[i] = cdce706_source_name[i];
491 } else {
492 cdce->clkin_name[i] = __clk_get_name(parent);
493 cdce->clkin_clk[i] = parent;
494 }
495 }
496
497 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_SOURCE, &source);
498 if (ret < 0)
499 return ret;
500 if ((source & CDCE706_CLKIN_SOURCE_MASK) ==
501 CDCE706_CLKIN_SOURCE_LVCMOS) {
502 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_CLOCK, &clock);
503 if (ret < 0)
504 return ret;
505 cdce->clkin[0].parent = !!(clock & CDCE706_CLKIN_CLOCK_MASK);
506 }
507
508 ret = cdce706_register_hw(cdce, cdce->clkin,
509 ARRAY_SIZE(cdce->clkin),
510 cdce706_clkin_name, &init);
511 return ret;
512}
513
514static int cdce706_register_plls(struct cdce706_dev_data *cdce)
515{
516 struct clk_init_data init = {
517 .ops = &cdce706_pll_ops,
518 .parent_names = cdce706_clkin_name,
519 .num_parents = ARRAY_SIZE(cdce706_clkin_name),
520 };
521 unsigned i;
522 int ret;
523 unsigned mux;
524
525 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux);
526 if (ret < 0)
527 return ret;
528
529 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) {
530 unsigned m, n, v;
531
532 ret = cdce706_reg_read(cdce, CDCE706_PLL_M_LOW(i), &m);
533 if (ret < 0)
534 return ret;
535 ret = cdce706_reg_read(cdce, CDCE706_PLL_N_LOW(i), &n);
536 if (ret < 0)
537 return ret;
538 ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v);
539 if (ret < 0)
540 return ret;
541 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8);
542 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) <<
543 (8 - CDCE706_PLL_HI_N_SHIFT));
544 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i);
545 dev_dbg(&cdce->client->dev,
546 "%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i,
547 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux);
548 }
549
550 ret = cdce706_register_hw(cdce, cdce->pll,
551 ARRAY_SIZE(cdce->pll),
552 cdce706_pll_name, &init);
553 return ret;
554}
555
556static int cdce706_register_dividers(struct cdce706_dev_data *cdce)
557{
558 struct clk_init_data init = {
559 .ops = &cdce706_divider_ops,
560 .parent_names = cdce706_divider_parent_name,
561 .num_parents = ARRAY_SIZE(cdce706_divider_parent_name),
562 .flags = CLK_SET_RATE_PARENT,
563 };
564 unsigned i;
565 int ret;
566
567 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
568 unsigned val;
569
570 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val);
571 if (ret < 0)
572 return ret;
573 cdce->divider[i].parent =
574 (val & CDCE706_DIVIDER_PLL_MASK(i)) >>
575 CDCE706_DIVIDER_PLL_SHIFT(i);
576
577 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val);
578 if (ret < 0)
579 return ret;
580 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
581 dev_dbg(&cdce->client->dev,
582 "%s: i: %u, parent: %u, div: %u\n", __func__, i,
583 cdce->divider[i].parent, cdce->divider[i].div);
584 }
585
586 ret = cdce706_register_hw(cdce, cdce->divider,
587 ARRAY_SIZE(cdce->divider),
588 cdce706_divider_name, &init);
589 return ret;
590}
591
592static int cdce706_register_clkouts(struct cdce706_dev_data *cdce)
593{
594 struct clk_init_data init = {
595 .ops = &cdce706_clkout_ops,
596 .parent_names = cdce706_divider_name,
597 .num_parents = ARRAY_SIZE(cdce706_divider_name),
598 .flags = CLK_SET_RATE_PARENT,
599 };
600 unsigned i;
601 int ret;
602
603 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) {
604 unsigned val;
605
606 ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val);
607 if (ret < 0)
608 return ret;
609 cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK;
610 dev_dbg(&cdce->client->dev,
611 "%s: i: %u, parent: %u\n", __func__, i,
612 cdce->clkout[i].parent);
613 }
614
615 ret = cdce706_register_hw(cdce, cdce->clkout,
616 ARRAY_SIZE(cdce->clkout),
617 cdce706_clkout_name, &init);
618 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i)
619 cdce->clks[i] = cdce->clkout[i].clk;
620
621 return ret;
622}
623
624static int cdce706_probe(struct i2c_client *client,
625 const struct i2c_device_id *id)
626{
627 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
628 struct cdce706_dev_data *cdce;
629 int ret;
630
631 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
632 return -EIO;
633
634 cdce = devm_kzalloc(&client->dev, sizeof(*cdce), GFP_KERNEL);
635 if (!cdce)
636 return -ENOMEM;
637
638 cdce->client = client;
639 cdce->regmap = devm_regmap_init_i2c(client, &cdce706_regmap_config);
640 if (IS_ERR(cdce->regmap)) {
641 dev_err(&client->dev, "Failed to initialize regmap\n");
642 return -EINVAL;
643 }
644
645 i2c_set_clientdata(client, cdce);
646
647 ret = cdce706_register_clkin(cdce);
648 if (ret < 0)
649 return ret;
650 ret = cdce706_register_plls(cdce);
651 if (ret < 0)
652 return ret;
653 ret = cdce706_register_dividers(cdce);
654 if (ret < 0)
655 return ret;
656 ret = cdce706_register_clkouts(cdce);
657 if (ret < 0)
658 return ret;
659 cdce->onecell.clks = cdce->clks;
660 cdce->onecell.clk_num = ARRAY_SIZE(cdce->clks);
661 ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
662 &cdce->onecell);
663
664 return ret;
665}
666
667static int cdce706_remove(struct i2c_client *client)
668{
669 return 0;
670}
671
672
673#ifdef CONFIG_OF
674static const struct of_device_id cdce706_dt_match[] = {
675 { .compatible = "ti,cdce706" },
676 { },
677};
678MODULE_DEVICE_TABLE(of, cdce706_dt_match);
679#endif
680
681static const struct i2c_device_id cdce706_id[] = {
682 { "cdce706", 0 },
683 { }
684};
685MODULE_DEVICE_TABLE(i2c, cdce706_id);
686
687static struct i2c_driver cdce706_i2c_driver = {
688 .driver = {
689 .name = "cdce706",
690 .of_match_table = of_match_ptr(cdce706_dt_match),
691 },
692 .probe = cdce706_probe,
693 .remove = cdce706_remove,
694 .id_table = cdce706_id,
695};
696module_i2c_driver(cdce706_i2c_driver);
697
698MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
699MODULE_DESCRIPTION("TI CDCE 706 clock synthesizer driver");
700MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 4386697236a7..956b7e54fa1c 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -27,7 +27,7 @@ static u8 clk_composite_get_parent(struct clk_hw *hw)
27 const struct clk_ops *mux_ops = composite->mux_ops; 27 const struct clk_ops *mux_ops = composite->mux_ops;
28 struct clk_hw *mux_hw = composite->mux_hw; 28 struct clk_hw *mux_hw = composite->mux_hw;
29 29
30 mux_hw->clk = hw->clk; 30 __clk_hw_set_clk(mux_hw, hw);
31 31
32 return mux_ops->get_parent(mux_hw); 32 return mux_ops->get_parent(mux_hw);
33} 33}
@@ -38,7 +38,7 @@ static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
38 const struct clk_ops *mux_ops = composite->mux_ops; 38 const struct clk_ops *mux_ops = composite->mux_ops;
39 struct clk_hw *mux_hw = composite->mux_hw; 39 struct clk_hw *mux_hw = composite->mux_hw;
40 40
41 mux_hw->clk = hw->clk; 41 __clk_hw_set_clk(mux_hw, hw);
42 42
43 return mux_ops->set_parent(mux_hw, index); 43 return mux_ops->set_parent(mux_hw, index);
44} 44}
@@ -50,12 +50,14 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
50 const struct clk_ops *rate_ops = composite->rate_ops; 50 const struct clk_ops *rate_ops = composite->rate_ops;
51 struct clk_hw *rate_hw = composite->rate_hw; 51 struct clk_hw *rate_hw = composite->rate_hw;
52 52
53 rate_hw->clk = hw->clk; 53 __clk_hw_set_clk(rate_hw, hw);
54 54
55 return rate_ops->recalc_rate(rate_hw, parent_rate); 55 return rate_ops->recalc_rate(rate_hw, parent_rate);
56} 56}
57 57
58static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, 58static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long min_rate,
60 unsigned long max_rate,
59 unsigned long *best_parent_rate, 61 unsigned long *best_parent_rate,
60 struct clk_hw **best_parent_p) 62 struct clk_hw **best_parent_p)
61{ 63{
@@ -72,8 +74,10 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
72 int i; 74 int i;
73 75
74 if (rate_hw && rate_ops && rate_ops->determine_rate) { 76 if (rate_hw && rate_ops && rate_ops->determine_rate) {
75 rate_hw->clk = hw->clk; 77 __clk_hw_set_clk(rate_hw, hw);
76 return rate_ops->determine_rate(rate_hw, rate, best_parent_rate, 78 return rate_ops->determine_rate(rate_hw, rate, min_rate,
79 max_rate,
80 best_parent_rate,
77 best_parent_p); 81 best_parent_p);
78 } else if (rate_hw && rate_ops && rate_ops->round_rate && 82 } else if (rate_hw && rate_ops && rate_ops->round_rate &&
79 mux_hw && mux_ops && mux_ops->set_parent) { 83 mux_hw && mux_ops && mux_ops->set_parent) {
@@ -116,8 +120,9 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
116 120
117 return best_rate; 121 return best_rate;
118 } else if (mux_hw && mux_ops && mux_ops->determine_rate) { 122 } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
119 mux_hw->clk = hw->clk; 123 __clk_hw_set_clk(mux_hw, hw);
120 return mux_ops->determine_rate(mux_hw, rate, best_parent_rate, 124 return mux_ops->determine_rate(mux_hw, rate, min_rate,
125 max_rate, best_parent_rate,
121 best_parent_p); 126 best_parent_p);
122 } else { 127 } else {
123 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n"); 128 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
@@ -132,7 +137,7 @@ static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
132 const struct clk_ops *rate_ops = composite->rate_ops; 137 const struct clk_ops *rate_ops = composite->rate_ops;
133 struct clk_hw *rate_hw = composite->rate_hw; 138 struct clk_hw *rate_hw = composite->rate_hw;
134 139
135 rate_hw->clk = hw->clk; 140 __clk_hw_set_clk(rate_hw, hw);
136 141
137 return rate_ops->round_rate(rate_hw, rate, prate); 142 return rate_ops->round_rate(rate_hw, rate, prate);
138} 143}
@@ -144,7 +149,7 @@ static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
144 const struct clk_ops *rate_ops = composite->rate_ops; 149 const struct clk_ops *rate_ops = composite->rate_ops;
145 struct clk_hw *rate_hw = composite->rate_hw; 150 struct clk_hw *rate_hw = composite->rate_hw;
146 151
147 rate_hw->clk = hw->clk; 152 __clk_hw_set_clk(rate_hw, hw);
148 153
149 return rate_ops->set_rate(rate_hw, rate, parent_rate); 154 return rate_ops->set_rate(rate_hw, rate, parent_rate);
150} 155}
@@ -155,7 +160,7 @@ static int clk_composite_is_enabled(struct clk_hw *hw)
155 const struct clk_ops *gate_ops = composite->gate_ops; 160 const struct clk_ops *gate_ops = composite->gate_ops;
156 struct clk_hw *gate_hw = composite->gate_hw; 161 struct clk_hw *gate_hw = composite->gate_hw;
157 162
158 gate_hw->clk = hw->clk; 163 __clk_hw_set_clk(gate_hw, hw);
159 164
160 return gate_ops->is_enabled(gate_hw); 165 return gate_ops->is_enabled(gate_hw);
161} 166}
@@ -166,7 +171,7 @@ static int clk_composite_enable(struct clk_hw *hw)
166 const struct clk_ops *gate_ops = composite->gate_ops; 171 const struct clk_ops *gate_ops = composite->gate_ops;
167 struct clk_hw *gate_hw = composite->gate_hw; 172 struct clk_hw *gate_hw = composite->gate_hw;
168 173
169 gate_hw->clk = hw->clk; 174 __clk_hw_set_clk(gate_hw, hw);
170 175
171 return gate_ops->enable(gate_hw); 176 return gate_ops->enable(gate_hw);
172} 177}
@@ -177,7 +182,7 @@ static void clk_composite_disable(struct clk_hw *hw)
177 const struct clk_ops *gate_ops = composite->gate_ops; 182 const struct clk_ops *gate_ops = composite->gate_ops;
178 struct clk_hw *gate_hw = composite->gate_hw; 183 struct clk_hw *gate_hw = composite->gate_hw;
179 184
180 gate_hw->clk = hw->clk; 185 __clk_hw_set_clk(gate_hw, hw);
181 186
182 gate_ops->disable(gate_hw); 187 gate_ops->disable(gate_hw);
183} 188}
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c0a842b335c5..db7f8bce7467 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -30,7 +30,7 @@
30 30
31#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 31#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
32 32
33#define div_mask(d) ((1 << ((d)->width)) - 1) 33#define div_mask(width) ((1 << (width)) - 1)
34 34
35static unsigned int _get_table_maxdiv(const struct clk_div_table *table) 35static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
36{ 36{
@@ -54,15 +54,16 @@ static unsigned int _get_table_mindiv(const struct clk_div_table *table)
54 return mindiv; 54 return mindiv;
55} 55}
56 56
57static unsigned int _get_maxdiv(struct clk_divider *divider) 57static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
58 unsigned long flags)
58{ 59{
59 if (divider->flags & CLK_DIVIDER_ONE_BASED) 60 if (flags & CLK_DIVIDER_ONE_BASED)
60 return div_mask(divider); 61 return div_mask(width);
61 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 62 if (flags & CLK_DIVIDER_POWER_OF_TWO)
62 return 1 << div_mask(divider); 63 return 1 << div_mask(width);
63 if (divider->table) 64 if (table)
64 return _get_table_maxdiv(divider->table); 65 return _get_table_maxdiv(table);
65 return div_mask(divider) + 1; 66 return div_mask(width) + 1;
66} 67}
67 68
68static unsigned int _get_table_div(const struct clk_div_table *table, 69static unsigned int _get_table_div(const struct clk_div_table *table,
@@ -76,14 +77,15 @@ static unsigned int _get_table_div(const struct clk_div_table *table,
76 return 0; 77 return 0;
77} 78}
78 79
79static unsigned int _get_div(struct clk_divider *divider, unsigned int val) 80static unsigned int _get_div(const struct clk_div_table *table,
81 unsigned int val, unsigned long flags)
80{ 82{
81 if (divider->flags & CLK_DIVIDER_ONE_BASED) 83 if (flags & CLK_DIVIDER_ONE_BASED)
82 return val; 84 return val;
83 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 85 if (flags & CLK_DIVIDER_POWER_OF_TWO)
84 return 1 << val; 86 return 1 << val;
85 if (divider->table) 87 if (table)
86 return _get_table_div(divider->table, val); 88 return _get_table_div(table, val);
87 return val + 1; 89 return val + 1;
88} 90}
89 91
@@ -98,29 +100,28 @@ static unsigned int _get_table_val(const struct clk_div_table *table,
98 return 0; 100 return 0;
99} 101}
100 102
101static unsigned int _get_val(struct clk_divider *divider, unsigned int div) 103static unsigned int _get_val(const struct clk_div_table *table,
104 unsigned int div, unsigned long flags)
102{ 105{
103 if (divider->flags & CLK_DIVIDER_ONE_BASED) 106 if (flags & CLK_DIVIDER_ONE_BASED)
104 return div; 107 return div;
105 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 108 if (flags & CLK_DIVIDER_POWER_OF_TWO)
106 return __ffs(div); 109 return __ffs(div);
107 if (divider->table) 110 if (table)
108 return _get_table_val(divider->table, div); 111 return _get_table_val(table, div);
109 return div - 1; 112 return div - 1;
110} 113}
111 114
112static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, 115unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
113 unsigned long parent_rate) 116 unsigned int val,
117 const struct clk_div_table *table,
118 unsigned long flags)
114{ 119{
115 struct clk_divider *divider = to_clk_divider(hw); 120 unsigned int div;
116 unsigned int div, val;
117 121
118 val = clk_readl(divider->reg) >> divider->shift; 122 div = _get_div(table, val, flags);
119 val &= div_mask(divider);
120
121 div = _get_div(divider, val);
122 if (!div) { 123 if (!div) {
123 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 124 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
124 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 125 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
125 __clk_get_name(hw->clk)); 126 __clk_get_name(hw->clk));
126 return parent_rate; 127 return parent_rate;
@@ -128,6 +129,20 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
128 129
129 return DIV_ROUND_UP(parent_rate, div); 130 return DIV_ROUND_UP(parent_rate, div);
130} 131}
132EXPORT_SYMBOL_GPL(divider_recalc_rate);
133
134static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
135 unsigned long parent_rate)
136{
137 struct clk_divider *divider = to_clk_divider(hw);
138 unsigned int val;
139
140 val = clk_readl(divider->reg) >> divider->shift;
141 val &= div_mask(divider->width);
142
143 return divider_recalc_rate(hw, parent_rate, val, divider->table,
144 divider->flags);
145}
131 146
132/* 147/*
133 * The reverse of DIV_ROUND_UP: The maximum number which 148 * The reverse of DIV_ROUND_UP: The maximum number which
@@ -146,12 +161,13 @@ static bool _is_valid_table_div(const struct clk_div_table *table,
146 return false; 161 return false;
147} 162}
148 163
149static bool _is_valid_div(struct clk_divider *divider, unsigned int div) 164static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
165 unsigned long flags)
150{ 166{
151 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 167 if (flags & CLK_DIVIDER_POWER_OF_TWO)
152 return is_power_of_2(div); 168 return is_power_of_2(div);
153 if (divider->table) 169 if (table)
154 return _is_valid_table_div(divider->table, div); 170 return _is_valid_table_div(table, div);
155 return true; 171 return true;
156} 172}
157 173
@@ -191,71 +207,76 @@ static int _round_down_table(const struct clk_div_table *table, int div)
191 return down; 207 return down;
192} 208}
193 209
194static int _div_round_up(struct clk_divider *divider, 210static int _div_round_up(const struct clk_div_table *table,
195 unsigned long parent_rate, unsigned long rate) 211 unsigned long parent_rate, unsigned long rate,
212 unsigned long flags)
196{ 213{
197 int div = DIV_ROUND_UP(parent_rate, rate); 214 int div = DIV_ROUND_UP(parent_rate, rate);
198 215
199 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 216 if (flags & CLK_DIVIDER_POWER_OF_TWO)
200 div = __roundup_pow_of_two(div); 217 div = __roundup_pow_of_two(div);
201 if (divider->table) 218 if (table)
202 div = _round_up_table(divider->table, div); 219 div = _round_up_table(table, div);
203 220
204 return div; 221 return div;
205} 222}
206 223
207static int _div_round_closest(struct clk_divider *divider, 224static int _div_round_closest(const struct clk_div_table *table,
208 unsigned long parent_rate, unsigned long rate) 225 unsigned long parent_rate, unsigned long rate,
226 unsigned long flags)
209{ 227{
210 int up, down, div; 228 int up, down, div;
211 229
212 up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate); 230 up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);
213 231
214 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) { 232 if (flags & CLK_DIVIDER_POWER_OF_TWO) {
215 up = __roundup_pow_of_two(div); 233 up = __roundup_pow_of_two(div);
216 down = __rounddown_pow_of_two(div); 234 down = __rounddown_pow_of_two(div);
217 } else if (divider->table) { 235 } else if (table) {
218 up = _round_up_table(divider->table, div); 236 up = _round_up_table(table, div);
219 down = _round_down_table(divider->table, div); 237 down = _round_down_table(table, div);
220 } 238 }
221 239
222 return (up - div) <= (div - down) ? up : down; 240 return (up - div) <= (div - down) ? up : down;
223} 241}
224 242
225static int _div_round(struct clk_divider *divider, unsigned long parent_rate, 243static int _div_round(const struct clk_div_table *table,
226 unsigned long rate) 244 unsigned long parent_rate, unsigned long rate,
245 unsigned long flags)
227{ 246{
228 if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST) 247 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
229 return _div_round_closest(divider, parent_rate, rate); 248 return _div_round_closest(table, parent_rate, rate, flags);
230 249
231 return _div_round_up(divider, parent_rate, rate); 250 return _div_round_up(table, parent_rate, rate, flags);
232} 251}
233 252
234static bool _is_best_div(struct clk_divider *divider, 253static bool _is_best_div(unsigned long rate, unsigned long now,
235 unsigned long rate, unsigned long now, unsigned long best) 254 unsigned long best, unsigned long flags)
236{ 255{
237 if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST) 256 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
238 return abs(rate - now) < abs(rate - best); 257 return abs(rate - now) < abs(rate - best);
239 258
240 return now <= rate && now > best; 259 return now <= rate && now > best;
241} 260}
242 261
243static int _next_div(struct clk_divider *divider, int div) 262static int _next_div(const struct clk_div_table *table, int div,
263 unsigned long flags)
244{ 264{
245 div++; 265 div++;
246 266
247 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 267 if (flags & CLK_DIVIDER_POWER_OF_TWO)
248 return __roundup_pow_of_two(div); 268 return __roundup_pow_of_two(div);
249 if (divider->table) 269 if (table)
250 return _round_up_table(divider->table, div); 270 return _round_up_table(table, div);
251 271
252 return div; 272 return div;
253} 273}
254 274
255static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, 275static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
256 unsigned long *best_parent_rate) 276 unsigned long *best_parent_rate,
277 const struct clk_div_table *table, u8 width,
278 unsigned long flags)
257{ 279{
258 struct clk_divider *divider = to_clk_divider(hw);
259 int i, bestdiv = 0; 280 int i, bestdiv = 0;
260 unsigned long parent_rate, best = 0, now, maxdiv; 281 unsigned long parent_rate, best = 0, now, maxdiv;
261 unsigned long parent_rate_saved = *best_parent_rate; 282 unsigned long parent_rate_saved = *best_parent_rate;
@@ -263,19 +284,11 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
263 if (!rate) 284 if (!rate)
264 rate = 1; 285 rate = 1;
265 286
266 /* if read only, just return current value */ 287 maxdiv = _get_maxdiv(table, width, flags);
267 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
268 bestdiv = readl(divider->reg) >> divider->shift;
269 bestdiv &= div_mask(divider);
270 bestdiv = _get_div(divider, bestdiv);
271 return bestdiv;
272 }
273
274 maxdiv = _get_maxdiv(divider);
275 288
276 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { 289 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
277 parent_rate = *best_parent_rate; 290 parent_rate = *best_parent_rate;
278 bestdiv = _div_round(divider, parent_rate, rate); 291 bestdiv = _div_round(table, parent_rate, rate, flags);
279 bestdiv = bestdiv == 0 ? 1 : bestdiv; 292 bestdiv = bestdiv == 0 ? 1 : bestdiv;
280 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; 293 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
281 return bestdiv; 294 return bestdiv;
@@ -287,8 +300,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
287 */ 300 */
288 maxdiv = min(ULONG_MAX / rate, maxdiv); 301 maxdiv = min(ULONG_MAX / rate, maxdiv);
289 302
290 for (i = 1; i <= maxdiv; i = _next_div(divider, i)) { 303 for (i = 1; i <= maxdiv; i = _next_div(table, i, flags)) {
291 if (!_is_valid_div(divider, i)) 304 if (!_is_valid_div(table, i, flags))
292 continue; 305 continue;
293 if (rate * i == parent_rate_saved) { 306 if (rate * i == parent_rate_saved) {
294 /* 307 /*
@@ -302,7 +315,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
302 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 315 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
303 MULT_ROUND_UP(rate, i)); 316 MULT_ROUND_UP(rate, i));
304 now = DIV_ROUND_UP(parent_rate, i); 317 now = DIV_ROUND_UP(parent_rate, i);
305 if (_is_best_div(divider, rate, now, best)) { 318 if (_is_best_div(rate, now, best, flags)) {
306 bestdiv = i; 319 bestdiv = i;
307 best = now; 320 best = now;
308 *best_parent_rate = parent_rate; 321 *best_parent_rate = parent_rate;
@@ -310,48 +323,79 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
310 } 323 }
311 324
312 if (!bestdiv) { 325 if (!bestdiv) {
313 bestdiv = _get_maxdiv(divider); 326 bestdiv = _get_maxdiv(table, width, flags);
314 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1); 327 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
315 } 328 }
316 329
317 return bestdiv; 330 return bestdiv;
318} 331}
319 332
320static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 333long divider_round_rate(struct clk_hw *hw, unsigned long rate,
321 unsigned long *prate) 334 unsigned long *prate, const struct clk_div_table *table,
335 u8 width, unsigned long flags)
322{ 336{
323 int div; 337 int div;
324 div = clk_divider_bestdiv(hw, rate, prate); 338
339 div = clk_divider_bestdiv(hw, rate, prate, table, width, flags);
325 340
326 return DIV_ROUND_UP(*prate, div); 341 return DIV_ROUND_UP(*prate, div);
327} 342}
343EXPORT_SYMBOL_GPL(divider_round_rate);
328 344
329static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 345static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
330 unsigned long parent_rate) 346 unsigned long *prate)
331{ 347{
332 struct clk_divider *divider = to_clk_divider(hw); 348 struct clk_divider *divider = to_clk_divider(hw);
349 int bestdiv;
350
351 /* if read only, just return current value */
352 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
353 bestdiv = readl(divider->reg) >> divider->shift;
354 bestdiv &= div_mask(divider->width);
355 bestdiv = _get_div(divider->table, bestdiv, divider->flags);
356 return bestdiv;
357 }
358
359 return divider_round_rate(hw, rate, prate, divider->table,
360 divider->width, divider->flags);
361}
362
363int divider_get_val(unsigned long rate, unsigned long parent_rate,
364 const struct clk_div_table *table, u8 width,
365 unsigned long flags)
366{
333 unsigned int div, value; 367 unsigned int div, value;
334 unsigned long flags = 0;
335 u32 val;
336 368
337 div = DIV_ROUND_UP(parent_rate, rate); 369 div = DIV_ROUND_UP(parent_rate, rate);
338 370
339 if (!_is_valid_div(divider, div)) 371 if (!_is_valid_div(table, div, flags))
340 return -EINVAL; 372 return -EINVAL;
341 373
342 value = _get_val(divider, div); 374 value = _get_val(table, div, flags);
375
376 return min_t(unsigned int, value, div_mask(width));
377}
378EXPORT_SYMBOL_GPL(divider_get_val);
379
380static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
381 unsigned long parent_rate)
382{
383 struct clk_divider *divider = to_clk_divider(hw);
384 unsigned int value;
385 unsigned long flags = 0;
386 u32 val;
343 387
344 if (value > div_mask(divider)) 388 value = divider_get_val(rate, parent_rate, divider->table,
345 value = div_mask(divider); 389 divider->width, divider->flags);
346 390
347 if (divider->lock) 391 if (divider->lock)
348 spin_lock_irqsave(divider->lock, flags); 392 spin_lock_irqsave(divider->lock, flags);
349 393
350 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { 394 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
351 val = div_mask(divider) << (divider->shift + 16); 395 val = div_mask(divider->width) << (divider->shift + 16);
352 } else { 396 } else {
353 val = clk_readl(divider->reg); 397 val = clk_readl(divider->reg);
354 val &= ~(div_mask(divider) << divider->shift); 398 val &= ~(div_mask(divider->width) << divider->shift);
355 } 399 }
356 val |= value << divider->shift; 400 val |= value << divider->shift;
357 clk_writel(val, divider->reg); 401 clk_writel(val, divider->reg);
@@ -463,3 +507,19 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
463 width, clk_divider_flags, table, lock); 507 width, clk_divider_flags, table, lock);
464} 508}
465EXPORT_SYMBOL_GPL(clk_register_divider_table); 509EXPORT_SYMBOL_GPL(clk_register_divider_table);
510
511void clk_unregister_divider(struct clk *clk)
512{
513 struct clk_divider *div;
514 struct clk_hw *hw;
515
516 hw = __clk_get_hw(clk);
517 if (!hw)
518 return;
519
520 div = to_clk_divider(hw);
521
522 clk_unregister(clk);
523 kfree(div);
524}
525EXPORT_SYMBOL_GPL(clk_unregister_divider);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 51fd87fb7ba6..3f0e4200cb5d 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -128,7 +128,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
128 struct clk_init_data init; 128 struct clk_init_data init;
129 129
130 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { 130 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
131 if (bit_idx > 16) { 131 if (bit_idx > 15) {
132 pr_err("gate bit exceeds LOWORD field\n"); 132 pr_err("gate bit exceeds LOWORD field\n");
133 return ERR_PTR(-EINVAL); 133 return ERR_PTR(-EINVAL);
134 } 134 }
@@ -162,3 +162,19 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
162 return clk; 162 return clk;
163} 163}
164EXPORT_SYMBOL_GPL(clk_register_gate); 164EXPORT_SYMBOL_GPL(clk_register_gate);
165
166void clk_unregister_gate(struct clk *clk)
167{
168 struct clk_gate *gate;
169 struct clk_hw *hw;
170
171 hw = __clk_get_hw(clk);
172 if (!hw)
173 return;
174
175 gate = to_clk_gate(hw);
176
177 clk_unregister(clk);
178 kfree(gate);
179}
180EXPORT_SYMBOL_GPL(clk_unregister_gate);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 6e1ecf94bf58..69a094c3783d 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -177,3 +177,19 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
177 NULL, lock); 177 NULL, lock);
178} 178}
179EXPORT_SYMBOL_GPL(clk_register_mux); 179EXPORT_SYMBOL_GPL(clk_register_mux);
180
181void clk_unregister_mux(struct clk *clk)
182{
183 struct clk_mux *mux;
184 struct clk_hw *hw;
185
186 hw = __clk_get_hw(clk);
187 if (!hw)
188 return;
189
190 mux = to_clk_mux(hw);
191
192 clk_unregister(clk);
193 kfree(mux);
194}
195EXPORT_SYMBOL_GPL(clk_unregister_mux);
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
index 0a47d6f49cd6..cda90a971e39 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c
@@ -5,8 +5,11 @@
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 * 7 *
8 * clock driver for Freescale PowerPC corenet SoCs. 8 * clock driver for Freescale QorIQ SoCs.
9 */ 9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
10#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
11#include <linux/io.h> 14#include <linux/io.h>
12#include <linux/kernel.h> 15#include <linux/kernel.h>
@@ -19,6 +22,7 @@
19struct cmux_clk { 22struct cmux_clk {
20 struct clk_hw hw; 23 struct clk_hw hw;
21 void __iomem *reg; 24 void __iomem *reg;
25 unsigned int clk_per_pll;
22 u32 flags; 26 u32 flags;
23}; 27};
24 28
@@ -27,14 +31,12 @@ struct cmux_clk {
27#define CLKSEL_ADJUST BIT(0) 31#define CLKSEL_ADJUST BIT(0)
28#define to_cmux_clk(p) container_of(p, struct cmux_clk, hw) 32#define to_cmux_clk(p) container_of(p, struct cmux_clk, hw)
29 33
30static unsigned int clocks_per_pll;
31
32static int cmux_set_parent(struct clk_hw *hw, u8 idx) 34static int cmux_set_parent(struct clk_hw *hw, u8 idx)
33{ 35{
34 struct cmux_clk *clk = to_cmux_clk(hw); 36 struct cmux_clk *clk = to_cmux_clk(hw);
35 u32 clksel; 37 u32 clksel;
36 38
37 clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll; 39 clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll;
38 if (clk->flags & CLKSEL_ADJUST) 40 if (clk->flags & CLKSEL_ADJUST)
39 clksel += 8; 41 clksel += 8;
40 clksel = (clksel & 0xf) << CLKSEL_SHIFT; 42 clksel = (clksel & 0xf) << CLKSEL_SHIFT;
@@ -52,12 +54,12 @@ static u8 cmux_get_parent(struct clk_hw *hw)
52 clksel = (clksel >> CLKSEL_SHIFT) & 0xf; 54 clksel = (clksel >> CLKSEL_SHIFT) & 0xf;
53 if (clk->flags & CLKSEL_ADJUST) 55 if (clk->flags & CLKSEL_ADJUST)
54 clksel -= 8; 56 clksel -= 8;
55 clksel = (clksel >> 2) * clocks_per_pll + clksel % 4; 57 clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4;
56 58
57 return clksel; 59 return clksel;
58} 60}
59 61
60const struct clk_ops cmux_ops = { 62static const struct clk_ops cmux_ops = {
61 .get_parent = cmux_get_parent, 63 .get_parent = cmux_get_parent,
62 .set_parent = cmux_set_parent, 64 .set_parent = cmux_set_parent,
63}; 65};
@@ -72,6 +74,7 @@ static void __init core_mux_init(struct device_node *np)
72 u32 offset; 74 u32 offset;
73 const char *clk_name; 75 const char *clk_name;
74 const char **parent_names; 76 const char **parent_names;
77 struct of_phandle_args clkspec;
75 78
76 rc = of_property_read_u32(np, "reg", &offset); 79 rc = of_property_read_u32(np, "reg", &offset);
77 if (rc) { 80 if (rc) {
@@ -85,32 +88,40 @@ static void __init core_mux_init(struct device_node *np)
85 pr_err("%s: get clock count error\n", np->name); 88 pr_err("%s: get clock count error\n", np->name);
86 return; 89 return;
87 } 90 }
88 parent_names = kzalloc((sizeof(char *) * count), GFP_KERNEL); 91 parent_names = kcalloc(count, sizeof(char *), GFP_KERNEL);
89 if (!parent_names) { 92 if (!parent_names)
90 pr_err("%s: could not allocate parent_names\n", __func__);
91 return; 93 return;
92 }
93 94
94 for (i = 0; i < count; i++) 95 for (i = 0; i < count; i++)
95 parent_names[i] = of_clk_get_parent_name(np, i); 96 parent_names[i] = of_clk_get_parent_name(np, i);
96 97
97 cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL); 98 cmux_clk = kzalloc(sizeof(*cmux_clk), GFP_KERNEL);
98 if (!cmux_clk) { 99 if (!cmux_clk)
99 pr_err("%s: could not allocate cmux_clk\n", __func__);
100 goto err_name; 100 goto err_name;
101 } 101
102 cmux_clk->reg = of_iomap(np, 0); 102 cmux_clk->reg = of_iomap(np, 0);
103 if (!cmux_clk->reg) { 103 if (!cmux_clk->reg) {
104 pr_err("%s: could not map register\n", __func__); 104 pr_err("%s: could not map register\n", __func__);
105 goto err_clk; 105 goto err_clk;
106 } 106 }
107 107
108 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,
109 &clkspec);
110 if (rc) {
111 pr_err("%s: parse clock node error\n", __func__);
112 goto err_clk;
113 }
114
115 cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np,
116 "clock-output-names");
117 of_node_put(clkspec.np);
118
108 node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"); 119 node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen");
109 if (node && (offset >= 0x80)) 120 if (node && (offset >= 0x80))
110 cmux_clk->flags = CLKSEL_ADJUST; 121 cmux_clk->flags = CLKSEL_ADJUST;
111 122
112 rc = of_property_read_string_index(np, "clock-output-names", 123 rc = of_property_read_string_index(np, "clock-output-names",
113 0, &clk_name); 124 0, &clk_name);
114 if (rc) { 125 if (rc) {
115 pr_err("%s: read clock names error\n", np->name); 126 pr_err("%s: read clock names error\n", np->name);
116 goto err_clk; 127 goto err_clk;
@@ -132,7 +143,7 @@ static void __init core_mux_init(struct device_node *np)
132 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); 143 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
133 if (rc) { 144 if (rc) {
134 pr_err("Could not register clock provider for node:%s\n", 145 pr_err("Could not register clock provider for node:%s\n",
135 np->name); 146 np->name);
136 goto err_clk; 147 goto err_clk;
137 } 148 }
138 goto err_name; 149 goto err_name;
@@ -155,7 +166,7 @@ static void __init core_pll_init(struct device_node *np)
155 166
156 base = of_iomap(np, 0); 167 base = of_iomap(np, 0);
157 if (!base) { 168 if (!base) {
158 pr_err("clk-ppc: iomap error\n"); 169 pr_err("iomap error\n");
159 return; 170 return;
160 } 171 }
161 172
@@ -181,24 +192,17 @@ static void __init core_pll_init(struct device_node *np)
181 goto err_map; 192 goto err_map;
182 } 193 }
183 194
184 /* output clock number per PLL */ 195 subclks = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
185 clocks_per_pll = count; 196 if (!subclks)
186
187 subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);
188 if (!subclks) {
189 pr_err("%s: could not allocate subclks\n", __func__);
190 goto err_map; 197 goto err_map;
191 }
192 198
193 onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); 199 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
194 if (!onecell_data) { 200 if (!onecell_data)
195 pr_err("%s: could not allocate onecell_data\n", __func__);
196 goto err_clks; 201 goto err_clks;
197 }
198 202
199 for (i = 0; i < count; i++) { 203 for (i = 0; i < count; i++) {
200 rc = of_property_read_string_index(np, "clock-output-names", 204 rc = of_property_read_string_index(np, "clock-output-names",
201 i, &clk_name); 205 i, &clk_name);
202 if (rc) { 206 if (rc) {
203 pr_err("%s: could not get clock names\n", np->name); 207 pr_err("%s: could not get clock names\n", np->name);
204 goto err_cell; 208 goto err_cell;
@@ -230,7 +234,7 @@ static void __init core_pll_init(struct device_node *np)
230 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); 234 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
231 if (rc) { 235 if (rc) {
232 pr_err("Could not register clk provider for node:%s\n", 236 pr_err("Could not register clk provider for node:%s\n",
233 np->name); 237 np->name);
234 goto err_cell; 238 goto err_cell;
235 } 239 }
236 240
@@ -252,7 +256,7 @@ static void __init sysclk_init(struct device_node *node)
252 u32 rate; 256 u32 rate;
253 257
254 if (!np) { 258 if (!np) {
255 pr_err("ppc-clk: could not get parent node\n"); 259 pr_err("could not get parent node\n");
256 return; 260 return;
257 } 261 }
258 262
@@ -268,39 +272,91 @@ static void __init sysclk_init(struct device_node *node)
268 of_clk_add_provider(np, of_clk_src_simple_get, clk); 272 of_clk_add_provider(np, of_clk_src_simple_get, clk);
269} 273}
270 274
271static const struct of_device_id clk_match[] __initconst = { 275static void __init pltfrm_pll_init(struct device_node *np)
272 { .compatible = "fsl,qoriq-sysclk-1.0", .data = sysclk_init, },
273 { .compatible = "fsl,qoriq-sysclk-2.0", .data = sysclk_init, },
274 { .compatible = "fsl,qoriq-core-pll-1.0", .data = core_pll_init, },
275 { .compatible = "fsl,qoriq-core-pll-2.0", .data = core_pll_init, },
276 { .compatible = "fsl,qoriq-core-mux-1.0", .data = core_mux_init, },
277 { .compatible = "fsl,qoriq-core-mux-2.0", .data = core_mux_init, },
278 {}
279};
280
281static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
282{ 276{
283 of_clk_init(clk_match); 277 void __iomem *base;
278 uint32_t mult;
279 const char *parent_name, *clk_name;
280 int i, _errno;
281 struct clk_onecell_data *cod;
284 282
285 return 0; 283 base = of_iomap(np, 0);
286} 284 if (!base) {
285 pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
286 return;
287 }
287 288
288static const struct of_device_id ppc_clk_ids[] __initconst = { 289 /* Get the multiple of PLL */
289 { .compatible = "fsl,qoriq-clockgen-1.0", }, 290 mult = ioread32be(base);
290 { .compatible = "fsl,qoriq-clockgen-2.0", },
291 {}
292};
293 291
294static struct platform_driver ppc_corenet_clk_driver = { 292 iounmap(base);
295 .driver = {
296 .name = "ppc_corenet_clock",
297 .of_match_table = ppc_clk_ids,
298 },
299 .probe = ppc_corenet_clk_probe,
300};
301 293
302static int __init ppc_corenet_clk_init(void) 294 /* Check if this PLL is disabled */
303{ 295 if (mult & PLL_KILL) {
304 return platform_driver_register(&ppc_corenet_clk_driver); 296 pr_debug("%s(): %s: Disabled\n", __func__, np->name);
297 return;
298 }
299 mult = (mult & GENMASK(6, 1)) >> 1;
300
301 parent_name = of_clk_get_parent_name(np, 0);
302 if (!parent_name) {
303 pr_err("%s(): %s: of_clk_get_parent_name() failed\n",
304 __func__, np->name);
305 return;
306 }
307
308 i = of_property_count_strings(np, "clock-output-names");
309 if (i < 0) {
310 pr_err("%s(): %s: of_property_count_strings(clock-output-names) = %d\n",
311 __func__, np->name, i);
312 return;
313 }
314
315 cod = kmalloc(sizeof(*cod) + i * sizeof(struct clk *), GFP_KERNEL);
316 if (!cod)
317 return;
318 cod->clks = (struct clk **)(cod + 1);
319 cod->clk_num = i;
320
321 for (i = 0; i < cod->clk_num; i++) {
322 _errno = of_property_read_string_index(np, "clock-output-names",
323 i, &clk_name);
324 if (_errno < 0) {
325 pr_err("%s(): %s: of_property_read_string_index(clock-output-names) = %d\n",
326 __func__, np->name, _errno);
327 goto return_clk_unregister;
328 }
329
330 cod->clks[i] = clk_register_fixed_factor(NULL, clk_name,
331 parent_name, 0, mult, 1 + i);
332 if (IS_ERR(cod->clks[i])) {
333 pr_err("%s(): %s: clk_register_fixed_factor(%s) = %ld\n",
334 __func__, np->name,
335 clk_name, PTR_ERR(cod->clks[i]));
336 goto return_clk_unregister;
337 }
338 }
339
340 _errno = of_clk_add_provider(np, of_clk_src_onecell_get, cod);
341 if (_errno < 0) {
342 pr_err("%s(): %s: of_clk_add_provider() = %d\n",
343 __func__, np->name, _errno);
344 goto return_clk_unregister;
345 }
346
347 return;
348
349return_clk_unregister:
350 while (--i >= 0)
351 clk_unregister(cod->clks[i]);
352 kfree(cod);
305} 353}
306subsys_initcall(ppc_corenet_clk_init); 354
355CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
356CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
357CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
358CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
359CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
360CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
361CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
362CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 642cf37124d3..eb0152961d3c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -9,7 +9,7 @@
9 * Standard functionality for the common clock API. See Documentation/clk.txt 9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */ 10 */
11 11
12#include <linux/clk-private.h> 12#include <linux/clk-provider.h>
13#include <linux/clk/clk-conf.h> 13#include <linux/clk/clk-conf.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/mutex.h> 15#include <linux/mutex.h>
@@ -37,6 +37,55 @@ static HLIST_HEAD(clk_root_list);
37static HLIST_HEAD(clk_orphan_list); 37static HLIST_HEAD(clk_orphan_list);
38static LIST_HEAD(clk_notifier_list); 38static LIST_HEAD(clk_notifier_list);
39 39
40static long clk_core_get_accuracy(struct clk_core *clk);
41static unsigned long clk_core_get_rate(struct clk_core *clk);
42static int clk_core_get_phase(struct clk_core *clk);
43static bool clk_core_is_prepared(struct clk_core *clk);
44static bool clk_core_is_enabled(struct clk_core *clk);
45static struct clk_core *clk_core_lookup(const char *name);
46
47/*** private data structures ***/
48
49struct clk_core {
50 const char *name;
51 const struct clk_ops *ops;
52 struct clk_hw *hw;
53 struct module *owner;
54 struct clk_core *parent;
55 const char **parent_names;
56 struct clk_core **parents;
57 u8 num_parents;
58 u8 new_parent_index;
59 unsigned long rate;
60 unsigned long req_rate;
61 unsigned long new_rate;
62 struct clk_core *new_parent;
63 struct clk_core *new_child;
64 unsigned long flags;
65 unsigned int enable_count;
66 unsigned int prepare_count;
67 unsigned long accuracy;
68 int phase;
69 struct hlist_head children;
70 struct hlist_node child_node;
71 struct hlist_node debug_node;
72 struct hlist_head clks;
73 unsigned int notifier_count;
74#ifdef CONFIG_DEBUG_FS
75 struct dentry *dentry;
76#endif
77 struct kref ref;
78};
79
80struct clk {
81 struct clk_core *core;
82 const char *dev_id;
83 const char *con_id;
84 unsigned long min_rate;
85 unsigned long max_rate;
86 struct hlist_node child_node;
87};
88
40/*** locking ***/ 89/*** locking ***/
41static void clk_prepare_lock(void) 90static void clk_prepare_lock(void)
42{ 91{
@@ -114,7 +163,8 @@ static struct hlist_head *orphan_list[] = {
114 NULL, 163 NULL,
115}; 164};
116 165
117static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level) 166static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
167 int level)
118{ 168{
119 if (!c) 169 if (!c)
120 return; 170 return;
@@ -122,14 +172,14 @@ static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
122 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n", 172 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
123 level * 3 + 1, "", 173 level * 3 + 1, "",
124 30 - level * 3, c->name, 174 30 - level * 3, c->name,
125 c->enable_count, c->prepare_count, clk_get_rate(c), 175 c->enable_count, c->prepare_count, clk_core_get_rate(c),
126 clk_get_accuracy(c), clk_get_phase(c)); 176 clk_core_get_accuracy(c), clk_core_get_phase(c));
127} 177}
128 178
129static void clk_summary_show_subtree(struct seq_file *s, struct clk *c, 179static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
130 int level) 180 int level)
131{ 181{
132 struct clk *child; 182 struct clk_core *child;
133 183
134 if (!c) 184 if (!c)
135 return; 185 return;
@@ -142,7 +192,7 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk *c,
142 192
143static int clk_summary_show(struct seq_file *s, void *data) 193static int clk_summary_show(struct seq_file *s, void *data)
144{ 194{
145 struct clk *c; 195 struct clk_core *c;
146 struct hlist_head **lists = (struct hlist_head **)s->private; 196 struct hlist_head **lists = (struct hlist_head **)s->private;
147 197
148 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n"); 198 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
@@ -172,7 +222,7 @@ static const struct file_operations clk_summary_fops = {
172 .release = single_release, 222 .release = single_release,
173}; 223};
174 224
175static void clk_dump_one(struct seq_file *s, struct clk *c, int level) 225static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
176{ 226{
177 if (!c) 227 if (!c)
178 return; 228 return;
@@ -180,14 +230,14 @@ static void clk_dump_one(struct seq_file *s, struct clk *c, int level)
180 seq_printf(s, "\"%s\": { ", c->name); 230 seq_printf(s, "\"%s\": { ", c->name);
181 seq_printf(s, "\"enable_count\": %d,", c->enable_count); 231 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
182 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count); 232 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
183 seq_printf(s, "\"rate\": %lu", clk_get_rate(c)); 233 seq_printf(s, "\"rate\": %lu", clk_core_get_rate(c));
184 seq_printf(s, "\"accuracy\": %lu", clk_get_accuracy(c)); 234 seq_printf(s, "\"accuracy\": %lu", clk_core_get_accuracy(c));
185 seq_printf(s, "\"phase\": %d", clk_get_phase(c)); 235 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
186} 236}
187 237
188static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level) 238static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
189{ 239{
190 struct clk *child; 240 struct clk_core *child;
191 241
192 if (!c) 242 if (!c)
193 return; 243 return;
@@ -204,7 +254,7 @@ static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level)
204 254
205static int clk_dump(struct seq_file *s, void *data) 255static int clk_dump(struct seq_file *s, void *data)
206{ 256{
207 struct clk *c; 257 struct clk_core *c;
208 bool first_node = true; 258 bool first_node = true;
209 struct hlist_head **lists = (struct hlist_head **)s->private; 259 struct hlist_head **lists = (struct hlist_head **)s->private;
210 260
@@ -240,7 +290,7 @@ static const struct file_operations clk_dump_fops = {
240 .release = single_release, 290 .release = single_release,
241}; 291};
242 292
243static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry) 293static int clk_debug_create_one(struct clk_core *clk, struct dentry *pdentry)
244{ 294{
245 struct dentry *d; 295 struct dentry *d;
246 int ret = -ENOMEM; 296 int ret = -ENOMEM;
@@ -315,7 +365,7 @@ out:
315 * initialized. Otherwise it bails out early since the debugfs clk tree 365 * initialized. Otherwise it bails out early since the debugfs clk tree
316 * will be created lazily by clk_debug_init as part of a late_initcall. 366 * will be created lazily by clk_debug_init as part of a late_initcall.
317 */ 367 */
318static int clk_debug_register(struct clk *clk) 368static int clk_debug_register(struct clk_core *clk)
319{ 369{
320 int ret = 0; 370 int ret = 0;
321 371
@@ -340,16 +390,12 @@ unlock:
340 * debugfs clk tree if clk->dentry points to debugfs created by 390 * debugfs clk tree if clk->dentry points to debugfs created by
341 * clk_debug_register in __clk_init. 391 * clk_debug_register in __clk_init.
342 */ 392 */
343static void clk_debug_unregister(struct clk *clk) 393static void clk_debug_unregister(struct clk_core *clk)
344{ 394{
345 mutex_lock(&clk_debug_lock); 395 mutex_lock(&clk_debug_lock);
346 if (!clk->dentry)
347 goto out;
348
349 hlist_del_init(&clk->debug_node); 396 hlist_del_init(&clk->debug_node);
350 debugfs_remove_recursive(clk->dentry); 397 debugfs_remove_recursive(clk->dentry);
351 clk->dentry = NULL; 398 clk->dentry = NULL;
352out:
353 mutex_unlock(&clk_debug_lock); 399 mutex_unlock(&clk_debug_lock);
354} 400}
355 401
@@ -358,8 +404,9 @@ struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
358{ 404{
359 struct dentry *d = NULL; 405 struct dentry *d = NULL;
360 406
361 if (hw->clk->dentry) 407 if (hw->core->dentry)
362 d = debugfs_create_file(name, mode, hw->clk->dentry, data, fops); 408 d = debugfs_create_file(name, mode, hw->core->dentry, data,
409 fops);
363 410
364 return d; 411 return d;
365} 412}
@@ -379,7 +426,7 @@ EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
379 */ 426 */
380static int __init clk_debug_init(void) 427static int __init clk_debug_init(void)
381{ 428{
382 struct clk *clk; 429 struct clk_core *clk;
383 struct dentry *d; 430 struct dentry *d;
384 431
385 rootdir = debugfs_create_dir("clk", NULL); 432 rootdir = debugfs_create_dir("clk", NULL);
@@ -418,22 +465,20 @@ static int __init clk_debug_init(void)
418} 465}
419late_initcall(clk_debug_init); 466late_initcall(clk_debug_init);
420#else 467#else
421static inline int clk_debug_register(struct clk *clk) { return 0; } 468static inline int clk_debug_register(struct clk_core *clk) { return 0; }
422static inline void clk_debug_reparent(struct clk *clk, struct clk *new_parent) 469static inline void clk_debug_reparent(struct clk_core *clk,
470 struct clk_core *new_parent)
423{ 471{
424} 472}
425static inline void clk_debug_unregister(struct clk *clk) 473static inline void clk_debug_unregister(struct clk_core *clk)
426{ 474{
427} 475}
428#endif 476#endif
429 477
430/* caller must hold prepare_lock */ 478/* caller must hold prepare_lock */
431static void clk_unprepare_unused_subtree(struct clk *clk) 479static void clk_unprepare_unused_subtree(struct clk_core *clk)
432{ 480{
433 struct clk *child; 481 struct clk_core *child;
434
435 if (!clk)
436 return;
437 482
438 hlist_for_each_entry(child, &clk->children, child_node) 483 hlist_for_each_entry(child, &clk->children, child_node)
439 clk_unprepare_unused_subtree(child); 484 clk_unprepare_unused_subtree(child);
@@ -444,7 +489,7 @@ static void clk_unprepare_unused_subtree(struct clk *clk)
444 if (clk->flags & CLK_IGNORE_UNUSED) 489 if (clk->flags & CLK_IGNORE_UNUSED)
445 return; 490 return;
446 491
447 if (__clk_is_prepared(clk)) { 492 if (clk_core_is_prepared(clk)) {
448 if (clk->ops->unprepare_unused) 493 if (clk->ops->unprepare_unused)
449 clk->ops->unprepare_unused(clk->hw); 494 clk->ops->unprepare_unused(clk->hw);
450 else if (clk->ops->unprepare) 495 else if (clk->ops->unprepare)
@@ -453,14 +498,11 @@ static void clk_unprepare_unused_subtree(struct clk *clk)
453} 498}
454 499
455/* caller must hold prepare_lock */ 500/* caller must hold prepare_lock */
456static void clk_disable_unused_subtree(struct clk *clk) 501static void clk_disable_unused_subtree(struct clk_core *clk)
457{ 502{
458 struct clk *child; 503 struct clk_core *child;
459 unsigned long flags; 504 unsigned long flags;
460 505
461 if (!clk)
462 goto out;
463
464 hlist_for_each_entry(child, &clk->children, child_node) 506 hlist_for_each_entry(child, &clk->children, child_node)
465 clk_disable_unused_subtree(child); 507 clk_disable_unused_subtree(child);
466 508
@@ -477,7 +519,7 @@ static void clk_disable_unused_subtree(struct clk *clk)
477 * sequence. call .disable_unused if available, otherwise fall 519 * sequence. call .disable_unused if available, otherwise fall
478 * back to .disable 520 * back to .disable
479 */ 521 */
480 if (__clk_is_enabled(clk)) { 522 if (clk_core_is_enabled(clk)) {
481 if (clk->ops->disable_unused) 523 if (clk->ops->disable_unused)
482 clk->ops->disable_unused(clk->hw); 524 clk->ops->disable_unused(clk->hw);
483 else if (clk->ops->disable) 525 else if (clk->ops->disable)
@@ -486,9 +528,6 @@ static void clk_disable_unused_subtree(struct clk *clk)
486 528
487unlock_out: 529unlock_out:
488 clk_enable_unlock(flags); 530 clk_enable_unlock(flags);
489
490out:
491 return;
492} 531}
493 532
494static bool clk_ignore_unused; 533static bool clk_ignore_unused;
@@ -501,7 +540,7 @@ __setup("clk_ignore_unused", clk_ignore_unused_setup);
501 540
502static int clk_disable_unused(void) 541static int clk_disable_unused(void)
503{ 542{
504 struct clk *clk; 543 struct clk_core *clk;
505 544
506 if (clk_ignore_unused) { 545 if (clk_ignore_unused) {
507 pr_warn("clk: Not disabling unused clocks\n"); 546 pr_warn("clk: Not disabling unused clocks\n");
@@ -532,48 +571,65 @@ late_initcall_sync(clk_disable_unused);
532 571
533const char *__clk_get_name(struct clk *clk) 572const char *__clk_get_name(struct clk *clk)
534{ 573{
535 return !clk ? NULL : clk->name; 574 return !clk ? NULL : clk->core->name;
536} 575}
537EXPORT_SYMBOL_GPL(__clk_get_name); 576EXPORT_SYMBOL_GPL(__clk_get_name);
538 577
539struct clk_hw *__clk_get_hw(struct clk *clk) 578struct clk_hw *__clk_get_hw(struct clk *clk)
540{ 579{
541 return !clk ? NULL : clk->hw; 580 return !clk ? NULL : clk->core->hw;
542} 581}
543EXPORT_SYMBOL_GPL(__clk_get_hw); 582EXPORT_SYMBOL_GPL(__clk_get_hw);
544 583
545u8 __clk_get_num_parents(struct clk *clk) 584u8 __clk_get_num_parents(struct clk *clk)
546{ 585{
547 return !clk ? 0 : clk->num_parents; 586 return !clk ? 0 : clk->core->num_parents;
548} 587}
549EXPORT_SYMBOL_GPL(__clk_get_num_parents); 588EXPORT_SYMBOL_GPL(__clk_get_num_parents);
550 589
551struct clk *__clk_get_parent(struct clk *clk) 590struct clk *__clk_get_parent(struct clk *clk)
552{ 591{
553 return !clk ? NULL : clk->parent; 592 if (!clk)
593 return NULL;
594
595 /* TODO: Create a per-user clk and change callers to call clk_put */
596 return !clk->core->parent ? NULL : clk->core->parent->hw->clk;
554} 597}
555EXPORT_SYMBOL_GPL(__clk_get_parent); 598EXPORT_SYMBOL_GPL(__clk_get_parent);
556 599
557struct clk *clk_get_parent_by_index(struct clk *clk, u8 index) 600static struct clk_core *clk_core_get_parent_by_index(struct clk_core *clk,
601 u8 index)
558{ 602{
559 if (!clk || index >= clk->num_parents) 603 if (!clk || index >= clk->num_parents)
560 return NULL; 604 return NULL;
561 else if (!clk->parents) 605 else if (!clk->parents)
562 return __clk_lookup(clk->parent_names[index]); 606 return clk_core_lookup(clk->parent_names[index]);
563 else if (!clk->parents[index]) 607 else if (!clk->parents[index])
564 return clk->parents[index] = 608 return clk->parents[index] =
565 __clk_lookup(clk->parent_names[index]); 609 clk_core_lookup(clk->parent_names[index]);
566 else 610 else
567 return clk->parents[index]; 611 return clk->parents[index];
568} 612}
613
614struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
615{
616 struct clk_core *parent;
617
618 if (!clk)
619 return NULL;
620
621 parent = clk_core_get_parent_by_index(clk->core, index);
622
623 return !parent ? NULL : parent->hw->clk;
624}
569EXPORT_SYMBOL_GPL(clk_get_parent_by_index); 625EXPORT_SYMBOL_GPL(clk_get_parent_by_index);
570 626
571unsigned int __clk_get_enable_count(struct clk *clk) 627unsigned int __clk_get_enable_count(struct clk *clk)
572{ 628{
573 return !clk ? 0 : clk->enable_count; 629 return !clk ? 0 : clk->core->enable_count;
574} 630}
575 631
576unsigned long __clk_get_rate(struct clk *clk) 632static unsigned long clk_core_get_rate_nolock(struct clk_core *clk)
577{ 633{
578 unsigned long ret; 634 unsigned long ret;
579 635
@@ -593,9 +649,17 @@ unsigned long __clk_get_rate(struct clk *clk)
593out: 649out:
594 return ret; 650 return ret;
595} 651}
652
653unsigned long __clk_get_rate(struct clk *clk)
654{
655 if (!clk)
656 return 0;
657
658 return clk_core_get_rate_nolock(clk->core);
659}
596EXPORT_SYMBOL_GPL(__clk_get_rate); 660EXPORT_SYMBOL_GPL(__clk_get_rate);
597 661
598static unsigned long __clk_get_accuracy(struct clk *clk) 662static unsigned long __clk_get_accuracy(struct clk_core *clk)
599{ 663{
600 if (!clk) 664 if (!clk)
601 return 0; 665 return 0;
@@ -605,11 +669,11 @@ static unsigned long __clk_get_accuracy(struct clk *clk)
605 669
606unsigned long __clk_get_flags(struct clk *clk) 670unsigned long __clk_get_flags(struct clk *clk)
607{ 671{
608 return !clk ? 0 : clk->flags; 672 return !clk ? 0 : clk->core->flags;
609} 673}
610EXPORT_SYMBOL_GPL(__clk_get_flags); 674EXPORT_SYMBOL_GPL(__clk_get_flags);
611 675
612bool __clk_is_prepared(struct clk *clk) 676static bool clk_core_is_prepared(struct clk_core *clk)
613{ 677{
614 int ret; 678 int ret;
615 679
@@ -630,7 +694,15 @@ out:
630 return !!ret; 694 return !!ret;
631} 695}
632 696
633bool __clk_is_enabled(struct clk *clk) 697bool __clk_is_prepared(struct clk *clk)
698{
699 if (!clk)
700 return false;
701
702 return clk_core_is_prepared(clk->core);
703}
704
705static bool clk_core_is_enabled(struct clk_core *clk)
634{ 706{
635 int ret; 707 int ret;
636 708
@@ -650,12 +722,21 @@ bool __clk_is_enabled(struct clk *clk)
650out: 722out:
651 return !!ret; 723 return !!ret;
652} 724}
725
726bool __clk_is_enabled(struct clk *clk)
727{
728 if (!clk)
729 return false;
730
731 return clk_core_is_enabled(clk->core);
732}
653EXPORT_SYMBOL_GPL(__clk_is_enabled); 733EXPORT_SYMBOL_GPL(__clk_is_enabled);
654 734
655static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk) 735static struct clk_core *__clk_lookup_subtree(const char *name,
736 struct clk_core *clk)
656{ 737{
657 struct clk *child; 738 struct clk_core *child;
658 struct clk *ret; 739 struct clk_core *ret;
659 740
660 if (!strcmp(clk->name, name)) 741 if (!strcmp(clk->name, name))
661 return clk; 742 return clk;
@@ -669,10 +750,10 @@ static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
669 return NULL; 750 return NULL;
670} 751}
671 752
672struct clk *__clk_lookup(const char *name) 753static struct clk_core *clk_core_lookup(const char *name)
673{ 754{
674 struct clk *root_clk; 755 struct clk_core *root_clk;
675 struct clk *ret; 756 struct clk_core *ret;
676 757
677 if (!name) 758 if (!name)
678 return NULL; 759 return NULL;
@@ -694,42 +775,53 @@ struct clk *__clk_lookup(const char *name)
694 return NULL; 775 return NULL;
695} 776}
696 777
697/* 778static bool mux_is_better_rate(unsigned long rate, unsigned long now,
698 * Helper for finding best parent to provide a given frequency. This can be used 779 unsigned long best, unsigned long flags)
699 * directly as a determine_rate callback (e.g. for a mux), or from a more
700 * complex clock that may combine a mux with other operations.
701 */
702long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
703 unsigned long *best_parent_rate,
704 struct clk_hw **best_parent_p)
705{ 780{
706 struct clk *clk = hw->clk, *parent, *best_parent = NULL; 781 if (flags & CLK_MUX_ROUND_CLOSEST)
782 return abs(now - rate) < abs(best - rate);
783
784 return now <= rate && now > best;
785}
786
787static long
788clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
789 unsigned long min_rate,
790 unsigned long max_rate,
791 unsigned long *best_parent_rate,
792 struct clk_hw **best_parent_p,
793 unsigned long flags)
794{
795 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
707 int i, num_parents; 796 int i, num_parents;
708 unsigned long parent_rate, best = 0; 797 unsigned long parent_rate, best = 0;
709 798
710 /* if NO_REPARENT flag set, pass through to current parent */ 799 /* if NO_REPARENT flag set, pass through to current parent */
711 if (clk->flags & CLK_SET_RATE_NO_REPARENT) { 800 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
712 parent = clk->parent; 801 parent = core->parent;
713 if (clk->flags & CLK_SET_RATE_PARENT) 802 if (core->flags & CLK_SET_RATE_PARENT)
714 best = __clk_round_rate(parent, rate); 803 best = __clk_determine_rate(parent ? parent->hw : NULL,
804 rate, min_rate, max_rate);
715 else if (parent) 805 else if (parent)
716 best = __clk_get_rate(parent); 806 best = clk_core_get_rate_nolock(parent);
717 else 807 else
718 best = __clk_get_rate(clk); 808 best = clk_core_get_rate_nolock(core);
719 goto out; 809 goto out;
720 } 810 }
721 811
722 /* find the parent that can provide the fastest rate <= rate */ 812 /* find the parent that can provide the fastest rate <= rate */
723 num_parents = clk->num_parents; 813 num_parents = core->num_parents;
724 for (i = 0; i < num_parents; i++) { 814 for (i = 0; i < num_parents; i++) {
725 parent = clk_get_parent_by_index(clk, i); 815 parent = clk_core_get_parent_by_index(core, i);
726 if (!parent) 816 if (!parent)
727 continue; 817 continue;
728 if (clk->flags & CLK_SET_RATE_PARENT) 818 if (core->flags & CLK_SET_RATE_PARENT)
729 parent_rate = __clk_round_rate(parent, rate); 819 parent_rate = __clk_determine_rate(parent->hw, rate,
820 min_rate,
821 max_rate);
730 else 822 else
731 parent_rate = __clk_get_rate(parent); 823 parent_rate = clk_core_get_rate_nolock(parent);
732 if (parent_rate <= rate && parent_rate > best) { 824 if (mux_is_better_rate(rate, parent_rate, best, flags)) {
733 best_parent = parent; 825 best_parent = parent;
734 best = parent_rate; 826 best = parent_rate;
735 } 827 }
@@ -742,11 +834,63 @@ out:
742 834
743 return best; 835 return best;
744} 836}
837
838struct clk *__clk_lookup(const char *name)
839{
840 struct clk_core *core = clk_core_lookup(name);
841
842 return !core ? NULL : core->hw->clk;
843}
844
845static void clk_core_get_boundaries(struct clk_core *clk,
846 unsigned long *min_rate,
847 unsigned long *max_rate)
848{
849 struct clk *clk_user;
850
851 *min_rate = 0;
852 *max_rate = ULONG_MAX;
853
854 hlist_for_each_entry(clk_user, &clk->clks, child_node)
855 *min_rate = max(*min_rate, clk_user->min_rate);
856
857 hlist_for_each_entry(clk_user, &clk->clks, child_node)
858 *max_rate = min(*max_rate, clk_user->max_rate);
859}
860
861/*
862 * Helper for finding best parent to provide a given frequency. This can be used
863 * directly as a determine_rate callback (e.g. for a mux), or from a more
864 * complex clock that may combine a mux with other operations.
865 */
866long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
867 unsigned long min_rate,
868 unsigned long max_rate,
869 unsigned long *best_parent_rate,
870 struct clk_hw **best_parent_p)
871{
872 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
873 best_parent_rate,
874 best_parent_p, 0);
875}
745EXPORT_SYMBOL_GPL(__clk_mux_determine_rate); 876EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
746 877
878long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
879 unsigned long min_rate,
880 unsigned long max_rate,
881 unsigned long *best_parent_rate,
882 struct clk_hw **best_parent_p)
883{
884 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
885 best_parent_rate,
886 best_parent_p,
887 CLK_MUX_ROUND_CLOSEST);
888}
889EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
890
747/*** clk api ***/ 891/*** clk api ***/
748 892
749void __clk_unprepare(struct clk *clk) 893static void clk_core_unprepare(struct clk_core *clk)
750{ 894{
751 if (!clk) 895 if (!clk)
752 return; 896 return;
@@ -762,7 +906,7 @@ void __clk_unprepare(struct clk *clk)
762 if (clk->ops->unprepare) 906 if (clk->ops->unprepare)
763 clk->ops->unprepare(clk->hw); 907 clk->ops->unprepare(clk->hw);
764 908
765 __clk_unprepare(clk->parent); 909 clk_core_unprepare(clk->parent);
766} 910}
767 911
768/** 912/**
@@ -782,12 +926,12 @@ void clk_unprepare(struct clk *clk)
782 return; 926 return;
783 927
784 clk_prepare_lock(); 928 clk_prepare_lock();
785 __clk_unprepare(clk); 929 clk_core_unprepare(clk->core);
786 clk_prepare_unlock(); 930 clk_prepare_unlock();
787} 931}
788EXPORT_SYMBOL_GPL(clk_unprepare); 932EXPORT_SYMBOL_GPL(clk_unprepare);
789 933
790int __clk_prepare(struct clk *clk) 934static int clk_core_prepare(struct clk_core *clk)
791{ 935{
792 int ret = 0; 936 int ret = 0;
793 937
@@ -795,14 +939,14 @@ int __clk_prepare(struct clk *clk)
795 return 0; 939 return 0;
796 940
797 if (clk->prepare_count == 0) { 941 if (clk->prepare_count == 0) {
798 ret = __clk_prepare(clk->parent); 942 ret = clk_core_prepare(clk->parent);
799 if (ret) 943 if (ret)
800 return ret; 944 return ret;
801 945
802 if (clk->ops->prepare) { 946 if (clk->ops->prepare) {
803 ret = clk->ops->prepare(clk->hw); 947 ret = clk->ops->prepare(clk->hw);
804 if (ret) { 948 if (ret) {
805 __clk_unprepare(clk->parent); 949 clk_core_unprepare(clk->parent);
806 return ret; 950 return ret;
807 } 951 }
808 } 952 }
@@ -829,15 +973,18 @@ int clk_prepare(struct clk *clk)
829{ 973{
830 int ret; 974 int ret;
831 975
976 if (!clk)
977 return 0;
978
832 clk_prepare_lock(); 979 clk_prepare_lock();
833 ret = __clk_prepare(clk); 980 ret = clk_core_prepare(clk->core);
834 clk_prepare_unlock(); 981 clk_prepare_unlock();
835 982
836 return ret; 983 return ret;
837} 984}
838EXPORT_SYMBOL_GPL(clk_prepare); 985EXPORT_SYMBOL_GPL(clk_prepare);
839 986
840static void __clk_disable(struct clk *clk) 987static void clk_core_disable(struct clk_core *clk)
841{ 988{
842 if (!clk) 989 if (!clk)
843 return; 990 return;
@@ -851,7 +998,15 @@ static void __clk_disable(struct clk *clk)
851 if (clk->ops->disable) 998 if (clk->ops->disable)
852 clk->ops->disable(clk->hw); 999 clk->ops->disable(clk->hw);
853 1000
854 __clk_disable(clk->parent); 1001 clk_core_disable(clk->parent);
1002}
1003
1004static void __clk_disable(struct clk *clk)
1005{
1006 if (!clk)
1007 return;
1008
1009 clk_core_disable(clk->core);
855} 1010}
856 1011
857/** 1012/**
@@ -879,7 +1034,7 @@ void clk_disable(struct clk *clk)
879} 1034}
880EXPORT_SYMBOL_GPL(clk_disable); 1035EXPORT_SYMBOL_GPL(clk_disable);
881 1036
882static int __clk_enable(struct clk *clk) 1037static int clk_core_enable(struct clk_core *clk)
883{ 1038{
884 int ret = 0; 1039 int ret = 0;
885 1040
@@ -890,7 +1045,7 @@ static int __clk_enable(struct clk *clk)
890 return -ESHUTDOWN; 1045 return -ESHUTDOWN;
891 1046
892 if (clk->enable_count == 0) { 1047 if (clk->enable_count == 0) {
893 ret = __clk_enable(clk->parent); 1048 ret = clk_core_enable(clk->parent);
894 1049
895 if (ret) 1050 if (ret)
896 return ret; 1051 return ret;
@@ -898,7 +1053,7 @@ static int __clk_enable(struct clk *clk)
898 if (clk->ops->enable) { 1053 if (clk->ops->enable) {
899 ret = clk->ops->enable(clk->hw); 1054 ret = clk->ops->enable(clk->hw);
900 if (ret) { 1055 if (ret) {
901 __clk_disable(clk->parent); 1056 clk_core_disable(clk->parent);
902 return ret; 1057 return ret;
903 } 1058 }
904 } 1059 }
@@ -908,6 +1063,14 @@ static int __clk_enable(struct clk *clk)
908 return 0; 1063 return 0;
909} 1064}
910 1065
1066static int __clk_enable(struct clk *clk)
1067{
1068 if (!clk)
1069 return 0;
1070
1071 return clk_core_enable(clk->core);
1072}
1073
911/** 1074/**
912 * clk_enable - ungate a clock 1075 * clk_enable - ungate a clock
913 * @clk: the clk being ungated 1076 * @clk: the clk being ungated
@@ -934,17 +1097,13 @@ int clk_enable(struct clk *clk)
934} 1097}
935EXPORT_SYMBOL_GPL(clk_enable); 1098EXPORT_SYMBOL_GPL(clk_enable);
936 1099
937/** 1100static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
938 * __clk_round_rate - round the given rate for a clk 1101 unsigned long rate,
939 * @clk: round the rate of this clock 1102 unsigned long min_rate,
940 * @rate: the rate which is to be rounded 1103 unsigned long max_rate)
941 *
942 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate
943 */
944unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
945{ 1104{
946 unsigned long parent_rate = 0; 1105 unsigned long parent_rate = 0;
947 struct clk *parent; 1106 struct clk_core *parent;
948 struct clk_hw *parent_hw; 1107 struct clk_hw *parent_hw;
949 1108
950 if (!clk) 1109 if (!clk)
@@ -956,15 +1115,59 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
956 1115
957 if (clk->ops->determine_rate) { 1116 if (clk->ops->determine_rate) {
958 parent_hw = parent ? parent->hw : NULL; 1117 parent_hw = parent ? parent->hw : NULL;
959 return clk->ops->determine_rate(clk->hw, rate, &parent_rate, 1118 return clk->ops->determine_rate(clk->hw, rate,
960 &parent_hw); 1119 min_rate, max_rate,
1120 &parent_rate, &parent_hw);
961 } else if (clk->ops->round_rate) 1121 } else if (clk->ops->round_rate)
962 return clk->ops->round_rate(clk->hw, rate, &parent_rate); 1122 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
963 else if (clk->flags & CLK_SET_RATE_PARENT) 1123 else if (clk->flags & CLK_SET_RATE_PARENT)
964 return __clk_round_rate(clk->parent, rate); 1124 return clk_core_round_rate_nolock(clk->parent, rate, min_rate,
1125 max_rate);
965 else 1126 else
966 return clk->rate; 1127 return clk->rate;
967} 1128}
1129
1130/**
1131 * __clk_determine_rate - get the closest rate actually supported by a clock
1132 * @hw: determine the rate of this clock
1133 * @rate: target rate
1134 * @min_rate: returned rate must be greater than this rate
1135 * @max_rate: returned rate must be less than this rate
1136 *
1137 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate and
1138 * .determine_rate.
1139 */
1140unsigned long __clk_determine_rate(struct clk_hw *hw,
1141 unsigned long rate,
1142 unsigned long min_rate,
1143 unsigned long max_rate)
1144{
1145 if (!hw)
1146 return 0;
1147
1148 return clk_core_round_rate_nolock(hw->core, rate, min_rate, max_rate);
1149}
1150EXPORT_SYMBOL_GPL(__clk_determine_rate);
1151
1152/**
1153 * __clk_round_rate - round the given rate for a clk
1154 * @clk: round the rate of this clock
1155 * @rate: the rate which is to be rounded
1156 *
1157 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate
1158 */
1159unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
1160{
1161 unsigned long min_rate;
1162 unsigned long max_rate;
1163
1164 if (!clk)
1165 return 0;
1166
1167 clk_core_get_boundaries(clk->core, &min_rate, &max_rate);
1168
1169 return clk_core_round_rate_nolock(clk->core, rate, min_rate, max_rate);
1170}
968EXPORT_SYMBOL_GPL(__clk_round_rate); 1171EXPORT_SYMBOL_GPL(__clk_round_rate);
969 1172
970/** 1173/**
@@ -980,6 +1183,9 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
980{ 1183{
981 unsigned long ret; 1184 unsigned long ret;
982 1185
1186 if (!clk)
1187 return 0;
1188
983 clk_prepare_lock(); 1189 clk_prepare_lock();
984 ret = __clk_round_rate(clk, rate); 1190 ret = __clk_round_rate(clk, rate);
985 clk_prepare_unlock(); 1191 clk_prepare_unlock();
@@ -1002,22 +1208,21 @@ EXPORT_SYMBOL_GPL(clk_round_rate);
1002 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if 1208 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
1003 * a driver returns that. 1209 * a driver returns that.
1004 */ 1210 */
1005static int __clk_notify(struct clk *clk, unsigned long msg, 1211static int __clk_notify(struct clk_core *clk, unsigned long msg,
1006 unsigned long old_rate, unsigned long new_rate) 1212 unsigned long old_rate, unsigned long new_rate)
1007{ 1213{
1008 struct clk_notifier *cn; 1214 struct clk_notifier *cn;
1009 struct clk_notifier_data cnd; 1215 struct clk_notifier_data cnd;
1010 int ret = NOTIFY_DONE; 1216 int ret = NOTIFY_DONE;
1011 1217
1012 cnd.clk = clk;
1013 cnd.old_rate = old_rate; 1218 cnd.old_rate = old_rate;
1014 cnd.new_rate = new_rate; 1219 cnd.new_rate = new_rate;
1015 1220
1016 list_for_each_entry(cn, &clk_notifier_list, node) { 1221 list_for_each_entry(cn, &clk_notifier_list, node) {
1017 if (cn->clk == clk) { 1222 if (cn->clk->core == clk) {
1223 cnd.clk = cn->clk;
1018 ret = srcu_notifier_call_chain(&cn->notifier_head, msg, 1224 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
1019 &cnd); 1225 &cnd);
1020 break;
1021 } 1226 }
1022 } 1227 }
1023 1228
@@ -1035,10 +1240,10 @@ static int __clk_notify(struct clk *clk, unsigned long msg,
1035 * 1240 *
1036 * Caller must hold prepare_lock. 1241 * Caller must hold prepare_lock.
1037 */ 1242 */
1038static void __clk_recalc_accuracies(struct clk *clk) 1243static void __clk_recalc_accuracies(struct clk_core *clk)
1039{ 1244{
1040 unsigned long parent_accuracy = 0; 1245 unsigned long parent_accuracy = 0;
1041 struct clk *child; 1246 struct clk_core *child;
1042 1247
1043 if (clk->parent) 1248 if (clk->parent)
1044 parent_accuracy = clk->parent->accuracy; 1249 parent_accuracy = clk->parent->accuracy;
@@ -1053,6 +1258,20 @@ static void __clk_recalc_accuracies(struct clk *clk)
1053 __clk_recalc_accuracies(child); 1258 __clk_recalc_accuracies(child);
1054} 1259}
1055 1260
1261static long clk_core_get_accuracy(struct clk_core *clk)
1262{
1263 unsigned long accuracy;
1264
1265 clk_prepare_lock();
1266 if (clk && (clk->flags & CLK_GET_ACCURACY_NOCACHE))
1267 __clk_recalc_accuracies(clk);
1268
1269 accuracy = __clk_get_accuracy(clk);
1270 clk_prepare_unlock();
1271
1272 return accuracy;
1273}
1274
1056/** 1275/**
1057 * clk_get_accuracy - return the accuracy of clk 1276 * clk_get_accuracy - return the accuracy of clk
1058 * @clk: the clk whose accuracy is being returned 1277 * @clk: the clk whose accuracy is being returned
@@ -1064,20 +1283,15 @@ static void __clk_recalc_accuracies(struct clk *clk)
1064 */ 1283 */
1065long clk_get_accuracy(struct clk *clk) 1284long clk_get_accuracy(struct clk *clk)
1066{ 1285{
1067 unsigned long accuracy; 1286 if (!clk)
1068 1287 return 0;
1069 clk_prepare_lock();
1070 if (clk && (clk->flags & CLK_GET_ACCURACY_NOCACHE))
1071 __clk_recalc_accuracies(clk);
1072
1073 accuracy = __clk_get_accuracy(clk);
1074 clk_prepare_unlock();
1075 1288
1076 return accuracy; 1289 return clk_core_get_accuracy(clk->core);
1077} 1290}
1078EXPORT_SYMBOL_GPL(clk_get_accuracy); 1291EXPORT_SYMBOL_GPL(clk_get_accuracy);
1079 1292
1080static unsigned long clk_recalc(struct clk *clk, unsigned long parent_rate) 1293static unsigned long clk_recalc(struct clk_core *clk,
1294 unsigned long parent_rate)
1081{ 1295{
1082 if (clk->ops->recalc_rate) 1296 if (clk->ops->recalc_rate)
1083 return clk->ops->recalc_rate(clk->hw, parent_rate); 1297 return clk->ops->recalc_rate(clk->hw, parent_rate);
@@ -1098,11 +1312,11 @@ static unsigned long clk_recalc(struct clk *clk, unsigned long parent_rate)
1098 * 1312 *
1099 * Caller must hold prepare_lock. 1313 * Caller must hold prepare_lock.
1100 */ 1314 */
1101static void __clk_recalc_rates(struct clk *clk, unsigned long msg) 1315static void __clk_recalc_rates(struct clk_core *clk, unsigned long msg)
1102{ 1316{
1103 unsigned long old_rate; 1317 unsigned long old_rate;
1104 unsigned long parent_rate = 0; 1318 unsigned long parent_rate = 0;
1105 struct clk *child; 1319 struct clk_core *child;
1106 1320
1107 old_rate = clk->rate; 1321 old_rate = clk->rate;
1108 1322
@@ -1122,15 +1336,7 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
1122 __clk_recalc_rates(child, msg); 1336 __clk_recalc_rates(child, msg);
1123} 1337}
1124 1338
1125/** 1339static unsigned long clk_core_get_rate(struct clk_core *clk)
1126 * clk_get_rate - return the rate of clk
1127 * @clk: the clk whose rate is being returned
1128 *
1129 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1130 * is set, which means a recalc_rate will be issued.
1131 * If clk is NULL then returns 0.
1132 */
1133unsigned long clk_get_rate(struct clk *clk)
1134{ 1340{
1135 unsigned long rate; 1341 unsigned long rate;
1136 1342
@@ -1139,14 +1345,32 @@ unsigned long clk_get_rate(struct clk *clk)
1139 if (clk && (clk->flags & CLK_GET_RATE_NOCACHE)) 1345 if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
1140 __clk_recalc_rates(clk, 0); 1346 __clk_recalc_rates(clk, 0);
1141 1347
1142 rate = __clk_get_rate(clk); 1348 rate = clk_core_get_rate_nolock(clk);
1143 clk_prepare_unlock(); 1349 clk_prepare_unlock();
1144 1350
1145 return rate; 1351 return rate;
1146} 1352}
1353EXPORT_SYMBOL_GPL(clk_core_get_rate);
1354
1355/**
1356 * clk_get_rate - return the rate of clk
1357 * @clk: the clk whose rate is being returned
1358 *
1359 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1360 * is set, which means a recalc_rate will be issued.
1361 * If clk is NULL then returns 0.
1362 */
1363unsigned long clk_get_rate(struct clk *clk)
1364{
1365 if (!clk)
1366 return 0;
1367
1368 return clk_core_get_rate(clk->core);
1369}
1147EXPORT_SYMBOL_GPL(clk_get_rate); 1370EXPORT_SYMBOL_GPL(clk_get_rate);
1148 1371
1149static int clk_fetch_parent_index(struct clk *clk, struct clk *parent) 1372static int clk_fetch_parent_index(struct clk_core *clk,
1373 struct clk_core *parent)
1150{ 1374{
1151 int i; 1375 int i;
1152 1376
@@ -1160,7 +1384,7 @@ static int clk_fetch_parent_index(struct clk *clk, struct clk *parent)
1160 /* 1384 /*
1161 * find index of new parent clock using cached parent ptrs, 1385 * find index of new parent clock using cached parent ptrs,
1162 * or if not yet cached, use string name comparison and cache 1386 * or if not yet cached, use string name comparison and cache
1163 * them now to avoid future calls to __clk_lookup. 1387 * them now to avoid future calls to clk_core_lookup.
1164 */ 1388 */
1165 for (i = 0; i < clk->num_parents; i++) { 1389 for (i = 0; i < clk->num_parents; i++) {
1166 if (clk->parents[i] == parent) 1390 if (clk->parents[i] == parent)
@@ -1170,7 +1394,7 @@ static int clk_fetch_parent_index(struct clk *clk, struct clk *parent)
1170 continue; 1394 continue;
1171 1395
1172 if (!strcmp(clk->parent_names[i], parent->name)) { 1396 if (!strcmp(clk->parent_names[i], parent->name)) {
1173 clk->parents[i] = __clk_lookup(parent->name); 1397 clk->parents[i] = clk_core_lookup(parent->name);
1174 return i; 1398 return i;
1175 } 1399 }
1176 } 1400 }
@@ -1178,7 +1402,7 @@ static int clk_fetch_parent_index(struct clk *clk, struct clk *parent)
1178 return -EINVAL; 1402 return -EINVAL;
1179} 1403}
1180 1404
1181static void clk_reparent(struct clk *clk, struct clk *new_parent) 1405static void clk_reparent(struct clk_core *clk, struct clk_core *new_parent)
1182{ 1406{
1183 hlist_del(&clk->child_node); 1407 hlist_del(&clk->child_node);
1184 1408
@@ -1195,10 +1419,11 @@ static void clk_reparent(struct clk *clk, struct clk *new_parent)
1195 clk->parent = new_parent; 1419 clk->parent = new_parent;
1196} 1420}
1197 1421
1198static struct clk *__clk_set_parent_before(struct clk *clk, struct clk *parent) 1422static struct clk_core *__clk_set_parent_before(struct clk_core *clk,
1423 struct clk_core *parent)
1199{ 1424{
1200 unsigned long flags; 1425 unsigned long flags;
1201 struct clk *old_parent = clk->parent; 1426 struct clk_core *old_parent = clk->parent;
1202 1427
1203 /* 1428 /*
1204 * Migrate prepare state between parents and prevent race with 1429 * Migrate prepare state between parents and prevent race with
@@ -1218,9 +1443,9 @@ static struct clk *__clk_set_parent_before(struct clk *clk, struct clk *parent)
1218 * See also: Comment for clk_set_parent() below. 1443 * See also: Comment for clk_set_parent() below.
1219 */ 1444 */
1220 if (clk->prepare_count) { 1445 if (clk->prepare_count) {
1221 __clk_prepare(parent); 1446 clk_core_prepare(parent);
1222 clk_enable(parent); 1447 clk_core_enable(parent);
1223 clk_enable(clk); 1448 clk_core_enable(clk);
1224 } 1449 }
1225 1450
1226 /* update the clk tree topology */ 1451 /* update the clk tree topology */
@@ -1231,25 +1456,27 @@ static struct clk *__clk_set_parent_before(struct clk *clk, struct clk *parent)
1231 return old_parent; 1456 return old_parent;
1232} 1457}
1233 1458
1234static void __clk_set_parent_after(struct clk *clk, struct clk *parent, 1459static void __clk_set_parent_after(struct clk_core *core,
1235 struct clk *old_parent) 1460 struct clk_core *parent,
1461 struct clk_core *old_parent)
1236{ 1462{
1237 /* 1463 /*
1238 * Finish the migration of prepare state and undo the changes done 1464 * Finish the migration of prepare state and undo the changes done
1239 * for preventing a race with clk_enable(). 1465 * for preventing a race with clk_enable().
1240 */ 1466 */
1241 if (clk->prepare_count) { 1467 if (core->prepare_count) {
1242 clk_disable(clk); 1468 clk_core_disable(core);
1243 clk_disable(old_parent); 1469 clk_core_disable(old_parent);
1244 __clk_unprepare(old_parent); 1470 clk_core_unprepare(old_parent);
1245 } 1471 }
1246} 1472}
1247 1473
1248static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index) 1474static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent,
1475 u8 p_index)
1249{ 1476{
1250 unsigned long flags; 1477 unsigned long flags;
1251 int ret = 0; 1478 int ret = 0;
1252 struct clk *old_parent; 1479 struct clk_core *old_parent;
1253 1480
1254 old_parent = __clk_set_parent_before(clk, parent); 1481 old_parent = __clk_set_parent_before(clk, parent);
1255 1482
@@ -1263,9 +1490,9 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
1263 clk_enable_unlock(flags); 1490 clk_enable_unlock(flags);
1264 1491
1265 if (clk->prepare_count) { 1492 if (clk->prepare_count) {
1266 clk_disable(clk); 1493 clk_core_disable(clk);
1267 clk_disable(parent); 1494 clk_core_disable(parent);
1268 __clk_unprepare(parent); 1495 clk_core_unprepare(parent);
1269 } 1496 }
1270 return ret; 1497 return ret;
1271 } 1498 }
@@ -1291,9 +1518,10 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
1291 * 1518 *
1292 * Caller must hold prepare_lock. 1519 * Caller must hold prepare_lock.
1293 */ 1520 */
1294static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate) 1521static int __clk_speculate_rates(struct clk_core *clk,
1522 unsigned long parent_rate)
1295{ 1523{
1296 struct clk *child; 1524 struct clk_core *child;
1297 unsigned long new_rate; 1525 unsigned long new_rate;
1298 int ret = NOTIFY_DONE; 1526 int ret = NOTIFY_DONE;
1299 1527
@@ -1319,10 +1547,10 @@ out:
1319 return ret; 1547 return ret;
1320} 1548}
1321 1549
1322static void clk_calc_subtree(struct clk *clk, unsigned long new_rate, 1550static void clk_calc_subtree(struct clk_core *clk, unsigned long new_rate,
1323 struct clk *new_parent, u8 p_index) 1551 struct clk_core *new_parent, u8 p_index)
1324{ 1552{
1325 struct clk *child; 1553 struct clk_core *child;
1326 1554
1327 clk->new_rate = new_rate; 1555 clk->new_rate = new_rate;
1328 clk->new_parent = new_parent; 1556 clk->new_parent = new_parent;
@@ -1342,13 +1570,16 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate,
1342 * calculate the new rates returning the topmost clock that has to be 1570 * calculate the new rates returning the topmost clock that has to be
1343 * changed. 1571 * changed.
1344 */ 1572 */
1345static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate) 1573static struct clk_core *clk_calc_new_rates(struct clk_core *clk,
1574 unsigned long rate)
1346{ 1575{
1347 struct clk *top = clk; 1576 struct clk_core *top = clk;
1348 struct clk *old_parent, *parent; 1577 struct clk_core *old_parent, *parent;
1349 struct clk_hw *parent_hw; 1578 struct clk_hw *parent_hw;
1350 unsigned long best_parent_rate = 0; 1579 unsigned long best_parent_rate = 0;
1351 unsigned long new_rate; 1580 unsigned long new_rate;
1581 unsigned long min_rate;
1582 unsigned long max_rate;
1352 int p_index = 0; 1583 int p_index = 0;
1353 1584
1354 /* sanity */ 1585 /* sanity */
@@ -1360,16 +1591,22 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
1360 if (parent) 1591 if (parent)
1361 best_parent_rate = parent->rate; 1592 best_parent_rate = parent->rate;
1362 1593
1594 clk_core_get_boundaries(clk, &min_rate, &max_rate);
1595
1363 /* find the closest rate and parent clk/rate */ 1596 /* find the closest rate and parent clk/rate */
1364 if (clk->ops->determine_rate) { 1597 if (clk->ops->determine_rate) {
1365 parent_hw = parent ? parent->hw : NULL; 1598 parent_hw = parent ? parent->hw : NULL;
1366 new_rate = clk->ops->determine_rate(clk->hw, rate, 1599 new_rate = clk->ops->determine_rate(clk->hw, rate,
1600 min_rate,
1601 max_rate,
1367 &best_parent_rate, 1602 &best_parent_rate,
1368 &parent_hw); 1603 &parent_hw);
1369 parent = parent_hw ? parent_hw->clk : NULL; 1604 parent = parent_hw ? parent_hw->core : NULL;
1370 } else if (clk->ops->round_rate) { 1605 } else if (clk->ops->round_rate) {
1371 new_rate = clk->ops->round_rate(clk->hw, rate, 1606 new_rate = clk->ops->round_rate(clk->hw, rate,
1372 &best_parent_rate); 1607 &best_parent_rate);
1608 if (new_rate < min_rate || new_rate > max_rate)
1609 return NULL;
1373 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) { 1610 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
1374 /* pass-through clock without adjustable parent */ 1611 /* pass-through clock without adjustable parent */
1375 clk->new_rate = clk->rate; 1612 clk->new_rate = clk->rate;
@@ -1390,7 +1627,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
1390 } 1627 }
1391 1628
1392 /* try finding the new parent index */ 1629 /* try finding the new parent index */
1393 if (parent) { 1630 if (parent && clk->num_parents > 1) {
1394 p_index = clk_fetch_parent_index(clk, parent); 1631 p_index = clk_fetch_parent_index(clk, parent);
1395 if (p_index < 0) { 1632 if (p_index < 0) {
1396 pr_debug("%s: clk %s can not be parent of clk %s\n", 1633 pr_debug("%s: clk %s can not be parent of clk %s\n",
@@ -1414,9 +1651,10 @@ out:
1414 * so that in case of an error we can walk down the whole tree again and 1651 * so that in case of an error we can walk down the whole tree again and
1415 * abort the change. 1652 * abort the change.
1416 */ 1653 */
1417static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event) 1654static struct clk_core *clk_propagate_rate_change(struct clk_core *clk,
1655 unsigned long event)
1418{ 1656{
1419 struct clk *child, *tmp_clk, *fail_clk = NULL; 1657 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
1420 int ret = NOTIFY_DONE; 1658 int ret = NOTIFY_DONE;
1421 1659
1422 if (clk->rate == clk->new_rate) 1660 if (clk->rate == clk->new_rate)
@@ -1451,14 +1689,14 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
1451 * walk down a subtree and set the new rates notifying the rate 1689 * walk down a subtree and set the new rates notifying the rate
1452 * change on the way 1690 * change on the way
1453 */ 1691 */
1454static void clk_change_rate(struct clk *clk) 1692static void clk_change_rate(struct clk_core *clk)
1455{ 1693{
1456 struct clk *child; 1694 struct clk_core *child;
1457 struct hlist_node *tmp; 1695 struct hlist_node *tmp;
1458 unsigned long old_rate; 1696 unsigned long old_rate;
1459 unsigned long best_parent_rate = 0; 1697 unsigned long best_parent_rate = 0;
1460 bool skip_set_rate = false; 1698 bool skip_set_rate = false;
1461 struct clk *old_parent; 1699 struct clk_core *old_parent;
1462 1700
1463 old_rate = clk->rate; 1701 old_rate = clk->rate;
1464 1702
@@ -1506,6 +1744,45 @@ static void clk_change_rate(struct clk *clk)
1506 clk_change_rate(clk->new_child); 1744 clk_change_rate(clk->new_child);
1507} 1745}
1508 1746
1747static int clk_core_set_rate_nolock(struct clk_core *clk,
1748 unsigned long req_rate)
1749{
1750 struct clk_core *top, *fail_clk;
1751 unsigned long rate = req_rate;
1752 int ret = 0;
1753
1754 if (!clk)
1755 return 0;
1756
1757 /* bail early if nothing to do */
1758 if (rate == clk_core_get_rate_nolock(clk))
1759 return 0;
1760
1761 if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count)
1762 return -EBUSY;
1763
1764 /* calculate new rates and get the topmost changed clock */
1765 top = clk_calc_new_rates(clk, rate);
1766 if (!top)
1767 return -EINVAL;
1768
1769 /* notify that we are about to change rates */
1770 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1771 if (fail_clk) {
1772 pr_debug("%s: failed to set %s rate\n", __func__,
1773 fail_clk->name);
1774 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1775 return -EBUSY;
1776 }
1777
1778 /* change the rates */
1779 clk_change_rate(top);
1780
1781 clk->req_rate = req_rate;
1782
1783 return ret;
1784}
1785
1509/** 1786/**
1510 * clk_set_rate - specify a new rate for clk 1787 * clk_set_rate - specify a new rate for clk
1511 * @clk: the clk whose rate is being changed 1788 * @clk: the clk whose rate is being changed
@@ -1529,8 +1806,7 @@ static void clk_change_rate(struct clk *clk)
1529 */ 1806 */
1530int clk_set_rate(struct clk *clk, unsigned long rate) 1807int clk_set_rate(struct clk *clk, unsigned long rate)
1531{ 1808{
1532 struct clk *top, *fail_clk; 1809 int ret;
1533 int ret = 0;
1534 1810
1535 if (!clk) 1811 if (!clk)
1536 return 0; 1812 return 0;
@@ -1538,41 +1814,81 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
1538 /* prevent racing with updates to the clock topology */ 1814 /* prevent racing with updates to the clock topology */
1539 clk_prepare_lock(); 1815 clk_prepare_lock();
1540 1816
1541 /* bail early if nothing to do */ 1817 ret = clk_core_set_rate_nolock(clk->core, rate);
1542 if (rate == clk_get_rate(clk))
1543 goto out;
1544 1818
1545 if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count) { 1819 clk_prepare_unlock();
1546 ret = -EBUSY;
1547 goto out;
1548 }
1549 1820
1550 /* calculate new rates and get the topmost changed clock */ 1821 return ret;
1551 top = clk_calc_new_rates(clk, rate); 1822}
1552 if (!top) { 1823EXPORT_SYMBOL_GPL(clk_set_rate);
1553 ret = -EINVAL;
1554 goto out;
1555 }
1556 1824
1557 /* notify that we are about to change rates */ 1825/**
1558 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE); 1826 * clk_set_rate_range - set a rate range for a clock source
1559 if (fail_clk) { 1827 * @clk: clock source
1560 pr_debug("%s: failed to set %s rate\n", __func__, 1828 * @min: desired minimum clock rate in Hz, inclusive
1561 fail_clk->name); 1829 * @max: desired maximum clock rate in Hz, inclusive
1562 clk_propagate_rate_change(top, ABORT_RATE_CHANGE); 1830 *
1563 ret = -EBUSY; 1831 * Returns success (0) or negative errno.
1564 goto out; 1832 */
1833int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
1834{
1835 int ret = 0;
1836
1837 if (!clk)
1838 return 0;
1839
1840 if (min > max) {
1841 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1842 __func__, clk->core->name, clk->dev_id, clk->con_id,
1843 min, max);
1844 return -EINVAL;
1565 } 1845 }
1566 1846
1567 /* change the rates */ 1847 clk_prepare_lock();
1568 clk_change_rate(top); 1848
1849 if (min != clk->min_rate || max != clk->max_rate) {
1850 clk->min_rate = min;
1851 clk->max_rate = max;
1852 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
1853 }
1569 1854
1570out:
1571 clk_prepare_unlock(); 1855 clk_prepare_unlock();
1572 1856
1573 return ret; 1857 return ret;
1574} 1858}
1575EXPORT_SYMBOL_GPL(clk_set_rate); 1859EXPORT_SYMBOL_GPL(clk_set_rate_range);
1860
1861/**
1862 * clk_set_min_rate - set a minimum clock rate for a clock source
1863 * @clk: clock source
1864 * @rate: desired minimum clock rate in Hz, inclusive
1865 *
1866 * Returns success (0) or negative errno.
1867 */
1868int clk_set_min_rate(struct clk *clk, unsigned long rate)
1869{
1870 if (!clk)
1871 return 0;
1872
1873 return clk_set_rate_range(clk, rate, clk->max_rate);
1874}
1875EXPORT_SYMBOL_GPL(clk_set_min_rate);
1876
1877/**
1878 * clk_set_max_rate - set a maximum clock rate for a clock source
1879 * @clk: clock source
1880 * @rate: desired maximum clock rate in Hz, inclusive
1881 *
1882 * Returns success (0) or negative errno.
1883 */
1884int clk_set_max_rate(struct clk *clk, unsigned long rate)
1885{
1886 if (!clk)
1887 return 0;
1888
1889 return clk_set_rate_range(clk, clk->min_rate, rate);
1890}
1891EXPORT_SYMBOL_GPL(clk_set_max_rate);
1576 1892
1577/** 1893/**
1578 * clk_get_parent - return the parent of a clk 1894 * clk_get_parent - return the parent of a clk
@@ -1599,11 +1915,11 @@ EXPORT_SYMBOL_GPL(clk_get_parent);
1599 * 1915 *
1600 * For single-parent clocks without .get_parent, first check to see if the 1916 * For single-parent clocks without .get_parent, first check to see if the
1601 * .parents array exists, and if so use it to avoid an expensive tree 1917 * .parents array exists, and if so use it to avoid an expensive tree
1602 * traversal. If .parents does not exist then walk the tree with __clk_lookup. 1918 * traversal. If .parents does not exist then walk the tree.
1603 */ 1919 */
1604static struct clk *__clk_init_parent(struct clk *clk) 1920static struct clk_core *__clk_init_parent(struct clk_core *clk)
1605{ 1921{
1606 struct clk *ret = NULL; 1922 struct clk_core *ret = NULL;
1607 u8 index; 1923 u8 index;
1608 1924
1609 /* handle the trivial cases */ 1925 /* handle the trivial cases */
@@ -1613,7 +1929,7 @@ static struct clk *__clk_init_parent(struct clk *clk)
1613 1929
1614 if (clk->num_parents == 1) { 1930 if (clk->num_parents == 1) {
1615 if (IS_ERR_OR_NULL(clk->parent)) 1931 if (IS_ERR_OR_NULL(clk->parent))
1616 clk->parent = __clk_lookup(clk->parent_names[0]); 1932 clk->parent = clk_core_lookup(clk->parent_names[0]);
1617 ret = clk->parent; 1933 ret = clk->parent;
1618 goto out; 1934 goto out;
1619 } 1935 }
@@ -1627,8 +1943,8 @@ static struct clk *__clk_init_parent(struct clk *clk)
1627 1943
1628 /* 1944 /*
1629 * Do our best to cache parent clocks in clk->parents. This prevents 1945 * Do our best to cache parent clocks in clk->parents. This prevents
1630 * unnecessary and expensive calls to __clk_lookup. We don't set 1946 * unnecessary and expensive lookups. We don't set clk->parent here;
1631 * clk->parent here; that is done by the calling function 1947 * that is done by the calling function.
1632 */ 1948 */
1633 1949
1634 index = clk->ops->get_parent(clk->hw); 1950 index = clk->ops->get_parent(clk->hw);
@@ -1638,13 +1954,14 @@ static struct clk *__clk_init_parent(struct clk *clk)
1638 kcalloc(clk->num_parents, sizeof(struct clk *), 1954 kcalloc(clk->num_parents, sizeof(struct clk *),
1639 GFP_KERNEL); 1955 GFP_KERNEL);
1640 1956
1641 ret = clk_get_parent_by_index(clk, index); 1957 ret = clk_core_get_parent_by_index(clk, index);
1642 1958
1643out: 1959out:
1644 return ret; 1960 return ret;
1645} 1961}
1646 1962
1647void __clk_reparent(struct clk *clk, struct clk *new_parent) 1963static void clk_core_reparent(struct clk_core *clk,
1964 struct clk_core *new_parent)
1648{ 1965{
1649 clk_reparent(clk, new_parent); 1966 clk_reparent(clk, new_parent);
1650 __clk_recalc_accuracies(clk); 1967 __clk_recalc_accuracies(clk);
@@ -1652,23 +1969,40 @@ void __clk_reparent(struct clk *clk, struct clk *new_parent)
1652} 1969}
1653 1970
1654/** 1971/**
1655 * clk_set_parent - switch the parent of a mux clk 1972 * clk_has_parent - check if a clock is a possible parent for another
1656 * @clk: the mux clk whose input we are switching 1973 * @clk: clock source
1657 * @parent: the new input to clk 1974 * @parent: parent clock source
1658 * 1975 *
1659 * Re-parent clk to use parent as its new input source. If clk is in 1976 * This function can be used in drivers that need to check that a clock can be
1660 * prepared state, the clk will get enabled for the duration of this call. If 1977 * the parent of another without actually changing the parent.
1661 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1662 * that, the reparenting is glitchy in hardware, etc), use the
1663 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1664 *
1665 * After successfully changing clk's parent clk_set_parent will update the
1666 * clk topology, sysfs topology and propagate rate recalculation via
1667 * __clk_recalc_rates.
1668 * 1978 *
1669 * Returns 0 on success, -EERROR otherwise. 1979 * Returns true if @parent is a possible parent for @clk, false otherwise.
1670 */ 1980 */
1671int clk_set_parent(struct clk *clk, struct clk *parent) 1981bool clk_has_parent(struct clk *clk, struct clk *parent)
1982{
1983 struct clk_core *core, *parent_core;
1984 unsigned int i;
1985
1986 /* NULL clocks should be nops, so return success if either is NULL. */
1987 if (!clk || !parent)
1988 return true;
1989
1990 core = clk->core;
1991 parent_core = parent->core;
1992
1993 /* Optimize for the case where the parent is already the parent. */
1994 if (core->parent == parent_core)
1995 return true;
1996
1997 for (i = 0; i < core->num_parents; i++)
1998 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1999 return true;
2000
2001 return false;
2002}
2003EXPORT_SYMBOL_GPL(clk_has_parent);
2004
2005static int clk_core_set_parent(struct clk_core *clk, struct clk_core *parent)
1672{ 2006{
1673 int ret = 0; 2007 int ret = 0;
1674 int p_index = 0; 2008 int p_index = 0;
@@ -1728,6 +2062,31 @@ out:
1728 2062
1729 return ret; 2063 return ret;
1730} 2064}
2065
2066/**
2067 * clk_set_parent - switch the parent of a mux clk
2068 * @clk: the mux clk whose input we are switching
2069 * @parent: the new input to clk
2070 *
2071 * Re-parent clk to use parent as its new input source. If clk is in
2072 * prepared state, the clk will get enabled for the duration of this call. If
2073 * that's not acceptable for a specific clk (Eg: the consumer can't handle
2074 * that, the reparenting is glitchy in hardware, etc), use the
2075 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
2076 *
2077 * After successfully changing clk's parent clk_set_parent will update the
2078 * clk topology, sysfs topology and propagate rate recalculation via
2079 * __clk_recalc_rates.
2080 *
2081 * Returns 0 on success, -EERROR otherwise.
2082 */
2083int clk_set_parent(struct clk *clk, struct clk *parent)
2084{
2085 if (!clk)
2086 return 0;
2087
2088 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
2089}
1731EXPORT_SYMBOL_GPL(clk_set_parent); 2090EXPORT_SYMBOL_GPL(clk_set_parent);
1732 2091
1733/** 2092/**
@@ -1764,13 +2123,13 @@ int clk_set_phase(struct clk *clk, int degrees)
1764 2123
1765 clk_prepare_lock(); 2124 clk_prepare_lock();
1766 2125
1767 if (!clk->ops->set_phase) 2126 if (!clk->core->ops->set_phase)
1768 goto out_unlock; 2127 goto out_unlock;
1769 2128
1770 ret = clk->ops->set_phase(clk->hw, degrees); 2129 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
1771 2130
1772 if (!ret) 2131 if (!ret)
1773 clk->phase = degrees; 2132 clk->core->phase = degrees;
1774 2133
1775out_unlock: 2134out_unlock:
1776 clk_prepare_unlock(); 2135 clk_prepare_unlock();
@@ -1778,15 +2137,9 @@ out_unlock:
1778out: 2137out:
1779 return ret; 2138 return ret;
1780} 2139}
2140EXPORT_SYMBOL_GPL(clk_set_phase);
1781 2141
1782/** 2142static int clk_core_get_phase(struct clk_core *clk)
1783 * clk_get_phase - return the phase shift of a clock signal
1784 * @clk: clock signal source
1785 *
1786 * Returns the phase shift of a clock node in degrees, otherwise returns
1787 * -EERROR.
1788 */
1789int clk_get_phase(struct clk *clk)
1790{ 2143{
1791 int ret = 0; 2144 int ret = 0;
1792 2145
@@ -1800,28 +2153,48 @@ int clk_get_phase(struct clk *clk)
1800out: 2153out:
1801 return ret; 2154 return ret;
1802} 2155}
2156EXPORT_SYMBOL_GPL(clk_get_phase);
2157
2158/**
2159 * clk_get_phase - return the phase shift of a clock signal
2160 * @clk: clock signal source
2161 *
2162 * Returns the phase shift of a clock node in degrees, otherwise returns
2163 * -EERROR.
2164 */
2165int clk_get_phase(struct clk *clk)
2166{
2167 if (!clk)
2168 return 0;
2169
2170 return clk_core_get_phase(clk->core);
2171}
1803 2172
1804/** 2173/**
1805 * __clk_init - initialize the data structures in a struct clk 2174 * __clk_init - initialize the data structures in a struct clk
1806 * @dev: device initializing this clk, placeholder for now 2175 * @dev: device initializing this clk, placeholder for now
1807 * @clk: clk being initialized 2176 * @clk: clk being initialized
1808 * 2177 *
1809 * Initializes the lists in struct clk, queries the hardware for the 2178 * Initializes the lists in struct clk_core, queries the hardware for the
1810 * parent and rate and sets them both. 2179 * parent and rate and sets them both.
1811 */ 2180 */
1812int __clk_init(struct device *dev, struct clk *clk) 2181static int __clk_init(struct device *dev, struct clk *clk_user)
1813{ 2182{
1814 int i, ret = 0; 2183 int i, ret = 0;
1815 struct clk *orphan; 2184 struct clk_core *orphan;
1816 struct hlist_node *tmp2; 2185 struct hlist_node *tmp2;
2186 struct clk_core *clk;
2187 unsigned long rate;
1817 2188
1818 if (!clk) 2189 if (!clk_user)
1819 return -EINVAL; 2190 return -EINVAL;
1820 2191
2192 clk = clk_user->core;
2193
1821 clk_prepare_lock(); 2194 clk_prepare_lock();
1822 2195
1823 /* check to see if a clock with this name is already registered */ 2196 /* check to see if a clock with this name is already registered */
1824 if (__clk_lookup(clk->name)) { 2197 if (clk_core_lookup(clk->name)) {
1825 pr_debug("%s: clk %s already initialized\n", 2198 pr_debug("%s: clk %s already initialized\n",
1826 __func__, clk->name); 2199 __func__, clk->name);
1827 ret = -EEXIST; 2200 ret = -EEXIST;
@@ -1873,7 +2246,7 @@ int __clk_init(struct device *dev, struct clk *clk)
1873 clk->parents = kcalloc(clk->num_parents, sizeof(struct clk *), 2246 clk->parents = kcalloc(clk->num_parents, sizeof(struct clk *),
1874 GFP_KERNEL); 2247 GFP_KERNEL);
1875 /* 2248 /*
1876 * __clk_lookup returns NULL for parents that have not been 2249 * clk_core_lookup returns NULL for parents that have not been
1877 * clk_init'd; thus any access to clk->parents[] must check 2250 * clk_init'd; thus any access to clk->parents[] must check
1878 * for a NULL pointer. We can always perform lazy lookups for 2251 * for a NULL pointer. We can always perform lazy lookups for
1879 * missing parents later on. 2252 * missing parents later on.
@@ -1881,7 +2254,7 @@ int __clk_init(struct device *dev, struct clk *clk)
1881 if (clk->parents) 2254 if (clk->parents)
1882 for (i = 0; i < clk->num_parents; i++) 2255 for (i = 0; i < clk->num_parents; i++)
1883 clk->parents[i] = 2256 clk->parents[i] =
1884 __clk_lookup(clk->parent_names[i]); 2257 clk_core_lookup(clk->parent_names[i]);
1885 } 2258 }
1886 2259
1887 clk->parent = __clk_init_parent(clk); 2260 clk->parent = __clk_init_parent(clk);
@@ -1936,12 +2309,13 @@ int __clk_init(struct device *dev, struct clk *clk)
1936 * then rate is set to zero. 2309 * then rate is set to zero.
1937 */ 2310 */
1938 if (clk->ops->recalc_rate) 2311 if (clk->ops->recalc_rate)
1939 clk->rate = clk->ops->recalc_rate(clk->hw, 2312 rate = clk->ops->recalc_rate(clk->hw,
1940 __clk_get_rate(clk->parent)); 2313 clk_core_get_rate_nolock(clk->parent));
1941 else if (clk->parent) 2314 else if (clk->parent)
1942 clk->rate = clk->parent->rate; 2315 rate = clk->parent->rate;
1943 else 2316 else
1944 clk->rate = 0; 2317 rate = 0;
2318 clk->rate = clk->req_rate = rate;
1945 2319
1946 /* 2320 /*
1947 * walk the list of orphan clocks and reparent any that are children of 2321 * walk the list of orphan clocks and reparent any that are children of
@@ -1951,13 +2325,13 @@ int __clk_init(struct device *dev, struct clk *clk)
1951 if (orphan->num_parents && orphan->ops->get_parent) { 2325 if (orphan->num_parents && orphan->ops->get_parent) {
1952 i = orphan->ops->get_parent(orphan->hw); 2326 i = orphan->ops->get_parent(orphan->hw);
1953 if (!strcmp(clk->name, orphan->parent_names[i])) 2327 if (!strcmp(clk->name, orphan->parent_names[i]))
1954 __clk_reparent(orphan, clk); 2328 clk_core_reparent(orphan, clk);
1955 continue; 2329 continue;
1956 } 2330 }
1957 2331
1958 for (i = 0; i < orphan->num_parents; i++) 2332 for (i = 0; i < orphan->num_parents; i++)
1959 if (!strcmp(clk->name, orphan->parent_names[i])) { 2333 if (!strcmp(clk->name, orphan->parent_names[i])) {
1960 __clk_reparent(orphan, clk); 2334 clk_core_reparent(orphan, clk);
1961 break; 2335 break;
1962 } 2336 }
1963 } 2337 }
@@ -1983,47 +2357,39 @@ out:
1983 return ret; 2357 return ret;
1984} 2358}
1985 2359
1986/** 2360struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
1987 * __clk_register - register a clock and return a cookie. 2361 const char *con_id)
1988 *
1989 * Same as clk_register, except that the .clk field inside hw shall point to a
1990 * preallocated (generally statically allocated) struct clk. None of the fields
1991 * of the struct clk need to be initialized.
1992 *
1993 * The data pointed to by .init and .clk field shall NOT be marked as init
1994 * data.
1995 *
1996 * __clk_register is only exposed via clk-private.h and is intended for use with
1997 * very large numbers of clocks that need to be statically initialized. It is
1998 * a layering violation to include clk-private.h from any code which implements
1999 * a clock's .ops; as such any statically initialized clock data MUST be in a
2000 * separate C file from the logic that implements its operations. Returns 0
2001 * on success, otherwise an error code.
2002 */
2003struct clk *__clk_register(struct device *dev, struct clk_hw *hw)
2004{ 2362{
2005 int ret;
2006 struct clk *clk; 2363 struct clk *clk;
2007 2364
2008 clk = hw->clk; 2365 /* This is to allow this function to be chained to others */
2009 clk->name = hw->init->name; 2366 if (!hw || IS_ERR(hw))
2010 clk->ops = hw->init->ops; 2367 return (struct clk *) hw;
2011 clk->hw = hw;
2012 clk->flags = hw->init->flags;
2013 clk->parent_names = hw->init->parent_names;
2014 clk->num_parents = hw->init->num_parents;
2015 if (dev && dev->driver)
2016 clk->owner = dev->driver->owner;
2017 else
2018 clk->owner = NULL;
2019 2368
2020 ret = __clk_init(dev, clk); 2369 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2021 if (ret) 2370 if (!clk)
2022 return ERR_PTR(ret); 2371 return ERR_PTR(-ENOMEM);
2372
2373 clk->core = hw->core;
2374 clk->dev_id = dev_id;
2375 clk->con_id = con_id;
2376 clk->max_rate = ULONG_MAX;
2377
2378 clk_prepare_lock();
2379 hlist_add_head(&clk->child_node, &hw->core->clks);
2380 clk_prepare_unlock();
2023 2381
2024 return clk; 2382 return clk;
2025} 2383}
2026EXPORT_SYMBOL_GPL(__clk_register); 2384
2385void __clk_free_clk(struct clk *clk)
2386{
2387 clk_prepare_lock();
2388 hlist_del(&clk->child_node);
2389 clk_prepare_unlock();
2390
2391 kfree(clk);
2392}
2027 2393
2028/** 2394/**
2029 * clk_register - allocate a new clock, register it and return an opaque cookie 2395 * clk_register - allocate a new clock, register it and return an opaque cookie
@@ -2039,7 +2405,7 @@ EXPORT_SYMBOL_GPL(__clk_register);
2039struct clk *clk_register(struct device *dev, struct clk_hw *hw) 2405struct clk *clk_register(struct device *dev, struct clk_hw *hw)
2040{ 2406{
2041 int i, ret; 2407 int i, ret;
2042 struct clk *clk; 2408 struct clk_core *clk;
2043 2409
2044 clk = kzalloc(sizeof(*clk), GFP_KERNEL); 2410 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2045 if (!clk) { 2411 if (!clk) {
@@ -2060,7 +2426,7 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
2060 clk->hw = hw; 2426 clk->hw = hw;
2061 clk->flags = hw->init->flags; 2427 clk->flags = hw->init->flags;
2062 clk->num_parents = hw->init->num_parents; 2428 clk->num_parents = hw->init->num_parents;
2063 hw->clk = clk; 2429 hw->core = clk;
2064 2430
2065 /* allocate local copy in case parent_names is __initdata */ 2431 /* allocate local copy in case parent_names is __initdata */
2066 clk->parent_names = kcalloc(clk->num_parents, sizeof(char *), 2432 clk->parent_names = kcalloc(clk->num_parents, sizeof(char *),
@@ -2084,9 +2450,21 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
2084 } 2450 }
2085 } 2451 }
2086 2452
2087 ret = __clk_init(dev, clk); 2453 INIT_HLIST_HEAD(&clk->clks);
2454
2455 hw->clk = __clk_create_clk(hw, NULL, NULL);
2456 if (IS_ERR(hw->clk)) {
2457 pr_err("%s: could not allocate per-user clk\n", __func__);
2458 ret = PTR_ERR(hw->clk);
2459 goto fail_parent_names_copy;
2460 }
2461
2462 ret = __clk_init(dev, hw->clk);
2088 if (!ret) 2463 if (!ret)
2089 return clk; 2464 return hw->clk;
2465
2466 __clk_free_clk(hw->clk);
2467 hw->clk = NULL;
2090 2468
2091fail_parent_names_copy: 2469fail_parent_names_copy:
2092 while (--i >= 0) 2470 while (--i >= 0)
@@ -2107,7 +2485,7 @@ EXPORT_SYMBOL_GPL(clk_register);
2107 */ 2485 */
2108static void __clk_release(struct kref *ref) 2486static void __clk_release(struct kref *ref)
2109{ 2487{
2110 struct clk *clk = container_of(ref, struct clk, ref); 2488 struct clk_core *clk = container_of(ref, struct clk_core, ref);
2111 int i = clk->num_parents; 2489 int i = clk->num_parents;
2112 2490
2113 kfree(clk->parents); 2491 kfree(clk->parents);
@@ -2165,12 +2543,13 @@ void clk_unregister(struct clk *clk)
2165 if (!clk || WARN_ON_ONCE(IS_ERR(clk))) 2543 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2166 return; 2544 return;
2167 2545
2168 clk_debug_unregister(clk); 2546 clk_debug_unregister(clk->core);
2169 2547
2170 clk_prepare_lock(); 2548 clk_prepare_lock();
2171 2549
2172 if (clk->ops == &clk_nodrv_ops) { 2550 if (clk->core->ops == &clk_nodrv_ops) {
2173 pr_err("%s: unregistered clock: %s\n", __func__, clk->name); 2551 pr_err("%s: unregistered clock: %s\n", __func__,
2552 clk->core->name);
2174 return; 2553 return;
2175 } 2554 }
2176 /* 2555 /*
@@ -2178,24 +2557,25 @@ void clk_unregister(struct clk *clk)
2178 * a reference to this clock. 2557 * a reference to this clock.
2179 */ 2558 */
2180 flags = clk_enable_lock(); 2559 flags = clk_enable_lock();
2181 clk->ops = &clk_nodrv_ops; 2560 clk->core->ops = &clk_nodrv_ops;
2182 clk_enable_unlock(flags); 2561 clk_enable_unlock(flags);
2183 2562
2184 if (!hlist_empty(&clk->children)) { 2563 if (!hlist_empty(&clk->core->children)) {
2185 struct clk *child; 2564 struct clk_core *child;
2186 struct hlist_node *t; 2565 struct hlist_node *t;
2187 2566
2188 /* Reparent all children to the orphan list. */ 2567 /* Reparent all children to the orphan list. */
2189 hlist_for_each_entry_safe(child, t, &clk->children, child_node) 2568 hlist_for_each_entry_safe(child, t, &clk->core->children,
2190 clk_set_parent(child, NULL); 2569 child_node)
2570 clk_core_set_parent(child, NULL);
2191 } 2571 }
2192 2572
2193 hlist_del_init(&clk->child_node); 2573 hlist_del_init(&clk->core->child_node);
2194 2574
2195 if (clk->prepare_count) 2575 if (clk->core->prepare_count)
2196 pr_warn("%s: unregistering prepared clock: %s\n", 2576 pr_warn("%s: unregistering prepared clock: %s\n",
2197 __func__, clk->name); 2577 __func__, clk->core->name);
2198 kref_put(&clk->ref, __clk_release); 2578 kref_put(&clk->core->ref, __clk_release);
2199 2579
2200 clk_prepare_unlock(); 2580 clk_prepare_unlock();
2201} 2581}
@@ -2263,11 +2643,13 @@ EXPORT_SYMBOL_GPL(devm_clk_unregister);
2263 */ 2643 */
2264int __clk_get(struct clk *clk) 2644int __clk_get(struct clk *clk)
2265{ 2645{
2266 if (clk) { 2646 struct clk_core *core = !clk ? NULL : clk->core;
2267 if (!try_module_get(clk->owner)) 2647
2648 if (core) {
2649 if (!try_module_get(core->owner))
2268 return 0; 2650 return 0;
2269 2651
2270 kref_get(&clk->ref); 2652 kref_get(&core->ref);
2271 } 2653 }
2272 return 1; 2654 return 1;
2273} 2655}
@@ -2280,11 +2662,20 @@ void __clk_put(struct clk *clk)
2280 return; 2662 return;
2281 2663
2282 clk_prepare_lock(); 2664 clk_prepare_lock();
2283 owner = clk->owner; 2665
2284 kref_put(&clk->ref, __clk_release); 2666 hlist_del(&clk->child_node);
2667 if (clk->min_rate > clk->core->req_rate ||
2668 clk->max_rate < clk->core->req_rate)
2669 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2670
2671 owner = clk->core->owner;
2672 kref_put(&clk->core->ref, __clk_release);
2673
2285 clk_prepare_unlock(); 2674 clk_prepare_unlock();
2286 2675
2287 module_put(owner); 2676 module_put(owner);
2677
2678 kfree(clk);
2288} 2679}
2289 2680
2290/*** clk rate change notifiers ***/ 2681/*** clk rate change notifiers ***/
@@ -2339,7 +2730,7 @@ int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2339 2730
2340 ret = srcu_notifier_chain_register(&cn->notifier_head, nb); 2731 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2341 2732
2342 clk->notifier_count++; 2733 clk->core->notifier_count++;
2343 2734
2344out: 2735out:
2345 clk_prepare_unlock(); 2736 clk_prepare_unlock();
@@ -2376,7 +2767,7 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2376 if (cn->clk == clk) { 2767 if (cn->clk == clk) {
2377 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb); 2768 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2378 2769
2379 clk->notifier_count--; 2770 clk->core->notifier_count--;
2380 2771
2381 /* XXX the notifier code should handle this better */ 2772 /* XXX the notifier code should handle this better */
2382 if (!cn->notifier_head.head) { 2773 if (!cn->notifier_head.head) {
@@ -2506,7 +2897,8 @@ void of_clk_del_provider(struct device_node *np)
2506} 2897}
2507EXPORT_SYMBOL_GPL(of_clk_del_provider); 2898EXPORT_SYMBOL_GPL(of_clk_del_provider);
2508 2899
2509struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec) 2900struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2901 const char *dev_id, const char *con_id)
2510{ 2902{
2511 struct of_clk_provider *provider; 2903 struct of_clk_provider *provider;
2512 struct clk *clk = ERR_PTR(-EPROBE_DEFER); 2904 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
@@ -2515,8 +2907,17 @@ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec)
2515 list_for_each_entry(provider, &of_clk_providers, link) { 2907 list_for_each_entry(provider, &of_clk_providers, link) {
2516 if (provider->node == clkspec->np) 2908 if (provider->node == clkspec->np)
2517 clk = provider->get(clkspec, provider->data); 2909 clk = provider->get(clkspec, provider->data);
2518 if (!IS_ERR(clk)) 2910 if (!IS_ERR(clk)) {
2911 clk = __clk_create_clk(__clk_get_hw(clk), dev_id,
2912 con_id);
2913
2914 if (!IS_ERR(clk) && !__clk_get(clk)) {
2915 __clk_free_clk(clk);
2916 clk = ERR_PTR(-ENOENT);
2917 }
2918
2519 break; 2919 break;
2920 }
2520 } 2921 }
2521 2922
2522 return clk; 2923 return clk;
@@ -2527,7 +2928,7 @@ struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
2527 struct clk *clk; 2928 struct clk *clk;
2528 2929
2529 mutex_lock(&of_clk_mutex); 2930 mutex_lock(&of_clk_mutex);
2530 clk = __of_clk_get_from_provider(clkspec); 2931 clk = __of_clk_get_from_provider(clkspec, NULL, __func__);
2531 mutex_unlock(&of_clk_mutex); 2932 mutex_unlock(&of_clk_mutex);
2532 2933
2533 return clk; 2934 return clk;
diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h
index c798138f023f..ba845408cc3e 100644
--- a/drivers/clk/clk.h
+++ b/drivers/clk/clk.h
@@ -9,9 +9,31 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12struct clk_hw;
13
12#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) 14#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
13struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec); 15struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec);
14struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec); 16struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
17 const char *dev_id, const char *con_id);
15void of_clk_lock(void); 18void of_clk_lock(void);
16void of_clk_unlock(void); 19void of_clk_unlock(void);
17#endif 20#endif
21
22#ifdef CONFIG_COMMON_CLK
23struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
24 const char *con_id);
25void __clk_free_clk(struct clk *clk);
26#else
27/* All these casts to avoid ifdefs in clkdev... */
28static inline struct clk *
29__clk_create_clk(struct clk_hw *hw, const char *dev_id, const char *con_id)
30{
31 return (struct clk *)hw;
32}
33static inline void __clk_free_clk(struct clk *clk) { }
34static struct clk_hw *__clk_get_hw(struct clk *clk)
35{
36 return (struct clk_hw *)clk;
37}
38
39#endif
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index da4bda8b7fc7..043fd3633373 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -19,6 +19,7 @@
19#include <linux/mutex.h> 19#include <linux/mutex.h>
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/clkdev.h> 21#include <linux/clkdev.h>
22#include <linux/clk-provider.h>
22#include <linux/of.h> 23#include <linux/of.h>
23 24
24#include "clk.h" 25#include "clk.h"
@@ -28,6 +29,20 @@ static DEFINE_MUTEX(clocks_mutex);
28 29
29#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) 30#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
30 31
32static struct clk *__of_clk_get_by_clkspec(struct of_phandle_args *clkspec,
33 const char *dev_id, const char *con_id)
34{
35 struct clk *clk;
36
37 if (!clkspec)
38 return ERR_PTR(-EINVAL);
39
40 of_clk_lock();
41 clk = __of_clk_get_from_provider(clkspec, dev_id, con_id);
42 of_clk_unlock();
43 return clk;
44}
45
31/** 46/**
32 * of_clk_get_by_clkspec() - Lookup a clock form a clock provider 47 * of_clk_get_by_clkspec() - Lookup a clock form a clock provider
33 * @clkspec: pointer to a clock specifier data structure 48 * @clkspec: pointer to a clock specifier data structure
@@ -38,22 +53,11 @@ static DEFINE_MUTEX(clocks_mutex);
38 */ 53 */
39struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec) 54struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec)
40{ 55{
41 struct clk *clk; 56 return __of_clk_get_by_clkspec(clkspec, NULL, __func__);
42
43 if (!clkspec)
44 return ERR_PTR(-EINVAL);
45
46 of_clk_lock();
47 clk = __of_clk_get_from_provider(clkspec);
48
49 if (!IS_ERR(clk) && !__clk_get(clk))
50 clk = ERR_PTR(-ENOENT);
51
52 of_clk_unlock();
53 return clk;
54} 57}
55 58
56struct clk *of_clk_get(struct device_node *np, int index) 59static struct clk *__of_clk_get(struct device_node *np, int index,
60 const char *dev_id, const char *con_id)
57{ 61{
58 struct of_phandle_args clkspec; 62 struct of_phandle_args clkspec;
59 struct clk *clk; 63 struct clk *clk;
@@ -67,22 +71,21 @@ struct clk *of_clk_get(struct device_node *np, int index)
67 if (rc) 71 if (rc)
68 return ERR_PTR(rc); 72 return ERR_PTR(rc);
69 73
70 clk = of_clk_get_by_clkspec(&clkspec); 74 clk = __of_clk_get_by_clkspec(&clkspec, dev_id, con_id);
71 of_node_put(clkspec.np); 75 of_node_put(clkspec.np);
76
72 return clk; 77 return clk;
73} 78}
79
80struct clk *of_clk_get(struct device_node *np, int index)
81{
82 return __of_clk_get(np, index, np->full_name, NULL);
83}
74EXPORT_SYMBOL(of_clk_get); 84EXPORT_SYMBOL(of_clk_get);
75 85
76/** 86static struct clk *__of_clk_get_by_name(struct device_node *np,
77 * of_clk_get_by_name() - Parse and lookup a clock referenced by a device node 87 const char *dev_id,
78 * @np: pointer to clock consumer node 88 const char *name)
79 * @name: name of consumer's clock input, or NULL for the first clock reference
80 *
81 * This function parses the clocks and clock-names properties,
82 * and uses them to look up the struct clk from the registered list of clock
83 * providers.
84 */
85struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
86{ 89{
87 struct clk *clk = ERR_PTR(-ENOENT); 90 struct clk *clk = ERR_PTR(-ENOENT);
88 91
@@ -97,10 +100,10 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
97 */ 100 */
98 if (name) 101 if (name)
99 index = of_property_match_string(np, "clock-names", name); 102 index = of_property_match_string(np, "clock-names", name);
100 clk = of_clk_get(np, index); 103 clk = __of_clk_get(np, index, dev_id, name);
101 if (!IS_ERR(clk)) 104 if (!IS_ERR(clk)) {
102 break; 105 break;
103 else if (name && index >= 0) { 106 } else if (name && index >= 0) {
104 if (PTR_ERR(clk) != -EPROBE_DEFER) 107 if (PTR_ERR(clk) != -EPROBE_DEFER)
105 pr_err("ERROR: could not get clock %s:%s(%i)\n", 108 pr_err("ERROR: could not get clock %s:%s(%i)\n",
106 np->full_name, name ? name : "", index); 109 np->full_name, name ? name : "", index);
@@ -119,7 +122,33 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
119 122
120 return clk; 123 return clk;
121} 124}
125
126/**
127 * of_clk_get_by_name() - Parse and lookup a clock referenced by a device node
128 * @np: pointer to clock consumer node
129 * @name: name of consumer's clock input, or NULL for the first clock reference
130 *
131 * This function parses the clocks and clock-names properties,
132 * and uses them to look up the struct clk from the registered list of clock
133 * providers.
134 */
135struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
136{
137 if (!np)
138 return ERR_PTR(-ENOENT);
139
140 return __of_clk_get_by_name(np, np->full_name, name);
141}
122EXPORT_SYMBOL(of_clk_get_by_name); 142EXPORT_SYMBOL(of_clk_get_by_name);
143
144#else /* defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK) */
145
146static struct clk *__of_clk_get_by_name(struct device_node *np,
147 const char *dev_id,
148 const char *name)
149{
150 return ERR_PTR(-ENOENT);
151}
123#endif 152#endif
124 153
125/* 154/*
@@ -168,14 +197,28 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
168struct clk *clk_get_sys(const char *dev_id, const char *con_id) 197struct clk *clk_get_sys(const char *dev_id, const char *con_id)
169{ 198{
170 struct clk_lookup *cl; 199 struct clk_lookup *cl;
200 struct clk *clk = NULL;
171 201
172 mutex_lock(&clocks_mutex); 202 mutex_lock(&clocks_mutex);
203
173 cl = clk_find(dev_id, con_id); 204 cl = clk_find(dev_id, con_id);
174 if (cl && !__clk_get(cl->clk)) 205 if (!cl)
206 goto out;
207
208 clk = __clk_create_clk(__clk_get_hw(cl->clk), dev_id, con_id);
209 if (IS_ERR(clk))
210 goto out;
211
212 if (!__clk_get(clk)) {
213 __clk_free_clk(clk);
175 cl = NULL; 214 cl = NULL;
215 goto out;
216 }
217
218out:
176 mutex_unlock(&clocks_mutex); 219 mutex_unlock(&clocks_mutex);
177 220
178 return cl ? cl->clk : ERR_PTR(-ENOENT); 221 return cl ? clk : ERR_PTR(-ENOENT);
179} 222}
180EXPORT_SYMBOL(clk_get_sys); 223EXPORT_SYMBOL(clk_get_sys);
181 224
@@ -185,10 +228,8 @@ struct clk *clk_get(struct device *dev, const char *con_id)
185 struct clk *clk; 228 struct clk *clk;
186 229
187 if (dev) { 230 if (dev) {
188 clk = of_clk_get_by_name(dev->of_node, con_id); 231 clk = __of_clk_get_by_name(dev->of_node, dev_id, con_id);
189 if (!IS_ERR(clk)) 232 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
190 return clk;
191 if (PTR_ERR(clk) == -EPROBE_DEFER)
192 return clk; 233 return clk;
193 } 234 }
194 235
@@ -331,6 +372,7 @@ int clk_register_clkdev(struct clk *clk, const char *con_id,
331 372
332 return 0; 373 return 0;
333} 374}
375EXPORT_SYMBOL(clk_register_clkdev);
334 376
335/** 377/**
336 * clk_register_clkdevs - register a set of clk_lookup for a struct clk 378 * clk_register_clkdevs - register a set of clk_lookup for a struct clk
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index 007144f81f50..2e4f6d432beb 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -295,6 +295,8 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
295} 295}
296 296
297static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate, 297static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
298 unsigned long min_rate,
299 unsigned long max_rate,
298 unsigned long *best_parent_rate, 300 unsigned long *best_parent_rate,
299 struct clk_hw **best_parent_p) 301 struct clk_hw **best_parent_p)
300{ 302{
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
index 48fa53c7ce5e..de6a873175d2 100644
--- a/drivers/clk/mmp/clk-mix.c
+++ b/drivers/clk/mmp/clk-mix.c
@@ -202,6 +202,8 @@ error:
202} 202}
203 203
204static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate, 204static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate,
205 unsigned long min_rate,
206 unsigned long max_rate,
205 unsigned long *best_parent_rate, 207 unsigned long *best_parent_rate,
206 struct clk_hw **best_parent_clk) 208 struct clk_hw **best_parent_clk)
207{ 209{
diff --git a/drivers/clk/pxa/Makefile b/drivers/clk/pxa/Makefile
index 38e915344605..38e37bf6b821 100644
--- a/drivers/clk/pxa/Makefile
+++ b/drivers/clk/pxa/Makefile
@@ -1,3 +1,4 @@
1obj-y += clk-pxa.o 1obj-y += clk-pxa.o
2obj-$(CONFIG_PXA25x) += clk-pxa25x.o 2obj-$(CONFIG_PXA25x) += clk-pxa25x.o
3obj-$(CONFIG_PXA27x) += clk-pxa27x.o 3obj-$(CONFIG_PXA27x) += clk-pxa27x.o
4obj-$(CONFIG_PXA3xx) += clk-pxa3xx.o
diff --git a/drivers/clk/pxa/clk-pxa.c b/drivers/clk/pxa/clk-pxa.c
index 4e834753ab09..29cee9e8d4d9 100644
--- a/drivers/clk/pxa/clk-pxa.c
+++ b/drivers/clk/pxa/clk-pxa.c
@@ -46,7 +46,7 @@ static unsigned long cken_recalc_rate(struct clk_hw *hw,
46 fix = &pclk->lp; 46 fix = &pclk->lp;
47 else 47 else
48 fix = &pclk->hp; 48 fix = &pclk->hp;
49 fix->hw.clk = hw->clk; 49 __clk_hw_set_clk(&fix->hw, hw);
50 return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate); 50 return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate);
51} 51}
52 52
diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c
new file mode 100644
index 000000000000..39f891bba09a
--- /dev/null
+++ b/drivers/clk/pxa/clk-pxa3xx.c
@@ -0,0 +1,364 @@
1/*
2 * Marvell PXA3xxx family clocks
3 *
4 * Copyright (C) 2014 Robert Jarzmik
5 *
6 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
13 * should go away.
14 */
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/of.h>
20#include <mach/smemc.h>
21#include <mach/pxa3xx-regs.h>
22
23#include <dt-bindings/clock/pxa-clock.h>
24#include "clk-pxa.h"
25
26#define KHz 1000
27#define MHz (1000 * 1000)
28
29enum {
30 PXA_CORE_60Mhz = 0,
31 PXA_CORE_RUN,
32 PXA_CORE_TURBO,
33};
34
35enum {
36 PXA_BUS_60Mhz = 0,
37 PXA_BUS_HSS,
38};
39
40/* crystal frequency to HSIO bus frequency multiplier (HSS) */
41static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
42
43/* crystal frequency to static memory controller multiplier (SMCFS) */
44static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
45static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
46
47static const char * const get_freq_khz[] = {
48 "core", "ring_osc_60mhz", "run", "cpll", "system_bus"
49};
50
51/*
52 * Get the clock frequency as reflected by ACSR and the turbo flag.
53 * We assume these values have been applied via a fcs.
54 * If info is not 0 we also display the current settings.
55 */
56unsigned int pxa3xx_get_clk_frequency_khz(int info)
57{
58 struct clk *clk;
59 unsigned long clks[5];
60 int i;
61
62 for (i = 0; i < 5; i++) {
63 clk = clk_get(NULL, get_freq_khz[i]);
64 if (IS_ERR(clk)) {
65 clks[i] = 0;
66 } else {
67 clks[i] = clk_get_rate(clk);
68 clk_put(clk);
69 }
70 }
71 if (info) {
72 pr_info("RO Mode clock: %ld.%02ldMHz\n",
73 clks[1] / 1000000, (clks[0] % 1000000) / 10000);
74 pr_info("Run Mode clock: %ld.%02ldMHz\n",
75 clks[2] / 1000000, (clks[1] % 1000000) / 10000);
76 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
77 clks[3] / 1000000, (clks[2] % 1000000) / 10000);
78 pr_info("System bus clock: %ld.%02ldMHz\n",
79 clks[4] / 1000000, (clks[4] % 1000000) / 10000);
80 }
81 return (unsigned int)clks[0];
82}
83
84static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,
85 unsigned long parent_rate)
86{
87 unsigned long ac97_div, rate;
88
89 ac97_div = AC97_DIV;
90
91 /* This may loose precision for some rates but won't for the
92 * standard 24.576MHz.
93 */
94 rate = parent_rate / 2;
95 rate /= ((ac97_div >> 12) & 0x7fff);
96 rate *= (ac97_div & 0xfff);
97
98 return rate;
99}
100PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
101RATE_RO_OPS(clk_pxa3xx_ac97, "ac97");
102
103static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw,
104 unsigned long parent_rate)
105{
106 unsigned long acsr = ACSR;
107 unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
108
109 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] /
110 df_clkdiv[(memclkcfg >> 16) & 0x3];
111}
112PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
113RATE_RO_OPS(clk_pxa3xx_smemc, "smemc");
114
115static bool pxa3xx_is_ring_osc_forced(void)
116{
117 unsigned long acsr = ACSR;
118
119 return acsr & ACCR_D0CS;
120}
121
122PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
123PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
124PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
125PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
126PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
127PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
128
129#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENA : &CKENB)
130#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp, \
131 div_hp, bit, is_lp, flags) \
132 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
133 mult_hp, div_hp, is_lp, CKEN_AB(bit), \
134 (CKEN_ ## bit % 32), flags)
135#define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp, \
136 mult_hp, div_hp, delay) \
137 PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp, \
138 div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0)
139#define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents) \
140 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
141 CKEN_AB(bit), (CKEN_ ## bit % 32), 0)
142
143static struct desc_clk_cken pxa3xx_clocks[] __initdata = {
144 PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1),
145 PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1),
146 PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1),
147 PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0),
148 PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
149 PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0),
150 PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0),
151 PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
152 PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
153 PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0),
154 PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0),
155 PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0),
156
157 PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
158 pxa3xx_32Khz_bus_parents),
159 PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
160 PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents),
161 PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents),
162 PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents),
163
164 PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97,
165 pxa3xx_is_ring_osc_forced, 0),
166 PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA,
167 pxa3xx_is_ring_osc_forced, 0),
168 PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD,
169 pxa3xx_is_ring_osc_forced, 0),
170 PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4,
171 1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED),
172};
173
174static struct desc_clk_cken pxa300_310_clocks[] __initdata = {
175
176 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
177 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
178 PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
179};
180
181static struct desc_clk_cken pxa320_clocks[] __initdata = {
182 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0),
183 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0),
184 PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
185};
186
187static struct desc_clk_cken pxa93x_clocks[] __initdata = {
188
189 PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
190 PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
191 PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
192};
193
194static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw,
195 unsigned long parent_rate)
196{
197 unsigned long acsr = ACSR;
198 unsigned int hss = (acsr >> 14) & 0x3;
199
200 if (pxa3xx_is_ring_osc_forced())
201 return parent_rate;
202 return parent_rate / 48 * hss_mult[hss];
203}
204
205static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw)
206{
207 if (pxa3xx_is_ring_osc_forced())
208 return PXA_BUS_60Mhz;
209 else
210 return PXA_BUS_HSS;
211}
212
213PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" };
214MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus");
215
216static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw,
217 unsigned long parent_rate)
218{
219 return parent_rate;
220}
221
222static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw)
223{
224 unsigned long xclkcfg;
225 unsigned int t;
226
227 if (pxa3xx_is_ring_osc_forced())
228 return PXA_CORE_60Mhz;
229
230 /* Read XCLKCFG register turbo bit */
231 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
232 t = xclkcfg & 0x1;
233
234 if (t)
235 return PXA_CORE_TURBO;
236 return PXA_CORE_RUN;
237}
238PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" };
239MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core");
240
241static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw,
242 unsigned long parent_rate)
243{
244 unsigned long acsr = ACSR;
245 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
246 unsigned int t, xclkcfg;
247
248 /* Read XCLKCFG register turbo bit */
249 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
250 t = xclkcfg & 0x1;
251
252 return t ? (parent_rate / xn) * 2 : parent_rate;
253}
254PARENTS(clk_pxa3xx_run) = { "cpll" };
255RATE_RO_OPS(clk_pxa3xx_run, "run");
256
257static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw,
258 unsigned long parent_rate)
259{
260 unsigned long acsr = ACSR;
261 unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
262 unsigned int xl = acsr & ACCR_XL_MASK;
263 unsigned int t, xclkcfg;
264
265 /* Read XCLKCFG register turbo bit */
266 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
267 t = xclkcfg & 0x1;
268
269 pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn);
270 return t ? parent_rate * xl * xn : parent_rate * xl;
271}
272PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" };
273RATE_RO_OPS(clk_pxa3xx_cpll, "cpll");
274
275static void __init pxa3xx_register_core(void)
276{
277 clk_register_clk_pxa3xx_cpll();
278 clk_register_clk_pxa3xx_run();
279
280 clkdev_pxa_register(CLK_CORE, "core", NULL,
281 clk_register_clk_pxa3xx_core());
282}
283
284static void __init pxa3xx_register_plls(void)
285{
286 clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
287 CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
288 13 * MHz);
289 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
290 CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
291 32768);
292 clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
293 CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
294 120 * MHz);
295 clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
296 clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
297 clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
298 0, 1, 2);
299}
300
301#define DUMMY_CLK(_con_id, _dev_id, _parent) \
302 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
303struct dummy_clk {
304 const char *con_id;
305 const char *dev_id;
306 const char *parent;
307};
308static struct dummy_clk dummy_clks[] __initdata = {
309 DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
310 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
311 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
312 DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
313};
314
315static void __init pxa3xx_dummy_clocks_init(void)
316{
317 struct clk *clk;
318 struct dummy_clk *d;
319 const char *name;
320 int i;
321
322 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
323 d = &dummy_clks[i];
324 name = d->dev_id ? d->dev_id : d->con_id;
325 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
326 clk_register_clkdev(clk, d->con_id, d->dev_id);
327 }
328}
329
330static void __init pxa3xx_base_clocks_init(void)
331{
332 pxa3xx_register_plls();
333 pxa3xx_register_core();
334 clk_register_clk_pxa3xx_system_bus();
335 clk_register_clk_pxa3xx_ac97();
336 clk_register_clk_pxa3xx_smemc();
337 clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0,
338 (void __iomem *)&OSCC, 11, 0, NULL);
339}
340
341int __init pxa3xx_clocks_init(void)
342{
343 int ret;
344
345 pxa3xx_base_clocks_init();
346 pxa3xx_dummy_clocks_init();
347 ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks));
348 if (ret)
349 return ret;
350 if (cpu_is_pxa320())
351 return clk_pxa_cken_init(pxa320_clocks,
352 ARRAY_SIZE(pxa320_clocks));
353 if (cpu_is_pxa300() || cpu_is_pxa310())
354 return clk_pxa_cken_init(pxa300_310_clocks,
355 ARRAY_SIZE(pxa300_310_clocks));
356 return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks));
357}
358
359static void __init pxa3xx_dt_clocks_init(struct device_node *np)
360{
361 pxa3xx_clocks_init();
362 clk_pxa_dt_common_init(np);
363}
364CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 1107351ed346..0d7ab52b7ab0 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -29,6 +29,15 @@ config IPQ_GCC_806X
29 Say Y if you want to use peripheral devices such as UART, SPI, 29 Say Y if you want to use peripheral devices such as UART, SPI,
30 i2c, USB, SD/eMMC, etc. 30 i2c, USB, SD/eMMC, etc.
31 31
32config IPQ_LCC_806X
33 tristate "IPQ806x LPASS Clock Controller"
34 select IPQ_GCC_806X
35 depends on COMMON_CLK_QCOM
36 help
37 Support for the LPASS clock controller on ipq806x devices.
38 Say Y if you want to use audio devices such as i2s, pcm,
39 S/PDIF, etc.
40
32config MSM_GCC_8660 41config MSM_GCC_8660
33 tristate "MSM8660 Global Clock Controller" 42 tristate "MSM8660 Global Clock Controller"
34 depends on COMMON_CLK_QCOM 43 depends on COMMON_CLK_QCOM
@@ -45,6 +54,15 @@ config MSM_GCC_8960
45 Say Y if you want to use peripheral devices such as UART, SPI, 54 Say Y if you want to use peripheral devices such as UART, SPI,
46 i2c, USB, SD/eMMC, SATA, PCIe, etc. 55 i2c, USB, SD/eMMC, SATA, PCIe, etc.
47 56
57config MSM_LCC_8960
58 tristate "APQ8064/MSM8960 LPASS Clock Controller"
59 select MSM_GCC_8960
60 depends on COMMON_CLK_QCOM
61 help
62 Support for the LPASS clock controller on apq8064/msm8960 devices.
63 Say Y if you want to use audio devices such as i2s, pcm,
64 SLIMBus, etc.
65
48config MSM_MMCC_8960 66config MSM_MMCC_8960
49 tristate "MSM8960 Multimedia Clock Controller" 67 tristate "MSM8960 Multimedia Clock Controller"
50 select MSM_GCC_8960 68 select MSM_GCC_8960
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 783cfb24faa4..617826469595 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -6,13 +6,17 @@ clk-qcom-y += clk-pll.o
6clk-qcom-y += clk-rcg.o 6clk-qcom-y += clk-rcg.o
7clk-qcom-y += clk-rcg2.o 7clk-qcom-y += clk-rcg2.o
8clk-qcom-y += clk-branch.o 8clk-qcom-y += clk-branch.o
9clk-qcom-y += clk-regmap-divider.o
10clk-qcom-y += clk-regmap-mux.o
9clk-qcom-y += reset.o 11clk-qcom-y += reset.o
10 12
11obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o 13obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
12obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o 14obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
13obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o 15obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
16obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
14obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o 17obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
15obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 18obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
19obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
16obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 20obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
17obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o 21obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
18obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o 22obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 60873a7f45d9..b4325f65a1bf 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -141,6 +141,7 @@ struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
141 141
142static long 142static long
143clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate, 143clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
144 unsigned long min_rate, unsigned long max_rate,
144 unsigned long *p_rate, struct clk_hw **p) 145 unsigned long *p_rate, struct clk_hw **p)
145{ 146{
146 struct clk_pll *pll = to_clk_pll(hw); 147 struct clk_pll *pll = to_clk_pll(hw);
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 0b93972c8807..0039bd7d3965 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -368,6 +368,7 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
368 368
369static long _freq_tbl_determine_rate(struct clk_hw *hw, 369static long _freq_tbl_determine_rate(struct clk_hw *hw,
370 const struct freq_tbl *f, unsigned long rate, 370 const struct freq_tbl *f, unsigned long rate,
371 unsigned long min_rate, unsigned long max_rate,
371 unsigned long *p_rate, struct clk_hw **p_hw) 372 unsigned long *p_rate, struct clk_hw **p_hw)
372{ 373{
373 unsigned long clk_flags; 374 unsigned long clk_flags;
@@ -397,22 +398,27 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
397} 398}
398 399
399static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, 400static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
401 unsigned long min_rate, unsigned long max_rate,
400 unsigned long *p_rate, struct clk_hw **p) 402 unsigned long *p_rate, struct clk_hw **p)
401{ 403{
402 struct clk_rcg *rcg = to_clk_rcg(hw); 404 struct clk_rcg *rcg = to_clk_rcg(hw);
403 405
404 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p); 406 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
407 max_rate, p_rate, p);
405} 408}
406 409
407static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, 410static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
411 unsigned long min_rate, unsigned long max_rate,
408 unsigned long *p_rate, struct clk_hw **p) 412 unsigned long *p_rate, struct clk_hw **p)
409{ 413{
410 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); 414 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
411 415
412 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p); 416 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
417 max_rate, p_rate, p);
413} 418}
414 419
415static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate, 420static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long min_rate, unsigned long max_rate,
416 unsigned long *p_rate, struct clk_hw **p_hw) 422 unsigned long *p_rate, struct clk_hw **p_hw)
417{ 423{
418 struct clk_rcg *rcg = to_clk_rcg(hw); 424 struct clk_rcg *rcg = to_clk_rcg(hw);
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 08b8b3729f53..742acfa18d63 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -208,6 +208,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
208} 208}
209 209
210static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, 210static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
211 unsigned long min_rate, unsigned long max_rate,
211 unsigned long *p_rate, struct clk_hw **p) 212 unsigned long *p_rate, struct clk_hw **p)
212{ 213{
213 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 214 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -361,6 +362,8 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
361} 362}
362 363
363static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, 364static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
365 unsigned long min_rate,
366 unsigned long max_rate,
364 unsigned long *p_rate, struct clk_hw **p) 367 unsigned long *p_rate, struct clk_hw **p)
365{ 368{
366 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 369 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -412,6 +415,7 @@ const struct clk_ops clk_edp_pixel_ops = {
412EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); 415EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
413 416
414static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate, 417static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
418 unsigned long min_rate, unsigned long max_rate,
415 unsigned long *p_rate, struct clk_hw **p_hw) 419 unsigned long *p_rate, struct clk_hw **p_hw)
416{ 420{
417 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 421 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -476,6 +480,8 @@ static const struct frac_entry frac_table_pixel[] = {
476}; 480};
477 481
478static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, 482static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
483 unsigned long min_rate,
484 unsigned long max_rate,
479 unsigned long *p_rate, struct clk_hw **p) 485 unsigned long *p_rate, struct clk_hw **p)
480{ 486{
481 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 487 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
new file mode 100644
index 000000000000..53484912301e
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-divider.c
@@ -0,0 +1,70 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/regmap.h>
17#include <linux/export.h>
18
19#include "clk-regmap-divider.h"
20
21static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
22{
23 return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
24}
25
26static long div_round_rate(struct clk_hw *hw, unsigned long rate,
27 unsigned long *prate)
28{
29 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
30
31 return divider_round_rate(hw, rate, prate, NULL, divider->width,
32 CLK_DIVIDER_ROUND_CLOSEST);
33}
34
35static int div_set_rate(struct clk_hw *hw, unsigned long rate,
36 unsigned long parent_rate)
37{
38 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
39 struct clk_regmap *clkr = &divider->clkr;
40 u32 div;
41
42 div = divider_get_val(rate, parent_rate, NULL, divider->width,
43 CLK_DIVIDER_ROUND_CLOSEST);
44
45 return regmap_update_bits(clkr->regmap, divider->reg,
46 (BIT(divider->width) - 1) << divider->shift,
47 div << divider->shift);
48}
49
50static unsigned long div_recalc_rate(struct clk_hw *hw,
51 unsigned long parent_rate)
52{
53 struct clk_regmap_div *divider = to_clk_regmap_div(hw);
54 struct clk_regmap *clkr = &divider->clkr;
55 u32 div;
56
57 regmap_read(clkr->regmap, divider->reg, &div);
58 div >>= divider->shift;
59 div &= BIT(divider->width) - 1;
60
61 return divider_recalc_rate(hw, parent_rate, div, NULL,
62 CLK_DIVIDER_ROUND_CLOSEST);
63}
64
65const struct clk_ops clk_regmap_div_ops = {
66 .round_rate = div_round_rate,
67 .set_rate = div_set_rate,
68 .recalc_rate = div_recalc_rate,
69};
70EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
diff --git a/drivers/clk/qcom/clk-regmap-divider.h b/drivers/clk/qcom/clk-regmap-divider.h
new file mode 100644
index 000000000000..fc4492e3a827
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-divider.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_REGMAP_DIVIDER_H__
15#define __QCOM_CLK_REGMAP_DIVIDER_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20struct clk_regmap_div {
21 u32 reg;
22 u32 shift;
23 u32 width;
24 struct clk_regmap clkr;
25};
26
27extern const struct clk_ops clk_regmap_div_ops;
28
29#endif
diff --git a/drivers/clk/qcom/clk-regmap-mux.c b/drivers/clk/qcom/clk-regmap-mux.c
new file mode 100644
index 000000000000..cae3071f384c
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux.c
@@ -0,0 +1,59 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/regmap.h>
17#include <linux/export.h>
18
19#include "clk-regmap-mux.h"
20
21static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw)
22{
23 return container_of(to_clk_regmap(hw), struct clk_regmap_mux, clkr);
24}
25
26static u8 mux_get_parent(struct clk_hw *hw)
27{
28 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
29 struct clk_regmap *clkr = to_clk_regmap(hw);
30 unsigned int mask = GENMASK(mux->width - 1, 0);
31 unsigned int val;
32
33 regmap_read(clkr->regmap, mux->reg, &val);
34
35 val >>= mux->shift;
36 val &= mask;
37
38 return val;
39}
40
41static int mux_set_parent(struct clk_hw *hw, u8 index)
42{
43 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
44 struct clk_regmap *clkr = to_clk_regmap(hw);
45 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
46 unsigned int val;
47
48 val = index;
49 val <<= mux->shift;
50
51 return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
52}
53
54const struct clk_ops clk_regmap_mux_closest_ops = {
55 .get_parent = mux_get_parent,
56 .set_parent = mux_set_parent,
57 .determine_rate = __clk_mux_determine_rate_closest,
58};
59EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);
diff --git a/drivers/clk/qcom/clk-regmap-mux.h b/drivers/clk/qcom/clk-regmap-mux.h
new file mode 100644
index 000000000000..5cec76154fda
--- /dev/null
+++ b/drivers/clk/qcom/clk-regmap-mux.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_REGMAP_MUX_H__
15#define __QCOM_CLK_REGMAP_MUX_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20struct clk_regmap_mux {
21 u32 reg;
22 u32 shift;
23 u32 width;
24 struct clk_regmap clkr;
25};
26
27extern const struct clk_ops clk_regmap_mux_closest_ops;
28
29#endif
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index afed5eb0691e..cbdc31dea7f4 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -75,6 +75,17 @@ static struct clk_pll pll3 = {
75 }, 75 },
76}; 76};
77 77
78static struct clk_regmap pll4_vote = {
79 .enable_reg = 0x34c0,
80 .enable_mask = BIT(4),
81 .hw.init = &(struct clk_init_data){
82 .name = "pll4_vote",
83 .parent_names = (const char *[]){ "pll4" },
84 .num_parents = 1,
85 .ops = &clk_pll_vote_ops,
86 },
87};
88
78static struct clk_pll pll8 = { 89static struct clk_pll pll8 = {
79 .l_reg = 0x3144, 90 .l_reg = 0x3144,
80 .m_reg = 0x3148, 91 .m_reg = 0x3148,
@@ -2163,6 +2174,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
2163 [PLL0] = &pll0.clkr, 2174 [PLL0] = &pll0.clkr,
2164 [PLL0_VOTE] = &pll0_vote, 2175 [PLL0_VOTE] = &pll0_vote,
2165 [PLL3] = &pll3.clkr, 2176 [PLL3] = &pll3.clkr,
2177 [PLL4_VOTE] = &pll4_vote,
2166 [PLL8] = &pll8.clkr, 2178 [PLL8] = &pll8.clkr,
2167 [PLL8_VOTE] = &pll8_vote, 2179 [PLL8_VOTE] = &pll8_vote,
2168 [PLL14] = &pll14.clkr, 2180 [PLL14] = &pll14.clkr,
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
new file mode 100644
index 000000000000..121ffde25dc3
--- /dev/null
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -0,0 +1,473 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23
24#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
25
26#include "common.h"
27#include "clk-regmap.h"
28#include "clk-pll.h"
29#include "clk-rcg.h"
30#include "clk-branch.h"
31#include "clk-regmap-divider.h"
32#include "clk-regmap-mux.h"
33
34static struct clk_pll pll4 = {
35 .l_reg = 0x4,
36 .m_reg = 0x8,
37 .n_reg = 0xc,
38 .config_reg = 0x14,
39 .mode_reg = 0x0,
40 .status_reg = 0x18,
41 .status_bit = 16,
42 .clkr.hw.init = &(struct clk_init_data){
43 .name = "pll4",
44 .parent_names = (const char *[]){ "pxo" },
45 .num_parents = 1,
46 .ops = &clk_pll_ops,
47 },
48};
49
50static const struct pll_config pll4_config = {
51 .l = 0xf,
52 .m = 0x91,
53 .n = 0xc7,
54 .vco_val = 0x0,
55 .vco_mask = BIT(17) | BIT(16),
56 .pre_div_val = 0x0,
57 .pre_div_mask = BIT(19),
58 .post_div_val = 0x0,
59 .post_div_mask = BIT(21) | BIT(20),
60 .mn_ena_mask = BIT(22),
61 .main_output_mask = BIT(23),
62};
63
64#define P_PXO 0
65#define P_PLL4 1
66
67static const u8 lcc_pxo_pll4_map[] = {
68 [P_PXO] = 0,
69 [P_PLL4] = 2,
70};
71
72static const char *lcc_pxo_pll4[] = {
73 "pxo",
74 "pll4_vote",
75};
76
77static struct freq_tbl clk_tbl_aif_mi2s[] = {
78 { 1024000, P_PLL4, 4, 1, 96 },
79 { 1411200, P_PLL4, 4, 2, 139 },
80 { 1536000, P_PLL4, 4, 1, 64 },
81 { 2048000, P_PLL4, 4, 1, 48 },
82 { 2116800, P_PLL4, 4, 2, 93 },
83 { 2304000, P_PLL4, 4, 2, 85 },
84 { 2822400, P_PLL4, 4, 6, 209 },
85 { 3072000, P_PLL4, 4, 1, 32 },
86 { 3175200, P_PLL4, 4, 1, 31 },
87 { 4096000, P_PLL4, 4, 1, 24 },
88 { 4233600, P_PLL4, 4, 9, 209 },
89 { 4608000, P_PLL4, 4, 3, 64 },
90 { 5644800, P_PLL4, 4, 12, 209 },
91 { 6144000, P_PLL4, 4, 1, 16 },
92 { 6350400, P_PLL4, 4, 2, 31 },
93 { 8192000, P_PLL4, 4, 1, 12 },
94 { 8467200, P_PLL4, 4, 18, 209 },
95 { 9216000, P_PLL4, 4, 3, 32 },
96 { 11289600, P_PLL4, 4, 24, 209 },
97 { 12288000, P_PLL4, 4, 1, 8 },
98 { 12700800, P_PLL4, 4, 27, 209 },
99 { 13824000, P_PLL4, 4, 9, 64 },
100 { 16384000, P_PLL4, 4, 1, 6 },
101 { 16934400, P_PLL4, 4, 41, 238 },
102 { 18432000, P_PLL4, 4, 3, 16 },
103 { 22579200, P_PLL4, 2, 24, 209 },
104 { 24576000, P_PLL4, 4, 1, 4 },
105 { 27648000, P_PLL4, 4, 9, 32 },
106 { 33868800, P_PLL4, 4, 41, 119 },
107 { 36864000, P_PLL4, 4, 3, 8 },
108 { 45158400, P_PLL4, 1, 24, 209 },
109 { 49152000, P_PLL4, 4, 1, 2 },
110 { 50803200, P_PLL4, 1, 27, 209 },
111 { }
112};
113
114static struct clk_rcg mi2s_osr_src = {
115 .ns_reg = 0x48,
116 .md_reg = 0x4c,
117 .mn = {
118 .mnctr_en_bit = 8,
119 .mnctr_reset_bit = 7,
120 .mnctr_mode_shift = 5,
121 .n_val_shift = 24,
122 .m_val_shift = 8,
123 .width = 8,
124 },
125 .p = {
126 .pre_div_shift = 3,
127 .pre_div_width = 2,
128 },
129 .s = {
130 .src_sel_shift = 0,
131 .parent_map = lcc_pxo_pll4_map,
132 },
133 .freq_tbl = clk_tbl_aif_mi2s,
134 .clkr = {
135 .enable_reg = 0x48,
136 .enable_mask = BIT(9),
137 .hw.init = &(struct clk_init_data){
138 .name = "mi2s_osr_src",
139 .parent_names = lcc_pxo_pll4,
140 .num_parents = 2,
141 .ops = &clk_rcg_ops,
142 .flags = CLK_SET_RATE_GATE,
143 },
144 },
145};
146
147static const char *lcc_mi2s_parents[] = {
148 "mi2s_osr_src",
149};
150
151static struct clk_branch mi2s_osr_clk = {
152 .halt_reg = 0x50,
153 .halt_bit = 1,
154 .halt_check = BRANCH_HALT_ENABLE,
155 .clkr = {
156 .enable_reg = 0x48,
157 .enable_mask = BIT(17),
158 .hw.init = &(struct clk_init_data){
159 .name = "mi2s_osr_clk",
160 .parent_names = lcc_mi2s_parents,
161 .num_parents = 1,
162 .ops = &clk_branch_ops,
163 .flags = CLK_SET_RATE_PARENT,
164 },
165 },
166};
167
168static struct clk_regmap_div mi2s_div_clk = {
169 .reg = 0x48,
170 .shift = 10,
171 .width = 4,
172 .clkr = {
173 .hw.init = &(struct clk_init_data){
174 .name = "mi2s_div_clk",
175 .parent_names = lcc_mi2s_parents,
176 .num_parents = 1,
177 .ops = &clk_regmap_div_ops,
178 },
179 },
180};
181
182static struct clk_branch mi2s_bit_div_clk = {
183 .halt_reg = 0x50,
184 .halt_bit = 0,
185 .halt_check = BRANCH_HALT_ENABLE,
186 .clkr = {
187 .enable_reg = 0x48,
188 .enable_mask = BIT(15),
189 .hw.init = &(struct clk_init_data){
190 .name = "mi2s_bit_div_clk",
191 .parent_names = (const char *[]){ "mi2s_div_clk" },
192 .num_parents = 1,
193 .ops = &clk_branch_ops,
194 .flags = CLK_SET_RATE_PARENT,
195 },
196 },
197};
198
199
200static struct clk_regmap_mux mi2s_bit_clk = {
201 .reg = 0x48,
202 .shift = 14,
203 .width = 1,
204 .clkr = {
205 .hw.init = &(struct clk_init_data){
206 .name = "mi2s_bit_clk",
207 .parent_names = (const char *[]){
208 "mi2s_bit_div_clk",
209 "mi2s_codec_clk",
210 },
211 .num_parents = 2,
212 .ops = &clk_regmap_mux_closest_ops,
213 .flags = CLK_SET_RATE_PARENT,
214 },
215 },
216};
217
218static struct freq_tbl clk_tbl_pcm[] = {
219 { 64000, P_PLL4, 4, 1, 1536 },
220 { 128000, P_PLL4, 4, 1, 768 },
221 { 256000, P_PLL4, 4, 1, 384 },
222 { 512000, P_PLL4, 4, 1, 192 },
223 { 1024000, P_PLL4, 4, 1, 96 },
224 { 2048000, P_PLL4, 4, 1, 48 },
225 { },
226};
227
228static struct clk_rcg pcm_src = {
229 .ns_reg = 0x54,
230 .md_reg = 0x58,
231 .mn = {
232 .mnctr_en_bit = 8,
233 .mnctr_reset_bit = 7,
234 .mnctr_mode_shift = 5,
235 .n_val_shift = 16,
236 .m_val_shift = 16,
237 .width = 16,
238 },
239 .p = {
240 .pre_div_shift = 3,
241 .pre_div_width = 2,
242 },
243 .s = {
244 .src_sel_shift = 0,
245 .parent_map = lcc_pxo_pll4_map,
246 },
247 .freq_tbl = clk_tbl_pcm,
248 .clkr = {
249 .enable_reg = 0x54,
250 .enable_mask = BIT(9),
251 .hw.init = &(struct clk_init_data){
252 .name = "pcm_src",
253 .parent_names = lcc_pxo_pll4,
254 .num_parents = 2,
255 .ops = &clk_rcg_ops,
256 .flags = CLK_SET_RATE_GATE,
257 },
258 },
259};
260
261static struct clk_branch pcm_clk_out = {
262 .halt_reg = 0x5c,
263 .halt_bit = 0,
264 .halt_check = BRANCH_HALT_ENABLE,
265 .clkr = {
266 .enable_reg = 0x54,
267 .enable_mask = BIT(11),
268 .hw.init = &(struct clk_init_data){
269 .name = "pcm_clk_out",
270 .parent_names = (const char *[]){ "pcm_src" },
271 .num_parents = 1,
272 .ops = &clk_branch_ops,
273 .flags = CLK_SET_RATE_PARENT,
274 },
275 },
276};
277
278static struct clk_regmap_mux pcm_clk = {
279 .reg = 0x54,
280 .shift = 10,
281 .width = 1,
282 .clkr = {
283 .hw.init = &(struct clk_init_data){
284 .name = "pcm_clk",
285 .parent_names = (const char *[]){
286 "pcm_clk_out",
287 "pcm_codec_clk",
288 },
289 .num_parents = 2,
290 .ops = &clk_regmap_mux_closest_ops,
291 .flags = CLK_SET_RATE_PARENT,
292 },
293 },
294};
295
296static struct freq_tbl clk_tbl_aif_osr[] = {
297 { 22050, P_PLL4, 1, 147, 20480 },
298 { 32000, P_PLL4, 1, 1, 96 },
299 { 44100, P_PLL4, 1, 147, 10240 },
300 { 48000, P_PLL4, 1, 1, 64 },
301 { 88200, P_PLL4, 1, 147, 5120 },
302 { 96000, P_PLL4, 1, 1, 32 },
303 { 176400, P_PLL4, 1, 147, 2560 },
304 { 192000, P_PLL4, 1, 1, 16 },
305 { },
306};
307
308static struct clk_rcg spdif_src = {
309 .ns_reg = 0xcc,
310 .md_reg = 0xd0,
311 .mn = {
312 .mnctr_en_bit = 8,
313 .mnctr_reset_bit = 7,
314 .mnctr_mode_shift = 5,
315 .n_val_shift = 16,
316 .m_val_shift = 16,
317 .width = 8,
318 },
319 .p = {
320 .pre_div_shift = 3,
321 .pre_div_width = 2,
322 },
323 .s = {
324 .src_sel_shift = 0,
325 .parent_map = lcc_pxo_pll4_map,
326 },
327 .freq_tbl = clk_tbl_aif_osr,
328 .clkr = {
329 .enable_reg = 0xcc,
330 .enable_mask = BIT(9),
331 .hw.init = &(struct clk_init_data){
332 .name = "spdif_src",
333 .parent_names = lcc_pxo_pll4,
334 .num_parents = 2,
335 .ops = &clk_rcg_ops,
336 .flags = CLK_SET_RATE_GATE,
337 },
338 },
339};
340
341static const char *lcc_spdif_parents[] = {
342 "spdif_src",
343};
344
345static struct clk_branch spdif_clk = {
346 .halt_reg = 0xd4,
347 .halt_bit = 1,
348 .halt_check = BRANCH_HALT_ENABLE,
349 .clkr = {
350 .enable_reg = 0xcc,
351 .enable_mask = BIT(12),
352 .hw.init = &(struct clk_init_data){
353 .name = "spdif_clk",
354 .parent_names = lcc_spdif_parents,
355 .num_parents = 1,
356 .ops = &clk_branch_ops,
357 .flags = CLK_SET_RATE_PARENT,
358 },
359 },
360};
361
362static struct freq_tbl clk_tbl_ahbix[] = {
363 { 131072, P_PLL4, 1, 1, 3 },
364 { },
365};
366
367static struct clk_rcg ahbix_clk = {
368 .ns_reg = 0x38,
369 .md_reg = 0x3c,
370 .mn = {
371 .mnctr_en_bit = 8,
372 .mnctr_reset_bit = 7,
373 .mnctr_mode_shift = 5,
374 .n_val_shift = 24,
375 .m_val_shift = 8,
376 .width = 8,
377 },
378 .p = {
379 .pre_div_shift = 3,
380 .pre_div_width = 2,
381 },
382 .s = {
383 .src_sel_shift = 0,
384 .parent_map = lcc_pxo_pll4_map,
385 },
386 .freq_tbl = clk_tbl_ahbix,
387 .clkr = {
388 .enable_reg = 0x38,
389 .enable_mask = BIT(10), /* toggle the gfmux to select mn/pxo */
390 .hw.init = &(struct clk_init_data){
391 .name = "ahbix",
392 .parent_names = lcc_pxo_pll4,
393 .num_parents = 2,
394 .ops = &clk_rcg_ops,
395 .flags = CLK_SET_RATE_GATE,
396 },
397 },
398};
399
400static struct clk_regmap *lcc_ipq806x_clks[] = {
401 [PLL4] = &pll4.clkr,
402 [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
403 [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
404 [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
405 [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
406 [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
407 [PCM_SRC] = &pcm_src.clkr,
408 [PCM_CLK_OUT] = &pcm_clk_out.clkr,
409 [PCM_CLK] = &pcm_clk.clkr,
410 [SPDIF_SRC] = &spdif_src.clkr,
411 [SPDIF_CLK] = &spdif_clk.clkr,
412 [AHBIX_CLK] = &ahbix_clk.clkr,
413};
414
415static const struct regmap_config lcc_ipq806x_regmap_config = {
416 .reg_bits = 32,
417 .reg_stride = 4,
418 .val_bits = 32,
419 .max_register = 0xfc,
420 .fast_io = true,
421};
422
423static const struct qcom_cc_desc lcc_ipq806x_desc = {
424 .config = &lcc_ipq806x_regmap_config,
425 .clks = lcc_ipq806x_clks,
426 .num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
427};
428
429static const struct of_device_id lcc_ipq806x_match_table[] = {
430 { .compatible = "qcom,lcc-ipq8064" },
431 { }
432};
433MODULE_DEVICE_TABLE(of, lcc_ipq806x_match_table);
434
435static int lcc_ipq806x_probe(struct platform_device *pdev)
436{
437 u32 val;
438 struct regmap *regmap;
439
440 regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
441 if (IS_ERR(regmap))
442 return PTR_ERR(regmap);
443
444 /* Configure the rate of PLL4 if the bootloader hasn't already */
445 val = regmap_read(regmap, 0x0, &val);
446 if (!val)
447 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
448 /* Enable PLL4 source on the LPASS Primary PLL Mux */
449 regmap_write(regmap, 0xc4, 0x1);
450
451 return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
452}
453
454static int lcc_ipq806x_remove(struct platform_device *pdev)
455{
456 qcom_cc_remove(pdev);
457 return 0;
458}
459
460static struct platform_driver lcc_ipq806x_driver = {
461 .probe = lcc_ipq806x_probe,
462 .remove = lcc_ipq806x_remove,
463 .driver = {
464 .name = "lcc-ipq806x",
465 .owner = THIS_MODULE,
466 .of_match_table = lcc_ipq806x_match_table,
467 },
468};
469module_platform_driver(lcc_ipq806x_driver);
470
471MODULE_DESCRIPTION("QCOM LCC IPQ806x Driver");
472MODULE_LICENSE("GPL v2");
473MODULE_ALIAS("platform:lcc-ipq806x");
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
new file mode 100644
index 000000000000..a75a408cfccd
--- /dev/null
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -0,0 +1,585 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23
24#include <dt-bindings/clock/qcom,lcc-msm8960.h>
25
26#include "common.h"
27#include "clk-regmap.h"
28#include "clk-pll.h"
29#include "clk-rcg.h"
30#include "clk-branch.h"
31#include "clk-regmap-divider.h"
32#include "clk-regmap-mux.h"
33
34static struct clk_pll pll4 = {
35 .l_reg = 0x4,
36 .m_reg = 0x8,
37 .n_reg = 0xc,
38 .config_reg = 0x14,
39 .mode_reg = 0x0,
40 .status_reg = 0x18,
41 .status_bit = 16,
42 .clkr.hw.init = &(struct clk_init_data){
43 .name = "pll4",
44 .parent_names = (const char *[]){ "pxo" },
45 .num_parents = 1,
46 .ops = &clk_pll_ops,
47 },
48};
49
50#define P_PXO 0
51#define P_PLL4 1
52
53static const u8 lcc_pxo_pll4_map[] = {
54 [P_PXO] = 0,
55 [P_PLL4] = 2,
56};
57
58static const char *lcc_pxo_pll4[] = {
59 "pxo",
60 "pll4_vote",
61};
62
63static struct freq_tbl clk_tbl_aif_osr_492[] = {
64 { 512000, P_PLL4, 4, 1, 240 },
65 { 768000, P_PLL4, 4, 1, 160 },
66 { 1024000, P_PLL4, 4, 1, 120 },
67 { 1536000, P_PLL4, 4, 1, 80 },
68 { 2048000, P_PLL4, 4, 1, 60 },
69 { 3072000, P_PLL4, 4, 1, 40 },
70 { 4096000, P_PLL4, 4, 1, 30 },
71 { 6144000, P_PLL4, 4, 1, 20 },
72 { 8192000, P_PLL4, 4, 1, 15 },
73 { 12288000, P_PLL4, 4, 1, 10 },
74 { 24576000, P_PLL4, 4, 1, 5 },
75 { 27000000, P_PXO, 1, 0, 0 },
76 { }
77};
78
79static struct freq_tbl clk_tbl_aif_osr_393[] = {
80 { 512000, P_PLL4, 4, 1, 192 },
81 { 768000, P_PLL4, 4, 1, 128 },
82 { 1024000, P_PLL4, 4, 1, 96 },
83 { 1536000, P_PLL4, 4, 1, 64 },
84 { 2048000, P_PLL4, 4, 1, 48 },
85 { 3072000, P_PLL4, 4, 1, 32 },
86 { 4096000, P_PLL4, 4, 1, 24 },
87 { 6144000, P_PLL4, 4, 1, 16 },
88 { 8192000, P_PLL4, 4, 1, 12 },
89 { 12288000, P_PLL4, 4, 1, 8 },
90 { 24576000, P_PLL4, 4, 1, 4 },
91 { 27000000, P_PXO, 1, 0, 0 },
92 { }
93};
94
95static struct clk_rcg mi2s_osr_src = {
96 .ns_reg = 0x48,
97 .md_reg = 0x4c,
98 .mn = {
99 .mnctr_en_bit = 8,
100 .mnctr_reset_bit = 7,
101 .mnctr_mode_shift = 5,
102 .n_val_shift = 24,
103 .m_val_shift = 8,
104 .width = 8,
105 },
106 .p = {
107 .pre_div_shift = 3,
108 .pre_div_width = 2,
109 },
110 .s = {
111 .src_sel_shift = 0,
112 .parent_map = lcc_pxo_pll4_map,
113 },
114 .freq_tbl = clk_tbl_aif_osr_393,
115 .clkr = {
116 .enable_reg = 0x48,
117 .enable_mask = BIT(9),
118 .hw.init = &(struct clk_init_data){
119 .name = "mi2s_osr_src",
120 .parent_names = lcc_pxo_pll4,
121 .num_parents = 2,
122 .ops = &clk_rcg_ops,
123 .flags = CLK_SET_RATE_GATE,
124 },
125 },
126};
127
128static const char *lcc_mi2s_parents[] = {
129 "mi2s_osr_src",
130};
131
132static struct clk_branch mi2s_osr_clk = {
133 .halt_reg = 0x50,
134 .halt_bit = 1,
135 .halt_check = BRANCH_HALT_ENABLE,
136 .clkr = {
137 .enable_reg = 0x48,
138 .enable_mask = BIT(17),
139 .hw.init = &(struct clk_init_data){
140 .name = "mi2s_osr_clk",
141 .parent_names = lcc_mi2s_parents,
142 .num_parents = 1,
143 .ops = &clk_branch_ops,
144 .flags = CLK_SET_RATE_PARENT,
145 },
146 },
147};
148
149static struct clk_regmap_div mi2s_div_clk = {
150 .reg = 0x48,
151 .shift = 10,
152 .width = 4,
153 .clkr = {
154 .enable_reg = 0x48,
155 .enable_mask = BIT(15),
156 .hw.init = &(struct clk_init_data){
157 .name = "mi2s_div_clk",
158 .parent_names = lcc_mi2s_parents,
159 .num_parents = 1,
160 .ops = &clk_regmap_div_ops,
161 },
162 },
163};
164
165static struct clk_branch mi2s_bit_div_clk = {
166 .halt_reg = 0x50,
167 .halt_bit = 0,
168 .halt_check = BRANCH_HALT_ENABLE,
169 .clkr = {
170 .enable_reg = 0x48,
171 .enable_mask = BIT(15),
172 .hw.init = &(struct clk_init_data){
173 .name = "mi2s_bit_div_clk",
174 .parent_names = (const char *[]){ "mi2s_div_clk" },
175 .num_parents = 1,
176 .ops = &clk_branch_ops,
177 .flags = CLK_SET_RATE_PARENT,
178 },
179 },
180};
181
182static struct clk_regmap_mux mi2s_bit_clk = {
183 .reg = 0x48,
184 .shift = 14,
185 .width = 1,
186 .clkr = {
187 .hw.init = &(struct clk_init_data){
188 .name = "mi2s_bit_clk",
189 .parent_names = (const char *[]){
190 "mi2s_bit_div_clk",
191 "mi2s_codec_clk",
192 },
193 .num_parents = 2,
194 .ops = &clk_regmap_mux_closest_ops,
195 .flags = CLK_SET_RATE_PARENT,
196 },
197 },
198};
199
200#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
201static struct clk_rcg prefix##_osr_src = { \
202 .ns_reg = _ns, \
203 .md_reg = _md, \
204 .mn = { \
205 .mnctr_en_bit = 8, \
206 .mnctr_reset_bit = 7, \
207 .mnctr_mode_shift = 5, \
208 .n_val_shift = 24, \
209 .m_val_shift = 8, \
210 .width = 8, \
211 }, \
212 .p = { \
213 .pre_div_shift = 3, \
214 .pre_div_width = 2, \
215 }, \
216 .s = { \
217 .src_sel_shift = 0, \
218 .parent_map = lcc_pxo_pll4_map, \
219 }, \
220 .freq_tbl = clk_tbl_aif_osr_393, \
221 .clkr = { \
222 .enable_reg = _ns, \
223 .enable_mask = BIT(9), \
224 .hw.init = &(struct clk_init_data){ \
225 .name = #prefix "_osr_src", \
226 .parent_names = lcc_pxo_pll4, \
227 .num_parents = 2, \
228 .ops = &clk_rcg_ops, \
229 .flags = CLK_SET_RATE_GATE, \
230 }, \
231 }, \
232}; \
233 \
234static const char *lcc_##prefix##_parents[] = { \
235 #prefix "_osr_src", \
236}; \
237 \
238static struct clk_branch prefix##_osr_clk = { \
239 .halt_reg = hr, \
240 .halt_bit = 1, \
241 .halt_check = BRANCH_HALT_ENABLE, \
242 .clkr = { \
243 .enable_reg = _ns, \
244 .enable_mask = BIT(21), \
245 .hw.init = &(struct clk_init_data){ \
246 .name = #prefix "_osr_clk", \
247 .parent_names = lcc_##prefix##_parents, \
248 .num_parents = 1, \
249 .ops = &clk_branch_ops, \
250 .flags = CLK_SET_RATE_PARENT, \
251 }, \
252 }, \
253}; \
254 \
255static struct clk_regmap_div prefix##_div_clk = { \
256 .reg = _ns, \
257 .shift = 10, \
258 .width = 8, \
259 .clkr = { \
260 .hw.init = &(struct clk_init_data){ \
261 .name = #prefix "_div_clk", \
262 .parent_names = lcc_##prefix##_parents, \
263 .num_parents = 1, \
264 .ops = &clk_regmap_div_ops, \
265 }, \
266 }, \
267}; \
268 \
269static struct clk_branch prefix##_bit_div_clk = { \
270 .halt_reg = hr, \
271 .halt_bit = 0, \
272 .halt_check = BRANCH_HALT_ENABLE, \
273 .clkr = { \
274 .enable_reg = _ns, \
275 .enable_mask = BIT(19), \
276 .hw.init = &(struct clk_init_data){ \
277 .name = #prefix "_bit_div_clk", \
278 .parent_names = (const char *[]){ \
279 #prefix "_div_clk" \
280 }, \
281 .num_parents = 1, \
282 .ops = &clk_branch_ops, \
283 .flags = CLK_SET_RATE_PARENT, \
284 }, \
285 }, \
286}; \
287 \
288static struct clk_regmap_mux prefix##_bit_clk = { \
289 .reg = _ns, \
290 .shift = 18, \
291 .width = 1, \
292 .clkr = { \
293 .hw.init = &(struct clk_init_data){ \
294 .name = #prefix "_bit_clk", \
295 .parent_names = (const char *[]){ \
296 #prefix "_bit_div_clk", \
297 #prefix "_codec_clk", \
298 }, \
299 .num_parents = 2, \
300 .ops = &clk_regmap_mux_closest_ops, \
301 .flags = CLK_SET_RATE_PARENT, \
302 }, \
303 }, \
304}
305
306CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
307CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
308CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
309CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
310
311static struct freq_tbl clk_tbl_pcm_492[] = {
312 { 256000, P_PLL4, 4, 1, 480 },
313 { 512000, P_PLL4, 4, 1, 240 },
314 { 768000, P_PLL4, 4, 1, 160 },
315 { 1024000, P_PLL4, 4, 1, 120 },
316 { 1536000, P_PLL4, 4, 1, 80 },
317 { 2048000, P_PLL4, 4, 1, 60 },
318 { 3072000, P_PLL4, 4, 1, 40 },
319 { 4096000, P_PLL4, 4, 1, 30 },
320 { 6144000, P_PLL4, 4, 1, 20 },
321 { 8192000, P_PLL4, 4, 1, 15 },
322 { 12288000, P_PLL4, 4, 1, 10 },
323 { 24576000, P_PLL4, 4, 1, 5 },
324 { 27000000, P_PXO, 1, 0, 0 },
325 { }
326};
327
328static struct freq_tbl clk_tbl_pcm_393[] = {
329 { 256000, P_PLL4, 4, 1, 384 },
330 { 512000, P_PLL4, 4, 1, 192 },
331 { 768000, P_PLL4, 4, 1, 128 },
332 { 1024000, P_PLL4, 4, 1, 96 },
333 { 1536000, P_PLL4, 4, 1, 64 },
334 { 2048000, P_PLL4, 4, 1, 48 },
335 { 3072000, P_PLL4, 4, 1, 32 },
336 { 4096000, P_PLL4, 4, 1, 24 },
337 { 6144000, P_PLL4, 4, 1, 16 },
338 { 8192000, P_PLL4, 4, 1, 12 },
339 { 12288000, P_PLL4, 4, 1, 8 },
340 { 24576000, P_PLL4, 4, 1, 4 },
341 { 27000000, P_PXO, 1, 0, 0 },
342 { }
343};
344
345static struct clk_rcg pcm_src = {
346 .ns_reg = 0x54,
347 .md_reg = 0x58,
348 .mn = {
349 .mnctr_en_bit = 8,
350 .mnctr_reset_bit = 7,
351 .mnctr_mode_shift = 5,
352 .n_val_shift = 16,
353 .m_val_shift = 16,
354 .width = 16,
355 },
356 .p = {
357 .pre_div_shift = 3,
358 .pre_div_width = 2,
359 },
360 .s = {
361 .src_sel_shift = 0,
362 .parent_map = lcc_pxo_pll4_map,
363 },
364 .freq_tbl = clk_tbl_pcm_393,
365 .clkr = {
366 .enable_reg = 0x54,
367 .enable_mask = BIT(9),
368 .hw.init = &(struct clk_init_data){
369 .name = "pcm_src",
370 .parent_names = lcc_pxo_pll4,
371 .num_parents = 2,
372 .ops = &clk_rcg_ops,
373 .flags = CLK_SET_RATE_GATE,
374 },
375 },
376};
377
378static struct clk_branch pcm_clk_out = {
379 .halt_reg = 0x5c,
380 .halt_bit = 0,
381 .halt_check = BRANCH_HALT_ENABLE,
382 .clkr = {
383 .enable_reg = 0x54,
384 .enable_mask = BIT(11),
385 .hw.init = &(struct clk_init_data){
386 .name = "pcm_clk_out",
387 .parent_names = (const char *[]){ "pcm_src" },
388 .num_parents = 1,
389 .ops = &clk_branch_ops,
390 .flags = CLK_SET_RATE_PARENT,
391 },
392 },
393};
394
395static struct clk_regmap_mux pcm_clk = {
396 .reg = 0x54,
397 .shift = 10,
398 .width = 1,
399 .clkr = {
400 .hw.init = &(struct clk_init_data){
401 .name = "pcm_clk",
402 .parent_names = (const char *[]){
403 "pcm_clk_out",
404 "pcm_codec_clk",
405 },
406 .num_parents = 2,
407 .ops = &clk_regmap_mux_closest_ops,
408 .flags = CLK_SET_RATE_PARENT,
409 },
410 },
411};
412
413static struct clk_rcg slimbus_src = {
414 .ns_reg = 0xcc,
415 .md_reg = 0xd0,
416 .mn = {
417 .mnctr_en_bit = 8,
418 .mnctr_reset_bit = 7,
419 .mnctr_mode_shift = 5,
420 .n_val_shift = 16,
421 .m_val_shift = 16,
422 .width = 8,
423 },
424 .p = {
425 .pre_div_shift = 3,
426 .pre_div_width = 2,
427 },
428 .s = {
429 .src_sel_shift = 0,
430 .parent_map = lcc_pxo_pll4_map,
431 },
432 .freq_tbl = clk_tbl_aif_osr_393,
433 .clkr = {
434 .enable_reg = 0xcc,
435 .enable_mask = BIT(9),
436 .hw.init = &(struct clk_init_data){
437 .name = "slimbus_src",
438 .parent_names = lcc_pxo_pll4,
439 .num_parents = 2,
440 .ops = &clk_rcg_ops,
441 .flags = CLK_SET_RATE_GATE,
442 },
443 },
444};
445
446static const char *lcc_slimbus_parents[] = {
447 "slimbus_src",
448};
449
450static struct clk_branch audio_slimbus_clk = {
451 .halt_reg = 0xd4,
452 .halt_bit = 0,
453 .halt_check = BRANCH_HALT_ENABLE,
454 .clkr = {
455 .enable_reg = 0xcc,
456 .enable_mask = BIT(10),
457 .hw.init = &(struct clk_init_data){
458 .name = "audio_slimbus_clk",
459 .parent_names = lcc_slimbus_parents,
460 .num_parents = 1,
461 .ops = &clk_branch_ops,
462 .flags = CLK_SET_RATE_PARENT,
463 },
464 },
465};
466
467static struct clk_branch sps_slimbus_clk = {
468 .halt_reg = 0xd4,
469 .halt_bit = 1,
470 .halt_check = BRANCH_HALT_ENABLE,
471 .clkr = {
472 .enable_reg = 0xcc,
473 .enable_mask = BIT(12),
474 .hw.init = &(struct clk_init_data){
475 .name = "sps_slimbus_clk",
476 .parent_names = lcc_slimbus_parents,
477 .num_parents = 1,
478 .ops = &clk_branch_ops,
479 .flags = CLK_SET_RATE_PARENT,
480 },
481 },
482};
483
484static struct clk_regmap *lcc_msm8960_clks[] = {
485 [PLL4] = &pll4.clkr,
486 [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
487 [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
488 [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
489 [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
490 [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
491 [PCM_SRC] = &pcm_src.clkr,
492 [PCM_CLK_OUT] = &pcm_clk_out.clkr,
493 [PCM_CLK] = &pcm_clk.clkr,
494 [SLIMBUS_SRC] = &slimbus_src.clkr,
495 [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
496 [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
497 [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
498 [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
499 [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
500 [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
501 [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
502 [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
503 [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
504 [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
505 [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
506 [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
507 [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
508 [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
509 [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
510 [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
511 [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
512 [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
513 [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
514 [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
515 [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
516 [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
517};
518
519static const struct regmap_config lcc_msm8960_regmap_config = {
520 .reg_bits = 32,
521 .reg_stride = 4,
522 .val_bits = 32,
523 .max_register = 0xfc,
524 .fast_io = true,
525};
526
527static const struct qcom_cc_desc lcc_msm8960_desc = {
528 .config = &lcc_msm8960_regmap_config,
529 .clks = lcc_msm8960_clks,
530 .num_clks = ARRAY_SIZE(lcc_msm8960_clks),
531};
532
533static const struct of_device_id lcc_msm8960_match_table[] = {
534 { .compatible = "qcom,lcc-msm8960" },
535 { .compatible = "qcom,lcc-apq8064" },
536 { }
537};
538MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table);
539
540static int lcc_msm8960_probe(struct platform_device *pdev)
541{
542 u32 val;
543 struct regmap *regmap;
544
545 regmap = qcom_cc_map(pdev, &lcc_msm8960_desc);
546 if (IS_ERR(regmap))
547 return PTR_ERR(regmap);
548
549 /* Use the correct frequency plan depending on speed of PLL4 */
550 val = regmap_read(regmap, 0x4, &val);
551 if (val == 0x12) {
552 slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
553 mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
554 codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
555 spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
556 codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
557 spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
558 pcm_src.freq_tbl = clk_tbl_pcm_492;
559 }
560 /* Enable PLL4 source on the LPASS Primary PLL Mux */
561 regmap_write(regmap, 0xc4, 0x1);
562
563 return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
564}
565
566static int lcc_msm8960_remove(struct platform_device *pdev)
567{
568 qcom_cc_remove(pdev);
569 return 0;
570}
571
572static struct platform_driver lcc_msm8960_driver = {
573 .probe = lcc_msm8960_probe,
574 .remove = lcc_msm8960_remove,
575 .driver = {
576 .name = "lcc-msm8960",
577 .owner = THIS_MODULE,
578 .of_match_table = lcc_msm8960_match_table,
579 },
580};
581module_platform_driver(lcc_msm8960_driver);
582
583MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver");
584MODULE_LICENSE("GPL v2");
585MODULE_ALIAS("platform:lcc-msm8960");
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index cbcddcc02475..05d7a0bc0599 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -535,44 +535,44 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
535 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0, 535 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
536 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS, 536 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
537 RK3288_CLKGATE_CON(1), 8, GFLAGS), 537 RK3288_CLKGATE_CON(1), 8, GFLAGS),
538 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0, 538 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
539 RK3288_CLKSEL_CON(17), 0, 539 RK3288_CLKSEL_CON(17), 0,
540 RK3288_CLKGATE_CON(1), 9, GFLAGS), 540 RK3288_CLKGATE_CON(1), 9, GFLAGS),
541 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, 0, 541 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
542 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS), 542 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS),
543 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0, 543 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
544 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS), 544 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
545 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0, 545 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
546 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS, 546 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
547 RK3288_CLKGATE_CON(1), 10, GFLAGS), 547 RK3288_CLKGATE_CON(1), 10, GFLAGS),
548 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", 0, 548 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
549 RK3288_CLKSEL_CON(18), 0, 549 RK3288_CLKSEL_CON(18), 0,
550 RK3288_CLKGATE_CON(1), 11, GFLAGS), 550 RK3288_CLKGATE_CON(1), 11, GFLAGS),
551 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, 0, 551 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
552 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS), 552 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS),
553 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0, 553 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
554 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS, 554 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
555 RK3288_CLKGATE_CON(1), 12, GFLAGS), 555 RK3288_CLKGATE_CON(1), 12, GFLAGS),
556 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", 0, 556 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
557 RK3288_CLKSEL_CON(19), 0, 557 RK3288_CLKSEL_CON(19), 0,
558 RK3288_CLKGATE_CON(1), 13, GFLAGS), 558 RK3288_CLKGATE_CON(1), 13, GFLAGS),
559 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, 0, 559 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
560 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS), 560 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS),
561 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0, 561 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
562 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS, 562 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
563 RK3288_CLKGATE_CON(1), 14, GFLAGS), 563 RK3288_CLKGATE_CON(1), 14, GFLAGS),
564 COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", 0, 564 COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
565 RK3288_CLKSEL_CON(20), 0, 565 RK3288_CLKSEL_CON(20), 0,
566 RK3288_CLKGATE_CON(1), 15, GFLAGS), 566 RK3288_CLKGATE_CON(1), 15, GFLAGS),
567 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, 0, 567 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
568 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS), 568 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS),
569 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0, 569 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
570 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS, 570 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
571 RK3288_CLKGATE_CON(2), 12, GFLAGS), 571 RK3288_CLKGATE_CON(2), 12, GFLAGS),
572 COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", 0, 572 COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
573 RK3288_CLKSEL_CON(7), 0, 573 RK3288_CLKSEL_CON(7), 0,
574 RK3288_CLKGATE_CON(2), 13, GFLAGS), 574 RK3288_CLKGATE_CON(2), 13, GFLAGS),
575 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0, 575 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
576 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS), 576 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
577 577
578 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, 578 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
@@ -598,7 +598,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
598 GATE(0, "jtag", "ext_jtag", 0, 598 GATE(0, "jtag", "ext_jtag", 0,
599 RK3288_CLKGATE_CON(4), 14, GFLAGS), 599 RK3288_CLKGATE_CON(4), 14, GFLAGS),
600 600
601 COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0, 601 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
602 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS, 602 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
603 RK3288_CLKGATE_CON(5), 14, GFLAGS), 603 RK3288_CLKGATE_CON(5), 14, GFLAGS),
604 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, 604 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
@@ -704,8 +704,8 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
704 704
705 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS), 705 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
706 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), 706 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
707 GATE(0, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), 707 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
708 GATE(0, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), 708 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
709 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), 709 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
710 710
711 /* sclk_gpu gates */ 711 /* sclk_gpu gates */
@@ -805,6 +805,20 @@ static int rk3288_clk_suspend(void)
805 rk3288_saved_cru_regs[i] = 805 rk3288_saved_cru_regs[i] =
806 readl_relaxed(rk3288_cru_base + reg_id); 806 readl_relaxed(rk3288_cru_base + reg_id);
807 } 807 }
808
809 /*
810 * Switch PLLs other than DPLL (for SDRAM) to slow mode to
811 * avoid crashes on resume. The Mask ROM on the system will
812 * put APLL, CPLL, and GPLL into slow mode at resume time
813 * anyway (which is why we restore them), but we might not
814 * even make it to the Mask ROM if this isn't done at suspend
815 * time.
816 *
817 * NOTE: only APLL truly matters here, but we'll do them all.
818 */
819
820 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
821
808 return 0; 822 return 0;
809} 823}
810 824
@@ -866,6 +880,14 @@ static void __init rk3288_clk_init(struct device_node *np)
866 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", 880 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
867 __func__, PTR_ERR(clk)); 881 __func__, PTR_ERR(clk));
868 882
883 /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
884 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
885 if (IS_ERR(clk))
886 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
887 __func__, PTR_ERR(clk));
888 else
889 rockchip_clk_add_lookup(clk, PCLK_WDT);
890
869 rockchip_clk_register_plls(rk3288_pll_clks, 891 rockchip_clk_register_plls(rk3288_pll_clks,
870 ARRAY_SIZE(rk3288_pll_clks), 892 ARRAY_SIZE(rk3288_pll_clks),
871 RK3288_GRF_SOC_STATUS1); 893 RK3288_GRF_SOC_STATUS1);
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index f2c2ccce49bb..454b02ae486a 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -82,6 +82,26 @@ static const struct of_device_id exynos_audss_clk_of_match[] = {
82 {}, 82 {},
83}; 83};
84 84
85static void exynos_audss_clk_teardown(void)
86{
87 int i;
88
89 for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
90 if (!IS_ERR(clk_table[i]))
91 clk_unregister_mux(clk_table[i]);
92 }
93
94 for (; i < EXYNOS_SRP_CLK; i++) {
95 if (!IS_ERR(clk_table[i]))
96 clk_unregister_divider(clk_table[i]);
97 }
98
99 for (; i < clk_data.clk_num; i++) {
100 if (!IS_ERR(clk_table[i]))
101 clk_unregister_gate(clk_table[i]);
102 }
103}
104
85/* register exynos_audss clocks */ 105/* register exynos_audss clocks */
86static int exynos_audss_clk_probe(struct platform_device *pdev) 106static int exynos_audss_clk_probe(struct platform_device *pdev)
87{ 107{
@@ -219,10 +239,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
219 return 0; 239 return 0;
220 240
221unregister: 241unregister:
222 for (i = 0; i < clk_data.clk_num; i++) { 242 exynos_audss_clk_teardown();
223 if (!IS_ERR(clk_table[i]))
224 clk_unregister(clk_table[i]);
225 }
226 243
227 if (!IS_ERR(epll)) 244 if (!IS_ERR(epll))
228 clk_disable_unprepare(epll); 245 clk_disable_unprepare(epll);
@@ -232,18 +249,13 @@ unregister:
232 249
233static int exynos_audss_clk_remove(struct platform_device *pdev) 250static int exynos_audss_clk_remove(struct platform_device *pdev)
234{ 251{
235 int i;
236
237#ifdef CONFIG_PM_SLEEP 252#ifdef CONFIG_PM_SLEEP
238 unregister_syscore_ops(&exynos_audss_clk_syscore_ops); 253 unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
239#endif 254#endif
240 255
241 of_clk_del_provider(pdev->dev.of_node); 256 of_clk_del_provider(pdev->dev.of_node);
242 257
243 for (i = 0; i < clk_data.clk_num; i++) { 258 exynos_audss_clk_teardown();
244 if (!IS_ERR(clk_table[i]))
245 clk_unregister(clk_table[i]);
246 }
247 259
248 if (!IS_ERR(epll)) 260 if (!IS_ERR(epll))
249 clk_disable_unprepare(epll); 261 clk_disable_unprepare(epll);
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 6e6cca392082..cc4c348d8a24 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -104,27 +104,6 @@
104#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 104#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
105#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 105#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
106 106
107/* list of PLLs to be registered */
108enum exynos3250_plls {
109 apll, mpll, vpll, upll,
110 nr_plls
111};
112
113/* list of PLLs in DMC block to be registered */
114enum exynos3250_dmc_plls {
115 bpll, epll,
116 nr_dmc_plls
117};
118
119static void __iomem *reg_base;
120static void __iomem *dmc_reg_base;
121
122/*
123 * Support for CMU save/restore across system suspends
124 */
125#ifdef CONFIG_PM_SLEEP
126static struct samsung_clk_reg_dump *exynos3250_clk_regs;
127
128static unsigned long exynos3250_cmu_clk_regs[] __initdata = { 107static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
129 SRC_LEFTBUS, 108 SRC_LEFTBUS,
130 DIV_LEFTBUS, 109 DIV_LEFTBUS,
@@ -195,43 +174,6 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
195 PWR_CTRL2, 174 PWR_CTRL2,
196}; 175};
197 176
198static int exynos3250_clk_suspend(void)
199{
200 samsung_clk_save(reg_base, exynos3250_clk_regs,
201 ARRAY_SIZE(exynos3250_cmu_clk_regs));
202 return 0;
203}
204
205static void exynos3250_clk_resume(void)
206{
207 samsung_clk_restore(reg_base, exynos3250_clk_regs,
208 ARRAY_SIZE(exynos3250_cmu_clk_regs));
209}
210
211static struct syscore_ops exynos3250_clk_syscore_ops = {
212 .suspend = exynos3250_clk_suspend,
213 .resume = exynos3250_clk_resume,
214};
215
216static void exynos3250_clk_sleep_init(void)
217{
218 exynos3250_clk_regs =
219 samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
220 ARRAY_SIZE(exynos3250_cmu_clk_regs));
221 if (!exynos3250_clk_regs) {
222 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
223 goto err;
224 }
225
226 register_syscore_ops(&exynos3250_clk_syscore_ops);
227 return;
228err:
229 kfree(exynos3250_clk_regs);
230}
231#else
232static inline void exynos3250_clk_sleep_init(void) { }
233#endif
234
235/* list of all parent clock list */ 177/* list of all parent clock list */
236PNAME(mout_vpllsrc_p) = { "fin_pll", }; 178PNAME(mout_vpllsrc_p) = { "fin_pll", };
237 179
@@ -782,18 +724,18 @@ static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
782 { /* sentinel */ } 724 { /* sentinel */ }
783}; 725};
784 726
785static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = { 727static struct samsung_pll_clock exynos3250_plls[] __initdata = {
786 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 728 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
787 APLL_LOCK, APLL_CON0, NULL), 729 APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
788 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 730 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
789 MPLL_LOCK, MPLL_CON0, NULL), 731 MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
790 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 732 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
791 VPLL_LOCK, VPLL_CON0, NULL), 733 VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
792 [upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll", 734 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
793 UPLL_LOCK, UPLL_CON0, NULL), 735 UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
794}; 736};
795 737
796static void __init exynos3_core_down_clock(void) 738static void __init exynos3_core_down_clock(void __iomem *reg_base)
797{ 739{
798 unsigned int tmp; 740 unsigned int tmp;
799 741
@@ -814,38 +756,31 @@ static void __init exynos3_core_down_clock(void)
814 __raw_writel(0x0, reg_base + PWR_CTRL2); 756 __raw_writel(0x0, reg_base + PWR_CTRL2);
815} 757}
816 758
759static struct samsung_cmu_info cmu_info __initdata = {
760 .pll_clks = exynos3250_plls,
761 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls),
762 .mux_clks = mux_clks,
763 .nr_mux_clks = ARRAY_SIZE(mux_clks),
764 .div_clks = div_clks,
765 .nr_div_clks = ARRAY_SIZE(div_clks),
766 .gate_clks = gate_clks,
767 .nr_gate_clks = ARRAY_SIZE(gate_clks),
768 .fixed_factor_clks = fixed_factor_clks,
769 .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
770 .nr_clk_ids = CLK_NR_CLKS,
771 .clk_regs = exynos3250_cmu_clk_regs,
772 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
773};
774
817static void __init exynos3250_cmu_init(struct device_node *np) 775static void __init exynos3250_cmu_init(struct device_node *np)
818{ 776{
819 struct samsung_clk_provider *ctx; 777 struct samsung_clk_provider *ctx;
820 778
821 reg_base = of_iomap(np, 0); 779 ctx = samsung_cmu_register_one(np, &cmu_info);
822 if (!reg_base)
823 panic("%s: failed to map registers\n", __func__);
824
825 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
826 if (!ctx) 780 if (!ctx)
827 panic("%s: unable to allocate context.\n", __func__); 781 return;
828
829 samsung_clk_register_fixed_factor(ctx, fixed_factor_clks,
830 ARRAY_SIZE(fixed_factor_clks));
831
832 exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
833 exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
834 exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
835 exynos3250_plls[upll].rate_table = exynos3250_pll_rates;
836
837 samsung_clk_register_pll(ctx, exynos3250_plls,
838 ARRAY_SIZE(exynos3250_plls), reg_base);
839
840 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
841 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
842 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
843
844 exynos3_core_down_clock();
845 782
846 exynos3250_clk_sleep_init(); 783 exynos3_core_down_clock(ctx->reg_base);
847
848 samsung_clk_of_add_provider(np, ctx);
849} 784}
850CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 785CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
851 786
@@ -872,12 +807,6 @@ CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
872#define EPLL_CON2 0x111c 807#define EPLL_CON2 0x111c
873#define SRC_EPLL 0x1120 808#define SRC_EPLL 0x1120
874 809
875/*
876 * Support for CMU save/restore across system suspends
877 */
878#ifdef CONFIG_PM_SLEEP
879static struct samsung_clk_reg_dump *exynos3250_dmc_clk_regs;
880
881static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = { 810static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
882 BPLL_LOCK, 811 BPLL_LOCK,
883 BPLL_CON0, 812 BPLL_CON0,
@@ -899,43 +828,6 @@ static unsigned long exynos3250_cmu_dmc_clk_regs[] __initdata = {
899 SRC_EPLL, 828 SRC_EPLL,
900}; 829};
901 830
902static int exynos3250_dmc_clk_suspend(void)
903{
904 samsung_clk_save(dmc_reg_base, exynos3250_dmc_clk_regs,
905 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
906 return 0;
907}
908
909static void exynos3250_dmc_clk_resume(void)
910{
911 samsung_clk_restore(dmc_reg_base, exynos3250_dmc_clk_regs,
912 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
913}
914
915static struct syscore_ops exynos3250_dmc_clk_syscore_ops = {
916 .suspend = exynos3250_dmc_clk_suspend,
917 .resume = exynos3250_dmc_clk_resume,
918};
919
920static void exynos3250_dmc_clk_sleep_init(void)
921{
922 exynos3250_dmc_clk_regs =
923 samsung_clk_alloc_reg_dump(exynos3250_cmu_dmc_clk_regs,
924 ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs));
925 if (!exynos3250_dmc_clk_regs) {
926 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
927 goto err;
928 }
929
930 register_syscore_ops(&exynos3250_dmc_clk_syscore_ops);
931 return;
932err:
933 kfree(exynos3250_dmc_clk_regs);
934}
935#else
936static inline void exynos3250_dmc_clk_sleep_init(void) { }
937#endif
938
939PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; 831PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
940PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 832PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
941PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", }; 833PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };
@@ -977,43 +869,28 @@ static struct samsung_div_clock dmc_div_clks[] __initdata = {
977 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3), 869 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
978}; 870};
979 871
980static struct samsung_pll_clock exynos3250_dmc_plls[nr_dmc_plls] __initdata = { 872static struct samsung_pll_clock exynos3250_dmc_plls[] __initdata = {
981 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", 873 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
982 BPLL_LOCK, BPLL_CON0, NULL), 874 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
983 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 875 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
984 EPLL_LOCK, EPLL_CON0, NULL), 876 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
877};
878
879static struct samsung_cmu_info dmc_cmu_info __initdata = {
880 .pll_clks = exynos3250_dmc_plls,
881 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),
882 .mux_clks = dmc_mux_clks,
883 .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),
884 .div_clks = dmc_div_clks,
885 .nr_div_clks = ARRAY_SIZE(dmc_div_clks),
886 .nr_clk_ids = NR_CLKS_DMC,
887 .clk_regs = exynos3250_cmu_dmc_clk_regs,
888 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
985}; 889};
986 890
987static void __init exynos3250_cmu_dmc_init(struct device_node *np) 891static void __init exynos3250_cmu_dmc_init(struct device_node *np)
988{ 892{
989 struct samsung_clk_provider *ctx; 893 samsung_cmu_register_one(np, &dmc_cmu_info);
990
991 dmc_reg_base = of_iomap(np, 0);
992 if (!dmc_reg_base)
993 panic("%s: failed to map registers\n", __func__);
994
995 ctx = samsung_clk_init(np, dmc_reg_base, NR_CLKS_DMC);
996 if (!ctx)
997 panic("%s: unable to allocate context.\n", __func__);
998
999 exynos3250_dmc_plls[bpll].rate_table = exynos3250_pll_rates;
1000 exynos3250_dmc_plls[epll].rate_table = exynos3250_epll_rates;
1001
1002 pr_err("CLK registering epll bpll: %d, %d, %d, %d\n",
1003 exynos3250_dmc_plls[bpll].rate_table[0].rate,
1004 exynos3250_dmc_plls[bpll].rate_table[0].mdiv,
1005 exynos3250_dmc_plls[bpll].rate_table[0].pdiv,
1006 exynos3250_dmc_plls[bpll].rate_table[0].sdiv
1007 );
1008 samsung_clk_register_pll(ctx, exynos3250_dmc_plls,
1009 ARRAY_SIZE(exynos3250_dmc_plls), dmc_reg_base);
1010
1011 samsung_clk_register_mux(ctx, dmc_mux_clks, ARRAY_SIZE(dmc_mux_clks));
1012 samsung_clk_register_div(ctx, dmc_div_clks, ARRAY_SIZE(dmc_div_clks));
1013
1014 exynos3250_dmc_clk_sleep_init();
1015
1016 samsung_clk_of_add_provider(np, ctx);
1017} 894}
1018CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", 895CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
1019 exynos3250_cmu_dmc_init); 896 exynos3250_cmu_dmc_init);
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 88e8c6bbd77f..51462e85675f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -703,12 +703,12 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
703 703
704/* list of divider clocks supported in all exynos4 soc's */ 704/* list of divider clocks supported in all exynos4 soc's */
705static struct samsung_div_clock exynos4_div_clks[] __initdata = { 705static struct samsung_div_clock exynos4_div_clks[] __initdata = {
706 DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), 706 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", 708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
709 CLKOUT_CMU_LEFTBUS, 8, 6), 709 CLKOUT_CMU_LEFTBUS, 8, 6),
710 710
711 DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3), 711 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", 713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
714 CLKOUT_CMU_RIGHTBUS, 8, 6), 714 CLKOUT_CMU_RIGHTBUS, 8, 6),
@@ -781,10 +781,10 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
781 CLK_SET_RATE_PARENT, 0), 781 CLK_SET_RATE_PARENT, 0),
782 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6), 782 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
783 783
784 DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3), 784 DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
785 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3), 785 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
786 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3), 786 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
787 DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3), 787 DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
788 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3), 788 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
789 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3), 789 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
790 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4), 790 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
@@ -829,7 +829,7 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
829 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 829 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
830 8, 3, CLK_GET_RATE_NOCACHE, 0), 830 8, 3, CLK_GET_RATE_NOCACHE, 0),
831 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 831 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
832 DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), 832 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
833 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), 833 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
834}; 834};
835 835
diff --git a/drivers/clk/samsung/clk-exynos4415.c b/drivers/clk/samsung/clk-exynos4415.c
index 2123fc251e0f..6c78b09c829f 100644
--- a/drivers/clk/samsung/clk-exynos4415.c
+++ b/drivers/clk/samsung/clk-exynos4415.c
@@ -113,19 +113,6 @@
113#define DIV_CPU0 0x14500 113#define DIV_CPU0 0x14500
114#define DIV_CPU1 0x14504 114#define DIV_CPU1 0x14504
115 115
116enum exynos4415_plls {
117 apll, epll, g3d_pll, isp_pll, disp_pll,
118 nr_plls,
119};
120
121static struct samsung_clk_provider *exynos4415_ctx;
122
123/*
124 * Support for CMU save/restore across system suspends
125 */
126#ifdef CONFIG_PM_SLEEP
127static struct samsung_clk_reg_dump *exynos4415_clk_regs;
128
129static unsigned long exynos4415_cmu_clk_regs[] __initdata = { 116static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
130 SRC_LEFTBUS, 117 SRC_LEFTBUS,
131 DIV_LEFTBUS, 118 DIV_LEFTBUS,
@@ -219,41 +206,6 @@ static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
219 DIV_CPU1, 206 DIV_CPU1,
220}; 207};
221 208
222static int exynos4415_clk_suspend(void)
223{
224 samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
225 ARRAY_SIZE(exynos4415_cmu_clk_regs));
226
227 return 0;
228}
229
230static void exynos4415_clk_resume(void)
231{
232 samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
233 ARRAY_SIZE(exynos4415_cmu_clk_regs));
234}
235
236static struct syscore_ops exynos4415_clk_syscore_ops = {
237 .suspend = exynos4415_clk_suspend,
238 .resume = exynos4415_clk_resume,
239};
240
241static void exynos4415_clk_sleep_init(void)
242{
243 exynos4415_clk_regs =
244 samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
245 ARRAY_SIZE(exynos4415_cmu_clk_regs));
246 if (!exynos4415_clk_regs) {
247 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
248 return;
249 }
250
251 register_syscore_ops(&exynos4415_clk_syscore_ops);
252}
253#else
254static inline void exynos4415_clk_sleep_init(void) { }
255#endif
256
257/* list of all parent clock list */ 209/* list of all parent clock list */
258PNAME(mout_g3d_pllsrc_p) = { "fin_pll", }; 210PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
259 211
@@ -959,56 +911,40 @@ static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
959 { /* sentinel */ } 911 { /* sentinel */ }
960}; 912};
961 913
962static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = { 914static struct samsung_pll_clock exynos4415_plls[] __initdata = {
963 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 915 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
964 APLL_LOCK, APLL_CON0, NULL), 916 APLL_LOCK, APLL_CON0, exynos4415_pll_rates),
965 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 917 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
966 EPLL_LOCK, EPLL_CON0, NULL), 918 EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates),
967 [g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", 919 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc",
968 "mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL), 920 G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates),
969 [isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll", 921 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
970 ISP_PLL_LOCK, ISP_PLL_CON0, NULL), 922 ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates),
971 [disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", 923 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
972 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL), 924 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates),
925};
926
927static struct samsung_cmu_info cmu_info __initdata = {
928 .pll_clks = exynos4415_plls,
929 .nr_pll_clks = ARRAY_SIZE(exynos4415_plls),
930 .mux_clks = exynos4415_mux_clks,
931 .nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks),
932 .div_clks = exynos4415_div_clks,
933 .nr_div_clks = ARRAY_SIZE(exynos4415_div_clks),
934 .gate_clks = exynos4415_gate_clks,
935 .nr_gate_clks = ARRAY_SIZE(exynos4415_gate_clks),
936 .fixed_clks = exynos4415_fixed_rate_clks,
937 .nr_fixed_clks = ARRAY_SIZE(exynos4415_fixed_rate_clks),
938 .fixed_factor_clks = exynos4415_fixed_factor_clks,
939 .nr_fixed_factor_clks = ARRAY_SIZE(exynos4415_fixed_factor_clks),
940 .nr_clk_ids = CLK_NR_CLKS,
941 .clk_regs = exynos4415_cmu_clk_regs,
942 .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_clk_regs),
973}; 943};
974 944
975static void __init exynos4415_cmu_init(struct device_node *np) 945static void __init exynos4415_cmu_init(struct device_node *np)
976{ 946{
977 void __iomem *reg_base; 947 samsung_cmu_register_one(np, &cmu_info);
978
979 reg_base = of_iomap(np, 0);
980 if (!reg_base)
981 panic("%s: failed to map registers\n", __func__);
982
983 exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
984 if (!exynos4415_ctx)
985 panic("%s: unable to allocate context.\n", __func__);
986
987 exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
988 exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
989 exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
990 exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
991 exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
992
993 samsung_clk_register_fixed_factor(exynos4415_ctx,
994 exynos4415_fixed_factor_clks,
995 ARRAY_SIZE(exynos4415_fixed_factor_clks));
996 samsung_clk_register_fixed_rate(exynos4415_ctx,
997 exynos4415_fixed_rate_clks,
998 ARRAY_SIZE(exynos4415_fixed_rate_clks));
999
1000 samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
1001 ARRAY_SIZE(exynos4415_plls), reg_base);
1002 samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
1003 ARRAY_SIZE(exynos4415_mux_clks));
1004 samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
1005 ARRAY_SIZE(exynos4415_div_clks));
1006 samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
1007 ARRAY_SIZE(exynos4415_gate_clks));
1008
1009 exynos4415_clk_sleep_init();
1010
1011 samsung_clk_of_add_provider(np, exynos4415_ctx);
1012} 948}
1013CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init); 949CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
1014 950
@@ -1027,16 +963,6 @@ CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
1027#define SRC_DMC 0x300 963#define SRC_DMC 0x300
1028#define DIV_DMC1 0x504 964#define DIV_DMC1 0x504
1029 965
1030enum exynos4415_dmc_plls {
1031 mpll, bpll,
1032 nr_dmc_plls,
1033};
1034
1035static struct samsung_clk_provider *exynos4415_dmc_ctx;
1036
1037#ifdef CONFIG_PM_SLEEP
1038static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
1039
1040static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = { 966static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
1041 MPLL_LOCK, 967 MPLL_LOCK,
1042 MPLL_CON0, 968 MPLL_CON0,
@@ -1050,42 +976,6 @@ static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
1050 DIV_DMC1, 976 DIV_DMC1,
1051}; 977};
1052 978
1053static int exynos4415_dmc_clk_suspend(void)
1054{
1055 samsung_clk_save(exynos4415_dmc_ctx->reg_base,
1056 exynos4415_dmc_clk_regs,
1057 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1058 return 0;
1059}
1060
1061static void exynos4415_dmc_clk_resume(void)
1062{
1063 samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
1064 exynos4415_dmc_clk_regs,
1065 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1066}
1067
1068static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
1069 .suspend = exynos4415_dmc_clk_suspend,
1070 .resume = exynos4415_dmc_clk_resume,
1071};
1072
1073static void exynos4415_dmc_clk_sleep_init(void)
1074{
1075 exynos4415_dmc_clk_regs =
1076 samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
1077 ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1078 if (!exynos4415_dmc_clk_regs) {
1079 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
1080 return;
1081 }
1082
1083 register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
1084}
1085#else
1086static inline void exynos4415_dmc_clk_sleep_init(void) { }
1087#endif /* CONFIG_PM_SLEEP */
1088
1089PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 979PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
1090PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", }; 980PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
1091PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", }; 981PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
@@ -1107,38 +997,28 @@ static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
1107 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2), 997 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
1108}; 998};
1109 999
1110static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = { 1000static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = {
1111 [mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll", 1001 PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1112 MPLL_LOCK, MPLL_CON0, NULL), 1002 MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates),
1113 [bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll", 1003 PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
1114 BPLL_LOCK, BPLL_CON0, NULL), 1004 BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates),
1005};
1006
1007static struct samsung_cmu_info cmu_dmc_info __initdata = {
1008 .pll_clks = exynos4415_dmc_plls,
1009 .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls),
1010 .mux_clks = exynos4415_dmc_mux_clks,
1011 .nr_mux_clks = ARRAY_SIZE(exynos4415_dmc_mux_clks),
1012 .div_clks = exynos4415_dmc_div_clks,
1013 .nr_div_clks = ARRAY_SIZE(exynos4415_dmc_div_clks),
1014 .nr_clk_ids = NR_CLKS_DMC,
1015 .clk_regs = exynos4415_cmu_dmc_clk_regs,
1016 .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs),
1115}; 1017};
1116 1018
1117static void __init exynos4415_cmu_dmc_init(struct device_node *np) 1019static void __init exynos4415_cmu_dmc_init(struct device_node *np)
1118{ 1020{
1119 void __iomem *reg_base; 1021 samsung_cmu_register_one(np, &cmu_dmc_info);
1120
1121 reg_base = of_iomap(np, 0);
1122 if (!reg_base)
1123 panic("%s: failed to map registers\n", __func__);
1124
1125 exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
1126 if (!exynos4415_dmc_ctx)
1127 panic("%s: unable to allocate context.\n", __func__);
1128
1129 exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
1130 exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
1131
1132 samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
1133 ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
1134 samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
1135 ARRAY_SIZE(exynos4415_dmc_mux_clks));
1136 samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
1137 ARRAY_SIZE(exynos4415_dmc_div_clks));
1138
1139 exynos4415_dmc_clk_sleep_init();
1140
1141 samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
1142} 1022}
1143CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc", 1023CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
1144 exynos4415_cmu_dmc_init); 1024 exynos4415_cmu_dmc_init);
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index ea4483b8d62e..03d36e847b78 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -34,6 +34,7 @@
34#define DIV_TOPC0 0x0600 34#define DIV_TOPC0 0x0600
35#define DIV_TOPC1 0x0604 35#define DIV_TOPC1 0x0604
36#define DIV_TOPC3 0x060C 36#define DIV_TOPC3 0x060C
37#define ENABLE_ACLK_TOPC1 0x0804
37 38
38static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 39static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
39 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), 40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
@@ -45,6 +46,7 @@ static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
45}; 46};
46 47
47/* List of parent clocks for Muxes in CMU_TOPC */ 48/* List of parent clocks for Muxes in CMU_TOPC */
49PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
48PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 50PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
49PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 51PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
50PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 52PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
@@ -104,9 +106,11 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
104 106
105 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, 107 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
106 MUX_SEL_TOPC1, 16, 1), 108 MUX_SEL_TOPC1, 16, 1),
109 MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
107 110
108 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 111 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
109 112
113 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
110 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 114 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
111}; 115};
112 116
@@ -114,6 +118,8 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
114 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 118 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
115 DIV_TOPC0, 4, 4), 119 DIV_TOPC0, 4, 4),
116 120
121 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
122 DIV_TOPC1, 20, 4),
117 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 123 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
118 DIV_TOPC1, 24, 4), 124 DIV_TOPC1, 24, 4),
119 125
@@ -125,6 +131,18 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
125 DIV_TOPC3, 12, 3), 131 DIV_TOPC3, 12, 3),
126 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", 132 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
127 DIV_TOPC3, 16, 3), 133 DIV_TOPC3, 16, 3),
134 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
135 DIV_TOPC3, 28, 3),
136};
137
138static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
139 PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
140 {},
141};
142
143static struct samsung_gate_clock topc_gate_clks[] __initdata = {
144 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
145 ENABLE_ACLK_TOPC1, 20, 0, 0),
128}; 146};
129 147
130static struct samsung_pll_clock topc_pll_clks[] __initdata = { 148static struct samsung_pll_clock topc_pll_clks[] __initdata = {
@@ -136,8 +154,8 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata = {
136 BUS1_DPLL_CON0, NULL), 154 BUS1_DPLL_CON0, NULL),
137 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 155 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
138 MFC_PLL_CON0, NULL), 156 MFC_PLL_CON0, NULL),
139 PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 157 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
140 AUD_PLL_CON0, NULL), 158 AUD_PLL_CON0, pll1460x_24mhz_tbl),
141}; 159};
142 160
143static struct samsung_cmu_info topc_cmu_info __initdata = { 161static struct samsung_cmu_info topc_cmu_info __initdata = {
@@ -147,6 +165,8 @@ static struct samsung_cmu_info topc_cmu_info __initdata = {
147 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 165 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
148 .div_clks = topc_div_clks, 166 .div_clks = topc_div_clks,
149 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 167 .nr_div_clks = ARRAY_SIZE(topc_div_clks),
168 .gate_clks = topc_gate_clks,
169 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
150 .fixed_factor_clks = topc_fixed_factor_clks, 170 .fixed_factor_clks = topc_fixed_factor_clks,
151 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 171 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
152 .nr_clk_ids = TOPC_NR_CLK, 172 .nr_clk_ids = TOPC_NR_CLK,
@@ -166,9 +186,18 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
166#define MUX_SEL_TOP00 0x0200 186#define MUX_SEL_TOP00 0x0200
167#define MUX_SEL_TOP01 0x0204 187#define MUX_SEL_TOP01 0x0204
168#define MUX_SEL_TOP03 0x020C 188#define MUX_SEL_TOP03 0x020C
189#define MUX_SEL_TOP0_PERIC0 0x0230
190#define MUX_SEL_TOP0_PERIC1 0x0234
191#define MUX_SEL_TOP0_PERIC2 0x0238
169#define MUX_SEL_TOP0_PERIC3 0x023C 192#define MUX_SEL_TOP0_PERIC3 0x023C
170#define DIV_TOP03 0x060C 193#define DIV_TOP03 0x060C
194#define DIV_TOP0_PERIC0 0x0630
195#define DIV_TOP0_PERIC1 0x0634
196#define DIV_TOP0_PERIC2 0x0638
171#define DIV_TOP0_PERIC3 0x063C 197#define DIV_TOP0_PERIC3 0x063C
198#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
199#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
200#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
172#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 201#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
173 202
174/* List of parent clocks for Muxes in CMU_TOP0 */ 203/* List of parent clocks for Muxes in CMU_TOP0 */
@@ -176,6 +205,7 @@ PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
176PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; 205PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
177PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; 206PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
178PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; 207PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
208PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" };
179 209
180PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", 210PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
181 "ffac_top0_bus0_pll_div2"}; 211 "ffac_top0_bus0_pll_div2"};
@@ -189,18 +219,34 @@ PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
189PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", 219PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
190 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", 220 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
191 "mout_top0_half_mfc_pll"}; 221 "mout_top0_half_mfc_pll"};
222PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
223 "ioclk_audiocdclk1", "ioclk_spdif_extclk",
224 "mout_top0_aud_pll", "mout_top0_half_bus0_pll",
225 "mout_top0_half_bus1_pll"};
226PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
227 "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
192 228
193static unsigned long top0_clk_regs[] __initdata = { 229static unsigned long top0_clk_regs[] __initdata = {
194 MUX_SEL_TOP00, 230 MUX_SEL_TOP00,
195 MUX_SEL_TOP01, 231 MUX_SEL_TOP01,
196 MUX_SEL_TOP03, 232 MUX_SEL_TOP03,
233 MUX_SEL_TOP0_PERIC0,
234 MUX_SEL_TOP0_PERIC1,
235 MUX_SEL_TOP0_PERIC2,
197 MUX_SEL_TOP0_PERIC3, 236 MUX_SEL_TOP0_PERIC3,
198 DIV_TOP03, 237 DIV_TOP03,
238 DIV_TOP0_PERIC0,
239 DIV_TOP0_PERIC1,
240 DIV_TOP0_PERIC2,
199 DIV_TOP0_PERIC3, 241 DIV_TOP0_PERIC3,
242 ENABLE_SCLK_TOP0_PERIC0,
243 ENABLE_SCLK_TOP0_PERIC1,
244 ENABLE_SCLK_TOP0_PERIC2,
200 ENABLE_SCLK_TOP0_PERIC3, 245 ENABLE_SCLK_TOP0_PERIC3,
201}; 246};
202 247
203static struct samsung_mux_clock top0_mux_clks[] __initdata = { 248static struct samsung_mux_clock top0_mux_clks[] __initdata = {
249 MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
204 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), 250 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
205 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), 251 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
206 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), 252 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
@@ -218,10 +264,20 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
218 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 264 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
219 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 265 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
220 266
267 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
268 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
269 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
270
271 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
272 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
273
274 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
275 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
221 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 276 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
222 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 277 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
223 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 278 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
224 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 279 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
280 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
225}; 281};
226 282
227static struct samsung_div_clock top0_div_clks[] __initdata = { 283static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -230,13 +286,40 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
230 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 286 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
231 DIV_TOP03, 20, 6), 287 DIV_TOP03, 20, 6),
232 288
289 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
290 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
291 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
292
293 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
294 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
295
296 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
297 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
298
233 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 299 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
234 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 300 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
235 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 301 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
236 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 302 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
303 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
237}; 304};
238 305
239static struct samsung_gate_clock top0_gate_clks[] __initdata = { 306static struct samsung_gate_clock top0_gate_clks[] __initdata = {
307 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
308 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
309 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
310 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
311 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
312 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
313
314 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
315 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
316 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
317 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
318
319 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
320 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
321 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
322 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
240 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 323 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
241 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 324 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
242 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 325 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
@@ -245,6 +328,8 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
245 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 328 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
246 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 329 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
247 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 330 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
331 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
332 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
248}; 333};
249 334
250static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 335static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
@@ -343,6 +428,8 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
343 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 428 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
344 429
345 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2), 430 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
431 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
432 MUX_SEL_TOP1_FSYS0, 28, 2),
346 433
347 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2), 434 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
348 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2), 435 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
@@ -356,6 +443,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
356 443
357 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 444 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
358 DIV_TOP1_FSYS0, 24, 4), 445 DIV_TOP1_FSYS0, 24, 4),
446 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
447 DIV_TOP1_FSYS0, 28, 4),
359 448
360 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 449 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
361 DIV_TOP1_FSYS1, 24, 4), 450 DIV_TOP1_FSYS1, 24, 4),
@@ -366,6 +455,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
366static struct samsung_gate_clock top1_gate_clks[] __initdata = { 455static struct samsung_gate_clock top1_gate_clks[] __initdata = {
367 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 456 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
368 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0), 457 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
458 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
459 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
369 460
370 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 461 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
371 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0), 462 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
@@ -514,6 +605,7 @@ static void __init exynos7_clk_peric0_init(struct device_node *np)
514/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 605/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
515#define MUX_SEL_PERIC10 0x0200 606#define MUX_SEL_PERIC10 0x0200
516#define MUX_SEL_PERIC11 0x0204 607#define MUX_SEL_PERIC11 0x0204
608#define MUX_SEL_PERIC12 0x0208
517#define ENABLE_PCLK_PERIC1 0x0900 609#define ENABLE_PCLK_PERIC1 0x0900
518#define ENABLE_SCLK_PERIC10 0x0A00 610#define ENABLE_SCLK_PERIC10 0x0A00
519 611
@@ -525,10 +617,16 @@ PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
525PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; 617PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
526PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; 618PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
527PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; 619PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
620PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
621PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
622PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
623PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
624PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
528 625
529static unsigned long peric1_clk_regs[] __initdata = { 626static unsigned long peric1_clk_regs[] __initdata = {
530 MUX_SEL_PERIC10, 627 MUX_SEL_PERIC10,
531 MUX_SEL_PERIC11, 628 MUX_SEL_PERIC11,
629 MUX_SEL_PERIC12,
532 ENABLE_PCLK_PERIC1, 630 ENABLE_PCLK_PERIC1,
533 ENABLE_SCLK_PERIC10, 631 ENABLE_SCLK_PERIC10,
534}; 632};
@@ -537,6 +635,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
537 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, 635 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
538 MUX_SEL_PERIC10, 0, 1), 636 MUX_SEL_PERIC10, 0, 1),
539 637
638 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
639 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
640 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
641 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
642 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
643 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
644 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
645 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
646 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
647 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
540 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, 648 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
541 MUX_SEL_PERIC11, 20, 1), 649 MUX_SEL_PERIC11, 20, 1),
542 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, 650 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
@@ -562,6 +670,22 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
562 ENABLE_PCLK_PERIC1, 10, 0, 0), 670 ENABLE_PCLK_PERIC1, 10, 0, 0),
563 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 671 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
564 ENABLE_PCLK_PERIC1, 11, 0, 0), 672 ENABLE_PCLK_PERIC1, 11, 0, 0),
673 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
674 ENABLE_PCLK_PERIC1, 12, 0, 0),
675 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
676 ENABLE_PCLK_PERIC1, 13, 0, 0),
677 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
678 ENABLE_PCLK_PERIC1, 14, 0, 0),
679 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
680 ENABLE_PCLK_PERIC1, 15, 0, 0),
681 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
682 ENABLE_PCLK_PERIC1, 16, 0, 0),
683 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
684 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
685 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
686 ENABLE_PCLK_PERIC1, 18, 0, 0),
687 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
688 ENABLE_PCLK_PERIC1, 19, 0, 0),
565 689
566 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 690 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
567 ENABLE_SCLK_PERIC10, 9, 0, 0), 691 ENABLE_SCLK_PERIC10, 9, 0, 0),
@@ -569,6 +693,22 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
569 ENABLE_SCLK_PERIC10, 10, 0, 0), 693 ENABLE_SCLK_PERIC10, 10, 0, 0),
570 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 694 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
571 ENABLE_SCLK_PERIC10, 11, 0, 0), 695 ENABLE_SCLK_PERIC10, 11, 0, 0),
696 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
697 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
698 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
699 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
700 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
701 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
702 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
703 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
704 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
705 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
706 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
707 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
708 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
709 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
710 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
711 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
572}; 712};
573 713
574static struct samsung_cmu_info peric1_cmu_info __initdata = { 714static struct samsung_cmu_info peric1_cmu_info __initdata = {
@@ -647,7 +787,12 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
647/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 787/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
648#define MUX_SEL_FSYS00 0x0200 788#define MUX_SEL_FSYS00 0x0200
649#define MUX_SEL_FSYS01 0x0204 789#define MUX_SEL_FSYS01 0x0204
790#define MUX_SEL_FSYS02 0x0208
791#define ENABLE_ACLK_FSYS00 0x0800
650#define ENABLE_ACLK_FSYS01 0x0804 792#define ENABLE_ACLK_FSYS01 0x0804
793#define ENABLE_SCLK_FSYS01 0x0A04
794#define ENABLE_SCLK_FSYS02 0x0A08
795#define ENABLE_SCLK_FSYS04 0x0A10
651 796
652/* 797/*
653 * List of parent clocks for Muxes in CMU_FSYS0 798 * List of parent clocks for Muxes in CMU_FSYS0
@@ -655,10 +800,29 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
655PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; 800PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
656PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; 801PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
657 802
803PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" };
804PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll",
805 "phyclk_usbdrd300_udrd30_phyclock" };
806PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
807 "phyclk_usbdrd300_udrd30_pipe_pclk" };
808
809/* fixed rate clocks used in the FSYS0 block */
810struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
811 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
812 CLK_IS_ROOT, 60000000),
813 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
814 CLK_IS_ROOT, 125000000),
815};
816
658static unsigned long fsys0_clk_regs[] __initdata = { 817static unsigned long fsys0_clk_regs[] __initdata = {
659 MUX_SEL_FSYS00, 818 MUX_SEL_FSYS00,
660 MUX_SEL_FSYS01, 819 MUX_SEL_FSYS01,
820 MUX_SEL_FSYS02,
821 ENABLE_ACLK_FSYS00,
661 ENABLE_ACLK_FSYS01, 822 ENABLE_ACLK_FSYS01,
823 ENABLE_SCLK_FSYS01,
824 ENABLE_SCLK_FSYS02,
825 ENABLE_SCLK_FSYS04,
662}; 826};
663 827
664static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 828static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
@@ -666,11 +830,49 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
666 MUX_SEL_FSYS00, 24, 1), 830 MUX_SEL_FSYS00, 24, 1),
667 831
668 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), 832 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
833 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
834 MUX_SEL_FSYS01, 28, 1),
835
836 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
837 mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
838 MUX_SEL_FSYS02, 24, 1),
839 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
840 mout_phyclk_usbdrd300_udrd30_phyclk_p,
841 MUX_SEL_FSYS02, 28, 1),
669}; 842};
670 843
671static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 844static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
845 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
846 "mout_aclk_fsys0_200_user",
847 ENABLE_ACLK_FSYS00, 19, 0, 0),
848 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
849 ENABLE_ACLK_FSYS00, 3, 0, 0),
850 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
851 ENABLE_ACLK_FSYS00, 4, 0, 0),
852
853 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
854 ENABLE_ACLK_FSYS01, 29, 0, 0),
672 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 855 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
673 ENABLE_ACLK_FSYS01, 31, 0, 0), 856 ENABLE_ACLK_FSYS01, 31, 0, 0),
857
858 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
859 "mout_sclk_usbdrd300_user",
860 ENABLE_SCLK_FSYS01, 4, 0, 0),
861 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
862 ENABLE_SCLK_FSYS01, 8, 0, 0),
863
864 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
865 "phyclk_usbdrd300_udrd30_pipe_pclk_user",
866 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
867 ENABLE_SCLK_FSYS02, 24, 0, 0),
868 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
869 "phyclk_usbdrd300_udrd30_phyclk_user",
870 "mout_phyclk_usbdrd300_udrd30_phyclk_user",
871 ENABLE_SCLK_FSYS02, 28, 0, 0),
872
873 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
874 "fin_pll",
875 ENABLE_SCLK_FSYS04, 28, 0, 0),
674}; 876};
675 877
676static struct samsung_cmu_info fsys0_cmu_info __initdata = { 878static struct samsung_cmu_info fsys0_cmu_info __initdata = {
@@ -741,3 +943,205 @@ static void __init exynos7_clk_fsys1_init(struct device_node *np)
741 943
742CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 944CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
743 exynos7_clk_fsys1_init); 945 exynos7_clk_fsys1_init);
946
947#define MUX_SEL_MSCL 0x0200
948#define DIV_MSCL 0x0600
949#define ENABLE_ACLK_MSCL 0x0800
950#define ENABLE_PCLK_MSCL 0x0900
951
952/* List of parent clocks for Muxes in CMU_MSCL */
953PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
954
955static unsigned long mscl_clk_regs[] __initdata = {
956 MUX_SEL_MSCL,
957 DIV_MSCL,
958 ENABLE_ACLK_MSCL,
959 ENABLE_PCLK_MSCL,
960};
961
962static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
963 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
964 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
965};
966static struct samsung_div_clock mscl_div_clks[] __initdata = {
967 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
968 DIV_MSCL, 0, 3),
969};
970static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
971
972 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
973 ENABLE_ACLK_MSCL, 31, 0, 0),
974 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
975 ENABLE_ACLK_MSCL, 30, 0, 0),
976 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
977 ENABLE_ACLK_MSCL, 29, 0, 0),
978 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
979 ENABLE_ACLK_MSCL, 28, 0, 0),
980 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
981 "usermux_aclk_mscl_532",
982 ENABLE_ACLK_MSCL, 27, 0, 0),
983 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
984 "usermux_aclk_mscl_532",
985 ENABLE_ACLK_MSCL, 26, 0, 0),
986 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
987 ENABLE_ACLK_MSCL, 25, 0, 0),
988 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
989 ENABLE_ACLK_MSCL, 24, 0, 0),
990 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
991 "usermux_aclk_mscl_532",
992 ENABLE_ACLK_MSCL, 23, 0, 0),
993 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
994 ENABLE_ACLK_MSCL, 22, 0, 0),
995 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
996 ENABLE_ACLK_MSCL, 21, 0, 0),
997 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
998 ENABLE_ACLK_MSCL, 20, 0, 0),
999 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
1000 ENABLE_ACLK_MSCL, 19, 0, 0),
1001 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
1002 ENABLE_ACLK_MSCL, 18, 0, 0),
1003 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
1004 ENABLE_ACLK_MSCL, 17, 0, 0),
1005 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
1006 ENABLE_ACLK_MSCL, 16, 0, 0),
1007 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
1008 "usermux_aclk_mscl_532",
1009 ENABLE_ACLK_MSCL, 15, 0, 0),
1010 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
1011 "usermux_aclk_mscl_532",
1012 ENABLE_ACLK_MSCL, 14, 0, 0),
1013
1014 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
1015 ENABLE_PCLK_MSCL, 31, 0, 0),
1016 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
1017 ENABLE_PCLK_MSCL, 30, 0, 0),
1018 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
1019 ENABLE_PCLK_MSCL, 29, 0, 0),
1020 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1021 ENABLE_PCLK_MSCL, 28, 0, 0),
1022 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
1023 ENABLE_PCLK_MSCL, 27, 0, 0),
1024 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
1025 ENABLE_PCLK_MSCL, 26, 0, 0),
1026 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
1027 ENABLE_PCLK_MSCL, 25, 0, 0),
1028 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
1029 ENABLE_PCLK_MSCL, 24, 0, 0),
1030 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
1031 ENABLE_PCLK_MSCL, 23, 0, 0),
1032 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
1033 ENABLE_PCLK_MSCL, 22, 0, 0),
1034 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
1035 ENABLE_PCLK_MSCL, 21, 0, 0),
1036 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
1037 ENABLE_PCLK_MSCL, 20, 0, 0),
1038};
1039
1040static struct samsung_cmu_info mscl_cmu_info __initdata = {
1041 .mux_clks = mscl_mux_clks,
1042 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
1043 .div_clks = mscl_div_clks,
1044 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
1045 .gate_clks = mscl_gate_clks,
1046 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
1047 .nr_clk_ids = MSCL_NR_CLK,
1048 .clk_regs = mscl_clk_regs,
1049 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
1050};
1051
1052static void __init exynos7_clk_mscl_init(struct device_node *np)
1053{
1054 samsung_cmu_register_one(np, &mscl_cmu_info);
1055}
1056
1057CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1058 exynos7_clk_mscl_init);
1059
1060/* Register Offset definitions for CMU_AUD (0x114C0000) */
1061#define MUX_SEL_AUD 0x0200
1062#define DIV_AUD0 0x0600
1063#define DIV_AUD1 0x0604
1064#define ENABLE_ACLK_AUD 0x0800
1065#define ENABLE_PCLK_AUD 0x0900
1066#define ENABLE_SCLK_AUD 0x0A00
1067
1068/*
1069 * List of parent clocks for Muxes in CMU_AUD
1070 */
1071PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
1072PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
1073
1074static unsigned long aud_clk_regs[] __initdata = {
1075 MUX_SEL_AUD,
1076 DIV_AUD0,
1077 DIV_AUD1,
1078 ENABLE_ACLK_AUD,
1079 ENABLE_PCLK_AUD,
1080 ENABLE_SCLK_AUD,
1081};
1082
1083static struct samsung_mux_clock aud_mux_clks[] __initdata = {
1084 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1085 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1086 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1087};
1088
1089static struct samsung_div_clock aud_div_clks[] __initdata = {
1090 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1091 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1092 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1093
1094 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1095 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1096 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1097 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1098 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1099};
1100
1101static struct samsung_gate_clock aud_gate_clks[] __initdata = {
1102 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1103 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1104 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1105 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1106 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1107 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1108 ENABLE_SCLK_AUD, 30, 0, 0),
1109
1110 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1111 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1112 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1113 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1114 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1115 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1116 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
1117 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1118 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
1119 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1120 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1121 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1122
1123 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1124 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1125 ENABLE_ACLK_AUD, 28, 0, 0),
1126 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
1127};
1128
1129static struct samsung_cmu_info aud_cmu_info __initdata = {
1130 .mux_clks = aud_mux_clks,
1131 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
1132 .div_clks = aud_div_clks,
1133 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
1134 .gate_clks = aud_gate_clks,
1135 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
1136 .nr_clk_ids = AUD_NR_CLK,
1137 .clk_regs = aud_clk_regs,
1138 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
1139};
1140
1141static void __init exynos7_clk_aud_init(struct device_node *np)
1142{
1143 samsung_cmu_register_one(np, &aud_cmu_info);
1144}
1145
1146CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
1147 exynos7_clk_aud_init);
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 4bda54095a16..9e1f88c04fd4 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -374,19 +374,24 @@ static void samsung_clk_sleep_init(void __iomem *reg_base,
374 * Common function which registers plls, muxes, dividers and gates 374 * Common function which registers plls, muxes, dividers and gates
375 * for each CMU. It also add CMU register list to register cache. 375 * for each CMU. It also add CMU register list to register cache.
376 */ 376 */
377void __init samsung_cmu_register_one(struct device_node *np, 377struct samsung_clk_provider * __init samsung_cmu_register_one(
378 struct device_node *np,
378 struct samsung_cmu_info *cmu) 379 struct samsung_cmu_info *cmu)
379{ 380{
380 void __iomem *reg_base; 381 void __iomem *reg_base;
381 struct samsung_clk_provider *ctx; 382 struct samsung_clk_provider *ctx;
382 383
383 reg_base = of_iomap(np, 0); 384 reg_base = of_iomap(np, 0);
384 if (!reg_base) 385 if (!reg_base) {
385 panic("%s: failed to map registers\n", __func__); 386 panic("%s: failed to map registers\n", __func__);
387 return NULL;
388 }
386 389
387 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); 390 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
388 if (!ctx) 391 if (!ctx) {
389 panic("%s: unable to alllocate ctx\n", __func__); 392 panic("%s: unable to alllocate ctx\n", __func__);
393 return ctx;
394 }
390 395
391 if (cmu->pll_clks) 396 if (cmu->pll_clks)
392 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks, 397 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
@@ -410,4 +415,6 @@ void __init samsung_cmu_register_one(struct device_node *np,
410 cmu->nr_clk_regs); 415 cmu->nr_clk_regs);
411 416
412 samsung_clk_of_add_provider(np, ctx); 417 samsung_clk_of_add_provider(np, ctx);
418
419 return ctx;
413} 420}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 8acabe1f32c4..e4c75383cea7 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -392,7 +392,8 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
392 struct samsung_pll_clock *pll_list, 392 struct samsung_pll_clock *pll_list,
393 unsigned int nr_clk, void __iomem *base); 393 unsigned int nr_clk, void __iomem *base);
394 394
395extern void __init samsung_cmu_register_one(struct device_node *, 395extern struct samsung_clk_provider __init *samsung_cmu_register_one(
396 struct device_node *,
396 struct samsung_cmu_info *); 397 struct samsung_cmu_info *);
397 398
398extern unsigned long _get_rate(const char *clk_name); 399extern unsigned long _get_rate(const char *clk_name);
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index f83980f2b956..0689d7fb2666 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -1,9 +1,11 @@
1obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o 1obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o 2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
3obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
3obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o 4obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
4obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o 5obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
5obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o 6obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
6obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o 7obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
8obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o
7obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o 9obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o
8obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o 10obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o
9obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o 11obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
index 639241e31e03..036a692c7219 100644
--- a/drivers/clk/shmobile/clk-div6.c
+++ b/drivers/clk/shmobile/clk-div6.c
@@ -54,12 +54,19 @@ static int cpg_div6_clock_enable(struct clk_hw *hw)
54static void cpg_div6_clock_disable(struct clk_hw *hw) 54static void cpg_div6_clock_disable(struct clk_hw *hw)
55{ 55{
56 struct div6_clock *clock = to_div6_clock(hw); 56 struct div6_clock *clock = to_div6_clock(hw);
57 u32 val;
57 58
58 /* DIV6 clocks require the divisor field to be non-zero when stopping 59 val = clk_readl(clock->reg);
59 * the clock. 60 val |= CPG_DIV6_CKSTP;
61 /*
62 * DIV6 clocks require the divisor field to be non-zero when stopping
63 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
64 * re-enabled later if the divisor field is changed when stopping the
65 * clock
60 */ 66 */
61 clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK, 67 if (!(val & CPG_DIV6_DIV_MASK))
62 clock->reg); 68 val |= CPG_DIV6_DIV_MASK;
69 clk_writel(val, clock->reg);
63} 70}
64 71
65static int cpg_div6_clock_is_enabled(struct clk_hw *hw) 72static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
@@ -83,6 +90,9 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
83{ 90{
84 unsigned int div; 91 unsigned int div;
85 92
93 if (!rate)
94 rate = 1;
95
86 div = DIV_ROUND_CLOSEST(parent_rate, rate); 96 div = DIV_ROUND_CLOSEST(parent_rate, rate);
87 return clamp_t(unsigned int, div, 1, 64); 97 return clamp_t(unsigned int, div, 1, 64);
88} 98}
diff --git a/drivers/clk/shmobile/clk-r8a73a4.c b/drivers/clk/shmobile/clk-r8a73a4.c
new file mode 100644
index 000000000000..29b9a0b0012a
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a73a4.c
@@ -0,0 +1,241 @@
1/*
2 * r8a73a4 Core CPG Clocks
3 *
4 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/shmobile.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/spinlock.h>
19
20struct r8a73a4_cpg {
21 struct clk_onecell_data data;
22 spinlock_t lock;
23 void __iomem *reg;
24};
25
26#define CPG_CKSCR 0xc0
27#define CPG_FRQCRA 0x00
28#define CPG_FRQCRB 0x04
29#define CPG_FRQCRC 0xe0
30#define CPG_PLL0CR 0xd8
31#define CPG_PLL1CR 0x28
32#define CPG_PLL2CR 0x2c
33#define CPG_PLL2HCR 0xe4
34#define CPG_PLL2SCR 0xf4
35
36#define CLK_ENABLE_ON_INIT BIT(0)
37
38struct div4_clk {
39 const char *name;
40 unsigned int reg;
41 unsigned int shift;
42};
43
44static struct div4_clk div4_clks[] = {
45 { "i", CPG_FRQCRA, 20 },
46 { "m3", CPG_FRQCRA, 12 },
47 { "b", CPG_FRQCRA, 8 },
48 { "m1", CPG_FRQCRA, 4 },
49 { "m2", CPG_FRQCRA, 0 },
50 { "zx", CPG_FRQCRB, 12 },
51 { "zs", CPG_FRQCRB, 8 },
52 { "hp", CPG_FRQCRB, 4 },
53 { NULL, 0, 0 },
54};
55
56static const struct clk_div_table div4_div_table[] = {
57 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
58 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
59 { 12, 10 }, { 0, 0 }
60};
61
62static struct clk * __init
63r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
64 const char *name)
65{
66 const struct clk_div_table *table = NULL;
67 const char *parent_name;
68 unsigned int shift, reg;
69 unsigned int mult = 1;
70 unsigned int div = 1;
71
72
73 if (!strcmp(name, "main")) {
74 u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR);
75
76 switch ((ckscr >> 28) & 3) {
77 case 0: /* extal1 */
78 parent_name = of_clk_get_parent_name(np, 0);
79 break;
80 case 1: /* extal1 / 2 */
81 parent_name = of_clk_get_parent_name(np, 0);
82 div = 2;
83 break;
84 case 2: /* extal2 */
85 parent_name = of_clk_get_parent_name(np, 1);
86 break;
87 case 3: /* extal2 / 2 */
88 parent_name = of_clk_get_parent_name(np, 1);
89 div = 2;
90 break;
91 }
92 } else if (!strcmp(name, "pll0")) {
93 /* PLL0/1 are configurable multiplier clocks. Register them as
94 * fixed factor clocks for now as there's no generic multiplier
95 * clock implementation and we currently have no need to change
96 * the multiplier value.
97 */
98 u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
99
100 parent_name = "main";
101 mult = ((value >> 24) & 0x7f) + 1;
102 if (value & BIT(20))
103 div = 2;
104 } else if (!strcmp(name, "pll1")) {
105 u32 value = clk_readl(cpg->reg + CPG_PLL1CR);
106
107 parent_name = "main";
108 /* XXX: enable bit? */
109 mult = ((value >> 24) & 0x7f) + 1;
110 if (value & BIT(7))
111 div = 2;
112 } else if (!strncmp(name, "pll2", 4)) {
113 u32 value, cr;
114
115 switch (name[4]) {
116 case 0:
117 cr = CPG_PLL2CR;
118 break;
119 case 's':
120 cr = CPG_PLL2SCR;
121 break;
122 case 'h':
123 cr = CPG_PLL2HCR;
124 break;
125 default:
126 return ERR_PTR(-EINVAL);
127 }
128 value = clk_readl(cpg->reg + cr);
129 switch ((value >> 5) & 7) {
130 case 0:
131 parent_name = "main";
132 div = 2;
133 break;
134 case 1:
135 parent_name = "extal2";
136 div = 2;
137 break;
138 case 3:
139 parent_name = "extal2";
140 div = 4;
141 break;
142 case 4:
143 parent_name = "main";
144 break;
145 case 5:
146 parent_name = "extal2";
147 break;
148 default:
149 pr_warn("%s: unexpected parent of %s\n", __func__,
150 name);
151 return ERR_PTR(-EINVAL);
152 }
153 /* XXX: enable bit? */
154 mult = ((value >> 24) & 0x7f) + 1;
155 } else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
156 u32 shift = 8;
157
158 parent_name = "pll0";
159 if (name[1] == '2') {
160 div = 2;
161 shift = 0;
162 }
163 div *= 32;
164 mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift)
165 & 0x1f);
166 } else {
167 struct div4_clk *c;
168
169 for (c = div4_clks; c->name; c++) {
170 if (!strcmp(name, c->name))
171 break;
172 }
173 if (!c->name)
174 return ERR_PTR(-EINVAL);
175
176 parent_name = "pll1";
177 table = div4_div_table;
178 reg = c->reg;
179 shift = c->shift;
180 }
181
182 if (!table) {
183 return clk_register_fixed_factor(NULL, name, parent_name, 0,
184 mult, div);
185 } else {
186 return clk_register_divider_table(NULL, name, parent_name, 0,
187 cpg->reg + reg, shift, 4, 0,
188 table, &cpg->lock);
189 }
190}
191
192static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
193{
194 struct r8a73a4_cpg *cpg;
195 struct clk **clks;
196 unsigned int i;
197 int num_clks;
198
199 num_clks = of_property_count_strings(np, "clock-output-names");
200 if (num_clks < 0) {
201 pr_err("%s: failed to count clocks\n", __func__);
202 return;
203 }
204
205 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
206 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
207 if (cpg == NULL || clks == NULL) {
208 /* We're leaking memory on purpose, there's no point in cleaning
209 * up as the system won't boot anyway.
210 */
211 return;
212 }
213
214 spin_lock_init(&cpg->lock);
215
216 cpg->data.clks = clks;
217 cpg->data.clk_num = num_clks;
218
219 cpg->reg = of_iomap(np, 0);
220 if (WARN_ON(cpg->reg == NULL))
221 return;
222
223 for (i = 0; i < num_clks; ++i) {
224 const char *name;
225 struct clk *clk;
226
227 of_property_read_string_index(np, "clock-output-names", i,
228 &name);
229
230 clk = r8a73a4_cpg_register_clock(np, cpg, name);
231 if (IS_ERR(clk))
232 pr_err("%s: failed to register %s %s clock (%ld)\n",
233 __func__, np->name, name, PTR_ERR(clk));
234 else
235 cpg->data.clks[i] = clk;
236 }
237
238 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
239}
240CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
241 r8a73a4_cpg_clocks_init);
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index e996425d06a9..acfb6d7dbd6b 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -33,6 +33,8 @@ struct rcar_gen2_cpg {
33#define CPG_FRQCRC 0x000000e0 33#define CPG_FRQCRC 0x000000e0
34#define CPG_FRQCRC_ZFC_MASK (0x1f << 8) 34#define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
35#define CPG_FRQCRC_ZFC_SHIFT 8 35#define CPG_FRQCRC_ZFC_SHIFT 8
36#define CPG_ADSPCKCR 0x0000025c
37#define CPG_RCANCKCR 0x00000270
36 38
37/* ----------------------------------------------------------------------------- 39/* -----------------------------------------------------------------------------
38 * Z Clock 40 * Z Clock
@@ -161,6 +163,88 @@ static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
161 return clk; 163 return clk;
162} 164}
163 165
166static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
167 struct device_node *np)
168{
169 const char *parent_name = of_clk_get_parent_name(np, 1);
170 struct clk_fixed_factor *fixed;
171 struct clk_gate *gate;
172 struct clk *clk;
173
174 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
175 if (!fixed)
176 return ERR_PTR(-ENOMEM);
177
178 fixed->mult = 1;
179 fixed->div = 6;
180
181 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
182 if (!gate) {
183 kfree(fixed);
184 return ERR_PTR(-ENOMEM);
185 }
186
187 gate->reg = cpg->reg + CPG_RCANCKCR;
188 gate->bit_idx = 8;
189 gate->flags = CLK_GATE_SET_TO_DISABLE;
190 gate->lock = &cpg->lock;
191
192 clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
193 &fixed->hw, &clk_fixed_factor_ops,
194 &gate->hw, &clk_gate_ops, 0);
195 if (IS_ERR(clk)) {
196 kfree(gate);
197 kfree(fixed);
198 }
199
200 return clk;
201}
202
203/* ADSP divisors */
204static const struct clk_div_table cpg_adsp_div_table[] = {
205 { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
206 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
207 { 10, 36 }, { 11, 48 }, { 0, 0 },
208};
209
210static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
211{
212 const char *parent_name = "pll1";
213 struct clk_divider *div;
214 struct clk_gate *gate;
215 struct clk *clk;
216
217 div = kzalloc(sizeof(*div), GFP_KERNEL);
218 if (!div)
219 return ERR_PTR(-ENOMEM);
220
221 div->reg = cpg->reg + CPG_ADSPCKCR;
222 div->width = 4;
223 div->table = cpg_adsp_div_table;
224 div->lock = &cpg->lock;
225
226 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
227 if (!gate) {
228 kfree(div);
229 return ERR_PTR(-ENOMEM);
230 }
231
232 gate->reg = cpg->reg + CPG_ADSPCKCR;
233 gate->bit_idx = 8;
234 gate->flags = CLK_GATE_SET_TO_DISABLE;
235 gate->lock = &cpg->lock;
236
237 clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
238 &div->hw, &clk_divider_ops,
239 &gate->hw, &clk_gate_ops, 0);
240 if (IS_ERR(clk)) {
241 kfree(gate);
242 kfree(div);
243 }
244
245 return clk;
246}
247
164/* ----------------------------------------------------------------------------- 248/* -----------------------------------------------------------------------------
165 * CPG Clock Data 249 * CPG Clock Data
166 */ 250 */
@@ -263,6 +347,10 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
263 shift = 0; 347 shift = 0;
264 } else if (!strcmp(name, "z")) { 348 } else if (!strcmp(name, "z")) {
265 return cpg_z_clk_register(cpg); 349 return cpg_z_clk_register(cpg);
350 } else if (!strcmp(name, "rcan")) {
351 return cpg_rcan_clk_register(cpg, np);
352 } else if (!strcmp(name, "adsp")) {
353 return cpg_adsp_clk_register(cpg);
266 } else { 354 } else {
267 return ERR_PTR(-EINVAL); 355 return ERR_PTR(-EINVAL);
268 } 356 }
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 2282cef9f2ff..bf12a25eb3a2 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -37,8 +37,8 @@ static int flexgen_enable(struct clk_hw *hw)
37 struct clk_hw *pgate_hw = &flexgen->pgate.hw; 37 struct clk_hw *pgate_hw = &flexgen->pgate.hw;
38 struct clk_hw *fgate_hw = &flexgen->fgate.hw; 38 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
39 39
40 pgate_hw->clk = hw->clk; 40 __clk_hw_set_clk(pgate_hw, hw);
41 fgate_hw->clk = hw->clk; 41 __clk_hw_set_clk(fgate_hw, hw);
42 42
43 clk_gate_ops.enable(pgate_hw); 43 clk_gate_ops.enable(pgate_hw);
44 44
@@ -54,7 +54,7 @@ static void flexgen_disable(struct clk_hw *hw)
54 struct clk_hw *fgate_hw = &flexgen->fgate.hw; 54 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
55 55
56 /* disable only the final gate */ 56 /* disable only the final gate */
57 fgate_hw->clk = hw->clk; 57 __clk_hw_set_clk(fgate_hw, hw);
58 58
59 clk_gate_ops.disable(fgate_hw); 59 clk_gate_ops.disable(fgate_hw);
60 60
@@ -66,7 +66,7 @@ static int flexgen_is_enabled(struct clk_hw *hw)
66 struct flexgen *flexgen = to_flexgen(hw); 66 struct flexgen *flexgen = to_flexgen(hw);
67 struct clk_hw *fgate_hw = &flexgen->fgate.hw; 67 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
68 68
69 fgate_hw->clk = hw->clk; 69 __clk_hw_set_clk(fgate_hw, hw);
70 70
71 if (!clk_gate_ops.is_enabled(fgate_hw)) 71 if (!clk_gate_ops.is_enabled(fgate_hw))
72 return 0; 72 return 0;
@@ -79,7 +79,7 @@ static u8 flexgen_get_parent(struct clk_hw *hw)
79 struct flexgen *flexgen = to_flexgen(hw); 79 struct flexgen *flexgen = to_flexgen(hw);
80 struct clk_hw *mux_hw = &flexgen->mux.hw; 80 struct clk_hw *mux_hw = &flexgen->mux.hw;
81 81
82 mux_hw->clk = hw->clk; 82 __clk_hw_set_clk(mux_hw, hw);
83 83
84 return clk_mux_ops.get_parent(mux_hw); 84 return clk_mux_ops.get_parent(mux_hw);
85} 85}
@@ -89,7 +89,7 @@ static int flexgen_set_parent(struct clk_hw *hw, u8 index)
89 struct flexgen *flexgen = to_flexgen(hw); 89 struct flexgen *flexgen = to_flexgen(hw);
90 struct clk_hw *mux_hw = &flexgen->mux.hw; 90 struct clk_hw *mux_hw = &flexgen->mux.hw;
91 91
92 mux_hw->clk = hw->clk; 92 __clk_hw_set_clk(mux_hw, hw);
93 93
94 return clk_mux_ops.set_parent(mux_hw, index); 94 return clk_mux_ops.set_parent(mux_hw, index);
95} 95}
@@ -124,8 +124,8 @@ unsigned long flexgen_recalc_rate(struct clk_hw *hw,
124 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; 124 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
125 unsigned long mid_rate; 125 unsigned long mid_rate;
126 126
127 pdiv_hw->clk = hw->clk; 127 __clk_hw_set_clk(pdiv_hw, hw);
128 fdiv_hw->clk = hw->clk; 128 __clk_hw_set_clk(fdiv_hw, hw);
129 129
130 mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate); 130 mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
131 131
@@ -138,16 +138,27 @@ static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
138 struct flexgen *flexgen = to_flexgen(hw); 138 struct flexgen *flexgen = to_flexgen(hw);
139 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; 139 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
140 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; 140 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
141 unsigned long primary_div = 0; 141 unsigned long div = 0;
142 int ret = 0; 142 int ret = 0;
143 143
144 pdiv_hw->clk = hw->clk; 144 __clk_hw_set_clk(pdiv_hw, hw);
145 fdiv_hw->clk = hw->clk; 145 __clk_hw_set_clk(fdiv_hw, hw);
146 146
147 primary_div = clk_best_div(parent_rate, rate); 147 div = clk_best_div(parent_rate, rate);
148 148
149 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); 149 /*
150 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div); 150 * pdiv is mainly targeted for low freq results, while fdiv
151 * should be used for div <= 64. The other way round can
152 * lead to 'duty cycle' issues.
153 */
154
155 if (div <= 64) {
156 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
157 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
158 } else {
159 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
160 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
161 }
151 162
152 return ret; 163 return ret;
153} 164}
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 79dc40b5cc68..9a15ec344a85 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -94,7 +94,7 @@ static int clkgena_divmux_enable(struct clk_hw *hw)
94 unsigned long timeout; 94 unsigned long timeout;
95 int ret = 0; 95 int ret = 0;
96 96
97 mux_hw->clk = hw->clk; 97 __clk_hw_set_clk(mux_hw, hw);
98 98
99 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel); 99 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
100 if (ret) 100 if (ret)
@@ -116,7 +116,7 @@ static void clkgena_divmux_disable(struct clk_hw *hw)
116 struct clkgena_divmux *genamux = to_clkgena_divmux(hw); 116 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
117 struct clk_hw *mux_hw = &genamux->mux.hw; 117 struct clk_hw *mux_hw = &genamux->mux.hw;
118 118
119 mux_hw->clk = hw->clk; 119 __clk_hw_set_clk(mux_hw, hw);
120 120
121 clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF); 121 clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
122} 122}
@@ -126,7 +126,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
126 struct clkgena_divmux *genamux = to_clkgena_divmux(hw); 126 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
127 struct clk_hw *mux_hw = &genamux->mux.hw; 127 struct clk_hw *mux_hw = &genamux->mux.hw;
128 128
129 mux_hw->clk = hw->clk; 129 __clk_hw_set_clk(mux_hw, hw);
130 130
131 return (s8)clk_mux_ops.get_parent(mux_hw) > 0; 131 return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
132} 132}
@@ -136,7 +136,7 @@ u8 clkgena_divmux_get_parent(struct clk_hw *hw)
136 struct clkgena_divmux *genamux = to_clkgena_divmux(hw); 136 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
137 struct clk_hw *mux_hw = &genamux->mux.hw; 137 struct clk_hw *mux_hw = &genamux->mux.hw;
138 138
139 mux_hw->clk = hw->clk; 139 __clk_hw_set_clk(mux_hw, hw);
140 140
141 genamux->muxsel = clk_mux_ops.get_parent(mux_hw); 141 genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
142 if ((s8)genamux->muxsel < 0) { 142 if ((s8)genamux->muxsel < 0) {
@@ -174,7 +174,7 @@ unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
174 struct clkgena_divmux *genamux = to_clkgena_divmux(hw); 174 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
175 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw; 175 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
176 176
177 div_hw->clk = hw->clk; 177 __clk_hw_set_clk(div_hw, hw);
178 178
179 return clk_divider_ops.recalc_rate(div_hw, parent_rate); 179 return clk_divider_ops.recalc_rate(div_hw, parent_rate);
180} 180}
@@ -185,7 +185,7 @@ static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
185 struct clkgena_divmux *genamux = to_clkgena_divmux(hw); 185 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
186 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw; 186 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
187 187
188 div_hw->clk = hw->clk; 188 __clk_hw_set_clk(div_hw, hw);
189 189
190 return clk_divider_ops.set_rate(div_hw, rate, parent_rate); 190 return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
191} 191}
@@ -196,7 +196,7 @@ static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
196 struct clkgena_divmux *genamux = to_clkgena_divmux(hw); 196 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
197 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw; 197 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
198 198
199 div_hw->clk = hw->clk; 199 __clk_hw_set_clk(div_hw, hw);
200 200
201 return clk_divider_ops.round_rate(div_hw, rate, prate); 201 return clk_divider_ops.round_rate(div_hw, rate, prate);
202} 202}
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index a66953c0f430..3a5292e3fcf8 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,6 +8,7 @@ obj-y += clk-a20-gmac.o
8obj-y += clk-mod0.o 8obj-y += clk-mod0.o
9obj-y += clk-sun8i-mbus.o 9obj-y += clk-sun8i-mbus.o
10obj-y += clk-sun9i-core.o 10obj-y += clk-sun9i-core.o
11obj-y += clk-sun9i-mmc.o
11 12
12obj-$(CONFIG_MFD_SUN6I_PRCM) += \ 13obj-$(CONFIG_MFD_SUN6I_PRCM) += \
13 clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \ 14 clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 62e08fb58554..8c20190a3e9f 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -80,6 +80,8 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
80} 80}
81 81
82static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate, 82static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
83 unsigned long min_rate,
84 unsigned long max_rate,
83 unsigned long *best_parent_rate, 85 unsigned long *best_parent_rate,
84 struct clk_hw **best_parent_p) 86 struct clk_hw **best_parent_p)
85{ 87{
@@ -156,9 +158,10 @@ static const struct clk_ops clk_factors_ops = {
156 .set_rate = clk_factors_set_rate, 158 .set_rate = clk_factors_set_rate,
157}; 159};
158 160
159struct clk * __init sunxi_factors_register(struct device_node *node, 161struct clk *sunxi_factors_register(struct device_node *node,
160 const struct factors_data *data, 162 const struct factors_data *data,
161 spinlock_t *lock) 163 spinlock_t *lock,
164 void __iomem *reg)
162{ 165{
163 struct clk *clk; 166 struct clk *clk;
164 struct clk_factors *factors; 167 struct clk_factors *factors;
@@ -168,11 +171,8 @@ struct clk * __init sunxi_factors_register(struct device_node *node,
168 struct clk_hw *mux_hw = NULL; 171 struct clk_hw *mux_hw = NULL;
169 const char *clk_name = node->name; 172 const char *clk_name = node->name;
170 const char *parents[FACTORS_MAX_PARENTS]; 173 const char *parents[FACTORS_MAX_PARENTS];
171 void __iomem *reg;
172 int i = 0; 174 int i = 0;
173 175
174 reg = of_iomap(node, 0);
175
176 /* if we have a mux, we will have >1 parents */ 176 /* if we have a mux, we will have >1 parents */
177 while (i < FACTORS_MAX_PARENTS && 177 while (i < FACTORS_MAX_PARENTS &&
178 (parents[i] = of_clk_get_parent_name(node, i)) != NULL) 178 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 912238fde132..171085ab5513 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -36,8 +36,9 @@ struct clk_factors {
36 spinlock_t *lock; 36 spinlock_t *lock;
37}; 37};
38 38
39struct clk * __init sunxi_factors_register(struct device_node *node, 39struct clk *sunxi_factors_register(struct device_node *node,
40 const struct factors_data *data, 40 const struct factors_data *data,
41 spinlock_t *lock); 41 spinlock_t *lock,
42 void __iomem *reg);
42 43
43#endif 44#endif
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index da0524eaee94..ec8f5a1fca09 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -17,6 +17,7 @@
17#include <linux/clk-provider.h> 17#include <linux/clk-provider.h>
18#include <linux/clkdev.h> 18#include <linux/clkdev.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/platform_device.h>
20 21
21#include "clk-factors.h" 22#include "clk-factors.h"
22 23
@@ -67,7 +68,7 @@ static struct clk_factors_config sun4i_a10_mod0_config = {
67 .pwidth = 2, 68 .pwidth = 2,
68}; 69};
69 70
70static const struct factors_data sun4i_a10_mod0_data __initconst = { 71static const struct factors_data sun4i_a10_mod0_data = {
71 .enable = 31, 72 .enable = 31,
72 .mux = 24, 73 .mux = 24,
73 .muxmask = BIT(1) | BIT(0), 74 .muxmask = BIT(1) | BIT(0),
@@ -79,15 +80,95 @@ static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
79 80
80static void __init sun4i_a10_mod0_setup(struct device_node *node) 81static void __init sun4i_a10_mod0_setup(struct device_node *node)
81{ 82{
82 sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun4i_a10_mod0_lock); 83 void __iomem *reg;
84
85 reg = of_iomap(node, 0);
86 if (!reg) {
87 /*
88 * This happens with mod0 clk nodes instantiated through
89 * mfd, as those do not have their resources assigned at
90 * CLK_OF_DECLARE time yet, so do not print an error.
91 */
92 return;
93 }
94
95 sunxi_factors_register(node, &sun4i_a10_mod0_data,
96 &sun4i_a10_mod0_lock, reg);
83} 97}
84CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup); 98CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
85 99
100static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
101{
102 struct device_node *np = pdev->dev.of_node;
103 struct resource *r;
104 void __iomem *reg;
105
106 if (!np)
107 return -ENODEV;
108
109 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110 reg = devm_ioremap_resource(&pdev->dev, r);
111 if (IS_ERR(reg))
112 return PTR_ERR(reg);
113
114 sunxi_factors_register(np, &sun4i_a10_mod0_data,
115 &sun4i_a10_mod0_lock, reg);
116 return 0;
117}
118
119static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
120 { .compatible = "allwinner,sun4i-a10-mod0-clk" },
121 { /* sentinel */ }
122};
123
124static struct platform_driver sun4i_a10_mod0_clk_driver = {
125 .driver = {
126 .name = "sun4i-a10-mod0-clk",
127 .of_match_table = sun4i_a10_mod0_clk_dt_ids,
128 },
129 .probe = sun4i_a10_mod0_clk_probe,
130};
131module_platform_driver(sun4i_a10_mod0_clk_driver);
132
133static const struct factors_data sun9i_a80_mod0_data __initconst = {
134 .enable = 31,
135 .mux = 24,
136 .muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
137 .table = &sun4i_a10_mod0_config,
138 .getter = sun4i_a10_get_mod0_factors,
139};
140
141static void __init sun9i_a80_mod0_setup(struct device_node *node)
142{
143 void __iomem *reg;
144
145 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
146 if (IS_ERR(reg)) {
147 pr_err("Could not get registers for mod0-clk: %s\n",
148 node->name);
149 return;
150 }
151
152 sunxi_factors_register(node, &sun9i_a80_mod0_data,
153 &sun4i_a10_mod0_lock, reg);
154}
155CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
156
86static DEFINE_SPINLOCK(sun5i_a13_mbus_lock); 157static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
87 158
88static void __init sun5i_a13_mbus_setup(struct device_node *node) 159static void __init sun5i_a13_mbus_setup(struct device_node *node)
89{ 160{
90 struct clk *mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data, &sun5i_a13_mbus_lock); 161 struct clk *mbus;
162 void __iomem *reg;
163
164 reg = of_iomap(node, 0);
165 if (!reg) {
166 pr_err("Could not get registers for a13-mbus-clk\n");
167 return;
168 }
169
170 mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
171 &sun5i_a13_mbus_lock, reg);
91 172
92 /* The MBUS clocks needs to be always enabled */ 173 /* The MBUS clocks needs to be always enabled */
93 __clk_get(mbus); 174 __clk_get(mbus);
@@ -95,14 +176,10 @@ static void __init sun5i_a13_mbus_setup(struct device_node *node)
95} 176}
96CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup); 177CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
97 178
98struct mmc_phase_data {
99 u8 offset;
100};
101
102struct mmc_phase { 179struct mmc_phase {
103 struct clk_hw hw; 180 struct clk_hw hw;
181 u8 offset;
104 void __iomem *reg; 182 void __iomem *reg;
105 struct mmc_phase_data *data;
106 spinlock_t *lock; 183 spinlock_t *lock;
107}; 184};
108 185
@@ -118,7 +195,7 @@ static int mmc_get_phase(struct clk_hw *hw)
118 u8 delay; 195 u8 delay;
119 196
120 value = readl(phase->reg); 197 value = readl(phase->reg);
121 delay = (value >> phase->data->offset) & 0x3; 198 delay = (value >> phase->offset) & 0x3;
122 199
123 if (!delay) 200 if (!delay)
124 return 180; 201 return 180;
@@ -206,8 +283,8 @@ static int mmc_set_phase(struct clk_hw *hw, int degrees)
206 283
207 spin_lock_irqsave(phase->lock, flags); 284 spin_lock_irqsave(phase->lock, flags);
208 value = readl(phase->reg); 285 value = readl(phase->reg);
209 value &= ~GENMASK(phase->data->offset + 3, phase->data->offset); 286 value &= ~GENMASK(phase->offset + 3, phase->offset);
210 value |= delay << phase->data->offset; 287 value |= delay << phase->offset;
211 writel(value, phase->reg); 288 writel(value, phase->reg);
212 spin_unlock_irqrestore(phase->lock, flags); 289 spin_unlock_irqrestore(phase->lock, flags);
213 290
@@ -219,66 +296,97 @@ static const struct clk_ops mmc_clk_ops = {
219 .set_phase = mmc_set_phase, 296 .set_phase = mmc_set_phase,
220}; 297};
221 298
222static void __init sun4i_a10_mmc_phase_setup(struct device_node *node, 299/*
223 struct mmc_phase_data *data) 300 * sunxi_mmc_setup - Common setup function for mmc module clocks
301 *
302 * The only difference between module clocks on different platforms is the
303 * width of the mux register bits and the valid values, which are passed in
304 * through struct factors_data. The phase clocks parts are identical.
305 */
306static void __init sunxi_mmc_setup(struct device_node *node,
307 const struct factors_data *data,
308 spinlock_t *lock)
224{ 309{
225 const char *parent_names[1] = { of_clk_get_parent_name(node, 0) }; 310 struct clk_onecell_data *clk_data;
226 struct clk_init_data init = { 311 const char *parent;
227 .num_parents = 1, 312 void __iomem *reg;
228 .parent_names = parent_names, 313 int i;
229 .ops = &mmc_clk_ops, 314
230 }; 315 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
231 316 if (IS_ERR(reg)) {
232 struct mmc_phase *phase; 317 pr_err("Couldn't map the %s clock registers\n", node->name);
233 struct clk *clk;
234
235 phase = kmalloc(sizeof(*phase), GFP_KERNEL);
236 if (!phase)
237 return; 318 return;
319 }
238 320
239 phase->hw.init = &init; 321 clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
240 322 if (!clk_data)
241 phase->reg = of_iomap(node, 0); 323 return;
242 if (!phase->reg)
243 goto err_free;
244
245 phase->data = data;
246 phase->lock = &sun4i_a10_mod0_lock;
247
248 if (of_property_read_string(node, "clock-output-names", &init.name))
249 init.name = node->name;
250 324
251 clk = clk_register(NULL, &phase->hw); 325 clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
252 if (IS_ERR(clk)) 326 if (!clk_data->clks)
253 goto err_unmap; 327 goto err_free_data;
328
329 clk_data->clk_num = 3;
330 clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
331 if (!clk_data->clks[0])
332 goto err_free_clks;
333
334 parent = __clk_get_name(clk_data->clks[0]);
335
336 for (i = 1; i < 3; i++) {
337 struct clk_init_data init = {
338 .num_parents = 1,
339 .parent_names = &parent,
340 .ops = &mmc_clk_ops,
341 };
342 struct mmc_phase *phase;
343
344 phase = kmalloc(sizeof(*phase), GFP_KERNEL);
345 if (!phase)
346 continue;
347
348 phase->hw.init = &init;
349 phase->reg = reg;
350 phase->lock = lock;
351
352 if (i == 1)
353 phase->offset = 8;
354 else
355 phase->offset = 20;
356
357 if (of_property_read_string_index(node, "clock-output-names",
358 i, &init.name))
359 init.name = node->name;
360
361 clk_data->clks[i] = clk_register(NULL, &phase->hw);
362 if (IS_ERR(clk_data->clks[i])) {
363 kfree(phase);
364 continue;
365 }
366 }
254 367
255 of_clk_add_provider(node, of_clk_src_simple_get, clk); 368 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
256 369
257 return; 370 return;
258 371
259err_unmap: 372err_free_clks:
260 iounmap(phase->reg); 373 kfree(clk_data->clks);
261err_free: 374err_free_data:
262 kfree(phase); 375 kfree(clk_data);
263} 376}
264 377
378static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);
265 379
266static struct mmc_phase_data mmc_output_clk = { 380static void __init sun4i_a10_mmc_setup(struct device_node *node)
267 .offset = 8,
268};
269
270static struct mmc_phase_data mmc_sample_clk = {
271 .offset = 20,
272};
273
274static void __init sun4i_a10_mmc_output_setup(struct device_node *node)
275{ 381{
276 sun4i_a10_mmc_phase_setup(node, &mmc_output_clk); 382 sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock);
277} 383}
278CLK_OF_DECLARE(sun4i_a10_mmc_output, "allwinner,sun4i-a10-mmc-output-clk", sun4i_a10_mmc_output_setup); 384CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
385
386static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);
279 387
280static void __init sun4i_a10_mmc_sample_setup(struct device_node *node) 388static void __init sun9i_a80_mmc_setup(struct device_node *node)
281{ 389{
282 sun4i_a10_mmc_phase_setup(node, &mmc_sample_clk); 390 sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock);
283} 391}
284CLK_OF_DECLARE(sun4i_a10_mmc_sample, "allwinner,sun4i-a10-mmc-sample-clk", sun4i_a10_mmc_sample_setup); 392CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index 3d282fb8f85c..63cf149195ae 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -45,6 +45,8 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw,
45} 45}
46 46
47static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, 47static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
48 unsigned long min_rate,
49 unsigned long max_rate,
48 unsigned long *best_parent_rate, 50 unsigned long *best_parent_rate,
49 struct clk_hw **best_parent_clk) 51 struct clk_hw **best_parent_clk)
50{ 52{
diff --git a/drivers/clk/sunxi/clk-sun8i-mbus.c b/drivers/clk/sunxi/clk-sun8i-mbus.c
index ef49786eefd3..14cd026064bf 100644
--- a/drivers/clk/sunxi/clk-sun8i-mbus.c
+++ b/drivers/clk/sunxi/clk-sun8i-mbus.c
@@ -69,8 +69,17 @@ static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
69 69
70static void __init sun8i_a23_mbus_setup(struct device_node *node) 70static void __init sun8i_a23_mbus_setup(struct device_node *node)
71{ 71{
72 struct clk *mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data, 72 struct clk *mbus;
73 &sun8i_a23_mbus_lock); 73 void __iomem *reg;
74
75 reg = of_iomap(node, 0);
76 if (!reg) {
77 pr_err("Could not get registers for a23-mbus-clk\n");
78 return;
79 }
80
81 mbus = sunxi_factors_register(node, &sun8i_a23_mbus_data,
82 &sun8i_a23_mbus_lock, reg);
74 83
75 /* The MBUS clocks needs to be always enabled */ 84 /* The MBUS clocks needs to be always enabled */
76 __clk_get(mbus); 85 __clk_get(mbus);
diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-sun9i-core.c
index 3cb9036d91bb..d8da77d72861 100644
--- a/drivers/clk/sunxi/clk-sun9i-core.c
+++ b/drivers/clk/sunxi/clk-sun9i-core.c
@@ -24,50 +24,51 @@
24 24
25 25
26/** 26/**
27 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1 27 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
28 * PLL4 rate is calculated as follows 28 * PLL4 rate is calculated as follows
29 * rate = (parent_rate * n >> p) / (m + 1); 29 * rate = (parent_rate * n >> p) / (m + 1);
30 * parent_rate is always 24Mhz 30 * parent_rate is always 24MHz
31 * 31 *
32 * p and m are named div1 and div2 in Allwinner's SDK 32 * p and m are named div1 and div2 in Allwinner's SDK
33 */ 33 */
34 34
35static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate, 35static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
36 u8 *n, u8 *k, u8 *m, u8 *p) 36 u8 *n_ret, u8 *k, u8 *m_ret, u8 *p_ret)
37{ 37{
38 int div; 38 int n;
39 int m = 1;
40 int p = 1;
39 41
40 /* Normalize value to a 6M multiple */ 42 /* Normalize value to a 6 MHz multiple (24 MHz / 4) */
41 div = DIV_ROUND_UP(*freq, 6000000); 43 n = DIV_ROUND_UP(*freq, 6000000);
42 44
43 /* divs above 256 cannot be odd */ 45 /* If n is too large switch to steps of 12 MHz */
44 if (div > 256) 46 if (n > 255) {
45 div = round_up(div, 2); 47 m = 0;
48 n = (n + 1) / 2;
49 }
50
51 /* If n is still too large switch to steps of 24 MHz */
52 if (n > 255) {
53 p = 0;
54 n = (n + 1) / 2;
55 }
46 56
47 /* divs above 512 must be a multiple of 4 */ 57 /* n must be between 12 and 255 */
48 if (div > 512) 58 if (n > 255)
49 div = round_up(div, 4); 59 n = 255;
60 else if (n < 12)
61 n = 12;
50 62
51 *freq = 6000000 * div; 63 *freq = ((24000000 * n) >> p) / (m + 1);
52 64
53 /* we were called to round the frequency, we can now return */ 65 /* we were called to round the frequency, we can now return */
54 if (n == NULL) 66 if (n_ret == NULL)
55 return; 67 return;
56 68
57 /* p will be 1 for divs under 512 */ 69 *n_ret = n;
58 if (div < 512) 70 *m_ret = m;
59 *p = 1; 71 *p_ret = p;
60 else
61 *p = 0;
62
63 /* m will be 1 if div is odd */
64 if (div & 1)
65 *m = 1;
66 else
67 *m = 0;
68
69 /* calculate a suitable n based on m and p */
70 *n = div / (*p + 1) / (*m + 1);
71} 72}
72 73
73static struct clk_factors_config sun9i_a80_pll4_config = { 74static struct clk_factors_config sun9i_a80_pll4_config = {
@@ -89,7 +90,17 @@ static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
89 90
90static void __init sun9i_a80_pll4_setup(struct device_node *node) 91static void __init sun9i_a80_pll4_setup(struct device_node *node)
91{ 92{
92 sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock); 93 void __iomem *reg;
94
95 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
96 if (!reg) {
97 pr_err("Could not get registers for a80-pll4-clk: %s\n",
98 node->name);
99 return;
100 }
101
102 sunxi_factors_register(node, &sun9i_a80_pll4_data,
103 &sun9i_a80_pll4_lock, reg);
93} 104}
94CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup); 105CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
95 106
@@ -139,8 +150,18 @@ static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
139 150
140static void __init sun9i_a80_gt_setup(struct device_node *node) 151static void __init sun9i_a80_gt_setup(struct device_node *node)
141{ 152{
142 struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data, 153 void __iomem *reg;
143 &sun9i_a80_gt_lock); 154 struct clk *gt;
155
156 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
157 if (!reg) {
158 pr_err("Could not get registers for a80-gt-clk: %s\n",
159 node->name);
160 return;
161 }
162
163 gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
164 &sun9i_a80_gt_lock, reg);
144 165
145 /* The GT bus clock needs to be always enabled */ 166 /* The GT bus clock needs to be always enabled */
146 __clk_get(gt); 167 __clk_get(gt);
@@ -194,7 +215,17 @@ static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
194 215
195static void __init sun9i_a80_ahb_setup(struct device_node *node) 216static void __init sun9i_a80_ahb_setup(struct device_node *node)
196{ 217{
197 sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock); 218 void __iomem *reg;
219
220 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
221 if (!reg) {
222 pr_err("Could not get registers for a80-ahb-clk: %s\n",
223 node->name);
224 return;
225 }
226
227 sunxi_factors_register(node, &sun9i_a80_ahb_data,
228 &sun9i_a80_ahb_lock, reg);
198} 229}
199CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup); 230CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
200 231
@@ -210,7 +241,17 @@ static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
210 241
211static void __init sun9i_a80_apb0_setup(struct device_node *node) 242static void __init sun9i_a80_apb0_setup(struct device_node *node)
212{ 243{
213 sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock); 244 void __iomem *reg;
245
246 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
247 if (!reg) {
248 pr_err("Could not get registers for a80-apb0-clk: %s\n",
249 node->name);
250 return;
251 }
252
253 sunxi_factors_register(node, &sun9i_a80_apb0_data,
254 &sun9i_a80_apb0_lock, reg);
214} 255}
215CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup); 256CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
216 257
@@ -266,6 +307,16 @@ static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
266 307
267static void __init sun9i_a80_apb1_setup(struct device_node *node) 308static void __init sun9i_a80_apb1_setup(struct device_node *node)
268{ 309{
269 sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock); 310 void __iomem *reg;
311
312 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
313 if (!reg) {
314 pr_err("Could not get registers for a80-apb1-clk: %s\n",
315 node->name);
316 return;
317 }
318
319 sunxi_factors_register(node, &sun9i_a80_apb1_data,
320 &sun9i_a80_apb1_lock, reg);
270} 321}
271CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup); 322CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c
new file mode 100644
index 000000000000..710c273648d7
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun9i-mmc.c
@@ -0,0 +1,219 @@
1/*
2 * Copyright 2015 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/reset.h>
23#include <linux/platform_device.h>
24#include <linux/reset-controller.h>
25#include <linux/spinlock.h>
26
27#define SUN9I_MMC_WIDTH 4
28
29#define SUN9I_MMC_GATE_BIT 16
30#define SUN9I_MMC_RESET_BIT 18
31
32struct sun9i_mmc_clk_data {
33 spinlock_t lock;
34 void __iomem *membase;
35 struct clk *clk;
36 struct reset_control *reset;
37 struct clk_onecell_data clk_data;
38 struct reset_controller_dev rcdev;
39};
40
41static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
42 unsigned long id)
43{
44 struct sun9i_mmc_clk_data *data = container_of(rcdev,
45 struct sun9i_mmc_clk_data,
46 rcdev);
47 unsigned long flags;
48 void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
49 u32 val;
50
51 clk_prepare_enable(data->clk);
52 spin_lock_irqsave(&data->lock, flags);
53
54 val = readl(reg);
55 writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
56
57 spin_unlock_irqrestore(&data->lock, flags);
58 clk_disable_unprepare(data->clk);
59
60 return 0;
61}
62
63static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
64 unsigned long id)
65{
66 struct sun9i_mmc_clk_data *data = container_of(rcdev,
67 struct sun9i_mmc_clk_data,
68 rcdev);
69 unsigned long flags;
70 void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
71 u32 val;
72
73 clk_prepare_enable(data->clk);
74 spin_lock_irqsave(&data->lock, flags);
75
76 val = readl(reg);
77 writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
78
79 spin_unlock_irqrestore(&data->lock, flags);
80 clk_disable_unprepare(data->clk);
81
82 return 0;
83}
84
85static struct reset_control_ops sun9i_mmc_reset_ops = {
86 .assert = sun9i_mmc_reset_assert,
87 .deassert = sun9i_mmc_reset_deassert,
88};
89
90static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
91{
92 struct device_node *np = pdev->dev.of_node;
93 struct sun9i_mmc_clk_data *data;
94 struct clk_onecell_data *clk_data;
95 const char *clk_name = np->name;
96 const char *clk_parent;
97 struct resource *r;
98 int count, i, ret;
99
100 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
101 if (!data)
102 return -ENOMEM;
103
104 spin_lock_init(&data->lock);
105
106 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107 /* one clock/reset pair per word */
108 count = DIV_ROUND_UP((r->end - r->start + 1), SUN9I_MMC_WIDTH);
109 data->membase = devm_ioremap_resource(&pdev->dev, r);
110 if (IS_ERR(data->membase))
111 return PTR_ERR(data->membase);
112
113 clk_data = &data->clk_data;
114 clk_data->clk_num = count;
115 clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
116 GFP_KERNEL);
117 if (!clk_data->clks)
118 return -ENOMEM;
119
120 data->clk = devm_clk_get(&pdev->dev, NULL);
121 if (IS_ERR(data->clk)) {
122 dev_err(&pdev->dev, "Could not get clock\n");
123 return PTR_ERR(data->clk);
124 }
125
126 data->reset = devm_reset_control_get(&pdev->dev, NULL);
127 if (IS_ERR(data->reset)) {
128 dev_err(&pdev->dev, "Could not get reset control\n");
129 return PTR_ERR(data->reset);
130 }
131
132 ret = reset_control_deassert(data->reset);
133 if (ret) {
134 dev_err(&pdev->dev, "Reset deassert err %d\n", ret);
135 return ret;
136 }
137
138 clk_parent = __clk_get_name(data->clk);
139 for (i = 0; i < count; i++) {
140 of_property_read_string_index(np, "clock-output-names",
141 i, &clk_name);
142
143 clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
144 clk_parent, 0,
145 data->membase + SUN9I_MMC_WIDTH * i,
146 SUN9I_MMC_GATE_BIT, 0,
147 &data->lock);
148
149 if (IS_ERR(clk_data->clks[i])) {
150 ret = PTR_ERR(clk_data->clks[i]);
151 goto err_clk_register;
152 }
153 }
154
155 ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
156 if (ret)
157 goto err_clk_provider;
158
159 data->rcdev.owner = THIS_MODULE;
160 data->rcdev.nr_resets = count;
161 data->rcdev.ops = &sun9i_mmc_reset_ops;
162 data->rcdev.of_node = pdev->dev.of_node;
163
164 ret = reset_controller_register(&data->rcdev);
165 if (ret)
166 goto err_rc_reg;
167
168 platform_set_drvdata(pdev, data);
169
170 return 0;
171
172err_rc_reg:
173 of_clk_del_provider(np);
174
175err_clk_provider:
176 for (i = 0; i < count; i++)
177 clk_unregister(clk_data->clks[i]);
178
179err_clk_register:
180 reset_control_assert(data->reset);
181
182 return ret;
183}
184
185static int sun9i_a80_mmc_config_clk_remove(struct platform_device *pdev)
186{
187 struct device_node *np = pdev->dev.of_node;
188 struct sun9i_mmc_clk_data *data = platform_get_drvdata(pdev);
189 struct clk_onecell_data *clk_data = &data->clk_data;
190 int i;
191
192 reset_controller_unregister(&data->rcdev);
193 of_clk_del_provider(np);
194 for (i = 0; i < clk_data->clk_num; i++)
195 clk_unregister(clk_data->clks[i]);
196
197 reset_control_assert(data->reset);
198
199 return 0;
200}
201
202static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
203 { .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
204 { /* sentinel */ }
205};
206
207static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
208 .driver = {
209 .name = "sun9i-a80-mmc-config-clk",
210 .of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
211 },
212 .probe = sun9i_a80_mmc_config_clk_probe,
213 .remove = sun9i_a80_mmc_config_clk_remove,
214};
215module_platform_driver(sun9i_a80_mmc_config_clk_driver);
216
217MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
218MODULE_DESCRIPTION("Allwinner A80 MMC clock/reset Driver");
219MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 1818f404538d..379324eb5486 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -20,11 +20,221 @@
20#include <linux/of_address.h> 20#include <linux/of_address.h>
21#include <linux/reset-controller.h> 21#include <linux/reset-controller.h>
22#include <linux/spinlock.h> 22#include <linux/spinlock.h>
23#include <linux/log2.h>
23 24
24#include "clk-factors.h" 25#include "clk-factors.h"
25 26
26static DEFINE_SPINLOCK(clk_lock); 27static DEFINE_SPINLOCK(clk_lock);
27 28
29/**
30 * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
31 */
32
33#define SUN6I_AHB1_MAX_PARENTS 4
34#define SUN6I_AHB1_MUX_PARENT_PLL6 3
35#define SUN6I_AHB1_MUX_SHIFT 12
36/* un-shifted mask is what mux_clk expects */
37#define SUN6I_AHB1_MUX_MASK 0x3
38#define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
39 SUN6I_AHB1_MUX_MASK)
40
41#define SUN6I_AHB1_DIV_SHIFT 4
42#define SUN6I_AHB1_DIV_MASK (0x3 << SUN6I_AHB1_DIV_SHIFT)
43#define SUN6I_AHB1_DIV_GET(reg) ((reg & SUN6I_AHB1_DIV_MASK) >> \
44 SUN6I_AHB1_DIV_SHIFT)
45#define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
46 (div << SUN6I_AHB1_DIV_SHIFT))
47#define SUN6I_AHB1_PLL6_DIV_SHIFT 6
48#define SUN6I_AHB1_PLL6_DIV_MASK (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
49#define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
50 SUN6I_AHB1_PLL6_DIV_SHIFT)
51#define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
52 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
53
54struct sun6i_ahb1_clk {
55 struct clk_hw hw;
56 void __iomem *reg;
57};
58
59#define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
60
61static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
63{
64 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
65 unsigned long rate;
66 u32 reg;
67
68 /* Fetch the register value */
69 reg = readl(ahb1->reg);
70
71 /* apply pre-divider first if parent is pll6 */
72 if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
73 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
74
75 /* clk divider */
76 rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
77
78 return rate;
79}
80
81static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
82 u8 parent, unsigned long parent_rate)
83{
84 u8 div, calcp, calcm = 1;
85
86 /*
87 * clock can only divide, so we will never be able to achieve
88 * frequencies higher than the parent frequency
89 */
90 if (parent_rate && rate > parent_rate)
91 rate = parent_rate;
92
93 div = DIV_ROUND_UP(parent_rate, rate);
94
95 /* calculate pre-divider if parent is pll6 */
96 if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
97 if (div < 4)
98 calcp = 0;
99 else if (div / 2 < 4)
100 calcp = 1;
101 else if (div / 4 < 4)
102 calcp = 2;
103 else
104 calcp = 3;
105
106 calcm = DIV_ROUND_UP(div, 1 << calcp);
107 } else {
108 calcp = __roundup_pow_of_two(div);
109 calcp = calcp > 3 ? 3 : calcp;
110 }
111
112 /* we were asked to pass back divider values */
113 if (divp) {
114 *divp = calcp;
115 *pre_divp = calcm - 1;
116 }
117
118 return (parent_rate / calcm) >> calcp;
119}
120
121static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
122 unsigned long min_rate,
123 unsigned long max_rate,
124 unsigned long *best_parent_rate,
125 struct clk_hw **best_parent_clk)
126{
127 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
128 int i, num_parents;
129 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
130
131 /* find the parent that can help provide the fastest rate <= rate */
132 num_parents = __clk_get_num_parents(clk);
133 for (i = 0; i < num_parents; i++) {
134 parent = clk_get_parent_by_index(clk, i);
135 if (!parent)
136 continue;
137 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
138 parent_rate = __clk_round_rate(parent, rate);
139 else
140 parent_rate = __clk_get_rate(parent);
141
142 child_rate = sun6i_ahb1_clk_round(rate, NULL, NULL, i,
143 parent_rate);
144
145 if (child_rate <= rate && child_rate > best_child_rate) {
146 best_parent = parent;
147 best = parent_rate;
148 best_child_rate = child_rate;
149 }
150 }
151
152 if (best_parent)
153 *best_parent_clk = __clk_get_hw(best_parent);
154 *best_parent_rate = best;
155
156 return best_child_rate;
157}
158
159static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
160 unsigned long parent_rate)
161{
162 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
163 unsigned long flags;
164 u8 div, pre_div, parent;
165 u32 reg;
166
167 spin_lock_irqsave(&clk_lock, flags);
168
169 reg = readl(ahb1->reg);
170
171 /* need to know which parent is used to apply pre-divider */
172 parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
173 sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
174
175 reg = SUN6I_AHB1_DIV_SET(reg, div);
176 reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
177 writel(reg, ahb1->reg);
178
179 spin_unlock_irqrestore(&clk_lock, flags);
180
181 return 0;
182}
183
184static const struct clk_ops sun6i_ahb1_clk_ops = {
185 .determine_rate = sun6i_ahb1_clk_determine_rate,
186 .recalc_rate = sun6i_ahb1_clk_recalc_rate,
187 .set_rate = sun6i_ahb1_clk_set_rate,
188};
189
190static void __init sun6i_ahb1_clk_setup(struct device_node *node)
191{
192 struct clk *clk;
193 struct sun6i_ahb1_clk *ahb1;
194 struct clk_mux *mux;
195 const char *clk_name = node->name;
196 const char *parents[SUN6I_AHB1_MAX_PARENTS];
197 void __iomem *reg;
198 int i = 0;
199
200 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
201
202 /* we have a mux, we will have >1 parents */
203 while (i < SUN6I_AHB1_MAX_PARENTS &&
204 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
205 i++;
206
207 of_property_read_string(node, "clock-output-names", &clk_name);
208
209 ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
210 if (!ahb1)
211 return;
212
213 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
214 if (!mux) {
215 kfree(ahb1);
216 return;
217 }
218
219 /* set up clock properties */
220 mux->reg = reg;
221 mux->shift = SUN6I_AHB1_MUX_SHIFT;
222 mux->mask = SUN6I_AHB1_MUX_MASK;
223 mux->lock = &clk_lock;
224 ahb1->reg = reg;
225
226 clk = clk_register_composite(NULL, clk_name, parents, i,
227 &mux->hw, &clk_mux_ops,
228 &ahb1->hw, &sun6i_ahb1_clk_ops,
229 NULL, NULL, 0);
230
231 if (!IS_ERR(clk)) {
232 of_clk_add_provider(node, of_clk_src_simple_get, clk);
233 clk_register_clkdev(clk, clk_name, NULL);
234 }
235}
236CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
237
28/* Maximum number of parents our clocks have */ 238/* Maximum number of parents our clocks have */
29#define SUNXI_MAX_PARENTS 5 239#define SUNXI_MAX_PARENTS 5
30 240
@@ -355,43 +565,6 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
355} 565}
356 566
357/** 567/**
358 * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
359 */
360
361void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output)
362{
363 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
364 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
365
366 struct clk_hw *hw = __clk_get_hw(clk);
367 struct clk_composite *composite = to_clk_composite(hw);
368 struct clk_hw *rate_hw = composite->rate_hw;
369 struct clk_factors *factors = to_clk_factors(rate_hw);
370 unsigned long flags = 0;
371 u32 reg;
372
373 if (factors->lock)
374 spin_lock_irqsave(factors->lock, flags);
375
376 reg = readl(factors->reg);
377
378 /* set sample clock phase control */
379 reg &= ~(0x7 << 20);
380 reg |= ((sample & 0x7) << 20);
381
382 /* set output clock phase control */
383 reg &= ~(0x7 << 8);
384 reg |= ((output & 0x7) << 8);
385
386 writel(reg, factors->reg);
387
388 if (factors->lock)
389 spin_unlock_irqrestore(factors->lock, flags);
390}
391EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
392
393
394/**
395 * sunxi_factors_clk_setup() - Setup function for factor clocks 568 * sunxi_factors_clk_setup() - Setup function for factor clocks
396 */ 569 */
397 570
@@ -413,6 +586,7 @@ static struct clk_factors_config sun6i_a31_pll1_config = {
413 .kwidth = 2, 586 .kwidth = 2,
414 .mshift = 0, 587 .mshift = 0,
415 .mwidth = 2, 588 .mwidth = 2,
589 .n_start = 1,
416}; 590};
417 591
418static struct clk_factors_config sun8i_a23_pll1_config = { 592static struct clk_factors_config sun8i_a23_pll1_config = {
@@ -520,7 +694,16 @@ static const struct factors_data sun7i_a20_out_data __initconst = {
520static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, 694static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
521 const struct factors_data *data) 695 const struct factors_data *data)
522{ 696{
523 return sunxi_factors_register(node, data, &clk_lock); 697 void __iomem *reg;
698
699 reg = of_iomap(node, 0);
700 if (!reg) {
701 pr_err("Could not get registers for factors-clk: %s\n",
702 node->name);
703 return NULL;
704 }
705
706 return sunxi_factors_register(node, data, &clk_lock, reg);
524} 707}
525 708
526 709
@@ -561,7 +744,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
561 of_property_read_string(node, "clock-output-names", &clk_name); 744 of_property_read_string(node, "clock-output-names", &clk_name);
562 745
563 clk = clk_register_mux(NULL, clk_name, parents, i, 746 clk = clk_register_mux(NULL, clk_name, parents, i,
564 CLK_SET_RATE_NO_REPARENT, reg, 747 CLK_SET_RATE_PARENT, reg,
565 data->shift, SUNXI_MUX_GATE_WIDTH, 748 data->shift, SUNXI_MUX_GATE_WIDTH,
566 0, &clk_lock); 749 0, &clk_lock);
567 750
@@ -1217,7 +1400,6 @@ CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1217 1400
1218static const char *sun6i_critical_clocks[] __initdata = { 1401static const char *sun6i_critical_clocks[] __initdata = {
1219 "cpu", 1402 "cpu",
1220 "ahb1_sdram",
1221}; 1403};
1222 1404
1223static void __init sun6i_init_clocks(struct device_node *node) 1405static void __init sun6i_init_clocks(struct device_node *node)
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f7dfb72884a4..edb8358fa6ce 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
16obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o 16obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
17obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o 17obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
18obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 0011d547a9f7..60738cc954cb 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -64,10 +64,8 @@ enum clk_id {
64 tegra_clk_disp2, 64 tegra_clk_disp2,
65 tegra_clk_dp2, 65 tegra_clk_dp2,
66 tegra_clk_dpaux, 66 tegra_clk_dpaux,
67 tegra_clk_dsia,
68 tegra_clk_dsialp, 67 tegra_clk_dsialp,
69 tegra_clk_dsia_mux, 68 tegra_clk_dsia_mux,
70 tegra_clk_dsib,
71 tegra_clk_dsiblp, 69 tegra_clk_dsiblp,
72 tegra_clk_dsib_mux, 70 tegra_clk_dsib_mux,
73 tegra_clk_dtv, 71 tegra_clk_dtv,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 9e899c18af86..d84ae49d0e05 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -28,7 +28,7 @@ static u8 clk_periph_get_parent(struct clk_hw *hw)
28 const struct clk_ops *mux_ops = periph->mux_ops; 28 const struct clk_ops *mux_ops = periph->mux_ops;
29 struct clk_hw *mux_hw = &periph->mux.hw; 29 struct clk_hw *mux_hw = &periph->mux.hw;
30 30
31 mux_hw->clk = hw->clk; 31 __clk_hw_set_clk(mux_hw, hw);
32 32
33 return mux_ops->get_parent(mux_hw); 33 return mux_ops->get_parent(mux_hw);
34} 34}
@@ -39,7 +39,7 @@ static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
39 const struct clk_ops *mux_ops = periph->mux_ops; 39 const struct clk_ops *mux_ops = periph->mux_ops;
40 struct clk_hw *mux_hw = &periph->mux.hw; 40 struct clk_hw *mux_hw = &periph->mux.hw;
41 41
42 mux_hw->clk = hw->clk; 42 __clk_hw_set_clk(mux_hw, hw);
43 43
44 return mux_ops->set_parent(mux_hw, index); 44 return mux_ops->set_parent(mux_hw, index);
45} 45}
@@ -51,7 +51,7 @@ static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
51 const struct clk_ops *div_ops = periph->div_ops; 51 const struct clk_ops *div_ops = periph->div_ops;
52 struct clk_hw *div_hw = &periph->divider.hw; 52 struct clk_hw *div_hw = &periph->divider.hw;
53 53
54 div_hw->clk = hw->clk; 54 __clk_hw_set_clk(div_hw, hw);
55 55
56 return div_ops->recalc_rate(div_hw, parent_rate); 56 return div_ops->recalc_rate(div_hw, parent_rate);
57} 57}
@@ -63,7 +63,7 @@ static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
63 const struct clk_ops *div_ops = periph->div_ops; 63 const struct clk_ops *div_ops = periph->div_ops;
64 struct clk_hw *div_hw = &periph->divider.hw; 64 struct clk_hw *div_hw = &periph->divider.hw;
65 65
66 div_hw->clk = hw->clk; 66 __clk_hw_set_clk(div_hw, hw);
67 67
68 return div_ops->round_rate(div_hw, rate, prate); 68 return div_ops->round_rate(div_hw, rate, prate);
69} 69}
@@ -75,7 +75,7 @@ static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate,
75 const struct clk_ops *div_ops = periph->div_ops; 75 const struct clk_ops *div_ops = periph->div_ops;
76 struct clk_hw *div_hw = &periph->divider.hw; 76 struct clk_hw *div_hw = &periph->divider.hw;
77 77
78 div_hw->clk = hw->clk; 78 __clk_hw_set_clk(div_hw, hw);
79 79
80 return div_ops->set_rate(div_hw, rate, parent_rate); 80 return div_ops->set_rate(div_hw, rate, parent_rate);
81} 81}
@@ -86,7 +86,7 @@ static int clk_periph_is_enabled(struct clk_hw *hw)
86 const struct clk_ops *gate_ops = periph->gate_ops; 86 const struct clk_ops *gate_ops = periph->gate_ops;
87 struct clk_hw *gate_hw = &periph->gate.hw; 87 struct clk_hw *gate_hw = &periph->gate.hw;
88 88
89 gate_hw->clk = hw->clk; 89 __clk_hw_set_clk(gate_hw, hw);
90 90
91 return gate_ops->is_enabled(gate_hw); 91 return gate_ops->is_enabled(gate_hw);
92} 92}
@@ -97,7 +97,7 @@ static int clk_periph_enable(struct clk_hw *hw)
97 const struct clk_ops *gate_ops = periph->gate_ops; 97 const struct clk_ops *gate_ops = periph->gate_ops;
98 struct clk_hw *gate_hw = &periph->gate.hw; 98 struct clk_hw *gate_hw = &periph->gate.hw;
99 99
100 gate_hw->clk = hw->clk; 100 __clk_hw_set_clk(gate_hw, hw);
101 101
102 return gate_ops->enable(gate_hw); 102 return gate_ops->enable(gate_hw);
103} 103}
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index c7c6d8fb32fb..bfef9abdf232 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -816,7 +816,9 @@ const struct clk_ops tegra_clk_plle_ops = {
816 .enable = clk_plle_enable, 816 .enable = clk_plle_enable,
817}; 817};
818 818
819#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) 819#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
820 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
821 defined(CONFIG_ARCH_TEGRA_132_SOC)
820 822
821static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 823static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
822 unsigned long parent_rate) 824 unsigned long parent_rate)
@@ -1505,7 +1507,9 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1505 return clk; 1507 return clk;
1506} 1508}
1507 1509
1508#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) 1510#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1511 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1512 defined(CONFIG_ARCH_TEGRA_132_SOC)
1509static const struct clk_ops tegra_clk_pllxc_ops = { 1513static const struct clk_ops tegra_clk_pllxc_ops = {
1510 .is_enabled = clk_pll_is_enabled, 1514 .is_enabled = clk_pll_is_enabled,
1511 .enable = clk_pll_iddq_enable, 1515 .enable = clk_pll_iddq_enable,
@@ -1565,7 +1569,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1565 parent = __clk_lookup(parent_name); 1569 parent = __clk_lookup(parent_name);
1566 if (!parent) { 1570 if (!parent) {
1567 WARN(1, "parent clk %s of %s must be registered first\n", 1571 WARN(1, "parent clk %s of %s must be registered first\n",
1568 name, parent_name); 1572 parent_name, name);
1569 return ERR_PTR(-EINVAL); 1573 return ERR_PTR(-EINVAL);
1570 } 1574 }
1571 1575
@@ -1665,7 +1669,7 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1665 parent = __clk_lookup(parent_name); 1669 parent = __clk_lookup(parent_name);
1666 if (!parent) { 1670 if (!parent) {
1667 WARN(1, "parent clk %s of %s must be registered first\n", 1671 WARN(1, "parent clk %s of %s must be registered first\n",
1668 name, parent_name); 1672 parent_name, name);
1669 return ERR_PTR(-EINVAL); 1673 return ERR_PTR(-EINVAL);
1670 } 1674 }
1671 1675
@@ -1706,7 +1710,7 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1706 parent = __clk_lookup(parent_name); 1710 parent = __clk_lookup(parent_name);
1707 if (!parent) { 1711 if (!parent) {
1708 WARN(1, "parent clk %s of %s must be registered first\n", 1712 WARN(1, "parent clk %s of %s must be registered first\n",
1709 name, parent_name); 1713 parent_name, name);
1710 return ERR_PTR(-EINVAL); 1714 return ERR_PTR(-EINVAL);
1711 } 1715 }
1712 1716
@@ -1802,7 +1806,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1802} 1806}
1803#endif 1807#endif
1804 1808
1805#ifdef CONFIG_ARCH_TEGRA_124_SOC 1809#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1806static const struct clk_ops tegra_clk_pllss_ops = { 1810static const struct clk_ops tegra_clk_pllss_ops = {
1807 .is_enabled = clk_pll_is_enabled, 1811 .is_enabled = clk_pll_is_enabled,
1808 .enable = clk_pll_iddq_enable, 1812 .enable = clk_pll_iddq_enable,
@@ -1830,7 +1834,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1830 parent = __clk_lookup(parent_name); 1834 parent = __clk_lookup(parent_name);
1831 if (!parent) { 1835 if (!parent) {
1832 WARN(1, "parent clk %s of %s must be registered first\n", 1836 WARN(1, "parent clk %s of %s must be registered first\n",
1833 name, parent_name); 1837 parent_name, name);
1834 return ERR_PTR(-EINVAL); 1838 return ERR_PTR(-EINVAL);
1835 } 1839 }
1836 1840
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 37f32c49674e..cef0727b9eec 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -434,10 +434,10 @@ static struct tegra_periph_init_data periph_clks[] = {
434 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), 434 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
435 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), 435 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
436 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), 436 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
437 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1), 437 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
438 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2), 438 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
439 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3), 439 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
440 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4), 440 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
441 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), 441 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
442 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), 442 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
443 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), 443 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
@@ -470,10 +470,10 @@ static struct tegra_periph_init_data periph_clks[] = {
470 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), 470 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
471 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), 471 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
472 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2), 472 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
473 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8), 473 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
474 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8), 474 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
475 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8), 475 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
476 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4_8), 476 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
477 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8), 477 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
478 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8), 478 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
479 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8), 479 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
@@ -537,8 +537,6 @@ static struct tegra_periph_init_data gate_clks[] = {
537 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0), 537 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
538 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0), 538 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
539 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0), 539 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
540 GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
541 GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
542 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED), 540 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
543 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), 541 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
544 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0), 542 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 0b03d2cf7264..d0766423a5d6 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -715,7 +715,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
715 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true }, 715 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
716 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true }, 716 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
717 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true }, 717 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
718 [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
719 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true }, 718 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
720 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true }, 719 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
721 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true }, 720 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
@@ -739,7 +738,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
739 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true }, 738 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
740 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true }, 739 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
741 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true }, 740 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
742 [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
743 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true }, 741 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
744 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true }, 742 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
745 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true }, 743 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
@@ -1224,6 +1222,14 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1224 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1222 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1225 clks[TEGRA114_CLK_DSIB_MUX] = clk; 1223 clks[TEGRA114_CLK_DSIB_MUX] = clk;
1226 1224
1225 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1226 0, 48, periph_clk_enb_refcnt);
1227 clks[TEGRA114_CLK_DSIA] = clk;
1228
1229 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1230 0, 82, periph_clk_enb_refcnt);
1231 clks[TEGRA114_CLK_DSIB] = clk;
1232
1227 /* emc mux */ 1233 /* emc mux */
1228 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1234 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1229 ARRAY_SIZE(mux_pllmcp_clkm), 1235 ARRAY_SIZE(mux_pllmcp_clkm),
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index f5f9baca7bb6..9a893f2fe8e9 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -28,6 +28,14 @@
28#include "clk.h" 28#include "clk.h"
29#include "clk-id.h" 29#include "clk-id.h"
30 30
31/*
32 * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
33 * banks present in the Tegra124/132 CAR IP block. The banks are
34 * identified by single letters, e.g.: L, H, U, V, W, X. See
35 * periph_regs[] in drivers/clk/tegra/clk.c
36 */
37#define TEGRA124_CAR_BANK_COUNT 6
38
31#define CLK_SOURCE_CSITE 0x1d4 39#define CLK_SOURCE_CSITE 0x1d4
32#define CLK_SOURCE_EMC 0x19c 40#define CLK_SOURCE_EMC 0x19c
33 41
@@ -128,7 +136,6 @@ static unsigned long osc_freq;
128static unsigned long pll_ref_freq; 136static unsigned long pll_ref_freq;
129 137
130static DEFINE_SPINLOCK(pll_d_lock); 138static DEFINE_SPINLOCK(pll_d_lock);
131static DEFINE_SPINLOCK(pll_d2_lock);
132static DEFINE_SPINLOCK(pll_e_lock); 139static DEFINE_SPINLOCK(pll_e_lock);
133static DEFINE_SPINLOCK(pll_re_lock); 140static DEFINE_SPINLOCK(pll_re_lock);
134static DEFINE_SPINLOCK(pll_u_lock); 141static DEFINE_SPINLOCK(pll_u_lock);
@@ -145,11 +152,6 @@ static unsigned long tegra124_input_freq[] = {
145 [12] = 260000000, 152 [12] = 260000000,
146}; 153};
147 154
148static const char *mux_plld_out0_plld2_out0[] = {
149 "pll_d_out0", "pll_d2_out0",
150};
151#define mux_plld_out0_plld2_out0_idx NULL
152
153static const char *mux_pllmcp_clkm[] = { 155static const char *mux_pllmcp_clkm[] = {
154 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", 156 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
155}; 157};
@@ -783,7 +785,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
783 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true }, 785 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
784 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true }, 786 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
785 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true }, 787 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
786 [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true },
787 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true }, 788 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
788 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true }, 789 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
789 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true }, 790 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
@@ -809,7 +810,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
809 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, 810 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
810 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, 811 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
811 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true }, 812 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
812 [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
813 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true }, 813 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
814 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true }, 814 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
815 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true }, 815 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
@@ -949,8 +949,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
949 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, 949 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
950 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, 950 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
951 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, 951 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
952 [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
953 [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
954}; 952};
955 953
956static struct tegra_devclk devclks[] __initdata = { 954static struct tegra_devclk devclks[] __initdata = {
@@ -1112,17 +1110,17 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1112 1, 2); 1110 1, 2);
1113 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; 1111 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1114 1112
1115 /* dsia mux */ 1113 clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,
1116 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1114 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1117 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1115 clks[TEGRA124_CLK_PLLD_DSI] = clk;
1118 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1116
1119 clks[TEGRA124_CLK_DSIA_MUX] = clk; 1117 clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,
1118 0, 48, periph_clk_enb_refcnt);
1119 clks[TEGRA124_CLK_DSIA] = clk;
1120 1120
1121 /* dsib mux */ 1121 clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,
1122 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1122 0, 82, periph_clk_enb_refcnt);
1123 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1123 clks[TEGRA124_CLK_DSIB] = clk;
1124 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1125 clks[TEGRA124_CLK_DSIB_MUX] = clk;
1126 1124
1127 /* emc mux */ 1125 /* emc mux */
1128 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1126 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -1351,7 +1349,7 @@ static const struct of_device_id pmc_match[] __initconst = {
1351 {}, 1349 {},
1352}; 1350};
1353 1351
1354static struct tegra_clk_init_table init_table[] __initdata = { 1352static struct tegra_clk_init_table common_init_table[] __initdata = {
1355 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0}, 1353 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1356 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0}, 1354 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1357 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0}, 1355 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
@@ -1368,6 +1366,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1368 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1366 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1369 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0}, 1367 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1370 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1}, 1368 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1369 {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
1370 {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
1371 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1}, 1371 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1372 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1}, 1372 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1373 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1}, 1373 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
@@ -1385,27 +1385,73 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1385 {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0}, 1385 {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
1386 {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0}, 1386 {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
1387 {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1}, 1387 {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},
1388 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1389 {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1}, 1388 {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
1390 {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1}, 1389 {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
1391 {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0}, 1390 {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
1391 /* This MUST be the last entry. */
1392 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1393};
1394
1395static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1392 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0}, 1396 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1397 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1398 /* This MUST be the last entry. */
1399 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1400};
1401
1402/* Tegra132 requires the SOC_THERM clock to remain active */
1403static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1404 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
1393 /* This MUST be the last entry. */ 1405 /* This MUST be the last entry. */
1394 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1406 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1395}; 1407};
1396 1408
1409/**
1410 * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1411 *
1412 * Program an initial clock rate and enable or disable clocks needed
1413 * by the rest of the kernel, for Tegra124 SoCs. It is intended to be
1414 * called by assigning a pointer to it to tegra_clk_apply_init_table -
1415 * this will be called as an arch_initcall. No return value.
1416 */
1397static void __init tegra124_clock_apply_init_table(void) 1417static void __init tegra124_clock_apply_init_table(void)
1398{ 1418{
1399 tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX); 1419 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1420 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1400} 1421}
1401 1422
1402static void __init tegra124_clock_init(struct device_node *np) 1423/**
1424 * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1425 *
1426 * Program an initial clock rate and enable or disable clocks needed
1427 * by the rest of the kernel, for Tegra132 SoCs. It is intended to be
1428 * called by assigning a pointer to it to tegra_clk_apply_init_table -
1429 * this will be called as an arch_initcall. No return value.
1430 */
1431static void __init tegra132_clock_apply_init_table(void)
1432{
1433 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1434 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1435}
1436
1437/**
1438 * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1439 * @np: struct device_node * of the DT node for the SoC CAR IP block
1440 *
1441 * Register most of the clocks controlled by the CAR IP block, along
1442 * with a few clocks controlled by the PMC IP block. Everything in
1443 * this function should be common to Tegra124 and Tegra132. XXX The
1444 * PMC clock initialization should probably be moved to PMC-specific
1445 * driver code. No return value.
1446 */
1447static void __init tegra124_132_clock_init_pre(struct device_node *np)
1403{ 1448{
1404 struct device_node *node; 1449 struct device_node *node;
1450 u32 plld_base;
1405 1451
1406 clk_base = of_iomap(np, 0); 1452 clk_base = of_iomap(np, 0);
1407 if (!clk_base) { 1453 if (!clk_base) {
1408 pr_err("ioremap tegra124 CAR failed\n"); 1454 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1409 return; 1455 return;
1410 } 1456 }
1411 1457
@@ -1423,7 +1469,8 @@ static void __init tegra124_clock_init(struct device_node *np)
1423 return; 1469 return;
1424 } 1470 }
1425 1471
1426 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6); 1472 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1473 TEGRA124_CAR_BANK_COUNT);
1427 if (!clks) 1474 if (!clks)
1428 return; 1475 return;
1429 1476
@@ -1437,13 +1484,76 @@ static void __init tegra124_clock_init(struct device_node *np)
1437 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params); 1484 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1438 tegra_pmc_clk_init(pmc_base, tegra124_clks); 1485 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1439 1486
1487 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1488 plld_base = clk_readl(clk_base + PLLD_BASE);
1489 plld_base &= ~BIT(25);
1490 clk_writel(plld_base, clk_base + PLLD_BASE);
1491}
1492
1493/**
1494 * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1495 * @np: struct device_node * of the DT node for the SoC CAR IP block
1496 *
1497 * Register most of the along with a few clocks controlled by the PMC
1498 * IP block. Everything in this function should be common to Tegra124
1499 * and Tegra132. This function must be called after
1500 * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1501 * not be set. No return value.
1502 */
1503static void __init tegra124_132_clock_init_post(struct device_node *np)
1504{
1440 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, 1505 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1441 &pll_x_params); 1506 &pll_x_params);
1442 tegra_add_of_provider(np); 1507 tegra_add_of_provider(np);
1443 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1508 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1444 1509
1510 tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1511}
1512
1513/**
1514 * tegra124_clock_init - Tegra124-specific clock initialization
1515 * @np: struct device_node * of the DT node for the SoC CAR IP block
1516 *
1517 * Register most SoC clocks for the Tegra124 system-on-chip. Most of
1518 * this code is shared between the Tegra124 and Tegra132 SoCs,
1519 * although some of the initial clock settings and CPU clocks differ.
1520 * Intended to be called by the OF init code when a DT node with the
1521 * "nvidia,tegra124-car" string is encountered, and declared with
1522 * CLK_OF_DECLARE. No return value.
1523 */
1524static void __init tegra124_clock_init(struct device_node *np)
1525{
1526 tegra124_132_clock_init_pre(np);
1445 tegra_clk_apply_init_table = tegra124_clock_apply_init_table; 1527 tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1528 tegra124_132_clock_init_post(np);
1529}
1446 1530
1447 tegra_cpu_car_ops = &tegra124_cpu_car_ops; 1531/**
1532 * tegra132_clock_init - Tegra132-specific clock initialization
1533 * @np: struct device_node * of the DT node for the SoC CAR IP block
1534 *
1535 * Register most SoC clocks for the Tegra132 system-on-chip. Most of
1536 * this code is shared between the Tegra124 and Tegra132 SoCs,
1537 * although some of the initial clock settings and CPU clocks differ.
1538 * Intended to be called by the OF init code when a DT node with the
1539 * "nvidia,tegra132-car" string is encountered, and declared with
1540 * CLK_OF_DECLARE. No return value.
1541 */
1542static void __init tegra132_clock_init(struct device_node *np)
1543{
1544 tegra124_132_clock_init_pre(np);
1545
1546 /*
1547 * On Tegra132, these clocks are controlled by the
1548 * CLUSTER_clocks IP block, located in the CPU complex
1549 */
1550 tegra124_clks[tegra_clk_cclk_g].present = false;
1551 tegra124_clks[tegra_clk_cclk_lp].present = false;
1552 tegra124_clks[tegra_clk_pll_x].present = false;
1553 tegra124_clks[tegra_clk_pll_x_out0].present = false;
1554
1555 tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1556 tegra124_132_clock_init_post(np);
1448} 1557}
1449CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init); 1558CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1559CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 97dc8595c3cd..9ddb7547cb43 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -302,10 +302,13 @@ struct clk ** __init tegra_lookup_dt_id(int clk_id,
302 302
303tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 303tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
304 304
305void __init tegra_clocks_apply_init_table(void) 305static int __init tegra_clocks_apply_init_table(void)
306{ 306{
307 if (!tegra_clk_apply_init_table) 307 if (!tegra_clk_apply_init_table)
308 return; 308 return 0;
309 309
310 tegra_clk_apply_init_table(); 310 tegra_clk_apply_init_table();
311
312 return 0;
311} 313}
314arch_initcall(tegra_clocks_apply_init_table);
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index ed4d0aaf8916..105ffd0f5e79 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,13 +1,17 @@
1ifneq ($(CONFIG_OF),)
2obj-y += clk.o autoidle.o clockdomain.o 1obj-y += clk.o autoidle.o clockdomain.o
3clk-common = dpll.o composite.o divider.o gate.o \ 2clk-common = dpll.o composite.o divider.o gate.o \
4 fixed-factor.o mux.o apll.o 3 fixed-factor.o mux.o apll.o
5obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o 4obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
5obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
6obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o 6obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
7obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o 7obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
8 clk-3xxx.o
8obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o 9obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
9obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o 10obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
10obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ 11obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
11 clk-dra7-atl.o 12 clk-dra7-atl.o
12obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o 13obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o
14
15ifdef CONFIG_ATAGS
16obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
13endif 17endif
diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c
new file mode 100644
index 000000000000..e0732a4c8f26
--- /dev/null
+++ b/drivers/clk/ti/clk-3xxx-legacy.c
@@ -0,0 +1,4653 @@
1/*
2 * OMAP3 Legacy clock data
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/clk-provider.h>
19#include <linux/clk/ti.h>
20
21#include "clock.h"
22
23static struct ti_clk_fixed virt_12m_ck_data = {
24 .frequency = 12000000,
25};
26
27static struct ti_clk virt_12m_ck = {
28 .name = "virt_12m_ck",
29 .type = TI_CLK_FIXED,
30 .data = &virt_12m_ck_data,
31};
32
33static struct ti_clk_fixed virt_13m_ck_data = {
34 .frequency = 13000000,
35};
36
37static struct ti_clk virt_13m_ck = {
38 .name = "virt_13m_ck",
39 .type = TI_CLK_FIXED,
40 .data = &virt_13m_ck_data,
41};
42
43static struct ti_clk_fixed virt_19200000_ck_data = {
44 .frequency = 19200000,
45};
46
47static struct ti_clk virt_19200000_ck = {
48 .name = "virt_19200000_ck",
49 .type = TI_CLK_FIXED,
50 .data = &virt_19200000_ck_data,
51};
52
53static struct ti_clk_fixed virt_26000000_ck_data = {
54 .frequency = 26000000,
55};
56
57static struct ti_clk virt_26000000_ck = {
58 .name = "virt_26000000_ck",
59 .type = TI_CLK_FIXED,
60 .data = &virt_26000000_ck_data,
61};
62
63static struct ti_clk_fixed virt_38_4m_ck_data = {
64 .frequency = 38400000,
65};
66
67static struct ti_clk virt_38_4m_ck = {
68 .name = "virt_38_4m_ck",
69 .type = TI_CLK_FIXED,
70 .data = &virt_38_4m_ck_data,
71};
72
73static struct ti_clk_fixed virt_16_8m_ck_data = {
74 .frequency = 16800000,
75};
76
77static struct ti_clk virt_16_8m_ck = {
78 .name = "virt_16_8m_ck",
79 .type = TI_CLK_FIXED,
80 .data = &virt_16_8m_ck_data,
81};
82
83static const char *osc_sys_ck_parents[] = {
84 "virt_12m_ck",
85 "virt_13m_ck",
86 "virt_19200000_ck",
87 "virt_26000000_ck",
88 "virt_38_4m_ck",
89 "virt_16_8m_ck",
90};
91
92static struct ti_clk_mux osc_sys_ck_data = {
93 .num_parents = ARRAY_SIZE(osc_sys_ck_parents),
94 .reg = 0xd40,
95 .module = TI_CLKM_PRM,
96 .parents = osc_sys_ck_parents,
97};
98
99static struct ti_clk osc_sys_ck = {
100 .name = "osc_sys_ck",
101 .type = TI_CLK_MUX,
102 .data = &osc_sys_ck_data,
103};
104
105static struct ti_clk_divider sys_ck_data = {
106 .parent = "osc_sys_ck",
107 .bit_shift = 6,
108 .max_div = 3,
109 .reg = 0x1270,
110 .module = TI_CLKM_PRM,
111 .flags = CLKF_INDEX_STARTS_AT_ONE,
112};
113
114static struct ti_clk sys_ck = {
115 .name = "sys_ck",
116 .type = TI_CLK_DIVIDER,
117 .data = &sys_ck_data,
118};
119
120static const char *dpll3_ck_parents[] = {
121 "sys_ck",
122 "sys_ck",
123};
124
125static struct ti_clk_dpll dpll3_ck_data = {
126 .num_parents = ARRAY_SIZE(dpll3_ck_parents),
127 .control_reg = 0xd00,
128 .idlest_reg = 0xd20,
129 .mult_div1_reg = 0xd40,
130 .autoidle_reg = 0xd30,
131 .module = TI_CLKM_CM,
132 .parents = dpll3_ck_parents,
133 .flags = CLKF_CORE,
134 .freqsel_mask = 0xf0,
135 .div1_mask = 0x7f00,
136 .idlest_mask = 0x1,
137 .auto_recal_bit = 0x3,
138 .max_divider = 0x80,
139 .min_divider = 0x1,
140 .recal_en_bit = 0x5,
141 .max_multiplier = 0x7ff,
142 .enable_mask = 0x7,
143 .mult_mask = 0x7ff0000,
144 .recal_st_bit = 0x5,
145 .autoidle_mask = 0x7,
146};
147
148static struct ti_clk dpll3_ck = {
149 .name = "dpll3_ck",
150 .clkdm_name = "dpll3_clkdm",
151 .type = TI_CLK_DPLL,
152 .data = &dpll3_ck_data,
153};
154
155static struct ti_clk_divider dpll3_m2_ck_data = {
156 .parent = "dpll3_ck",
157 .bit_shift = 27,
158 .max_div = 31,
159 .reg = 0xd40,
160 .module = TI_CLKM_CM,
161 .flags = CLKF_INDEX_STARTS_AT_ONE,
162};
163
164static struct ti_clk dpll3_m2_ck = {
165 .name = "dpll3_m2_ck",
166 .type = TI_CLK_DIVIDER,
167 .data = &dpll3_m2_ck_data,
168};
169
170static struct ti_clk_fixed_factor core_ck_data = {
171 .parent = "dpll3_m2_ck",
172 .div = 1,
173 .mult = 1,
174};
175
176static struct ti_clk core_ck = {
177 .name = "core_ck",
178 .type = TI_CLK_FIXED_FACTOR,
179 .data = &core_ck_data,
180};
181
182static struct ti_clk_divider l3_ick_data = {
183 .parent = "core_ck",
184 .max_div = 3,
185 .reg = 0xa40,
186 .module = TI_CLKM_CM,
187 .flags = CLKF_INDEX_STARTS_AT_ONE,
188};
189
190static struct ti_clk l3_ick = {
191 .name = "l3_ick",
192 .type = TI_CLK_DIVIDER,
193 .data = &l3_ick_data,
194};
195
196static struct ti_clk_fixed_factor security_l3_ick_data = {
197 .parent = "l3_ick",
198 .div = 1,
199 .mult = 1,
200};
201
202static struct ti_clk security_l3_ick = {
203 .name = "security_l3_ick",
204 .type = TI_CLK_FIXED_FACTOR,
205 .data = &security_l3_ick_data,
206};
207
208static struct ti_clk_fixed_factor wkup_l4_ick_data = {
209 .parent = "sys_ck",
210 .div = 1,
211 .mult = 1,
212};
213
214static struct ti_clk wkup_l4_ick = {
215 .name = "wkup_l4_ick",
216 .type = TI_CLK_FIXED_FACTOR,
217 .data = &wkup_l4_ick_data,
218};
219
220static struct ti_clk_gate usim_ick_data = {
221 .parent = "wkup_l4_ick",
222 .bit_shift = 9,
223 .reg = 0xc10,
224 .module = TI_CLKM_CM,
225 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
226};
227
228static struct ti_clk usim_ick = {
229 .name = "usim_ick",
230 .clkdm_name = "wkup_clkdm",
231 .type = TI_CLK_GATE,
232 .data = &usim_ick_data,
233};
234
235static struct ti_clk_gate dss2_alwon_fck_data = {
236 .parent = "sys_ck",
237 .bit_shift = 1,
238 .reg = 0xe00,
239 .module = TI_CLKM_CM,
240};
241
242static struct ti_clk dss2_alwon_fck = {
243 .name = "dss2_alwon_fck",
244 .clkdm_name = "dss_clkdm",
245 .type = TI_CLK_GATE,
246 .data = &dss2_alwon_fck_data,
247};
248
249static struct ti_clk_divider l4_ick_data = {
250 .parent = "l3_ick",
251 .bit_shift = 2,
252 .max_div = 3,
253 .reg = 0xa40,
254 .module = TI_CLKM_CM,
255 .flags = CLKF_INDEX_STARTS_AT_ONE,
256};
257
258static struct ti_clk l4_ick = {
259 .name = "l4_ick",
260 .type = TI_CLK_DIVIDER,
261 .data = &l4_ick_data,
262};
263
264static struct ti_clk_fixed_factor core_l4_ick_data = {
265 .parent = "l4_ick",
266 .div = 1,
267 .mult = 1,
268};
269
270static struct ti_clk core_l4_ick = {
271 .name = "core_l4_ick",
272 .type = TI_CLK_FIXED_FACTOR,
273 .data = &core_l4_ick_data,
274};
275
276static struct ti_clk_gate mmchs2_ick_data = {
277 .parent = "core_l4_ick",
278 .bit_shift = 25,
279 .reg = 0xa10,
280 .module = TI_CLKM_CM,
281 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
282};
283
284static struct ti_clk mmchs2_ick = {
285 .name = "mmchs2_ick",
286 .clkdm_name = "core_l4_clkdm",
287 .type = TI_CLK_GATE,
288 .data = &mmchs2_ick_data,
289};
290
291static const char *dpll4_ck_parents[] = {
292 "sys_ck",
293 "sys_ck",
294};
295
296static struct ti_clk_dpll dpll4_ck_data = {
297 .num_parents = ARRAY_SIZE(dpll4_ck_parents),
298 .control_reg = 0xd00,
299 .idlest_reg = 0xd20,
300 .mult_div1_reg = 0xd44,
301 .autoidle_reg = 0xd30,
302 .module = TI_CLKM_CM,
303 .parents = dpll4_ck_parents,
304 .flags = CLKF_PER,
305 .freqsel_mask = 0xf00000,
306 .modes = 0x82,
307 .div1_mask = 0x7f,
308 .idlest_mask = 0x2,
309 .auto_recal_bit = 0x13,
310 .max_divider = 0x80,
311 .min_divider = 0x1,
312 .recal_en_bit = 0x6,
313 .max_multiplier = 0x7ff,
314 .enable_mask = 0x70000,
315 .mult_mask = 0x7ff00,
316 .recal_st_bit = 0x6,
317 .autoidle_mask = 0x38,
318};
319
320static struct ti_clk dpll4_ck = {
321 .name = "dpll4_ck",
322 .clkdm_name = "dpll4_clkdm",
323 .type = TI_CLK_DPLL,
324 .data = &dpll4_ck_data,
325};
326
327static struct ti_clk_divider dpll4_m2_ck_data = {
328 .parent = "dpll4_ck",
329 .max_div = 63,
330 .reg = 0xd48,
331 .module = TI_CLKM_CM,
332 .flags = CLKF_INDEX_STARTS_AT_ONE,
333};
334
335static struct ti_clk dpll4_m2_ck = {
336 .name = "dpll4_m2_ck",
337 .type = TI_CLK_DIVIDER,
338 .data = &dpll4_m2_ck_data,
339};
340
341static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
342 .parent = "dpll4_m2_ck",
343 .div = 1,
344 .mult = 2,
345};
346
347static struct ti_clk dpll4_m2x2_mul_ck = {
348 .name = "dpll4_m2x2_mul_ck",
349 .type = TI_CLK_FIXED_FACTOR,
350 .data = &dpll4_m2x2_mul_ck_data,
351};
352
353static struct ti_clk_gate dpll4_m2x2_ck_data = {
354 .parent = "dpll4_m2x2_mul_ck",
355 .bit_shift = 0x1b,
356 .reg = 0xd00,
357 .module = TI_CLKM_CM,
358 .flags = CLKF_SET_BIT_TO_DISABLE,
359};
360
361static struct ti_clk dpll4_m2x2_ck = {
362 .name = "dpll4_m2x2_ck",
363 .type = TI_CLK_GATE,
364 .data = &dpll4_m2x2_ck_data,
365};
366
367static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
368 .parent = "dpll4_m2x2_ck",
369 .div = 1,
370 .mult = 1,
371};
372
373static struct ti_clk omap_96m_alwon_fck = {
374 .name = "omap_96m_alwon_fck",
375 .type = TI_CLK_FIXED_FACTOR,
376 .data = &omap_96m_alwon_fck_data,
377};
378
379static struct ti_clk_fixed_factor cm_96m_fck_data = {
380 .parent = "omap_96m_alwon_fck",
381 .div = 1,
382 .mult = 1,
383};
384
385static struct ti_clk cm_96m_fck = {
386 .name = "cm_96m_fck",
387 .type = TI_CLK_FIXED_FACTOR,
388 .data = &cm_96m_fck_data,
389};
390
391static const char *omap_96m_fck_parents[] = {
392 "cm_96m_fck",
393 "sys_ck",
394};
395
396static struct ti_clk_mux omap_96m_fck_data = {
397 .bit_shift = 6,
398 .num_parents = ARRAY_SIZE(omap_96m_fck_parents),
399 .reg = 0xd40,
400 .module = TI_CLKM_CM,
401 .parents = omap_96m_fck_parents,
402};
403
404static struct ti_clk omap_96m_fck = {
405 .name = "omap_96m_fck",
406 .type = TI_CLK_MUX,
407 .data = &omap_96m_fck_data,
408};
409
410static struct ti_clk_fixed_factor core_96m_fck_data = {
411 .parent = "omap_96m_fck",
412 .div = 1,
413 .mult = 1,
414};
415
416static struct ti_clk core_96m_fck = {
417 .name = "core_96m_fck",
418 .type = TI_CLK_FIXED_FACTOR,
419 .data = &core_96m_fck_data,
420};
421
422static struct ti_clk_gate mspro_fck_data = {
423 .parent = "core_96m_fck",
424 .bit_shift = 23,
425 .reg = 0xa00,
426 .module = TI_CLKM_CM,
427 .flags = CLKF_WAIT,
428};
429
430static struct ti_clk mspro_fck = {
431 .name = "mspro_fck",
432 .clkdm_name = "core_l4_clkdm",
433 .type = TI_CLK_GATE,
434 .data = &mspro_fck_data,
435};
436
437static struct ti_clk_gate dss_ick_3430es2_data = {
438 .parent = "l4_ick",
439 .bit_shift = 0,
440 .reg = 0xe10,
441 .module = TI_CLKM_CM,
442 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
443};
444
445static struct ti_clk dss_ick_3430es2 = {
446 .name = "dss_ick",
447 .clkdm_name = "dss_clkdm",
448 .type = TI_CLK_GATE,
449 .data = &dss_ick_3430es2_data,
450};
451
452static struct ti_clk_gate uart4_ick_am35xx_data = {
453 .parent = "core_l4_ick",
454 .bit_shift = 23,
455 .reg = 0xa10,
456 .module = TI_CLKM_CM,
457 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
458};
459
460static struct ti_clk uart4_ick_am35xx = {
461 .name = "uart4_ick_am35xx",
462 .clkdm_name = "core_l4_clkdm",
463 .type = TI_CLK_GATE,
464 .data = &uart4_ick_am35xx_data,
465};
466
467static struct ti_clk_fixed_factor security_l4_ick2_data = {
468 .parent = "l4_ick",
469 .div = 1,
470 .mult = 1,
471};
472
473static struct ti_clk security_l4_ick2 = {
474 .name = "security_l4_ick2",
475 .type = TI_CLK_FIXED_FACTOR,
476 .data = &security_l4_ick2_data,
477};
478
479static struct ti_clk_gate aes1_ick_data = {
480 .parent = "security_l4_ick2",
481 .bit_shift = 3,
482 .reg = 0xa14,
483 .module = TI_CLKM_CM,
484 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
485};
486
487static struct ti_clk aes1_ick = {
488 .name = "aes1_ick",
489 .type = TI_CLK_GATE,
490 .data = &aes1_ick_data,
491};
492
493static const char *dpll5_ck_parents[] = {
494 "sys_ck",
495 "sys_ck",
496};
497
498static struct ti_clk_dpll dpll5_ck_data = {
499 .num_parents = ARRAY_SIZE(dpll5_ck_parents),
500 .control_reg = 0xd04,
501 .idlest_reg = 0xd24,
502 .mult_div1_reg = 0xd4c,
503 .autoidle_reg = 0xd34,
504 .module = TI_CLKM_CM,
505 .parents = dpll5_ck_parents,
506 .freqsel_mask = 0xf0,
507 .modes = 0x82,
508 .div1_mask = 0x7f,
509 .idlest_mask = 0x1,
510 .auto_recal_bit = 0x3,
511 .max_divider = 0x80,
512 .min_divider = 0x1,
513 .recal_en_bit = 0x19,
514 .max_multiplier = 0x7ff,
515 .enable_mask = 0x7,
516 .mult_mask = 0x7ff00,
517 .recal_st_bit = 0x19,
518 .autoidle_mask = 0x7,
519};
520
521static struct ti_clk dpll5_ck = {
522 .name = "dpll5_ck",
523 .clkdm_name = "dpll5_clkdm",
524 .type = TI_CLK_DPLL,
525 .data = &dpll5_ck_data,
526};
527
528static struct ti_clk_divider dpll5_m2_ck_data = {
529 .parent = "dpll5_ck",
530 .max_div = 31,
531 .reg = 0xd50,
532 .module = TI_CLKM_CM,
533 .flags = CLKF_INDEX_STARTS_AT_ONE,
534};
535
536static struct ti_clk dpll5_m2_ck = {
537 .name = "dpll5_m2_ck",
538 .type = TI_CLK_DIVIDER,
539 .data = &dpll5_m2_ck_data,
540};
541
542static struct ti_clk_gate usbhost_120m_fck_data = {
543 .parent = "dpll5_m2_ck",
544 .bit_shift = 1,
545 .reg = 0x1400,
546 .module = TI_CLKM_CM,
547};
548
549static struct ti_clk usbhost_120m_fck = {
550 .name = "usbhost_120m_fck",
551 .clkdm_name = "usbhost_clkdm",
552 .type = TI_CLK_GATE,
553 .data = &usbhost_120m_fck_data,
554};
555
556static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
557 .parent = "cm_96m_fck",
558 .div = 2,
559 .mult = 1,
560};
561
562static struct ti_clk cm_96m_d2_fck = {
563 .name = "cm_96m_d2_fck",
564 .type = TI_CLK_FIXED_FACTOR,
565 .data = &cm_96m_d2_fck_data,
566};
567
568static struct ti_clk_fixed sys_altclk_data = {
569 .frequency = 0x0,
570};
571
572static struct ti_clk sys_altclk = {
573 .name = "sys_altclk",
574 .type = TI_CLK_FIXED,
575 .data = &sys_altclk_data,
576};
577
578static const char *omap_48m_fck_parents[] = {
579 "cm_96m_d2_fck",
580 "sys_altclk",
581};
582
583static struct ti_clk_mux omap_48m_fck_data = {
584 .bit_shift = 3,
585 .num_parents = ARRAY_SIZE(omap_48m_fck_parents),
586 .reg = 0xd40,
587 .module = TI_CLKM_CM,
588 .parents = omap_48m_fck_parents,
589};
590
591static struct ti_clk omap_48m_fck = {
592 .name = "omap_48m_fck",
593 .type = TI_CLK_MUX,
594 .data = &omap_48m_fck_data,
595};
596
597static struct ti_clk_fixed_factor core_48m_fck_data = {
598 .parent = "omap_48m_fck",
599 .div = 1,
600 .mult = 1,
601};
602
603static struct ti_clk core_48m_fck = {
604 .name = "core_48m_fck",
605 .type = TI_CLK_FIXED_FACTOR,
606 .data = &core_48m_fck_data,
607};
608
609static struct ti_clk_fixed mcbsp_clks_data = {
610 .frequency = 0x0,
611};
612
613static struct ti_clk mcbsp_clks = {
614 .name = "mcbsp_clks",
615 .type = TI_CLK_FIXED,
616 .data = &mcbsp_clks_data,
617};
618
619static struct ti_clk_gate mcbsp2_gate_fck_data = {
620 .parent = "mcbsp_clks",
621 .bit_shift = 0,
622 .reg = 0x1000,
623 .module = TI_CLKM_CM,
624};
625
626static struct ti_clk_fixed_factor per_96m_fck_data = {
627 .parent = "omap_96m_alwon_fck",
628 .div = 1,
629 .mult = 1,
630};
631
632static struct ti_clk per_96m_fck = {
633 .name = "per_96m_fck",
634 .type = TI_CLK_FIXED_FACTOR,
635 .data = &per_96m_fck_data,
636};
637
638static const char *mcbsp2_mux_fck_parents[] = {
639 "per_96m_fck",
640 "mcbsp_clks",
641};
642
643static struct ti_clk_mux mcbsp2_mux_fck_data = {
644 .bit_shift = 6,
645 .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
646 .reg = 0x274,
647 .module = TI_CLKM_SCRM,
648 .parents = mcbsp2_mux_fck_parents,
649};
650
651static struct ti_clk_composite mcbsp2_fck_data = {
652 .mux = &mcbsp2_mux_fck_data,
653 .gate = &mcbsp2_gate_fck_data,
654};
655
656static struct ti_clk mcbsp2_fck = {
657 .name = "mcbsp2_fck",
658 .type = TI_CLK_COMPOSITE,
659 .data = &mcbsp2_fck_data,
660};
661
662static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
663 .parent = "dpll3_m2_ck",
664 .div = 1,
665 .mult = 2,
666};
667
668static struct ti_clk dpll3_m2x2_ck = {
669 .name = "dpll3_m2x2_ck",
670 .type = TI_CLK_FIXED_FACTOR,
671 .data = &dpll3_m2x2_ck_data,
672};
673
674static struct ti_clk_fixed_factor corex2_fck_data = {
675 .parent = "dpll3_m2x2_ck",
676 .div = 1,
677 .mult = 1,
678};
679
680static struct ti_clk corex2_fck = {
681 .name = "corex2_fck",
682 .type = TI_CLK_FIXED_FACTOR,
683 .data = &corex2_fck_data,
684};
685
686static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
687 .parent = "corex2_fck",
688 .bit_shift = 0,
689 .reg = 0xa00,
690 .module = TI_CLKM_CM,
691 .flags = CLKF_NO_WAIT,
692};
693
694static int ssi_ssr_div_fck_3430es1_divs[] = {
695 0,
696 1,
697 2,
698 3,
699 4,
700 0,
701 6,
702 0,
703 8,
704};
705
706static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
707 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
708 .parent = "corex2_fck",
709 .bit_shift = 8,
710 .dividers = ssi_ssr_div_fck_3430es1_divs,
711 .reg = 0xa40,
712 .module = TI_CLKM_CM,
713};
714
715static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
716 .gate = &ssi_ssr_gate_fck_3430es1_data,
717 .divider = &ssi_ssr_div_fck_3430es1_data,
718};
719
720static struct ti_clk ssi_ssr_fck_3430es1 = {
721 .name = "ssi_ssr_fck",
722 .type = TI_CLK_COMPOSITE,
723 .data = &ssi_ssr_fck_3430es1_data,
724};
725
726static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
727 .parent = "ssi_ssr_fck",
728 .div = 2,
729 .mult = 1,
730};
731
732static struct ti_clk ssi_sst_fck_3430es1 = {
733 .name = "ssi_sst_fck",
734 .type = TI_CLK_FIXED_FACTOR,
735 .data = &ssi_sst_fck_3430es1_data,
736};
737
738static struct ti_clk_fixed omap_32k_fck_data = {
739 .frequency = 32768,
740};
741
742static struct ti_clk omap_32k_fck = {
743 .name = "omap_32k_fck",
744 .type = TI_CLK_FIXED,
745 .data = &omap_32k_fck_data,
746};
747
748static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
749 .parent = "omap_32k_fck",
750 .div = 1,
751 .mult = 1,
752};
753
754static struct ti_clk per_32k_alwon_fck = {
755 .name = "per_32k_alwon_fck",
756 .type = TI_CLK_FIXED_FACTOR,
757 .data = &per_32k_alwon_fck_data,
758};
759
760static struct ti_clk_gate gpio5_dbck_data = {
761 .parent = "per_32k_alwon_fck",
762 .bit_shift = 16,
763 .reg = 0x1000,
764 .module = TI_CLKM_CM,
765};
766
767static struct ti_clk gpio5_dbck = {
768 .name = "gpio5_dbck",
769 .clkdm_name = "per_clkdm",
770 .type = TI_CLK_GATE,
771 .data = &gpio5_dbck_data,
772};
773
774static struct ti_clk_gate gpt1_ick_data = {
775 .parent = "wkup_l4_ick",
776 .bit_shift = 0,
777 .reg = 0xc10,
778 .module = TI_CLKM_CM,
779 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
780};
781
782static struct ti_clk gpt1_ick = {
783 .name = "gpt1_ick",
784 .clkdm_name = "wkup_clkdm",
785 .type = TI_CLK_GATE,
786 .data = &gpt1_ick_data,
787};
788
789static struct ti_clk_gate mcspi3_fck_data = {
790 .parent = "core_48m_fck",
791 .bit_shift = 20,
792 .reg = 0xa00,
793 .module = TI_CLKM_CM,
794 .flags = CLKF_WAIT,
795};
796
797static struct ti_clk mcspi3_fck = {
798 .name = "mcspi3_fck",
799 .clkdm_name = "core_l4_clkdm",
800 .type = TI_CLK_GATE,
801 .data = &mcspi3_fck_data,
802};
803
804static struct ti_clk_gate gpt2_gate_fck_data = {
805 .parent = "sys_ck",
806 .bit_shift = 3,
807 .reg = 0x1000,
808 .module = TI_CLKM_CM,
809};
810
811static const char *gpt2_mux_fck_parents[] = {
812 "omap_32k_fck",
813 "sys_ck",
814};
815
816static struct ti_clk_mux gpt2_mux_fck_data = {
817 .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
818 .reg = 0x1040,
819 .module = TI_CLKM_CM,
820 .parents = gpt2_mux_fck_parents,
821};
822
823static struct ti_clk_composite gpt2_fck_data = {
824 .mux = &gpt2_mux_fck_data,
825 .gate = &gpt2_gate_fck_data,
826};
827
828static struct ti_clk gpt2_fck = {
829 .name = "gpt2_fck",
830 .type = TI_CLK_COMPOSITE,
831 .data = &gpt2_fck_data,
832};
833
834static struct ti_clk_gate gpt10_ick_data = {
835 .parent = "core_l4_ick",
836 .bit_shift = 11,
837 .reg = 0xa10,
838 .module = TI_CLKM_CM,
839 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
840};
841
842static struct ti_clk gpt10_ick = {
843 .name = "gpt10_ick",
844 .clkdm_name = "core_l4_clkdm",
845 .type = TI_CLK_GATE,
846 .data = &gpt10_ick_data,
847};
848
849static struct ti_clk_gate uart2_fck_data = {
850 .parent = "core_48m_fck",
851 .bit_shift = 14,
852 .reg = 0xa00,
853 .module = TI_CLKM_CM,
854 .flags = CLKF_WAIT,
855};
856
857static struct ti_clk uart2_fck = {
858 .name = "uart2_fck",
859 .clkdm_name = "core_l4_clkdm",
860 .type = TI_CLK_GATE,
861 .data = &uart2_fck_data,
862};
863
864static struct ti_clk_fixed_factor sr_l4_ick_data = {
865 .parent = "l4_ick",
866 .div = 1,
867 .mult = 1,
868};
869
870static struct ti_clk sr_l4_ick = {
871 .name = "sr_l4_ick",
872 .type = TI_CLK_FIXED_FACTOR,
873 .data = &sr_l4_ick_data,
874};
875
876static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
877 .parent = "omap_96m_fck",
878 .div = 8,
879 .mult = 1,
880};
881
882static struct ti_clk omap_96m_d8_fck = {
883 .name = "omap_96m_d8_fck",
884 .type = TI_CLK_FIXED_FACTOR,
885 .data = &omap_96m_d8_fck_data,
886};
887
888static struct ti_clk_divider dpll4_m5_ck_data = {
889 .parent = "dpll4_ck",
890 .max_div = 63,
891 .reg = 0xf40,
892 .module = TI_CLKM_CM,
893 .flags = CLKF_INDEX_STARTS_AT_ONE,
894};
895
896static struct ti_clk dpll4_m5_ck = {
897 .name = "dpll4_m5_ck",
898 .type = TI_CLK_DIVIDER,
899 .data = &dpll4_m5_ck_data,
900};
901
902static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
903 .parent = "dpll4_m5_ck",
904 .div = 1,
905 .mult = 2,
906 .flags = CLKF_SET_RATE_PARENT,
907};
908
909static struct ti_clk dpll4_m5x2_mul_ck = {
910 .name = "dpll4_m5x2_mul_ck",
911 .type = TI_CLK_FIXED_FACTOR,
912 .data = &dpll4_m5x2_mul_ck_data,
913};
914
915static struct ti_clk_gate dpll4_m5x2_ck_data = {
916 .parent = "dpll4_m5x2_mul_ck",
917 .bit_shift = 0x1e,
918 .reg = 0xd00,
919 .module = TI_CLKM_CM,
920 .flags = CLKF_SET_BIT_TO_DISABLE,
921};
922
923static struct ti_clk dpll4_m5x2_ck = {
924 .name = "dpll4_m5x2_ck",
925 .type = TI_CLK_GATE,
926 .data = &dpll4_m5x2_ck_data,
927};
928
929static struct ti_clk_gate cam_mclk_data = {
930 .parent = "dpll4_m5x2_ck",
931 .bit_shift = 0,
932 .reg = 0xf00,
933 .module = TI_CLKM_CM,
934 .flags = CLKF_SET_RATE_PARENT,
935};
936
937static struct ti_clk cam_mclk = {
938 .name = "cam_mclk",
939 .type = TI_CLK_GATE,
940 .data = &cam_mclk_data,
941};
942
943static struct ti_clk_gate mcbsp3_gate_fck_data = {
944 .parent = "mcbsp_clks",
945 .bit_shift = 1,
946 .reg = 0x1000,
947 .module = TI_CLKM_CM,
948};
949
950static const char *mcbsp3_mux_fck_parents[] = {
951 "per_96m_fck",
952 "mcbsp_clks",
953};
954
955static struct ti_clk_mux mcbsp3_mux_fck_data = {
956 .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
957 .reg = 0x2d8,
958 .module = TI_CLKM_SCRM,
959 .parents = mcbsp3_mux_fck_parents,
960};
961
962static struct ti_clk_composite mcbsp3_fck_data = {
963 .mux = &mcbsp3_mux_fck_data,
964 .gate = &mcbsp3_gate_fck_data,
965};
966
967static struct ti_clk mcbsp3_fck = {
968 .name = "mcbsp3_fck",
969 .type = TI_CLK_COMPOSITE,
970 .data = &mcbsp3_fck_data,
971};
972
973static struct ti_clk_gate csi2_96m_fck_data = {
974 .parent = "core_96m_fck",
975 .bit_shift = 1,
976 .reg = 0xf00,
977 .module = TI_CLKM_CM,
978};
979
980static struct ti_clk csi2_96m_fck = {
981 .name = "csi2_96m_fck",
982 .clkdm_name = "cam_clkdm",
983 .type = TI_CLK_GATE,
984 .data = &csi2_96m_fck_data,
985};
986
987static struct ti_clk_gate gpt9_gate_fck_data = {
988 .parent = "sys_ck",
989 .bit_shift = 10,
990 .reg = 0x1000,
991 .module = TI_CLKM_CM,
992};
993
994static const char *gpt9_mux_fck_parents[] = {
995 "omap_32k_fck",
996 "sys_ck",
997};
998
999static struct ti_clk_mux gpt9_mux_fck_data = {
1000 .bit_shift = 7,
1001 .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
1002 .reg = 0x1040,
1003 .module = TI_CLKM_CM,
1004 .parents = gpt9_mux_fck_parents,
1005};
1006
1007static struct ti_clk_composite gpt9_fck_data = {
1008 .mux = &gpt9_mux_fck_data,
1009 .gate = &gpt9_gate_fck_data,
1010};
1011
1012static struct ti_clk gpt9_fck = {
1013 .name = "gpt9_fck",
1014 .type = TI_CLK_COMPOSITE,
1015 .data = &gpt9_fck_data,
1016};
1017
1018static struct ti_clk_divider dpll3_m3_ck_data = {
1019 .parent = "dpll3_ck",
1020 .bit_shift = 16,
1021 .max_div = 31,
1022 .reg = 0x1140,
1023 .module = TI_CLKM_CM,
1024 .flags = CLKF_INDEX_STARTS_AT_ONE,
1025};
1026
1027static struct ti_clk dpll3_m3_ck = {
1028 .name = "dpll3_m3_ck",
1029 .type = TI_CLK_DIVIDER,
1030 .data = &dpll3_m3_ck_data,
1031};
1032
1033static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
1034 .parent = "dpll3_m3_ck",
1035 .div = 1,
1036 .mult = 2,
1037};
1038
1039static struct ti_clk dpll3_m3x2_mul_ck = {
1040 .name = "dpll3_m3x2_mul_ck",
1041 .type = TI_CLK_FIXED_FACTOR,
1042 .data = &dpll3_m3x2_mul_ck_data,
1043};
1044
1045static struct ti_clk_gate sr2_fck_data = {
1046 .parent = "sys_ck",
1047 .bit_shift = 7,
1048 .reg = 0xc00,
1049 .module = TI_CLKM_CM,
1050 .flags = CLKF_WAIT,
1051};
1052
1053static struct ti_clk sr2_fck = {
1054 .name = "sr2_fck",
1055 .clkdm_name = "wkup_clkdm",
1056 .type = TI_CLK_GATE,
1057 .data = &sr2_fck_data,
1058};
1059
1060static struct ti_clk_fixed pclk_ck_data = {
1061 .frequency = 27000000,
1062};
1063
1064static struct ti_clk pclk_ck = {
1065 .name = "pclk_ck",
1066 .type = TI_CLK_FIXED,
1067 .data = &pclk_ck_data,
1068};
1069
1070static struct ti_clk_gate wdt2_ick_data = {
1071 .parent = "wkup_l4_ick",
1072 .bit_shift = 5,
1073 .reg = 0xc10,
1074 .module = TI_CLKM_CM,
1075 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1076};
1077
1078static struct ti_clk wdt2_ick = {
1079 .name = "wdt2_ick",
1080 .clkdm_name = "wkup_clkdm",
1081 .type = TI_CLK_GATE,
1082 .data = &wdt2_ick_data,
1083};
1084
1085static struct ti_clk_fixed_factor core_l3_ick_data = {
1086 .parent = "l3_ick",
1087 .div = 1,
1088 .mult = 1,
1089};
1090
1091static struct ti_clk core_l3_ick = {
1092 .name = "core_l3_ick",
1093 .type = TI_CLK_FIXED_FACTOR,
1094 .data = &core_l3_ick_data,
1095};
1096
1097static struct ti_clk_gate mcspi4_fck_data = {
1098 .parent = "core_48m_fck",
1099 .bit_shift = 21,
1100 .reg = 0xa00,
1101 .module = TI_CLKM_CM,
1102 .flags = CLKF_WAIT,
1103};
1104
1105static struct ti_clk mcspi4_fck = {
1106 .name = "mcspi4_fck",
1107 .clkdm_name = "core_l4_clkdm",
1108 .type = TI_CLK_GATE,
1109 .data = &mcspi4_fck_data,
1110};
1111
1112static struct ti_clk_fixed_factor per_48m_fck_data = {
1113 .parent = "omap_48m_fck",
1114 .div = 1,
1115 .mult = 1,
1116};
1117
1118static struct ti_clk per_48m_fck = {
1119 .name = "per_48m_fck",
1120 .type = TI_CLK_FIXED_FACTOR,
1121 .data = &per_48m_fck_data,
1122};
1123
1124static struct ti_clk_gate uart4_fck_data = {
1125 .parent = "per_48m_fck",
1126 .bit_shift = 18,
1127 .reg = 0x1000,
1128 .module = TI_CLKM_CM,
1129 .flags = CLKF_WAIT,
1130};
1131
1132static struct ti_clk uart4_fck = {
1133 .name = "uart4_fck",
1134 .clkdm_name = "per_clkdm",
1135 .type = TI_CLK_GATE,
1136 .data = &uart4_fck_data,
1137};
1138
1139static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
1140 .parent = "omap_96m_fck",
1141 .div = 10,
1142 .mult = 1,
1143};
1144
1145static struct ti_clk omap_96m_d10_fck = {
1146 .name = "omap_96m_d10_fck",
1147 .type = TI_CLK_FIXED_FACTOR,
1148 .data = &omap_96m_d10_fck_data,
1149};
1150
1151static struct ti_clk_gate usim_gate_fck_data = {
1152 .parent = "omap_96m_fck",
1153 .bit_shift = 9,
1154 .reg = 0xc00,
1155 .module = TI_CLKM_CM,
1156};
1157
1158static struct ti_clk_fixed_factor per_l4_ick_data = {
1159 .parent = "l4_ick",
1160 .div = 1,
1161 .mult = 1,
1162};
1163
1164static struct ti_clk per_l4_ick = {
1165 .name = "per_l4_ick",
1166 .type = TI_CLK_FIXED_FACTOR,
1167 .data = &per_l4_ick_data,
1168};
1169
1170static struct ti_clk_gate gpt5_ick_data = {
1171 .parent = "per_l4_ick",
1172 .bit_shift = 6,
1173 .reg = 0x1010,
1174 .module = TI_CLKM_CM,
1175 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1176};
1177
1178static struct ti_clk gpt5_ick = {
1179 .name = "gpt5_ick",
1180 .clkdm_name = "per_clkdm",
1181 .type = TI_CLK_GATE,
1182 .data = &gpt5_ick_data,
1183};
1184
1185static struct ti_clk_gate mcspi2_ick_data = {
1186 .parent = "core_l4_ick",
1187 .bit_shift = 19,
1188 .reg = 0xa10,
1189 .module = TI_CLKM_CM,
1190 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1191};
1192
1193static struct ti_clk mcspi2_ick = {
1194 .name = "mcspi2_ick",
1195 .clkdm_name = "core_l4_clkdm",
1196 .type = TI_CLK_GATE,
1197 .data = &mcspi2_ick_data,
1198};
1199
1200static struct ti_clk_fixed_factor ssi_l4_ick_data = {
1201 .parent = "l4_ick",
1202 .div = 1,
1203 .mult = 1,
1204};
1205
1206static struct ti_clk ssi_l4_ick = {
1207 .name = "ssi_l4_ick",
1208 .clkdm_name = "core_l4_clkdm",
1209 .type = TI_CLK_FIXED_FACTOR,
1210 .data = &ssi_l4_ick_data,
1211};
1212
1213static struct ti_clk_gate ssi_ick_3430es1_data = {
1214 .parent = "ssi_l4_ick",
1215 .bit_shift = 0,
1216 .reg = 0xa10,
1217 .module = TI_CLKM_CM,
1218 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1219};
1220
1221static struct ti_clk ssi_ick_3430es1 = {
1222 .name = "ssi_ick",
1223 .clkdm_name = "core_l4_clkdm",
1224 .type = TI_CLK_GATE,
1225 .data = &ssi_ick_3430es1_data,
1226};
1227
1228static struct ti_clk_gate i2c2_fck_data = {
1229 .parent = "core_96m_fck",
1230 .bit_shift = 16,
1231 .reg = 0xa00,
1232 .module = TI_CLKM_CM,
1233 .flags = CLKF_WAIT,
1234};
1235
1236static struct ti_clk i2c2_fck = {
1237 .name = "i2c2_fck",
1238 .clkdm_name = "core_l4_clkdm",
1239 .type = TI_CLK_GATE,
1240 .data = &i2c2_fck_data,
1241};
1242
1243static struct ti_clk_divider dpll1_fck_data = {
1244 .parent = "core_ck",
1245 .bit_shift = 19,
1246 .max_div = 7,
1247 .reg = 0x940,
1248 .module = TI_CLKM_CM,
1249 .flags = CLKF_INDEX_STARTS_AT_ONE,
1250};
1251
1252static struct ti_clk dpll1_fck = {
1253 .name = "dpll1_fck",
1254 .type = TI_CLK_DIVIDER,
1255 .data = &dpll1_fck_data,
1256};
1257
1258static const char *dpll1_ck_parents[] = {
1259 "sys_ck",
1260 "dpll1_fck",
1261};
1262
1263static struct ti_clk_dpll dpll1_ck_data = {
1264 .num_parents = ARRAY_SIZE(dpll1_ck_parents),
1265 .control_reg = 0x904,
1266 .idlest_reg = 0x924,
1267 .mult_div1_reg = 0x940,
1268 .autoidle_reg = 0x934,
1269 .module = TI_CLKM_CM,
1270 .parents = dpll1_ck_parents,
1271 .freqsel_mask = 0xf0,
1272 .modes = 0xa0,
1273 .div1_mask = 0x7f,
1274 .idlest_mask = 0x1,
1275 .auto_recal_bit = 0x3,
1276 .max_divider = 0x80,
1277 .min_divider = 0x1,
1278 .recal_en_bit = 0x7,
1279 .max_multiplier = 0x7ff,
1280 .enable_mask = 0x7,
1281 .mult_mask = 0x7ff00,
1282 .recal_st_bit = 0x7,
1283 .autoidle_mask = 0x7,
1284};
1285
1286static struct ti_clk dpll1_ck = {
1287 .name = "dpll1_ck",
1288 .clkdm_name = "dpll1_clkdm",
1289 .type = TI_CLK_DPLL,
1290 .data = &dpll1_ck_data,
1291};
1292
1293static struct ti_clk_fixed secure_32k_fck_data = {
1294 .frequency = 32768,
1295};
1296
1297static struct ti_clk secure_32k_fck = {
1298 .name = "secure_32k_fck",
1299 .type = TI_CLK_FIXED,
1300 .data = &secure_32k_fck_data,
1301};
1302
1303static struct ti_clk_gate gpio5_ick_data = {
1304 .parent = "per_l4_ick",
1305 .bit_shift = 16,
1306 .reg = 0x1010,
1307 .module = TI_CLKM_CM,
1308 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1309};
1310
1311static struct ti_clk gpio5_ick = {
1312 .name = "gpio5_ick",
1313 .clkdm_name = "per_clkdm",
1314 .type = TI_CLK_GATE,
1315 .data = &gpio5_ick_data,
1316};
1317
1318static struct ti_clk_divider dpll4_m4_ck_data = {
1319 .parent = "dpll4_ck",
1320 .max_div = 32,
1321 .reg = 0xe40,
1322 .module = TI_CLKM_CM,
1323 .flags = CLKF_INDEX_STARTS_AT_ONE,
1324};
1325
1326static struct ti_clk dpll4_m4_ck = {
1327 .name = "dpll4_m4_ck",
1328 .type = TI_CLK_DIVIDER,
1329 .data = &dpll4_m4_ck_data,
1330};
1331
1332static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
1333 .parent = "dpll4_m4_ck",
1334 .div = 1,
1335 .mult = 2,
1336 .flags = CLKF_SET_RATE_PARENT,
1337};
1338
1339static struct ti_clk dpll4_m4x2_mul_ck = {
1340 .name = "dpll4_m4x2_mul_ck",
1341 .type = TI_CLK_FIXED_FACTOR,
1342 .data = &dpll4_m4x2_mul_ck_data,
1343};
1344
1345static struct ti_clk_gate dpll4_m4x2_ck_data = {
1346 .parent = "dpll4_m4x2_mul_ck",
1347 .bit_shift = 0x1d,
1348 .reg = 0xd00,
1349 .module = TI_CLKM_CM,
1350 .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
1351};
1352
1353static struct ti_clk dpll4_m4x2_ck = {
1354 .name = "dpll4_m4x2_ck",
1355 .type = TI_CLK_GATE,
1356 .data = &dpll4_m4x2_ck_data,
1357};
1358
1359static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
1360 .parent = "dpll4_m4x2_ck",
1361 .bit_shift = 0,
1362 .reg = 0xe00,
1363 .module = TI_CLKM_CM,
1364 .flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
1365};
1366
1367static struct ti_clk dss1_alwon_fck_3430es2 = {
1368 .name = "dss1_alwon_fck",
1369 .clkdm_name = "dss_clkdm",
1370 .type = TI_CLK_GATE,
1371 .data = &dss1_alwon_fck_3430es2_data,
1372};
1373
1374static struct ti_clk_gate uart3_ick_data = {
1375 .parent = "per_l4_ick",
1376 .bit_shift = 11,
1377 .reg = 0x1010,
1378 .module = TI_CLKM_CM,
1379 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1380};
1381
1382static struct ti_clk uart3_ick = {
1383 .name = "uart3_ick",
1384 .clkdm_name = "per_clkdm",
1385 .type = TI_CLK_GATE,
1386 .data = &uart3_ick_data,
1387};
1388
1389static struct ti_clk_divider dpll4_m3_ck_data = {
1390 .parent = "dpll4_ck",
1391 .bit_shift = 8,
1392 .max_div = 32,
1393 .reg = 0xe40,
1394 .module = TI_CLKM_CM,
1395 .flags = CLKF_INDEX_STARTS_AT_ONE,
1396};
1397
1398static struct ti_clk dpll4_m3_ck = {
1399 .name = "dpll4_m3_ck",
1400 .type = TI_CLK_DIVIDER,
1401 .data = &dpll4_m3_ck_data,
1402};
1403
1404static struct ti_clk_gate mcbsp3_ick_data = {
1405 .parent = "per_l4_ick",
1406 .bit_shift = 1,
1407 .reg = 0x1010,
1408 .module = TI_CLKM_CM,
1409 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1410};
1411
1412static struct ti_clk mcbsp3_ick = {
1413 .name = "mcbsp3_ick",
1414 .clkdm_name = "per_clkdm",
1415 .type = TI_CLK_GATE,
1416 .data = &mcbsp3_ick_data,
1417};
1418
1419static struct ti_clk_gate gpio3_dbck_data = {
1420 .parent = "per_32k_alwon_fck",
1421 .bit_shift = 14,
1422 .reg = 0x1000,
1423 .module = TI_CLKM_CM,
1424};
1425
1426static struct ti_clk gpio3_dbck = {
1427 .name = "gpio3_dbck",
1428 .clkdm_name = "per_clkdm",
1429 .type = TI_CLK_GATE,
1430 .data = &gpio3_dbck_data,
1431};
1432
1433static struct ti_clk_gate fac_ick_data = {
1434 .parent = "core_l4_ick",
1435 .bit_shift = 8,
1436 .reg = 0xa10,
1437 .module = TI_CLKM_CM,
1438 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1439};
1440
1441static struct ti_clk fac_ick = {
1442 .name = "fac_ick",
1443 .clkdm_name = "core_l4_clkdm",
1444 .type = TI_CLK_GATE,
1445 .data = &fac_ick_data,
1446};
1447
1448static struct ti_clk_gate clkout2_src_gate_ck_data = {
1449 .parent = "core_ck",
1450 .bit_shift = 7,
1451 .reg = 0xd70,
1452 .module = TI_CLKM_CM,
1453 .flags = CLKF_NO_WAIT,
1454};
1455
1456static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
1457 .parent = "dpll4_m3_ck",
1458 .div = 1,
1459 .mult = 2,
1460};
1461
1462static struct ti_clk dpll4_m3x2_mul_ck = {
1463 .name = "dpll4_m3x2_mul_ck",
1464 .type = TI_CLK_FIXED_FACTOR,
1465 .data = &dpll4_m3x2_mul_ck_data,
1466};
1467
1468static struct ti_clk_gate dpll4_m3x2_ck_data = {
1469 .parent = "dpll4_m3x2_mul_ck",
1470 .bit_shift = 0x1c,
1471 .reg = 0xd00,
1472 .module = TI_CLKM_CM,
1473 .flags = CLKF_SET_BIT_TO_DISABLE,
1474};
1475
1476static struct ti_clk dpll4_m3x2_ck = {
1477 .name = "dpll4_m3x2_ck",
1478 .type = TI_CLK_GATE,
1479 .data = &dpll4_m3x2_ck_data,
1480};
1481
1482static const char *omap_54m_fck_parents[] = {
1483 "dpll4_m3x2_ck",
1484 "sys_altclk",
1485};
1486
1487static struct ti_clk_mux omap_54m_fck_data = {
1488 .bit_shift = 5,
1489 .num_parents = ARRAY_SIZE(omap_54m_fck_parents),
1490 .reg = 0xd40,
1491 .module = TI_CLKM_CM,
1492 .parents = omap_54m_fck_parents,
1493};
1494
1495static struct ti_clk omap_54m_fck = {
1496 .name = "omap_54m_fck",
1497 .type = TI_CLK_MUX,
1498 .data = &omap_54m_fck_data,
1499};
1500
1501static const char *clkout2_src_mux_ck_parents[] = {
1502 "core_ck",
1503 "sys_ck",
1504 "cm_96m_fck",
1505 "omap_54m_fck",
1506};
1507
1508static struct ti_clk_mux clkout2_src_mux_ck_data = {
1509 .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
1510 .reg = 0xd70,
1511 .module = TI_CLKM_CM,
1512 .parents = clkout2_src_mux_ck_parents,
1513};
1514
1515static struct ti_clk_composite clkout2_src_ck_data = {
1516 .mux = &clkout2_src_mux_ck_data,
1517 .gate = &clkout2_src_gate_ck_data,
1518};
1519
1520static struct ti_clk clkout2_src_ck = {
1521 .name = "clkout2_src_ck",
1522 .type = TI_CLK_COMPOSITE,
1523 .data = &clkout2_src_ck_data,
1524};
1525
1526static struct ti_clk_gate i2c1_fck_data = {
1527 .parent = "core_96m_fck",
1528 .bit_shift = 15,
1529 .reg = 0xa00,
1530 .module = TI_CLKM_CM,
1531 .flags = CLKF_WAIT,
1532};
1533
1534static struct ti_clk i2c1_fck = {
1535 .name = "i2c1_fck",
1536 .clkdm_name = "core_l4_clkdm",
1537 .type = TI_CLK_GATE,
1538 .data = &i2c1_fck_data,
1539};
1540
1541static struct ti_clk_gate wdt3_fck_data = {
1542 .parent = "per_32k_alwon_fck",
1543 .bit_shift = 12,
1544 .reg = 0x1000,
1545 .module = TI_CLKM_CM,
1546 .flags = CLKF_WAIT,
1547};
1548
1549static struct ti_clk wdt3_fck = {
1550 .name = "wdt3_fck",
1551 .clkdm_name = "per_clkdm",
1552 .type = TI_CLK_GATE,
1553 .data = &wdt3_fck_data,
1554};
1555
1556static struct ti_clk_gate gpt7_gate_fck_data = {
1557 .parent = "sys_ck",
1558 .bit_shift = 8,
1559 .reg = 0x1000,
1560 .module = TI_CLKM_CM,
1561};
1562
1563static const char *gpt7_mux_fck_parents[] = {
1564 "omap_32k_fck",
1565 "sys_ck",
1566};
1567
1568static struct ti_clk_mux gpt7_mux_fck_data = {
1569 .bit_shift = 5,
1570 .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
1571 .reg = 0x1040,
1572 .module = TI_CLKM_CM,
1573 .parents = gpt7_mux_fck_parents,
1574};
1575
1576static struct ti_clk_composite gpt7_fck_data = {
1577 .mux = &gpt7_mux_fck_data,
1578 .gate = &gpt7_gate_fck_data,
1579};
1580
1581static struct ti_clk gpt7_fck = {
1582 .name = "gpt7_fck",
1583 .type = TI_CLK_COMPOSITE,
1584 .data = &gpt7_fck_data,
1585};
1586
1587static struct ti_clk_gate usb_l4_gate_ick_data = {
1588 .parent = "l4_ick",
1589 .bit_shift = 5,
1590 .reg = 0xa10,
1591 .module = TI_CLKM_CM,
1592 .flags = CLKF_INTERFACE,
1593};
1594
1595static struct ti_clk_divider usb_l4_div_ick_data = {
1596 .parent = "l4_ick",
1597 .bit_shift = 4,
1598 .max_div = 1,
1599 .reg = 0xa40,
1600 .module = TI_CLKM_CM,
1601 .flags = CLKF_INDEX_STARTS_AT_ONE,
1602};
1603
1604static struct ti_clk_composite usb_l4_ick_data = {
1605 .gate = &usb_l4_gate_ick_data,
1606 .divider = &usb_l4_div_ick_data,
1607};
1608
1609static struct ti_clk usb_l4_ick = {
1610 .name = "usb_l4_ick",
1611 .type = TI_CLK_COMPOSITE,
1612 .data = &usb_l4_ick_data,
1613};
1614
1615static struct ti_clk_gate uart4_ick_data = {
1616 .parent = "per_l4_ick",
1617 .bit_shift = 18,
1618 .reg = 0x1010,
1619 .module = TI_CLKM_CM,
1620 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1621};
1622
1623static struct ti_clk uart4_ick = {
1624 .name = "uart4_ick",
1625 .clkdm_name = "per_clkdm",
1626 .type = TI_CLK_GATE,
1627 .data = &uart4_ick_data,
1628};
1629
1630static struct ti_clk_fixed dummy_ck_data = {
1631 .frequency = 0,
1632};
1633
1634static struct ti_clk dummy_ck = {
1635 .name = "dummy_ck",
1636 .type = TI_CLK_FIXED,
1637 .data = &dummy_ck_data,
1638};
1639
1640static const char *gpt3_mux_fck_parents[] = {
1641 "omap_32k_fck",
1642 "sys_ck",
1643};
1644
1645static struct ti_clk_mux gpt3_mux_fck_data = {
1646 .bit_shift = 1,
1647 .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
1648 .reg = 0x1040,
1649 .module = TI_CLKM_CM,
1650 .parents = gpt3_mux_fck_parents,
1651};
1652
1653static struct ti_clk_gate gpt9_ick_data = {
1654 .parent = "per_l4_ick",
1655 .bit_shift = 10,
1656 .reg = 0x1010,
1657 .module = TI_CLKM_CM,
1658 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1659};
1660
1661static struct ti_clk gpt9_ick = {
1662 .name = "gpt9_ick",
1663 .clkdm_name = "per_clkdm",
1664 .type = TI_CLK_GATE,
1665 .data = &gpt9_ick_data,
1666};
1667
1668static struct ti_clk_gate gpt10_gate_fck_data = {
1669 .parent = "sys_ck",
1670 .bit_shift = 11,
1671 .reg = 0xa00,
1672 .module = TI_CLKM_CM,
1673};
1674
1675static struct ti_clk_gate dss_ick_3430es1_data = {
1676 .parent = "l4_ick",
1677 .bit_shift = 0,
1678 .reg = 0xe10,
1679 .module = TI_CLKM_CM,
1680 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1681};
1682
1683static struct ti_clk dss_ick_3430es1 = {
1684 .name = "dss_ick",
1685 .clkdm_name = "dss_clkdm",
1686 .type = TI_CLK_GATE,
1687 .data = &dss_ick_3430es1_data,
1688};
1689
1690static struct ti_clk_gate gpt11_ick_data = {
1691 .parent = "core_l4_ick",
1692 .bit_shift = 12,
1693 .reg = 0xa10,
1694 .module = TI_CLKM_CM,
1695 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1696};
1697
1698static struct ti_clk gpt11_ick = {
1699 .name = "gpt11_ick",
1700 .clkdm_name = "core_l4_clkdm",
1701 .type = TI_CLK_GATE,
1702 .data = &gpt11_ick_data,
1703};
1704
1705static struct ti_clk_divider dpll2_fck_data = {
1706 .parent = "core_ck",
1707 .bit_shift = 19,
1708 .max_div = 7,
1709 .reg = 0x40,
1710 .module = TI_CLKM_CM,
1711 .flags = CLKF_INDEX_STARTS_AT_ONE,
1712};
1713
1714static struct ti_clk dpll2_fck = {
1715 .name = "dpll2_fck",
1716 .type = TI_CLK_DIVIDER,
1717 .data = &dpll2_fck_data,
1718};
1719
1720static struct ti_clk_gate uart1_fck_data = {
1721 .parent = "core_48m_fck",
1722 .bit_shift = 13,
1723 .reg = 0xa00,
1724 .module = TI_CLKM_CM,
1725 .flags = CLKF_WAIT,
1726};
1727
1728static struct ti_clk uart1_fck = {
1729 .name = "uart1_fck",
1730 .clkdm_name = "core_l4_clkdm",
1731 .type = TI_CLK_GATE,
1732 .data = &uart1_fck_data,
1733};
1734
1735static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
1736 .parent = "core_l3_ick",
1737 .bit_shift = 4,
1738 .reg = 0xa10,
1739 .module = TI_CLKM_CM,
1740 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
1741};
1742
1743static struct ti_clk hsotgusb_ick_3430es1 = {
1744 .name = "hsotgusb_ick_3430es1",
1745 .clkdm_name = "core_l3_clkdm",
1746 .type = TI_CLK_GATE,
1747 .data = &hsotgusb_ick_3430es1_data,
1748};
1749
1750static struct ti_clk_gate gpio2_ick_data = {
1751 .parent = "per_l4_ick",
1752 .bit_shift = 13,
1753 .reg = 0x1010,
1754 .module = TI_CLKM_CM,
1755 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1756};
1757
1758static struct ti_clk gpio2_ick = {
1759 .name = "gpio2_ick",
1760 .clkdm_name = "per_clkdm",
1761 .type = TI_CLK_GATE,
1762 .data = &gpio2_ick_data,
1763};
1764
1765static struct ti_clk_gate mmchs1_ick_data = {
1766 .parent = "core_l4_ick",
1767 .bit_shift = 24,
1768 .reg = 0xa10,
1769 .module = TI_CLKM_CM,
1770 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1771};
1772
1773static struct ti_clk mmchs1_ick = {
1774 .name = "mmchs1_ick",
1775 .clkdm_name = "core_l4_clkdm",
1776 .type = TI_CLK_GATE,
1777 .data = &mmchs1_ick_data,
1778};
1779
1780static struct ti_clk_gate modem_fck_data = {
1781 .parent = "sys_ck",
1782 .bit_shift = 31,
1783 .reg = 0xa00,
1784 .module = TI_CLKM_CM,
1785 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1786};
1787
1788static struct ti_clk modem_fck = {
1789 .name = "modem_fck",
1790 .clkdm_name = "d2d_clkdm",
1791 .type = TI_CLK_GATE,
1792 .data = &modem_fck_data,
1793};
1794
1795static struct ti_clk_gate mcbsp4_ick_data = {
1796 .parent = "per_l4_ick",
1797 .bit_shift = 2,
1798 .reg = 0x1010,
1799 .module = TI_CLKM_CM,
1800 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1801};
1802
1803static struct ti_clk mcbsp4_ick = {
1804 .name = "mcbsp4_ick",
1805 .clkdm_name = "per_clkdm",
1806 .type = TI_CLK_GATE,
1807 .data = &mcbsp4_ick_data,
1808};
1809
1810static struct ti_clk_gate gpio1_ick_data = {
1811 .parent = "wkup_l4_ick",
1812 .bit_shift = 3,
1813 .reg = 0xc10,
1814 .module = TI_CLKM_CM,
1815 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
1816};
1817
1818static struct ti_clk gpio1_ick = {
1819 .name = "gpio1_ick",
1820 .clkdm_name = "wkup_clkdm",
1821 .type = TI_CLK_GATE,
1822 .data = &gpio1_ick_data,
1823};
1824
1825static const char *gpt6_mux_fck_parents[] = {
1826 "omap_32k_fck",
1827 "sys_ck",
1828};
1829
1830static struct ti_clk_mux gpt6_mux_fck_data = {
1831 .bit_shift = 4,
1832 .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
1833 .reg = 0x1040,
1834 .module = TI_CLKM_CM,
1835 .parents = gpt6_mux_fck_parents,
1836};
1837
1838static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
1839 .parent = "dpll1_ck",
1840 .div = 1,
1841 .mult = 2,
1842};
1843
1844static struct ti_clk dpll1_x2_ck = {
1845 .name = "dpll1_x2_ck",
1846 .type = TI_CLK_FIXED_FACTOR,
1847 .data = &dpll1_x2_ck_data,
1848};
1849
1850static struct ti_clk_divider dpll1_x2m2_ck_data = {
1851 .parent = "dpll1_x2_ck",
1852 .max_div = 31,
1853 .reg = 0x944,
1854 .module = TI_CLKM_CM,
1855 .flags = CLKF_INDEX_STARTS_AT_ONE,
1856};
1857
1858static struct ti_clk dpll1_x2m2_ck = {
1859 .name = "dpll1_x2m2_ck",
1860 .type = TI_CLK_DIVIDER,
1861 .data = &dpll1_x2m2_ck_data,
1862};
1863
1864static struct ti_clk_fixed_factor mpu_ck_data = {
1865 .parent = "dpll1_x2m2_ck",
1866 .div = 1,
1867 .mult = 1,
1868};
1869
1870static struct ti_clk mpu_ck = {
1871 .name = "mpu_ck",
1872 .type = TI_CLK_FIXED_FACTOR,
1873 .data = &mpu_ck_data,
1874};
1875
1876static struct ti_clk_divider arm_fck_data = {
1877 .parent = "mpu_ck",
1878 .max_div = 2,
1879 .reg = 0x924,
1880 .module = TI_CLKM_CM,
1881};
1882
1883static struct ti_clk arm_fck = {
1884 .name = "arm_fck",
1885 .type = TI_CLK_DIVIDER,
1886 .data = &arm_fck_data,
1887};
1888
1889static struct ti_clk_fixed_factor core_d3_ck_data = {
1890 .parent = "core_ck",
1891 .div = 3,
1892 .mult = 1,
1893};
1894
1895static struct ti_clk core_d3_ck = {
1896 .name = "core_d3_ck",
1897 .type = TI_CLK_FIXED_FACTOR,
1898 .data = &core_d3_ck_data,
1899};
1900
1901static struct ti_clk_gate gpt11_gate_fck_data = {
1902 .parent = "sys_ck",
1903 .bit_shift = 12,
1904 .reg = 0xa00,
1905 .module = TI_CLKM_CM,
1906};
1907
1908static const char *gpt11_mux_fck_parents[] = {
1909 "omap_32k_fck",
1910 "sys_ck",
1911};
1912
1913static struct ti_clk_mux gpt11_mux_fck_data = {
1914 .bit_shift = 7,
1915 .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
1916 .reg = 0xa40,
1917 .module = TI_CLKM_CM,
1918 .parents = gpt11_mux_fck_parents,
1919};
1920
1921static struct ti_clk_composite gpt11_fck_data = {
1922 .mux = &gpt11_mux_fck_data,
1923 .gate = &gpt11_gate_fck_data,
1924};
1925
1926static struct ti_clk gpt11_fck = {
1927 .name = "gpt11_fck",
1928 .type = TI_CLK_COMPOSITE,
1929 .data = &gpt11_fck_data,
1930};
1931
1932static struct ti_clk_fixed_factor core_d6_ck_data = {
1933 .parent = "core_ck",
1934 .div = 6,
1935 .mult = 1,
1936};
1937
1938static struct ti_clk core_d6_ck = {
1939 .name = "core_d6_ck",
1940 .type = TI_CLK_FIXED_FACTOR,
1941 .data = &core_d6_ck_data,
1942};
1943
1944static struct ti_clk_gate uart4_fck_am35xx_data = {
1945 .parent = "core_48m_fck",
1946 .bit_shift = 23,
1947 .reg = 0xa00,
1948 .module = TI_CLKM_CM,
1949 .flags = CLKF_WAIT,
1950};
1951
1952static struct ti_clk uart4_fck_am35xx = {
1953 .name = "uart4_fck_am35xx",
1954 .clkdm_name = "core_l4_clkdm",
1955 .type = TI_CLK_GATE,
1956 .data = &uart4_fck_am35xx_data,
1957};
1958
1959static struct ti_clk_gate dpll3_m3x2_ck_data = {
1960 .parent = "dpll3_m3x2_mul_ck",
1961 .bit_shift = 0xc,
1962 .reg = 0xd00,
1963 .module = TI_CLKM_CM,
1964 .flags = CLKF_SET_BIT_TO_DISABLE,
1965};
1966
1967static struct ti_clk dpll3_m3x2_ck = {
1968 .name = "dpll3_m3x2_ck",
1969 .type = TI_CLK_GATE,
1970 .data = &dpll3_m3x2_ck_data,
1971};
1972
1973static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
1974 .parent = "dpll3_m3x2_ck",
1975 .div = 1,
1976 .mult = 1,
1977};
1978
1979static struct ti_clk emu_core_alwon_ck = {
1980 .name = "emu_core_alwon_ck",
1981 .type = TI_CLK_FIXED_FACTOR,
1982 .data = &emu_core_alwon_ck_data,
1983};
1984
1985static struct ti_clk_divider dpll4_m6_ck_data = {
1986 .parent = "dpll4_ck",
1987 .bit_shift = 24,
1988 .max_div = 63,
1989 .reg = 0x1140,
1990 .module = TI_CLKM_CM,
1991 .flags = CLKF_INDEX_STARTS_AT_ONE,
1992};
1993
1994static struct ti_clk dpll4_m6_ck = {
1995 .name = "dpll4_m6_ck",
1996 .type = TI_CLK_DIVIDER,
1997 .data = &dpll4_m6_ck_data,
1998};
1999
2000static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
2001 .parent = "dpll4_m6_ck",
2002 .div = 1,
2003 .mult = 2,
2004};
2005
2006static struct ti_clk dpll4_m6x2_mul_ck = {
2007 .name = "dpll4_m6x2_mul_ck",
2008 .type = TI_CLK_FIXED_FACTOR,
2009 .data = &dpll4_m6x2_mul_ck_data,
2010};
2011
2012static struct ti_clk_gate dpll4_m6x2_ck_data = {
2013 .parent = "dpll4_m6x2_mul_ck",
2014 .bit_shift = 0x1f,
2015 .reg = 0xd00,
2016 .module = TI_CLKM_CM,
2017 .flags = CLKF_SET_BIT_TO_DISABLE,
2018};
2019
2020static struct ti_clk dpll4_m6x2_ck = {
2021 .name = "dpll4_m6x2_ck",
2022 .type = TI_CLK_GATE,
2023 .data = &dpll4_m6x2_ck_data,
2024};
2025
2026static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
2027 .parent = "dpll4_m6x2_ck",
2028 .div = 1,
2029 .mult = 1,
2030};
2031
2032static struct ti_clk emu_per_alwon_ck = {
2033 .name = "emu_per_alwon_ck",
2034 .type = TI_CLK_FIXED_FACTOR,
2035 .data = &emu_per_alwon_ck_data,
2036};
2037
2038static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
2039 .parent = "mpu_ck",
2040 .div = 1,
2041 .mult = 1,
2042};
2043
2044static struct ti_clk emu_mpu_alwon_ck = {
2045 .name = "emu_mpu_alwon_ck",
2046 .type = TI_CLK_FIXED_FACTOR,
2047 .data = &emu_mpu_alwon_ck_data,
2048};
2049
2050static const char *emu_src_mux_ck_parents[] = {
2051 "sys_ck",
2052 "emu_core_alwon_ck",
2053 "emu_per_alwon_ck",
2054 "emu_mpu_alwon_ck",
2055};
2056
2057static struct ti_clk_mux emu_src_mux_ck_data = {
2058 .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
2059 .reg = 0x1140,
2060 .module = TI_CLKM_CM,
2061 .parents = emu_src_mux_ck_parents,
2062};
2063
2064static struct ti_clk emu_src_mux_ck = {
2065 .name = "emu_src_mux_ck",
2066 .type = TI_CLK_MUX,
2067 .data = &emu_src_mux_ck_data,
2068};
2069
2070static struct ti_clk_gate emu_src_ck_data = {
2071 .parent = "emu_src_mux_ck",
2072 .flags = CLKF_CLKDM,
2073};
2074
2075static struct ti_clk emu_src_ck = {
2076 .name = "emu_src_ck",
2077 .clkdm_name = "emu_clkdm",
2078 .type = TI_CLK_GATE,
2079 .data = &emu_src_ck_data,
2080};
2081
2082static struct ti_clk_divider atclk_fck_data = {
2083 .parent = "emu_src_ck",
2084 .bit_shift = 4,
2085 .max_div = 3,
2086 .reg = 0x1140,
2087 .module = TI_CLKM_CM,
2088 .flags = CLKF_INDEX_STARTS_AT_ONE,
2089};
2090
2091static struct ti_clk atclk_fck = {
2092 .name = "atclk_fck",
2093 .type = TI_CLK_DIVIDER,
2094 .data = &atclk_fck_data,
2095};
2096
2097static struct ti_clk_gate ipss_ick_data = {
2098 .parent = "core_l3_ick",
2099 .bit_shift = 4,
2100 .reg = 0xa10,
2101 .module = TI_CLKM_CM,
2102 .flags = CLKF_AM35XX | CLKF_INTERFACE,
2103};
2104
2105static struct ti_clk ipss_ick = {
2106 .name = "ipss_ick",
2107 .clkdm_name = "core_l3_clkdm",
2108 .type = TI_CLK_GATE,
2109 .data = &ipss_ick_data,
2110};
2111
2112static struct ti_clk_gate emac_ick_data = {
2113 .parent = "ipss_ick",
2114 .bit_shift = 1,
2115 .reg = 0x59c,
2116 .module = TI_CLKM_SCRM,
2117 .flags = CLKF_AM35XX,
2118};
2119
2120static struct ti_clk emac_ick = {
2121 .name = "emac_ick",
2122 .clkdm_name = "core_l3_clkdm",
2123 .type = TI_CLK_GATE,
2124 .data = &emac_ick_data,
2125};
2126
2127static struct ti_clk_gate vpfe_ick_data = {
2128 .parent = "ipss_ick",
2129 .bit_shift = 2,
2130 .reg = 0x59c,
2131 .module = TI_CLKM_SCRM,
2132 .flags = CLKF_AM35XX,
2133};
2134
2135static struct ti_clk vpfe_ick = {
2136 .name = "vpfe_ick",
2137 .clkdm_name = "core_l3_clkdm",
2138 .type = TI_CLK_GATE,
2139 .data = &vpfe_ick_data,
2140};
2141
2142static const char *dpll2_ck_parents[] = {
2143 "sys_ck",
2144 "dpll2_fck",
2145};
2146
2147static struct ti_clk_dpll dpll2_ck_data = {
2148 .num_parents = ARRAY_SIZE(dpll2_ck_parents),
2149 .control_reg = 0x4,
2150 .idlest_reg = 0x24,
2151 .mult_div1_reg = 0x40,
2152 .autoidle_reg = 0x34,
2153 .module = TI_CLKM_CM,
2154 .parents = dpll2_ck_parents,
2155 .freqsel_mask = 0xf0,
2156 .modes = 0xa2,
2157 .div1_mask = 0x7f,
2158 .idlest_mask = 0x1,
2159 .auto_recal_bit = 0x3,
2160 .max_divider = 0x80,
2161 .min_divider = 0x1,
2162 .recal_en_bit = 0x8,
2163 .max_multiplier = 0x7ff,
2164 .enable_mask = 0x7,
2165 .mult_mask = 0x7ff00,
2166 .recal_st_bit = 0x8,
2167 .autoidle_mask = 0x7,
2168};
2169
2170static struct ti_clk dpll2_ck = {
2171 .name = "dpll2_ck",
2172 .clkdm_name = "dpll2_clkdm",
2173 .type = TI_CLK_DPLL,
2174 .data = &dpll2_ck_data,
2175};
2176
2177static struct ti_clk_divider dpll2_m2_ck_data = {
2178 .parent = "dpll2_ck",
2179 .max_div = 31,
2180 .reg = 0x44,
2181 .module = TI_CLKM_CM,
2182 .flags = CLKF_INDEX_STARTS_AT_ONE,
2183};
2184
2185static struct ti_clk dpll2_m2_ck = {
2186 .name = "dpll2_m2_ck",
2187 .type = TI_CLK_DIVIDER,
2188 .data = &dpll2_m2_ck_data,
2189};
2190
2191static const char *mcbsp4_mux_fck_parents[] = {
2192 "per_96m_fck",
2193 "mcbsp_clks",
2194};
2195
2196static struct ti_clk_mux mcbsp4_mux_fck_data = {
2197 .bit_shift = 2,
2198 .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
2199 .reg = 0x2d8,
2200 .module = TI_CLKM_SCRM,
2201 .parents = mcbsp4_mux_fck_parents,
2202};
2203
2204static const char *mcbsp1_mux_fck_parents[] = {
2205 "core_96m_fck",
2206 "mcbsp_clks",
2207};
2208
2209static struct ti_clk_mux mcbsp1_mux_fck_data = {
2210 .bit_shift = 2,
2211 .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
2212 .reg = 0x274,
2213 .module = TI_CLKM_SCRM,
2214 .parents = mcbsp1_mux_fck_parents,
2215};
2216
2217static struct ti_clk_gate gpt8_gate_fck_data = {
2218 .parent = "sys_ck",
2219 .bit_shift = 9,
2220 .reg = 0x1000,
2221 .module = TI_CLKM_CM,
2222};
2223
2224static struct ti_clk_gate gpt8_ick_data = {
2225 .parent = "per_l4_ick",
2226 .bit_shift = 9,
2227 .reg = 0x1010,
2228 .module = TI_CLKM_CM,
2229 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2230};
2231
2232static struct ti_clk gpt8_ick = {
2233 .name = "gpt8_ick",
2234 .clkdm_name = "per_clkdm",
2235 .type = TI_CLK_GATE,
2236 .data = &gpt8_ick_data,
2237};
2238
2239static const char *gpt10_mux_fck_parents[] = {
2240 "omap_32k_fck",
2241 "sys_ck",
2242};
2243
2244static struct ti_clk_mux gpt10_mux_fck_data = {
2245 .bit_shift = 6,
2246 .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
2247 .reg = 0xa40,
2248 .module = TI_CLKM_CM,
2249 .parents = gpt10_mux_fck_parents,
2250};
2251
2252static struct ti_clk_gate mmchs3_ick_data = {
2253 .parent = "core_l4_ick",
2254 .bit_shift = 30,
2255 .reg = 0xa10,
2256 .module = TI_CLKM_CM,
2257 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2258};
2259
2260static struct ti_clk mmchs3_ick = {
2261 .name = "mmchs3_ick",
2262 .clkdm_name = "core_l4_clkdm",
2263 .type = TI_CLK_GATE,
2264 .data = &mmchs3_ick_data,
2265};
2266
2267static struct ti_clk_gate gpio3_ick_data = {
2268 .parent = "per_l4_ick",
2269 .bit_shift = 14,
2270 .reg = 0x1010,
2271 .module = TI_CLKM_CM,
2272 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2273};
2274
2275static struct ti_clk gpio3_ick = {
2276 .name = "gpio3_ick",
2277 .clkdm_name = "per_clkdm",
2278 .type = TI_CLK_GATE,
2279 .data = &gpio3_ick_data,
2280};
2281
2282static const char *traceclk_src_fck_parents[] = {
2283 "sys_ck",
2284 "emu_core_alwon_ck",
2285 "emu_per_alwon_ck",
2286 "emu_mpu_alwon_ck",
2287};
2288
2289static struct ti_clk_mux traceclk_src_fck_data = {
2290 .bit_shift = 2,
2291 .num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
2292 .reg = 0x1140,
2293 .module = TI_CLKM_CM,
2294 .parents = traceclk_src_fck_parents,
2295};
2296
2297static struct ti_clk traceclk_src_fck = {
2298 .name = "traceclk_src_fck",
2299 .type = TI_CLK_MUX,
2300 .data = &traceclk_src_fck_data,
2301};
2302
2303static struct ti_clk_divider traceclk_fck_data = {
2304 .parent = "traceclk_src_fck",
2305 .bit_shift = 11,
2306 .max_div = 7,
2307 .reg = 0x1140,
2308 .module = TI_CLKM_CM,
2309 .flags = CLKF_INDEX_STARTS_AT_ONE,
2310};
2311
2312static struct ti_clk traceclk_fck = {
2313 .name = "traceclk_fck",
2314 .type = TI_CLK_DIVIDER,
2315 .data = &traceclk_fck_data,
2316};
2317
2318static struct ti_clk_gate mcbsp5_gate_fck_data = {
2319 .parent = "mcbsp_clks",
2320 .bit_shift = 10,
2321 .reg = 0xa00,
2322 .module = TI_CLKM_CM,
2323};
2324
2325static struct ti_clk_gate sad2d_ick_data = {
2326 .parent = "l3_ick",
2327 .bit_shift = 3,
2328 .reg = 0xa10,
2329 .module = TI_CLKM_CM,
2330 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2331};
2332
2333static struct ti_clk sad2d_ick = {
2334 .name = "sad2d_ick",
2335 .clkdm_name = "d2d_clkdm",
2336 .type = TI_CLK_GATE,
2337 .data = &sad2d_ick_data,
2338};
2339
2340static const char *gpt1_mux_fck_parents[] = {
2341 "omap_32k_fck",
2342 "sys_ck",
2343};
2344
2345static struct ti_clk_mux gpt1_mux_fck_data = {
2346 .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
2347 .reg = 0xc40,
2348 .module = TI_CLKM_CM,
2349 .parents = gpt1_mux_fck_parents,
2350};
2351
2352static struct ti_clk_gate hecc_ck_data = {
2353 .parent = "sys_ck",
2354 .bit_shift = 3,
2355 .reg = 0x59c,
2356 .module = TI_CLKM_SCRM,
2357 .flags = CLKF_AM35XX,
2358};
2359
2360static struct ti_clk hecc_ck = {
2361 .name = "hecc_ck",
2362 .clkdm_name = "core_l3_clkdm",
2363 .type = TI_CLK_GATE,
2364 .data = &hecc_ck_data,
2365};
2366
2367static struct ti_clk_gate gpt1_gate_fck_data = {
2368 .parent = "sys_ck",
2369 .bit_shift = 0,
2370 .reg = 0xc00,
2371 .module = TI_CLKM_CM,
2372};
2373
2374static struct ti_clk_composite gpt1_fck_data = {
2375 .mux = &gpt1_mux_fck_data,
2376 .gate = &gpt1_gate_fck_data,
2377};
2378
2379static struct ti_clk gpt1_fck = {
2380 .name = "gpt1_fck",
2381 .type = TI_CLK_COMPOSITE,
2382 .data = &gpt1_fck_data,
2383};
2384
2385static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
2386 .parent = "dpll4_m2x2_mul_ck",
2387 .bit_shift = 0x1b,
2388 .reg = 0xd00,
2389 .module = TI_CLKM_CM,
2390 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2391};
2392
2393static struct ti_clk dpll4_m2x2_ck_omap36xx = {
2394 .name = "dpll4_m2x2_ck",
2395 .type = TI_CLK_GATE,
2396 .data = &dpll4_m2x2_ck_omap36xx_data,
2397 .patch = &dpll4_m2x2_ck,
2398};
2399
2400static struct ti_clk_divider gfx_l3_fck_data = {
2401 .parent = "l3_ick",
2402 .max_div = 7,
2403 .reg = 0xb40,
2404 .module = TI_CLKM_CM,
2405 .flags = CLKF_INDEX_STARTS_AT_ONE,
2406};
2407
2408static struct ti_clk gfx_l3_fck = {
2409 .name = "gfx_l3_fck",
2410 .type = TI_CLK_DIVIDER,
2411 .data = &gfx_l3_fck_data,
2412};
2413
2414static struct ti_clk_gate gfx_cg1_ck_data = {
2415 .parent = "gfx_l3_fck",
2416 .bit_shift = 1,
2417 .reg = 0xb00,
2418 .module = TI_CLKM_CM,
2419 .flags = CLKF_WAIT,
2420};
2421
2422static struct ti_clk gfx_cg1_ck = {
2423 .name = "gfx_cg1_ck",
2424 .clkdm_name = "gfx_3430es1_clkdm",
2425 .type = TI_CLK_GATE,
2426 .data = &gfx_cg1_ck_data,
2427};
2428
2429static struct ti_clk_gate mailboxes_ick_data = {
2430 .parent = "core_l4_ick",
2431 .bit_shift = 7,
2432 .reg = 0xa10,
2433 .module = TI_CLKM_CM,
2434 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2435};
2436
2437static struct ti_clk mailboxes_ick = {
2438 .name = "mailboxes_ick",
2439 .clkdm_name = "core_l4_clkdm",
2440 .type = TI_CLK_GATE,
2441 .data = &mailboxes_ick_data,
2442};
2443
2444static struct ti_clk_gate sha11_ick_data = {
2445 .parent = "security_l4_ick2",
2446 .bit_shift = 1,
2447 .reg = 0xa14,
2448 .module = TI_CLKM_CM,
2449 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2450};
2451
2452static struct ti_clk sha11_ick = {
2453 .name = "sha11_ick",
2454 .type = TI_CLK_GATE,
2455 .data = &sha11_ick_data,
2456};
2457
2458static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
2459 .parent = "ipss_ick",
2460 .bit_shift = 0,
2461 .reg = 0x59c,
2462 .module = TI_CLKM_SCRM,
2463 .flags = CLKF_AM35XX,
2464};
2465
2466static struct ti_clk hsotgusb_ick_am35xx = {
2467 .name = "hsotgusb_ick_am35xx",
2468 .clkdm_name = "core_l3_clkdm",
2469 .type = TI_CLK_GATE,
2470 .data = &hsotgusb_ick_am35xx_data,
2471};
2472
2473static struct ti_clk_gate mmchs3_fck_data = {
2474 .parent = "core_96m_fck",
2475 .bit_shift = 30,
2476 .reg = 0xa00,
2477 .module = TI_CLKM_CM,
2478 .flags = CLKF_WAIT,
2479};
2480
2481static struct ti_clk mmchs3_fck = {
2482 .name = "mmchs3_fck",
2483 .clkdm_name = "core_l4_clkdm",
2484 .type = TI_CLK_GATE,
2485 .data = &mmchs3_fck_data,
2486};
2487
2488static struct ti_clk_divider pclk_fck_data = {
2489 .parent = "emu_src_ck",
2490 .bit_shift = 8,
2491 .max_div = 7,
2492 .reg = 0x1140,
2493 .module = TI_CLKM_CM,
2494 .flags = CLKF_INDEX_STARTS_AT_ONE,
2495};
2496
2497static struct ti_clk pclk_fck = {
2498 .name = "pclk_fck",
2499 .type = TI_CLK_DIVIDER,
2500 .data = &pclk_fck_data,
2501};
2502
2503static const char *dpll4_ck_omap36xx_parents[] = {
2504 "sys_ck",
2505 "sys_ck",
2506};
2507
2508static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
2509 .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
2510 .control_reg = 0xd00,
2511 .idlest_reg = 0xd20,
2512 .mult_div1_reg = 0xd44,
2513 .autoidle_reg = 0xd30,
2514 .module = TI_CLKM_CM,
2515 .parents = dpll4_ck_omap36xx_parents,
2516 .modes = 0x82,
2517 .div1_mask = 0x7f,
2518 .idlest_mask = 0x2,
2519 .auto_recal_bit = 0x13,
2520 .max_divider = 0x80,
2521 .min_divider = 0x1,
2522 .recal_en_bit = 0x6,
2523 .max_multiplier = 0xfff,
2524 .enable_mask = 0x70000,
2525 .mult_mask = 0xfff00,
2526 .recal_st_bit = 0x6,
2527 .autoidle_mask = 0x38,
2528 .sddiv_mask = 0xff000000,
2529 .dco_mask = 0xe00000,
2530 .flags = CLKF_PER | CLKF_J_TYPE,
2531};
2532
2533static struct ti_clk dpll4_ck_omap36xx = {
2534 .name = "dpll4_ck",
2535 .type = TI_CLK_DPLL,
2536 .data = &dpll4_ck_omap36xx_data,
2537 .patch = &dpll4_ck,
2538};
2539
2540static struct ti_clk_gate uart3_fck_data = {
2541 .parent = "per_48m_fck",
2542 .bit_shift = 11,
2543 .reg = 0x1000,
2544 .module = TI_CLKM_CM,
2545 .flags = CLKF_WAIT,
2546};
2547
2548static struct ti_clk uart3_fck = {
2549 .name = "uart3_fck",
2550 .clkdm_name = "per_clkdm",
2551 .type = TI_CLK_GATE,
2552 .data = &uart3_fck_data,
2553};
2554
2555static struct ti_clk_fixed_factor wkup_32k_fck_data = {
2556 .parent = "omap_32k_fck",
2557 .div = 1,
2558 .mult = 1,
2559};
2560
2561static struct ti_clk wkup_32k_fck = {
2562 .name = "wkup_32k_fck",
2563 .type = TI_CLK_FIXED_FACTOR,
2564 .data = &wkup_32k_fck_data,
2565};
2566
2567static struct ti_clk_gate sys_clkout1_data = {
2568 .parent = "osc_sys_ck",
2569 .bit_shift = 7,
2570 .reg = 0xd70,
2571 .module = TI_CLKM_PRM,
2572};
2573
2574static struct ti_clk sys_clkout1 = {
2575 .name = "sys_clkout1",
2576 .type = TI_CLK_GATE,
2577 .data = &sys_clkout1_data,
2578};
2579
2580static struct ti_clk_fixed_factor gpmc_fck_data = {
2581 .parent = "core_l3_ick",
2582 .div = 1,
2583 .mult = 1,
2584};
2585
2586static struct ti_clk gpmc_fck = {
2587 .name = "gpmc_fck",
2588 .type = TI_CLK_FIXED_FACTOR,
2589 .data = &gpmc_fck_data,
2590};
2591
2592static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
2593 .parent = "dpll5_m2_ck",
2594 .div = 20,
2595 .mult = 1,
2596};
2597
2598static struct ti_clk dpll5_m2_d20_ck = {
2599 .name = "dpll5_m2_d20_ck",
2600 .type = TI_CLK_FIXED_FACTOR,
2601 .data = &dpll5_m2_d20_ck_data,
2602};
2603
2604static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
2605 .parent = "dpll4_m5x2_mul_ck",
2606 .bit_shift = 0x1e,
2607 .reg = 0xd00,
2608 .module = TI_CLKM_CM,
2609 .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
2610};
2611
2612static struct ti_clk dpll4_m5x2_ck_omap36xx = {
2613 .name = "dpll4_m5x2_ck",
2614 .type = TI_CLK_GATE,
2615 .data = &dpll4_m5x2_ck_omap36xx_data,
2616 .patch = &dpll4_m5x2_ck,
2617};
2618
2619static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
2620 .parent = "corex2_fck",
2621 .bit_shift = 0,
2622 .reg = 0xa00,
2623 .module = TI_CLKM_CM,
2624 .flags = CLKF_NO_WAIT,
2625};
2626
2627static struct ti_clk_gate uart1_ick_data = {
2628 .parent = "core_l4_ick",
2629 .bit_shift = 13,
2630 .reg = 0xa10,
2631 .module = TI_CLKM_CM,
2632 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2633};
2634
2635static struct ti_clk uart1_ick = {
2636 .name = "uart1_ick",
2637 .clkdm_name = "core_l4_clkdm",
2638 .type = TI_CLK_GATE,
2639 .data = &uart1_ick_data,
2640};
2641
2642static struct ti_clk_gate iva2_ck_data = {
2643 .parent = "dpll2_m2_ck",
2644 .bit_shift = 0,
2645 .reg = 0x0,
2646 .module = TI_CLKM_CM,
2647 .flags = CLKF_WAIT,
2648};
2649
2650static struct ti_clk iva2_ck = {
2651 .name = "iva2_ck",
2652 .clkdm_name = "iva2_clkdm",
2653 .type = TI_CLK_GATE,
2654 .data = &iva2_ck_data,
2655};
2656
2657static struct ti_clk_gate pka_ick_data = {
2658 .parent = "security_l3_ick",
2659 .bit_shift = 4,
2660 .reg = 0xa14,
2661 .module = TI_CLKM_CM,
2662 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2663};
2664
2665static struct ti_clk pka_ick = {
2666 .name = "pka_ick",
2667 .type = TI_CLK_GATE,
2668 .data = &pka_ick_data,
2669};
2670
2671static struct ti_clk_gate gpt12_ick_data = {
2672 .parent = "wkup_l4_ick",
2673 .bit_shift = 1,
2674 .reg = 0xc10,
2675 .module = TI_CLKM_CM,
2676 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2677};
2678
2679static struct ti_clk gpt12_ick = {
2680 .name = "gpt12_ick",
2681 .clkdm_name = "wkup_clkdm",
2682 .type = TI_CLK_GATE,
2683 .data = &gpt12_ick_data,
2684};
2685
2686static const char *mcbsp5_mux_fck_parents[] = {
2687 "core_96m_fck",
2688 "mcbsp_clks",
2689};
2690
2691static struct ti_clk_mux mcbsp5_mux_fck_data = {
2692 .bit_shift = 4,
2693 .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
2694 .reg = 0x2d8,
2695 .module = TI_CLKM_SCRM,
2696 .parents = mcbsp5_mux_fck_parents,
2697};
2698
2699static struct ti_clk_composite mcbsp5_fck_data = {
2700 .mux = &mcbsp5_mux_fck_data,
2701 .gate = &mcbsp5_gate_fck_data,
2702};
2703
2704static struct ti_clk mcbsp5_fck = {
2705 .name = "mcbsp5_fck",
2706 .type = TI_CLK_COMPOSITE,
2707 .data = &mcbsp5_fck_data,
2708};
2709
2710static struct ti_clk_gate usbhost_48m_fck_data = {
2711 .parent = "omap_48m_fck",
2712 .bit_shift = 0,
2713 .reg = 0x1400,
2714 .module = TI_CLKM_CM,
2715 .flags = CLKF_DSS,
2716};
2717
2718static struct ti_clk usbhost_48m_fck = {
2719 .name = "usbhost_48m_fck",
2720 .clkdm_name = "usbhost_clkdm",
2721 .type = TI_CLK_GATE,
2722 .data = &usbhost_48m_fck_data,
2723};
2724
2725static struct ti_clk_gate des1_ick_data = {
2726 .parent = "security_l4_ick2",
2727 .bit_shift = 0,
2728 .reg = 0xa14,
2729 .module = TI_CLKM_CM,
2730 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
2731};
2732
2733static struct ti_clk des1_ick = {
2734 .name = "des1_ick",
2735 .type = TI_CLK_GATE,
2736 .data = &des1_ick_data,
2737};
2738
2739static struct ti_clk_gate sgx_gate_fck_data = {
2740 .parent = "core_ck",
2741 .bit_shift = 1,
2742 .reg = 0xb00,
2743 .module = TI_CLKM_CM,
2744};
2745
2746static struct ti_clk_fixed_factor core_d4_ck_data = {
2747 .parent = "core_ck",
2748 .div = 4,
2749 .mult = 1,
2750};
2751
2752static struct ti_clk core_d4_ck = {
2753 .name = "core_d4_ck",
2754 .type = TI_CLK_FIXED_FACTOR,
2755 .data = &core_d4_ck_data,
2756};
2757
2758static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
2759 .parent = "dpll4_m2x2_ck",
2760 .div = 1,
2761 .mult = 1,
2762};
2763
2764static struct ti_clk omap_192m_alwon_fck = {
2765 .name = "omap_192m_alwon_fck",
2766 .type = TI_CLK_FIXED_FACTOR,
2767 .data = &omap_192m_alwon_fck_data,
2768};
2769
2770static struct ti_clk_fixed_factor core_d2_ck_data = {
2771 .parent = "core_ck",
2772 .div = 2,
2773 .mult = 1,
2774};
2775
2776static struct ti_clk core_d2_ck = {
2777 .name = "core_d2_ck",
2778 .type = TI_CLK_FIXED_FACTOR,
2779 .data = &core_d2_ck_data,
2780};
2781
2782static struct ti_clk_fixed_factor corex2_d3_fck_data = {
2783 .parent = "corex2_fck",
2784 .div = 3,
2785 .mult = 1,
2786};
2787
2788static struct ti_clk corex2_d3_fck = {
2789 .name = "corex2_d3_fck",
2790 .type = TI_CLK_FIXED_FACTOR,
2791 .data = &corex2_d3_fck_data,
2792};
2793
2794static struct ti_clk_fixed_factor corex2_d5_fck_data = {
2795 .parent = "corex2_fck",
2796 .div = 5,
2797 .mult = 1,
2798};
2799
2800static struct ti_clk corex2_d5_fck = {
2801 .name = "corex2_d5_fck",
2802 .type = TI_CLK_FIXED_FACTOR,
2803 .data = &corex2_d5_fck_data,
2804};
2805
2806static const char *sgx_mux_fck_parents[] = {
2807 "core_d3_ck",
2808 "core_d4_ck",
2809 "core_d6_ck",
2810 "cm_96m_fck",
2811 "omap_192m_alwon_fck",
2812 "core_d2_ck",
2813 "corex2_d3_fck",
2814 "corex2_d5_fck",
2815};
2816
2817static struct ti_clk_mux sgx_mux_fck_data = {
2818 .num_parents = ARRAY_SIZE(sgx_mux_fck_parents),
2819 .reg = 0xb40,
2820 .module = TI_CLKM_CM,
2821 .parents = sgx_mux_fck_parents,
2822};
2823
2824static struct ti_clk_composite sgx_fck_data = {
2825 .mux = &sgx_mux_fck_data,
2826 .gate = &sgx_gate_fck_data,
2827};
2828
2829static struct ti_clk sgx_fck = {
2830 .name = "sgx_fck",
2831 .type = TI_CLK_COMPOSITE,
2832 .data = &sgx_fck_data,
2833};
2834
2835static struct ti_clk_gate mcspi1_fck_data = {
2836 .parent = "core_48m_fck",
2837 .bit_shift = 18,
2838 .reg = 0xa00,
2839 .module = TI_CLKM_CM,
2840 .flags = CLKF_WAIT,
2841};
2842
2843static struct ti_clk mcspi1_fck = {
2844 .name = "mcspi1_fck",
2845 .clkdm_name = "core_l4_clkdm",
2846 .type = TI_CLK_GATE,
2847 .data = &mcspi1_fck_data,
2848};
2849
2850static struct ti_clk_gate mmchs2_fck_data = {
2851 .parent = "core_96m_fck",
2852 .bit_shift = 25,
2853 .reg = 0xa00,
2854 .module = TI_CLKM_CM,
2855 .flags = CLKF_WAIT,
2856};
2857
2858static struct ti_clk mmchs2_fck = {
2859 .name = "mmchs2_fck",
2860 .clkdm_name = "core_l4_clkdm",
2861 .type = TI_CLK_GATE,
2862 .data = &mmchs2_fck_data,
2863};
2864
2865static struct ti_clk_gate mcspi2_fck_data = {
2866 .parent = "core_48m_fck",
2867 .bit_shift = 19,
2868 .reg = 0xa00,
2869 .module = TI_CLKM_CM,
2870 .flags = CLKF_WAIT,
2871};
2872
2873static struct ti_clk mcspi2_fck = {
2874 .name = "mcspi2_fck",
2875 .clkdm_name = "core_l4_clkdm",
2876 .type = TI_CLK_GATE,
2877 .data = &mcspi2_fck_data,
2878};
2879
2880static struct ti_clk_gate vpfe_fck_data = {
2881 .parent = "pclk_ck",
2882 .bit_shift = 10,
2883 .reg = 0x59c,
2884 .module = TI_CLKM_SCRM,
2885};
2886
2887static struct ti_clk vpfe_fck = {
2888 .name = "vpfe_fck",
2889 .type = TI_CLK_GATE,
2890 .data = &vpfe_fck_data,
2891};
2892
2893static struct ti_clk_gate gpt4_gate_fck_data = {
2894 .parent = "sys_ck",
2895 .bit_shift = 5,
2896 .reg = 0x1000,
2897 .module = TI_CLKM_CM,
2898};
2899
2900static struct ti_clk_gate mcbsp1_gate_fck_data = {
2901 .parent = "mcbsp_clks",
2902 .bit_shift = 9,
2903 .reg = 0xa00,
2904 .module = TI_CLKM_CM,
2905};
2906
2907static struct ti_clk_gate gpt5_gate_fck_data = {
2908 .parent = "sys_ck",
2909 .bit_shift = 6,
2910 .reg = 0x1000,
2911 .module = TI_CLKM_CM,
2912};
2913
2914static const char *gpt5_mux_fck_parents[] = {
2915 "omap_32k_fck",
2916 "sys_ck",
2917};
2918
2919static struct ti_clk_mux gpt5_mux_fck_data = {
2920 .bit_shift = 3,
2921 .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents),
2922 .reg = 0x1040,
2923 .module = TI_CLKM_CM,
2924 .parents = gpt5_mux_fck_parents,
2925};
2926
2927static struct ti_clk_composite gpt5_fck_data = {
2928 .mux = &gpt5_mux_fck_data,
2929 .gate = &gpt5_gate_fck_data,
2930};
2931
2932static struct ti_clk gpt5_fck = {
2933 .name = "gpt5_fck",
2934 .type = TI_CLK_COMPOSITE,
2935 .data = &gpt5_fck_data,
2936};
2937
2938static struct ti_clk_gate ts_fck_data = {
2939 .parent = "omap_32k_fck",
2940 .bit_shift = 1,
2941 .reg = 0xa08,
2942 .module = TI_CLKM_CM,
2943};
2944
2945static struct ti_clk ts_fck = {
2946 .name = "ts_fck",
2947 .clkdm_name = "core_l4_clkdm",
2948 .type = TI_CLK_GATE,
2949 .data = &ts_fck_data,
2950};
2951
2952static struct ti_clk_fixed_factor wdt1_fck_data = {
2953 .parent = "secure_32k_fck",
2954 .div = 1,
2955 .mult = 1,
2956};
2957
2958static struct ti_clk wdt1_fck = {
2959 .name = "wdt1_fck",
2960 .type = TI_CLK_FIXED_FACTOR,
2961 .data = &wdt1_fck_data,
2962};
2963
2964static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = {
2965 .parent = "dpll4_m6x2_mul_ck",
2966 .bit_shift = 0x1f,
2967 .reg = 0xd00,
2968 .module = TI_CLKM_CM,
2969 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
2970};
2971
2972static struct ti_clk dpll4_m6x2_ck_omap36xx = {
2973 .name = "dpll4_m6x2_ck",
2974 .type = TI_CLK_GATE,
2975 .data = &dpll4_m6x2_ck_omap36xx_data,
2976 .patch = &dpll4_m6x2_ck,
2977};
2978
2979static const char *gpt4_mux_fck_parents[] = {
2980 "omap_32k_fck",
2981 "sys_ck",
2982};
2983
2984static struct ti_clk_mux gpt4_mux_fck_data = {
2985 .bit_shift = 2,
2986 .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents),
2987 .reg = 0x1040,
2988 .module = TI_CLKM_CM,
2989 .parents = gpt4_mux_fck_parents,
2990};
2991
2992static struct ti_clk_gate usbhost_ick_data = {
2993 .parent = "l4_ick",
2994 .bit_shift = 0,
2995 .reg = 0x1410,
2996 .module = TI_CLKM_CM,
2997 .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
2998};
2999
3000static struct ti_clk usbhost_ick = {
3001 .name = "usbhost_ick",
3002 .clkdm_name = "usbhost_clkdm",
3003 .type = TI_CLK_GATE,
3004 .data = &usbhost_ick_data,
3005};
3006
3007static struct ti_clk_gate mcbsp2_ick_data = {
3008 .parent = "per_l4_ick",
3009 .bit_shift = 0,
3010 .reg = 0x1010,
3011 .module = TI_CLKM_CM,
3012 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3013};
3014
3015static struct ti_clk mcbsp2_ick = {
3016 .name = "mcbsp2_ick",
3017 .clkdm_name = "per_clkdm",
3018 .type = TI_CLK_GATE,
3019 .data = &mcbsp2_ick_data,
3020};
3021
3022static struct ti_clk_gate omapctrl_ick_data = {
3023 .parent = "core_l4_ick",
3024 .bit_shift = 6,
3025 .reg = 0xa10,
3026 .module = TI_CLKM_CM,
3027 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3028};
3029
3030static struct ti_clk omapctrl_ick = {
3031 .name = "omapctrl_ick",
3032 .clkdm_name = "core_l4_clkdm",
3033 .type = TI_CLK_GATE,
3034 .data = &omapctrl_ick_data,
3035};
3036
3037static struct ti_clk_fixed_factor omap_96m_d4_fck_data = {
3038 .parent = "omap_96m_fck",
3039 .div = 4,
3040 .mult = 1,
3041};
3042
3043static struct ti_clk omap_96m_d4_fck = {
3044 .name = "omap_96m_d4_fck",
3045 .type = TI_CLK_FIXED_FACTOR,
3046 .data = &omap_96m_d4_fck_data,
3047};
3048
3049static struct ti_clk_gate gpt6_ick_data = {
3050 .parent = "per_l4_ick",
3051 .bit_shift = 7,
3052 .reg = 0x1010,
3053 .module = TI_CLKM_CM,
3054 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3055};
3056
3057static struct ti_clk gpt6_ick = {
3058 .name = "gpt6_ick",
3059 .clkdm_name = "per_clkdm",
3060 .type = TI_CLK_GATE,
3061 .data = &gpt6_ick_data,
3062};
3063
3064static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = {
3065 .parent = "dpll3_m3x2_mul_ck",
3066 .bit_shift = 0xc,
3067 .reg = 0xd00,
3068 .module = TI_CLKM_CM,
3069 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3070};
3071
3072static struct ti_clk dpll3_m3x2_ck_omap36xx = {
3073 .name = "dpll3_m3x2_ck",
3074 .type = TI_CLK_GATE,
3075 .data = &dpll3_m3x2_ck_omap36xx_data,
3076 .patch = &dpll3_m3x2_ck,
3077};
3078
3079static struct ti_clk_gate i2c3_ick_data = {
3080 .parent = "core_l4_ick",
3081 .bit_shift = 17,
3082 .reg = 0xa10,
3083 .module = TI_CLKM_CM,
3084 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3085};
3086
3087static struct ti_clk i2c3_ick = {
3088 .name = "i2c3_ick",
3089 .clkdm_name = "core_l4_clkdm",
3090 .type = TI_CLK_GATE,
3091 .data = &i2c3_ick_data,
3092};
3093
3094static struct ti_clk_gate gpio6_ick_data = {
3095 .parent = "per_l4_ick",
3096 .bit_shift = 17,
3097 .reg = 0x1010,
3098 .module = TI_CLKM_CM,
3099 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3100};
3101
3102static struct ti_clk gpio6_ick = {
3103 .name = "gpio6_ick",
3104 .clkdm_name = "per_clkdm",
3105 .type = TI_CLK_GATE,
3106 .data = &gpio6_ick_data,
3107};
3108
3109static struct ti_clk_gate mspro_ick_data = {
3110 .parent = "core_l4_ick",
3111 .bit_shift = 23,
3112 .reg = 0xa10,
3113 .module = TI_CLKM_CM,
3114 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3115};
3116
3117static struct ti_clk mspro_ick = {
3118 .name = "mspro_ick",
3119 .clkdm_name = "core_l4_clkdm",
3120 .type = TI_CLK_GATE,
3121 .data = &mspro_ick_data,
3122};
3123
3124static struct ti_clk_composite mcbsp1_fck_data = {
3125 .mux = &mcbsp1_mux_fck_data,
3126 .gate = &mcbsp1_gate_fck_data,
3127};
3128
3129static struct ti_clk mcbsp1_fck = {
3130 .name = "mcbsp1_fck",
3131 .type = TI_CLK_COMPOSITE,
3132 .data = &mcbsp1_fck_data,
3133};
3134
3135static struct ti_clk_gate gpt3_gate_fck_data = {
3136 .parent = "sys_ck",
3137 .bit_shift = 4,
3138 .reg = 0x1000,
3139 .module = TI_CLKM_CM,
3140};
3141
3142static struct ti_clk_fixed rmii_ck_data = {
3143 .frequency = 50000000,
3144};
3145
3146static struct ti_clk rmii_ck = {
3147 .name = "rmii_ck",
3148 .type = TI_CLK_FIXED,
3149 .data = &rmii_ck_data,
3150};
3151
3152static struct ti_clk_gate gpt6_gate_fck_data = {
3153 .parent = "sys_ck",
3154 .bit_shift = 7,
3155 .reg = 0x1000,
3156 .module = TI_CLKM_CM,
3157};
3158
3159static struct ti_clk_composite gpt6_fck_data = {
3160 .mux = &gpt6_mux_fck_data,
3161 .gate = &gpt6_gate_fck_data,
3162};
3163
3164static struct ti_clk gpt6_fck = {
3165 .name = "gpt6_fck",
3166 .type = TI_CLK_COMPOSITE,
3167 .data = &gpt6_fck_data,
3168};
3169
3170static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = {
3171 .parent = "dpll5_m2_ck",
3172 .div = 4,
3173 .mult = 1,
3174};
3175
3176static struct ti_clk dpll5_m2_d4_ck = {
3177 .name = "dpll5_m2_d4_ck",
3178 .type = TI_CLK_FIXED_FACTOR,
3179 .data = &dpll5_m2_d4_ck_data,
3180};
3181
3182static struct ti_clk_fixed_factor sys_d2_ck_data = {
3183 .parent = "sys_ck",
3184 .div = 2,
3185 .mult = 1,
3186};
3187
3188static struct ti_clk sys_d2_ck = {
3189 .name = "sys_d2_ck",
3190 .type = TI_CLK_FIXED_FACTOR,
3191 .data = &sys_d2_ck_data,
3192};
3193
3194static struct ti_clk_fixed_factor omap_96m_d2_fck_data = {
3195 .parent = "omap_96m_fck",
3196 .div = 2,
3197 .mult = 1,
3198};
3199
3200static struct ti_clk omap_96m_d2_fck = {
3201 .name = "omap_96m_d2_fck",
3202 .type = TI_CLK_FIXED_FACTOR,
3203 .data = &omap_96m_d2_fck_data,
3204};
3205
3206static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = {
3207 .parent = "dpll5_m2_ck",
3208 .div = 8,
3209 .mult = 1,
3210};
3211
3212static struct ti_clk dpll5_m2_d8_ck = {
3213 .name = "dpll5_m2_d8_ck",
3214 .type = TI_CLK_FIXED_FACTOR,
3215 .data = &dpll5_m2_d8_ck_data,
3216};
3217
3218static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = {
3219 .parent = "dpll5_m2_ck",
3220 .div = 16,
3221 .mult = 1,
3222};
3223
3224static struct ti_clk dpll5_m2_d16_ck = {
3225 .name = "dpll5_m2_d16_ck",
3226 .type = TI_CLK_FIXED_FACTOR,
3227 .data = &dpll5_m2_d16_ck_data,
3228};
3229
3230static const char *usim_mux_fck_parents[] = {
3231 "sys_ck",
3232 "sys_d2_ck",
3233 "omap_96m_d2_fck",
3234 "omap_96m_d4_fck",
3235 "omap_96m_d8_fck",
3236 "omap_96m_d10_fck",
3237 "dpll5_m2_d4_ck",
3238 "dpll5_m2_d8_ck",
3239 "dpll5_m2_d16_ck",
3240 "dpll5_m2_d20_ck",
3241};
3242
3243static struct ti_clk_mux usim_mux_fck_data = {
3244 .bit_shift = 3,
3245 .num_parents = ARRAY_SIZE(usim_mux_fck_parents),
3246 .reg = 0xc40,
3247 .module = TI_CLKM_CM,
3248 .parents = usim_mux_fck_parents,
3249 .flags = CLKF_INDEX_STARTS_AT_ONE,
3250};
3251
3252static struct ti_clk_composite usim_fck_data = {
3253 .mux = &usim_mux_fck_data,
3254 .gate = &usim_gate_fck_data,
3255};
3256
3257static struct ti_clk usim_fck = {
3258 .name = "usim_fck",
3259 .type = TI_CLK_COMPOSITE,
3260 .data = &usim_fck_data,
3261};
3262
3263static int ssi_ssr_div_fck_3430es2_divs[] = {
3264 0,
3265 1,
3266 2,
3267 3,
3268 4,
3269 0,
3270 6,
3271 0,
3272 8,
3273};
3274
3275static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = {
3276 .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs),
3277 .parent = "corex2_fck",
3278 .bit_shift = 8,
3279 .dividers = ssi_ssr_div_fck_3430es2_divs,
3280 .reg = 0xa40,
3281 .module = TI_CLKM_CM,
3282};
3283
3284static struct ti_clk_composite ssi_ssr_fck_3430es2_data = {
3285 .gate = &ssi_ssr_gate_fck_3430es2_data,
3286 .divider = &ssi_ssr_div_fck_3430es2_data,
3287};
3288
3289static struct ti_clk ssi_ssr_fck_3430es2 = {
3290 .name = "ssi_ssr_fck",
3291 .type = TI_CLK_COMPOSITE,
3292 .data = &ssi_ssr_fck_3430es2_data,
3293};
3294
3295static struct ti_clk_gate dss1_alwon_fck_3430es1_data = {
3296 .parent = "dpll4_m4x2_ck",
3297 .bit_shift = 0,
3298 .reg = 0xe00,
3299 .module = TI_CLKM_CM,
3300 .flags = CLKF_SET_RATE_PARENT,
3301};
3302
3303static struct ti_clk dss1_alwon_fck_3430es1 = {
3304 .name = "dss1_alwon_fck",
3305 .clkdm_name = "dss_clkdm",
3306 .type = TI_CLK_GATE,
3307 .data = &dss1_alwon_fck_3430es1_data,
3308};
3309
3310static struct ti_clk_gate gpt3_ick_data = {
3311 .parent = "per_l4_ick",
3312 .bit_shift = 4,
3313 .reg = 0x1010,
3314 .module = TI_CLKM_CM,
3315 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3316};
3317
3318static struct ti_clk gpt3_ick = {
3319 .name = "gpt3_ick",
3320 .clkdm_name = "per_clkdm",
3321 .type = TI_CLK_GATE,
3322 .data = &gpt3_ick_data,
3323};
3324
3325static struct ti_clk_fixed_factor omap_12m_fck_data = {
3326 .parent = "omap_48m_fck",
3327 .div = 4,
3328 .mult = 1,
3329};
3330
3331static struct ti_clk omap_12m_fck = {
3332 .name = "omap_12m_fck",
3333 .type = TI_CLK_FIXED_FACTOR,
3334 .data = &omap_12m_fck_data,
3335};
3336
3337static struct ti_clk_fixed_factor core_12m_fck_data = {
3338 .parent = "omap_12m_fck",
3339 .div = 1,
3340 .mult = 1,
3341};
3342
3343static struct ti_clk core_12m_fck = {
3344 .name = "core_12m_fck",
3345 .type = TI_CLK_FIXED_FACTOR,
3346 .data = &core_12m_fck_data,
3347};
3348
3349static struct ti_clk_gate hdq_fck_data = {
3350 .parent = "core_12m_fck",
3351 .bit_shift = 22,
3352 .reg = 0xa00,
3353 .module = TI_CLKM_CM,
3354 .flags = CLKF_WAIT,
3355};
3356
3357static struct ti_clk hdq_fck = {
3358 .name = "hdq_fck",
3359 .clkdm_name = "core_l4_clkdm",
3360 .type = TI_CLK_GATE,
3361 .data = &hdq_fck_data,
3362};
3363
3364static struct ti_clk_gate usbtll_fck_data = {
3365 .parent = "dpll5_m2_ck",
3366 .bit_shift = 2,
3367 .reg = 0xa08,
3368 .module = TI_CLKM_CM,
3369 .flags = CLKF_WAIT,
3370};
3371
3372static struct ti_clk usbtll_fck = {
3373 .name = "usbtll_fck",
3374 .clkdm_name = "core_l4_clkdm",
3375 .type = TI_CLK_GATE,
3376 .data = &usbtll_fck_data,
3377};
3378
3379static struct ti_clk_gate hsotgusb_fck_am35xx_data = {
3380 .parent = "sys_ck",
3381 .bit_shift = 8,
3382 .reg = 0x59c,
3383 .module = TI_CLKM_SCRM,
3384};
3385
3386static struct ti_clk hsotgusb_fck_am35xx = {
3387 .name = "hsotgusb_fck_am35xx",
3388 .clkdm_name = "core_l3_clkdm",
3389 .type = TI_CLK_GATE,
3390 .data = &hsotgusb_fck_am35xx_data,
3391};
3392
3393static struct ti_clk_gate hsotgusb_ick_3430es2_data = {
3394 .parent = "core_l3_ick",
3395 .bit_shift = 4,
3396 .reg = 0xa10,
3397 .module = TI_CLKM_CM,
3398 .flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE,
3399};
3400
3401static struct ti_clk hsotgusb_ick_3430es2 = {
3402 .name = "hsotgusb_ick_3430es2",
3403 .clkdm_name = "core_l3_clkdm",
3404 .type = TI_CLK_GATE,
3405 .data = &hsotgusb_ick_3430es2_data,
3406};
3407
3408static struct ti_clk_gate gfx_l3_ck_data = {
3409 .parent = "l3_ick",
3410 .bit_shift = 0,
3411 .reg = 0xb10,
3412 .module = TI_CLKM_CM,
3413 .flags = CLKF_WAIT,
3414};
3415
3416static struct ti_clk gfx_l3_ck = {
3417 .name = "gfx_l3_ck",
3418 .clkdm_name = "gfx_3430es1_clkdm",
3419 .type = TI_CLK_GATE,
3420 .data = &gfx_l3_ck_data,
3421};
3422
3423static struct ti_clk_fixed_factor gfx_l3_ick_data = {
3424 .parent = "gfx_l3_ck",
3425 .div = 1,
3426 .mult = 1,
3427};
3428
3429static struct ti_clk gfx_l3_ick = {
3430 .name = "gfx_l3_ick",
3431 .type = TI_CLK_FIXED_FACTOR,
3432 .data = &gfx_l3_ick_data,
3433};
3434
3435static struct ti_clk_gate mcbsp1_ick_data = {
3436 .parent = "core_l4_ick",
3437 .bit_shift = 9,
3438 .reg = 0xa10,
3439 .module = TI_CLKM_CM,
3440 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3441};
3442
3443static struct ti_clk mcbsp1_ick = {
3444 .name = "mcbsp1_ick",
3445 .clkdm_name = "core_l4_clkdm",
3446 .type = TI_CLK_GATE,
3447 .data = &mcbsp1_ick_data,
3448};
3449
3450static struct ti_clk_fixed_factor gpt12_fck_data = {
3451 .parent = "secure_32k_fck",
3452 .div = 1,
3453 .mult = 1,
3454};
3455
3456static struct ti_clk gpt12_fck = {
3457 .name = "gpt12_fck",
3458 .type = TI_CLK_FIXED_FACTOR,
3459 .data = &gpt12_fck_data,
3460};
3461
3462static struct ti_clk_gate gfx_cg2_ck_data = {
3463 .parent = "gfx_l3_fck",
3464 .bit_shift = 2,
3465 .reg = 0xb00,
3466 .module = TI_CLKM_CM,
3467 .flags = CLKF_WAIT,
3468};
3469
3470static struct ti_clk gfx_cg2_ck = {
3471 .name = "gfx_cg2_ck",
3472 .clkdm_name = "gfx_3430es1_clkdm",
3473 .type = TI_CLK_GATE,
3474 .data = &gfx_cg2_ck_data,
3475};
3476
3477static struct ti_clk_gate i2c2_ick_data = {
3478 .parent = "core_l4_ick",
3479 .bit_shift = 16,
3480 .reg = 0xa10,
3481 .module = TI_CLKM_CM,
3482 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3483};
3484
3485static struct ti_clk i2c2_ick = {
3486 .name = "i2c2_ick",
3487 .clkdm_name = "core_l4_clkdm",
3488 .type = TI_CLK_GATE,
3489 .data = &i2c2_ick_data,
3490};
3491
3492static struct ti_clk_gate gpio4_dbck_data = {
3493 .parent = "per_32k_alwon_fck",
3494 .bit_shift = 15,
3495 .reg = 0x1000,
3496 .module = TI_CLKM_CM,
3497};
3498
3499static struct ti_clk gpio4_dbck = {
3500 .name = "gpio4_dbck",
3501 .clkdm_name = "per_clkdm",
3502 .type = TI_CLK_GATE,
3503 .data = &gpio4_dbck_data,
3504};
3505
3506static struct ti_clk_gate i2c3_fck_data = {
3507 .parent = "core_96m_fck",
3508 .bit_shift = 17,
3509 .reg = 0xa00,
3510 .module = TI_CLKM_CM,
3511 .flags = CLKF_WAIT,
3512};
3513
3514static struct ti_clk i2c3_fck = {
3515 .name = "i2c3_fck",
3516 .clkdm_name = "core_l4_clkdm",
3517 .type = TI_CLK_GATE,
3518 .data = &i2c3_fck_data,
3519};
3520
3521static struct ti_clk_composite gpt3_fck_data = {
3522 .mux = &gpt3_mux_fck_data,
3523 .gate = &gpt3_gate_fck_data,
3524};
3525
3526static struct ti_clk gpt3_fck = {
3527 .name = "gpt3_fck",
3528 .type = TI_CLK_COMPOSITE,
3529 .data = &gpt3_fck_data,
3530};
3531
3532static struct ti_clk_gate i2c1_ick_data = {
3533 .parent = "core_l4_ick",
3534 .bit_shift = 15,
3535 .reg = 0xa10,
3536 .module = TI_CLKM_CM,
3537 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3538};
3539
3540static struct ti_clk i2c1_ick = {
3541 .name = "i2c1_ick",
3542 .clkdm_name = "core_l4_clkdm",
3543 .type = TI_CLK_GATE,
3544 .data = &i2c1_ick_data,
3545};
3546
3547static struct ti_clk_gate omap_32ksync_ick_data = {
3548 .parent = "wkup_l4_ick",
3549 .bit_shift = 2,
3550 .reg = 0xc10,
3551 .module = TI_CLKM_CM,
3552 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3553};
3554
3555static struct ti_clk omap_32ksync_ick = {
3556 .name = "omap_32ksync_ick",
3557 .clkdm_name = "wkup_clkdm",
3558 .type = TI_CLK_GATE,
3559 .data = &omap_32ksync_ick_data,
3560};
3561
3562static struct ti_clk_gate aes2_ick_data = {
3563 .parent = "core_l4_ick",
3564 .bit_shift = 28,
3565 .reg = 0xa10,
3566 .module = TI_CLKM_CM,
3567 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3568};
3569
3570static struct ti_clk aes2_ick = {
3571 .name = "aes2_ick",
3572 .clkdm_name = "core_l4_clkdm",
3573 .type = TI_CLK_GATE,
3574 .data = &aes2_ick_data,
3575};
3576
3577static const char *gpt8_mux_fck_parents[] = {
3578 "omap_32k_fck",
3579 "sys_ck",
3580};
3581
3582static struct ti_clk_mux gpt8_mux_fck_data = {
3583 .bit_shift = 6,
3584 .num_parents = ARRAY_SIZE(gpt8_mux_fck_parents),
3585 .reg = 0x1040,
3586 .module = TI_CLKM_CM,
3587 .parents = gpt8_mux_fck_parents,
3588};
3589
3590static struct ti_clk_composite gpt8_fck_data = {
3591 .mux = &gpt8_mux_fck_data,
3592 .gate = &gpt8_gate_fck_data,
3593};
3594
3595static struct ti_clk gpt8_fck = {
3596 .name = "gpt8_fck",
3597 .type = TI_CLK_COMPOSITE,
3598 .data = &gpt8_fck_data,
3599};
3600
3601static struct ti_clk_gate mcbsp4_gate_fck_data = {
3602 .parent = "mcbsp_clks",
3603 .bit_shift = 2,
3604 .reg = 0x1000,
3605 .module = TI_CLKM_CM,
3606};
3607
3608static struct ti_clk_composite mcbsp4_fck_data = {
3609 .mux = &mcbsp4_mux_fck_data,
3610 .gate = &mcbsp4_gate_fck_data,
3611};
3612
3613static struct ti_clk mcbsp4_fck = {
3614 .name = "mcbsp4_fck",
3615 .type = TI_CLK_COMPOSITE,
3616 .data = &mcbsp4_fck_data,
3617};
3618
3619static struct ti_clk_gate gpio2_dbck_data = {
3620 .parent = "per_32k_alwon_fck",
3621 .bit_shift = 13,
3622 .reg = 0x1000,
3623 .module = TI_CLKM_CM,
3624};
3625
3626static struct ti_clk gpio2_dbck = {
3627 .name = "gpio2_dbck",
3628 .clkdm_name = "per_clkdm",
3629 .type = TI_CLK_GATE,
3630 .data = &gpio2_dbck_data,
3631};
3632
3633static struct ti_clk_gate usbtll_ick_data = {
3634 .parent = "core_l4_ick",
3635 .bit_shift = 2,
3636 .reg = 0xa18,
3637 .module = TI_CLKM_CM,
3638 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3639};
3640
3641static struct ti_clk usbtll_ick = {
3642 .name = "usbtll_ick",
3643 .clkdm_name = "core_l4_clkdm",
3644 .type = TI_CLK_GATE,
3645 .data = &usbtll_ick_data,
3646};
3647
3648static struct ti_clk_gate mcspi4_ick_data = {
3649 .parent = "core_l4_ick",
3650 .bit_shift = 21,
3651 .reg = 0xa10,
3652 .module = TI_CLKM_CM,
3653 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3654};
3655
3656static struct ti_clk mcspi4_ick = {
3657 .name = "mcspi4_ick",
3658 .clkdm_name = "core_l4_clkdm",
3659 .type = TI_CLK_GATE,
3660 .data = &mcspi4_ick_data,
3661};
3662
3663static struct ti_clk_gate dss_96m_fck_data = {
3664 .parent = "omap_96m_fck",
3665 .bit_shift = 2,
3666 .reg = 0xe00,
3667 .module = TI_CLKM_CM,
3668};
3669
3670static struct ti_clk dss_96m_fck = {
3671 .name = "dss_96m_fck",
3672 .clkdm_name = "dss_clkdm",
3673 .type = TI_CLK_GATE,
3674 .data = &dss_96m_fck_data,
3675};
3676
3677static struct ti_clk_divider rm_ick_data = {
3678 .parent = "l4_ick",
3679 .bit_shift = 1,
3680 .max_div = 3,
3681 .reg = 0xc40,
3682 .module = TI_CLKM_CM,
3683 .flags = CLKF_INDEX_STARTS_AT_ONE,
3684};
3685
3686static struct ti_clk rm_ick = {
3687 .name = "rm_ick",
3688 .type = TI_CLK_DIVIDER,
3689 .data = &rm_ick_data,
3690};
3691
3692static struct ti_clk_gate hdq_ick_data = {
3693 .parent = "core_l4_ick",
3694 .bit_shift = 22,
3695 .reg = 0xa10,
3696 .module = TI_CLKM_CM,
3697 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3698};
3699
3700static struct ti_clk hdq_ick = {
3701 .name = "hdq_ick",
3702 .clkdm_name = "core_l4_clkdm",
3703 .type = TI_CLK_GATE,
3704 .data = &hdq_ick_data,
3705};
3706
3707static struct ti_clk_fixed_factor dpll3_x2_ck_data = {
3708 .parent = "dpll3_ck",
3709 .div = 1,
3710 .mult = 2,
3711};
3712
3713static struct ti_clk dpll3_x2_ck = {
3714 .name = "dpll3_x2_ck",
3715 .type = TI_CLK_FIXED_FACTOR,
3716 .data = &dpll3_x2_ck_data,
3717};
3718
3719static struct ti_clk_gate mad2d_ick_data = {
3720 .parent = "l3_ick",
3721 .bit_shift = 3,
3722 .reg = 0xa18,
3723 .module = TI_CLKM_CM,
3724 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3725};
3726
3727static struct ti_clk mad2d_ick = {
3728 .name = "mad2d_ick",
3729 .clkdm_name = "d2d_clkdm",
3730 .type = TI_CLK_GATE,
3731 .data = &mad2d_ick_data,
3732};
3733
3734static struct ti_clk_gate fshostusb_fck_data = {
3735 .parent = "core_48m_fck",
3736 .bit_shift = 5,
3737 .reg = 0xa00,
3738 .module = TI_CLKM_CM,
3739 .flags = CLKF_WAIT,
3740};
3741
3742static struct ti_clk fshostusb_fck = {
3743 .name = "fshostusb_fck",
3744 .clkdm_name = "core_l4_clkdm",
3745 .type = TI_CLK_GATE,
3746 .data = &fshostusb_fck_data,
3747};
3748
3749static struct ti_clk_gate sr1_fck_data = {
3750 .parent = "sys_ck",
3751 .bit_shift = 6,
3752 .reg = 0xc00,
3753 .module = TI_CLKM_CM,
3754 .flags = CLKF_WAIT,
3755};
3756
3757static struct ti_clk sr1_fck = {
3758 .name = "sr1_fck",
3759 .clkdm_name = "wkup_clkdm",
3760 .type = TI_CLK_GATE,
3761 .data = &sr1_fck_data,
3762};
3763
3764static struct ti_clk_gate des2_ick_data = {
3765 .parent = "core_l4_ick",
3766 .bit_shift = 26,
3767 .reg = 0xa10,
3768 .module = TI_CLKM_CM,
3769 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3770};
3771
3772static struct ti_clk des2_ick = {
3773 .name = "des2_ick",
3774 .clkdm_name = "core_l4_clkdm",
3775 .type = TI_CLK_GATE,
3776 .data = &des2_ick_data,
3777};
3778
3779static struct ti_clk_gate sdrc_ick_data = {
3780 .parent = "core_l3_ick",
3781 .bit_shift = 1,
3782 .reg = 0xa10,
3783 .module = TI_CLKM_CM,
3784 .flags = CLKF_WAIT,
3785};
3786
3787static struct ti_clk sdrc_ick = {
3788 .name = "sdrc_ick",
3789 .clkdm_name = "core_l3_clkdm",
3790 .type = TI_CLK_GATE,
3791 .data = &sdrc_ick_data,
3792};
3793
3794static struct ti_clk_composite gpt4_fck_data = {
3795 .mux = &gpt4_mux_fck_data,
3796 .gate = &gpt4_gate_fck_data,
3797};
3798
3799static struct ti_clk gpt4_fck = {
3800 .name = "gpt4_fck",
3801 .type = TI_CLK_COMPOSITE,
3802 .data = &gpt4_fck_data,
3803};
3804
3805static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = {
3806 .parent = "dpll4_m3x2_mul_ck",
3807 .bit_shift = 0x1c,
3808 .reg = 0xd00,
3809 .module = TI_CLKM_CM,
3810 .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
3811};
3812
3813static struct ti_clk dpll4_m3x2_ck_omap36xx = {
3814 .name = "dpll4_m3x2_ck",
3815 .type = TI_CLK_GATE,
3816 .data = &dpll4_m3x2_ck_omap36xx_data,
3817 .patch = &dpll4_m3x2_ck,
3818};
3819
3820static struct ti_clk_gate cpefuse_fck_data = {
3821 .parent = "sys_ck",
3822 .bit_shift = 0,
3823 .reg = 0xa08,
3824 .module = TI_CLKM_CM,
3825};
3826
3827static struct ti_clk cpefuse_fck = {
3828 .name = "cpefuse_fck",
3829 .clkdm_name = "core_l4_clkdm",
3830 .type = TI_CLK_GATE,
3831 .data = &cpefuse_fck_data,
3832};
3833
3834static struct ti_clk_gate mcspi3_ick_data = {
3835 .parent = "core_l4_ick",
3836 .bit_shift = 20,
3837 .reg = 0xa10,
3838 .module = TI_CLKM_CM,
3839 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3840};
3841
3842static struct ti_clk mcspi3_ick = {
3843 .name = "mcspi3_ick",
3844 .clkdm_name = "core_l4_clkdm",
3845 .type = TI_CLK_GATE,
3846 .data = &mcspi3_ick_data,
3847};
3848
3849static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = {
3850 .parent = "ssi_ssr_fck",
3851 .div = 2,
3852 .mult = 1,
3853};
3854
3855static struct ti_clk ssi_sst_fck_3430es2 = {
3856 .name = "ssi_sst_fck",
3857 .type = TI_CLK_FIXED_FACTOR,
3858 .data = &ssi_sst_fck_3430es2_data,
3859};
3860
3861static struct ti_clk_gate gpio1_dbck_data = {
3862 .parent = "wkup_32k_fck",
3863 .bit_shift = 3,
3864 .reg = 0xc00,
3865 .module = TI_CLKM_CM,
3866};
3867
3868static struct ti_clk gpio1_dbck = {
3869 .name = "gpio1_dbck",
3870 .clkdm_name = "wkup_clkdm",
3871 .type = TI_CLK_GATE,
3872 .data = &gpio1_dbck_data,
3873};
3874
3875static struct ti_clk_gate gpt4_ick_data = {
3876 .parent = "per_l4_ick",
3877 .bit_shift = 5,
3878 .reg = 0x1010,
3879 .module = TI_CLKM_CM,
3880 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3881};
3882
3883static struct ti_clk gpt4_ick = {
3884 .name = "gpt4_ick",
3885 .clkdm_name = "per_clkdm",
3886 .type = TI_CLK_GATE,
3887 .data = &gpt4_ick_data,
3888};
3889
3890static struct ti_clk_gate gpt2_ick_data = {
3891 .parent = "per_l4_ick",
3892 .bit_shift = 3,
3893 .reg = 0x1010,
3894 .module = TI_CLKM_CM,
3895 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3896};
3897
3898static struct ti_clk gpt2_ick = {
3899 .name = "gpt2_ick",
3900 .clkdm_name = "per_clkdm",
3901 .type = TI_CLK_GATE,
3902 .data = &gpt2_ick_data,
3903};
3904
3905static struct ti_clk_gate mmchs1_fck_data = {
3906 .parent = "core_96m_fck",
3907 .bit_shift = 24,
3908 .reg = 0xa00,
3909 .module = TI_CLKM_CM,
3910 .flags = CLKF_WAIT,
3911};
3912
3913static struct ti_clk mmchs1_fck = {
3914 .name = "mmchs1_fck",
3915 .clkdm_name = "core_l4_clkdm",
3916 .type = TI_CLK_GATE,
3917 .data = &mmchs1_fck_data,
3918};
3919
3920static struct ti_clk_fixed dummy_apb_pclk_data = {
3921 .frequency = 0x0,
3922};
3923
3924static struct ti_clk dummy_apb_pclk = {
3925 .name = "dummy_apb_pclk",
3926 .type = TI_CLK_FIXED,
3927 .data = &dummy_apb_pclk_data,
3928};
3929
3930static struct ti_clk_gate gpio6_dbck_data = {
3931 .parent = "per_32k_alwon_fck",
3932 .bit_shift = 17,
3933 .reg = 0x1000,
3934 .module = TI_CLKM_CM,
3935};
3936
3937static struct ti_clk gpio6_dbck = {
3938 .name = "gpio6_dbck",
3939 .clkdm_name = "per_clkdm",
3940 .type = TI_CLK_GATE,
3941 .data = &gpio6_dbck_data,
3942};
3943
3944static struct ti_clk_gate uart2_ick_data = {
3945 .parent = "core_l4_ick",
3946 .bit_shift = 14,
3947 .reg = 0xa10,
3948 .module = TI_CLKM_CM,
3949 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3950};
3951
3952static struct ti_clk uart2_ick = {
3953 .name = "uart2_ick",
3954 .clkdm_name = "core_l4_clkdm",
3955 .type = TI_CLK_GATE,
3956 .data = &uart2_ick_data,
3957};
3958
3959static struct ti_clk_fixed_factor dpll4_x2_ck_data = {
3960 .parent = "dpll4_ck",
3961 .div = 1,
3962 .mult = 2,
3963};
3964
3965static struct ti_clk dpll4_x2_ck = {
3966 .name = "dpll4_x2_ck",
3967 .type = TI_CLK_FIXED_FACTOR,
3968 .data = &dpll4_x2_ck_data,
3969};
3970
3971static struct ti_clk_gate gpt7_ick_data = {
3972 .parent = "per_l4_ick",
3973 .bit_shift = 8,
3974 .reg = 0x1010,
3975 .module = TI_CLKM_CM,
3976 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
3977};
3978
3979static struct ti_clk gpt7_ick = {
3980 .name = "gpt7_ick",
3981 .clkdm_name = "per_clkdm",
3982 .type = TI_CLK_GATE,
3983 .data = &gpt7_ick_data,
3984};
3985
3986static struct ti_clk_gate dss_tv_fck_data = {
3987 .parent = "omap_54m_fck",
3988 .bit_shift = 2,
3989 .reg = 0xe00,
3990 .module = TI_CLKM_CM,
3991};
3992
3993static struct ti_clk dss_tv_fck = {
3994 .name = "dss_tv_fck",
3995 .clkdm_name = "dss_clkdm",
3996 .type = TI_CLK_GATE,
3997 .data = &dss_tv_fck_data,
3998};
3999
4000static struct ti_clk_gate mcbsp5_ick_data = {
4001 .parent = "core_l4_ick",
4002 .bit_shift = 10,
4003 .reg = 0xa10,
4004 .module = TI_CLKM_CM,
4005 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4006};
4007
4008static struct ti_clk mcbsp5_ick = {
4009 .name = "mcbsp5_ick",
4010 .clkdm_name = "core_l4_clkdm",
4011 .type = TI_CLK_GATE,
4012 .data = &mcbsp5_ick_data,
4013};
4014
4015static struct ti_clk_gate mcspi1_ick_data = {
4016 .parent = "core_l4_ick",
4017 .bit_shift = 18,
4018 .reg = 0xa10,
4019 .module = TI_CLKM_CM,
4020 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4021};
4022
4023static struct ti_clk mcspi1_ick = {
4024 .name = "mcspi1_ick",
4025 .clkdm_name = "core_l4_clkdm",
4026 .type = TI_CLK_GATE,
4027 .data = &mcspi1_ick_data,
4028};
4029
4030static struct ti_clk_gate d2d_26m_fck_data = {
4031 .parent = "sys_ck",
4032 .bit_shift = 3,
4033 .reg = 0xa00,
4034 .module = TI_CLKM_CM,
4035 .flags = CLKF_WAIT,
4036};
4037
4038static struct ti_clk d2d_26m_fck = {
4039 .name = "d2d_26m_fck",
4040 .clkdm_name = "d2d_clkdm",
4041 .type = TI_CLK_GATE,
4042 .data = &d2d_26m_fck_data,
4043};
4044
4045static struct ti_clk_gate wdt3_ick_data = {
4046 .parent = "per_l4_ick",
4047 .bit_shift = 12,
4048 .reg = 0x1010,
4049 .module = TI_CLKM_CM,
4050 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4051};
4052
4053static struct ti_clk wdt3_ick = {
4054 .name = "wdt3_ick",
4055 .clkdm_name = "per_clkdm",
4056 .type = TI_CLK_GATE,
4057 .data = &wdt3_ick_data,
4058};
4059
4060static struct ti_clk_divider pclkx2_fck_data = {
4061 .parent = "emu_src_ck",
4062 .bit_shift = 6,
4063 .max_div = 3,
4064 .reg = 0x1140,
4065 .module = TI_CLKM_CM,
4066 .flags = CLKF_INDEX_STARTS_AT_ONE,
4067};
4068
4069static struct ti_clk pclkx2_fck = {
4070 .name = "pclkx2_fck",
4071 .type = TI_CLK_DIVIDER,
4072 .data = &pclkx2_fck_data,
4073};
4074
4075static struct ti_clk_gate sha12_ick_data = {
4076 .parent = "core_l4_ick",
4077 .bit_shift = 27,
4078 .reg = 0xa10,
4079 .module = TI_CLKM_CM,
4080 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4081};
4082
4083static struct ti_clk sha12_ick = {
4084 .name = "sha12_ick",
4085 .clkdm_name = "core_l4_clkdm",
4086 .type = TI_CLK_GATE,
4087 .data = &sha12_ick_data,
4088};
4089
4090static struct ti_clk_gate emac_fck_data = {
4091 .parent = "rmii_ck",
4092 .bit_shift = 9,
4093 .reg = 0x59c,
4094 .module = TI_CLKM_SCRM,
4095};
4096
4097static struct ti_clk emac_fck = {
4098 .name = "emac_fck",
4099 .type = TI_CLK_GATE,
4100 .data = &emac_fck_data,
4101};
4102
4103static struct ti_clk_composite gpt10_fck_data = {
4104 .mux = &gpt10_mux_fck_data,
4105 .gate = &gpt10_gate_fck_data,
4106};
4107
4108static struct ti_clk gpt10_fck = {
4109 .name = "gpt10_fck",
4110 .type = TI_CLK_COMPOSITE,
4111 .data = &gpt10_fck_data,
4112};
4113
4114static struct ti_clk_gate wdt2_fck_data = {
4115 .parent = "wkup_32k_fck",
4116 .bit_shift = 5,
4117 .reg = 0xc00,
4118 .module = TI_CLKM_CM,
4119 .flags = CLKF_WAIT,
4120};
4121
4122static struct ti_clk wdt2_fck = {
4123 .name = "wdt2_fck",
4124 .clkdm_name = "wkup_clkdm",
4125 .type = TI_CLK_GATE,
4126 .data = &wdt2_fck_data,
4127};
4128
4129static struct ti_clk_gate cam_ick_data = {
4130 .parent = "l4_ick",
4131 .bit_shift = 0,
4132 .reg = 0xf10,
4133 .module = TI_CLKM_CM,
4134 .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
4135};
4136
4137static struct ti_clk cam_ick = {
4138 .name = "cam_ick",
4139 .clkdm_name = "cam_clkdm",
4140 .type = TI_CLK_GATE,
4141 .data = &cam_ick_data,
4142};
4143
4144static struct ti_clk_gate ssi_ick_3430es2_data = {
4145 .parent = "ssi_l4_ick",
4146 .bit_shift = 0,
4147 .reg = 0xa10,
4148 .module = TI_CLKM_CM,
4149 .flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE,
4150};
4151
4152static struct ti_clk ssi_ick_3430es2 = {
4153 .name = "ssi_ick",
4154 .clkdm_name = "core_l4_clkdm",
4155 .type = TI_CLK_GATE,
4156 .data = &ssi_ick_3430es2_data,
4157};
4158
4159static struct ti_clk_gate gpio4_ick_data = {
4160 .parent = "per_l4_ick",
4161 .bit_shift = 15,
4162 .reg = 0x1010,
4163 .module = TI_CLKM_CM,
4164 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4165};
4166
4167static struct ti_clk gpio4_ick = {
4168 .name = "gpio4_ick",
4169 .clkdm_name = "per_clkdm",
4170 .type = TI_CLK_GATE,
4171 .data = &gpio4_ick_data,
4172};
4173
4174static struct ti_clk_gate wdt1_ick_data = {
4175 .parent = "wkup_l4_ick",
4176 .bit_shift = 4,
4177 .reg = 0xc10,
4178 .module = TI_CLKM_CM,
4179 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4180};
4181
4182static struct ti_clk wdt1_ick = {
4183 .name = "wdt1_ick",
4184 .clkdm_name = "wkup_clkdm",
4185 .type = TI_CLK_GATE,
4186 .data = &wdt1_ick_data,
4187};
4188
4189static struct ti_clk_gate rng_ick_data = {
4190 .parent = "security_l4_ick2",
4191 .bit_shift = 2,
4192 .reg = 0xa14,
4193 .module = TI_CLKM_CM,
4194 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4195};
4196
4197static struct ti_clk rng_ick = {
4198 .name = "rng_ick",
4199 .type = TI_CLK_GATE,
4200 .data = &rng_ick_data,
4201};
4202
4203static struct ti_clk_gate icr_ick_data = {
4204 .parent = "core_l4_ick",
4205 .bit_shift = 29,
4206 .reg = 0xa10,
4207 .module = TI_CLKM_CM,
4208 .flags = CLKF_OMAP3 | CLKF_INTERFACE,
4209};
4210
4211static struct ti_clk icr_ick = {
4212 .name = "icr_ick",
4213 .clkdm_name = "core_l4_clkdm",
4214 .type = TI_CLK_GATE,
4215 .data = &icr_ick_data,
4216};
4217
4218static struct ti_clk_gate sgx_ick_data = {
4219 .parent = "l3_ick",
4220 .bit_shift = 0,
4221 .reg = 0xb10,
4222 .module = TI_CLKM_CM,
4223 .flags = CLKF_WAIT,
4224};
4225
4226static struct ti_clk sgx_ick = {
4227 .name = "sgx_ick",
4228 .clkdm_name = "sgx_clkdm",
4229 .type = TI_CLK_GATE,
4230 .data = &sgx_ick_data,
4231};
4232
4233static struct ti_clk_divider sys_clkout2_data = {
4234 .parent = "clkout2_src_ck",
4235 .bit_shift = 3,
4236 .max_div = 64,
4237 .reg = 0xd70,
4238 .module = TI_CLKM_CM,
4239 .flags = CLKF_INDEX_POWER_OF_TWO,
4240};
4241
4242static struct ti_clk sys_clkout2 = {
4243 .name = "sys_clkout2",
4244 .type = TI_CLK_DIVIDER,
4245 .data = &sys_clkout2_data,
4246};
4247
4248static struct ti_clk_alias omap34xx_omap36xx_clks[] = {
4249 CLK(NULL, "security_l4_ick2", &security_l4_ick2),
4250 CLK(NULL, "aes1_ick", &aes1_ick),
4251 CLK("omap_rng", "ick", &rng_ick),
4252 CLK("omap3-rom-rng", "ick", &rng_ick),
4253 CLK(NULL, "sha11_ick", &sha11_ick),
4254 CLK(NULL, "des1_ick", &des1_ick),
4255 CLK(NULL, "cam_mclk", &cam_mclk),
4256 CLK(NULL, "cam_ick", &cam_ick),
4257 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
4258 CLK(NULL, "security_l3_ick", &security_l3_ick),
4259 CLK(NULL, "pka_ick", &pka_ick),
4260 CLK(NULL, "icr_ick", &icr_ick),
4261 CLK(NULL, "des2_ick", &des2_ick),
4262 CLK(NULL, "mspro_ick", &mspro_ick),
4263 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
4264 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
4265 CLK(NULL, "sr1_fck", &sr1_fck),
4266 CLK(NULL, "sr2_fck", &sr2_fck),
4267 CLK(NULL, "sr_l4_ick", &sr_l4_ick),
4268 CLK(NULL, "dpll2_fck", &dpll2_fck),
4269 CLK(NULL, "dpll2_ck", &dpll2_ck),
4270 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
4271 CLK(NULL, "iva2_ck", &iva2_ck),
4272 CLK(NULL, "modem_fck", &modem_fck),
4273 CLK(NULL, "sad2d_ick", &sad2d_ick),
4274 CLK(NULL, "mad2d_ick", &mad2d_ick),
4275 CLK(NULL, "mspro_fck", &mspro_fck),
4276 { NULL },
4277};
4278
4279static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = {
4280 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
4281 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
4282 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
4283 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
4284 CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
4285 CLK(NULL, "sys_d2_ck", &sys_d2_ck),
4286 CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck),
4287 CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck),
4288 CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck),
4289 CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck),
4290 CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck),
4291 CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck),
4292 CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck),
4293 CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck),
4294 CLK(NULL, "usim_fck", &usim_fck),
4295 CLK(NULL, "usim_ick", &usim_ick),
4296 { NULL },
4297};
4298
4299static struct ti_clk_alias omap3xxx_clks[] = {
4300 CLK(NULL, "apb_pclk", &dummy_apb_pclk),
4301 CLK(NULL, "omap_32k_fck", &omap_32k_fck),
4302 CLK(NULL, "virt_12m_ck", &virt_12m_ck),
4303 CLK(NULL, "virt_13m_ck", &virt_13m_ck),
4304 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
4305 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
4306 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
4307 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
4308 CLK(NULL, "osc_sys_ck", &osc_sys_ck),
4309 CLK("twl", "fck", &osc_sys_ck),
4310 CLK(NULL, "sys_ck", &sys_ck),
4311 CLK(NULL, "timer_sys_ck", &sys_ck),
4312 CLK(NULL, "dpll4_ck", &dpll4_ck),
4313 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
4314 CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck),
4315 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
4316 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
4317 CLK(NULL, "dpll3_ck", &dpll3_ck),
4318 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
4319 CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck),
4320 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
4321 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
4322 CLK(NULL, "sys_altclk", &sys_altclk),
4323 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
4324 CLK(NULL, "sys_clkout1", &sys_clkout1),
4325 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
4326 CLK(NULL, "core_ck", &core_ck),
4327 CLK(NULL, "dpll1_fck", &dpll1_fck),
4328 CLK(NULL, "dpll1_ck", &dpll1_ck),
4329 CLK(NULL, "cpufreq_ck", &dpll1_ck),
4330 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
4331 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
4332 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
4333 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
4334 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
4335 CLK(NULL, "cm_96m_fck", &cm_96m_fck),
4336 CLK(NULL, "omap_96m_fck", &omap_96m_fck),
4337 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
4338 CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck),
4339 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
4340 CLK(NULL, "omap_54m_fck", &omap_54m_fck),
4341 CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck),
4342 CLK(NULL, "omap_48m_fck", &omap_48m_fck),
4343 CLK(NULL, "omap_12m_fck", &omap_12m_fck),
4344 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
4345 CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck),
4346 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
4347 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
4348 CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck),
4349 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
4350 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
4351 CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck),
4352 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
4353 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
4354 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
4355 CLK(NULL, "sys_clkout2", &sys_clkout2),
4356 CLK(NULL, "corex2_fck", &corex2_fck),
4357 CLK(NULL, "mpu_ck", &mpu_ck),
4358 CLK(NULL, "arm_fck", &arm_fck),
4359 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
4360 CLK(NULL, "l3_ick", &l3_ick),
4361 CLK(NULL, "l4_ick", &l4_ick),
4362 CLK(NULL, "rm_ick", &rm_ick),
4363 CLK(NULL, "timer_32k_ck", &omap_32k_fck),
4364 CLK(NULL, "gpt10_fck", &gpt10_fck),
4365 CLK(NULL, "gpt11_fck", &gpt11_fck),
4366 CLK(NULL, "core_96m_fck", &core_96m_fck),
4367 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
4368 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
4369 CLK(NULL, "i2c3_fck", &i2c3_fck),
4370 CLK(NULL, "i2c2_fck", &i2c2_fck),
4371 CLK(NULL, "i2c1_fck", &i2c1_fck),
4372 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
4373 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
4374 CLK(NULL, "core_48m_fck", &core_48m_fck),
4375 CLK(NULL, "mcspi4_fck", &mcspi4_fck),
4376 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
4377 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
4378 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
4379 CLK(NULL, "uart2_fck", &uart2_fck),
4380 CLK(NULL, "uart1_fck", &uart1_fck),
4381 CLK(NULL, "core_12m_fck", &core_12m_fck),
4382 CLK("omap_hdq.0", "fck", &hdq_fck),
4383 CLK(NULL, "hdq_fck", &hdq_fck),
4384 CLK(NULL, "core_l3_ick", &core_l3_ick),
4385 CLK(NULL, "sdrc_ick", &sdrc_ick),
4386 CLK(NULL, "gpmc_fck", &gpmc_fck),
4387 CLK(NULL, "core_l4_ick", &core_l4_ick),
4388 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
4389 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
4390 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
4391 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
4392 CLK("omap_hdq.0", "ick", &hdq_ick),
4393 CLK(NULL, "hdq_ick", &hdq_ick),
4394 CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
4395 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
4396 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
4397 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
4398 CLK(NULL, "mcspi4_ick", &mcspi4_ick),
4399 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
4400 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
4401 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
4402 CLK("omap_i2c.3", "ick", &i2c3_ick),
4403 CLK("omap_i2c.2", "ick", &i2c2_ick),
4404 CLK("omap_i2c.1", "ick", &i2c1_ick),
4405 CLK(NULL, "i2c3_ick", &i2c3_ick),
4406 CLK(NULL, "i2c2_ick", &i2c2_ick),
4407 CLK(NULL, "i2c1_ick", &i2c1_ick),
4408 CLK(NULL, "uart2_ick", &uart2_ick),
4409 CLK(NULL, "uart1_ick", &uart1_ick),
4410 CLK(NULL, "gpt11_ick", &gpt11_ick),
4411 CLK(NULL, "gpt10_ick", &gpt10_ick),
4412 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
4413 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
4414 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
4415 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
4416 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
4417 CLK(NULL, "dss_tv_fck", &dss_tv_fck),
4418 CLK(NULL, "dss_96m_fck", &dss_96m_fck),
4419 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
4420 CLK(NULL, "init_60m_fclk", &dummy_ck),
4421 CLK(NULL, "gpt1_fck", &gpt1_fck),
4422 CLK(NULL, "aes2_ick", &aes2_ick),
4423 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
4424 CLK(NULL, "gpio1_dbck", &gpio1_dbck),
4425 CLK(NULL, "sha12_ick", &sha12_ick),
4426 CLK(NULL, "wdt2_fck", &wdt2_fck),
4427 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
4428 CLK("omap_wdt", "ick", &wdt2_ick),
4429 CLK(NULL, "wdt2_ick", &wdt2_ick),
4430 CLK(NULL, "wdt1_ick", &wdt1_ick),
4431 CLK(NULL, "gpio1_ick", &gpio1_ick),
4432 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
4433 CLK(NULL, "gpt12_ick", &gpt12_ick),
4434 CLK(NULL, "gpt1_ick", &gpt1_ick),
4435 CLK(NULL, "per_96m_fck", &per_96m_fck),
4436 CLK(NULL, "per_48m_fck", &per_48m_fck),
4437 CLK(NULL, "uart3_fck", &uart3_fck),
4438 CLK(NULL, "gpt2_fck", &gpt2_fck),
4439 CLK(NULL, "gpt3_fck", &gpt3_fck),
4440 CLK(NULL, "gpt4_fck", &gpt4_fck),
4441 CLK(NULL, "gpt5_fck", &gpt5_fck),
4442 CLK(NULL, "gpt6_fck", &gpt6_fck),
4443 CLK(NULL, "gpt7_fck", &gpt7_fck),
4444 CLK(NULL, "gpt8_fck", &gpt8_fck),
4445 CLK(NULL, "gpt9_fck", &gpt9_fck),
4446 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
4447 CLK(NULL, "gpio6_dbck", &gpio6_dbck),
4448 CLK(NULL, "gpio5_dbck", &gpio5_dbck),
4449 CLK(NULL, "gpio4_dbck", &gpio4_dbck),
4450 CLK(NULL, "gpio3_dbck", &gpio3_dbck),
4451 CLK(NULL, "gpio2_dbck", &gpio2_dbck),
4452 CLK(NULL, "wdt3_fck", &wdt3_fck),
4453 CLK(NULL, "per_l4_ick", &per_l4_ick),
4454 CLK(NULL, "gpio6_ick", &gpio6_ick),
4455 CLK(NULL, "gpio5_ick", &gpio5_ick),
4456 CLK(NULL, "gpio4_ick", &gpio4_ick),
4457 CLK(NULL, "gpio3_ick", &gpio3_ick),
4458 CLK(NULL, "gpio2_ick", &gpio2_ick),
4459 CLK(NULL, "wdt3_ick", &wdt3_ick),
4460 CLK(NULL, "uart3_ick", &uart3_ick),
4461 CLK(NULL, "uart4_ick", &uart4_ick),
4462 CLK(NULL, "gpt9_ick", &gpt9_ick),
4463 CLK(NULL, "gpt8_ick", &gpt8_ick),
4464 CLK(NULL, "gpt7_ick", &gpt7_ick),
4465 CLK(NULL, "gpt6_ick", &gpt6_ick),
4466 CLK(NULL, "gpt5_ick", &gpt5_ick),
4467 CLK(NULL, "gpt4_ick", &gpt4_ick),
4468 CLK(NULL, "gpt3_ick", &gpt3_ick),
4469 CLK(NULL, "gpt2_ick", &gpt2_ick),
4470 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
4471 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
4472 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
4473 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
4474 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
4475 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
4476 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
4477 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
4478 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
4479 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4480 CLK("etb", "emu_src_ck", &emu_src_ck),
4481 CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
4482 CLK(NULL, "emu_src_ck", &emu_src_ck),
4483 CLK(NULL, "pclk_fck", &pclk_fck),
4484 CLK(NULL, "pclkx2_fck", &pclkx2_fck),
4485 CLK(NULL, "atclk_fck", &atclk_fck),
4486 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
4487 CLK(NULL, "traceclk_fck", &traceclk_fck),
4488 CLK(NULL, "secure_32k_fck", &secure_32k_fck),
4489 CLK(NULL, "gpt12_fck", &gpt12_fck),
4490 CLK(NULL, "wdt1_fck", &wdt1_fck),
4491 { NULL },
4492};
4493
4494static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = {
4495 CLK(NULL, "dpll5_ck", &dpll5_ck),
4496 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
4497 CLK(NULL, "core_d3_ck", &core_d3_ck),
4498 CLK(NULL, "core_d4_ck", &core_d4_ck),
4499 CLK(NULL, "core_d6_ck", &core_d6_ck),
4500 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
4501 CLK(NULL, "core_d2_ck", &core_d2_ck),
4502 CLK(NULL, "corex2_d3_fck", &corex2_d3_fck),
4503 CLK(NULL, "corex2_d5_fck", &corex2_d5_fck),
4504 CLK(NULL, "sgx_fck", &sgx_fck),
4505 CLK(NULL, "sgx_ick", &sgx_ick),
4506 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
4507 CLK(NULL, "ts_fck", &ts_fck),
4508 CLK(NULL, "usbtll_fck", &usbtll_fck),
4509 CLK(NULL, "usbtll_ick", &usbtll_ick),
4510 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
4511 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
4512 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
4513 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
4514 CLK("omapdss_dss", "ick", &dss_ick_3430es2),
4515 CLK(NULL, "dss_ick", &dss_ick_3430es2),
4516 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
4517 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
4518 CLK(NULL, "usbhost_ick", &usbhost_ick),
4519 { NULL },
4520};
4521
4522static struct ti_clk_alias omap3430es1_clks[] = {
4523 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
4524 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
4525 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
4526 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
4527 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
4528 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
4529 CLK(NULL, "fshostusb_fck", &fshostusb_fck),
4530 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
4531 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
4532 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
4533 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
4534 CLK(NULL, "fac_ick", &fac_ick),
4535 CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
4536 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
4537 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
4538 CLK("omapdss_dss", "ick", &dss_ick_3430es1),
4539 CLK(NULL, "dss_ick", &dss_ick_3430es1),
4540 { NULL },
4541};
4542
4543static struct ti_clk_alias omap36xx_clks[] = {
4544 CLK(NULL, "uart4_fck", &uart4_fck),
4545 { NULL },
4546};
4547
4548static struct ti_clk_alias am35xx_clks[] = {
4549 CLK(NULL, "ipss_ick", &ipss_ick),
4550 CLK(NULL, "rmii_ck", &rmii_ck),
4551 CLK(NULL, "pclk_ck", &pclk_ck),
4552 CLK(NULL, "emac_ick", &emac_ick),
4553 CLK(NULL, "emac_fck", &emac_fck),
4554 CLK("davinci_emac.0", NULL, &emac_ick),
4555 CLK("davinci_mdio.0", NULL, &emac_fck),
4556 CLK("vpfe-capture", "master", &vpfe_ick),
4557 CLK("vpfe-capture", "slave", &vpfe_fck),
4558 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
4559 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
4560 CLK(NULL, "hecc_ck", &hecc_ck),
4561 CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
4562 CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
4563 { NULL },
4564};
4565
4566static struct ti_clk *omap36xx_clk_patches[] = {
4567 &dpll4_m3x2_ck_omap36xx,
4568 &dpll3_m3x2_ck_omap36xx,
4569 &dpll4_m6x2_ck_omap36xx,
4570 &dpll4_m2x2_ck_omap36xx,
4571 &dpll4_m5x2_ck_omap36xx,
4572 &dpll4_ck_omap36xx,
4573 NULL,
4574};
4575
4576static const char *enable_init_clks[] = {
4577 "sdrc_ick",
4578 "gpmc_fck",
4579 "omapctrl_ick",
4580};
4581
4582static void __init omap3_clk_legacy_common_init(void)
4583{
4584 omap2_clk_disable_autoidle_all();
4585
4586 omap2_clk_enable_init_clocks(enable_init_clks,
4587 ARRAY_SIZE(enable_init_clks));
4588
4589 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
4590 (clk_get_rate(osc_sys_ck.clk) / 1000000),
4591 (clk_get_rate(osc_sys_ck.clk) / 100000) % 10,
4592 (clk_get_rate(core_ck.clk) / 1000000),
4593 (clk_get_rate(arm_fck.clk) / 1000000));
4594}
4595
4596int __init omap3430es1_clk_legacy_init(void)
4597{
4598 int r;
4599
4600 r = ti_clk_register_legacy_clks(omap3430es1_clks);
4601 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4602 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4603
4604 omap3_clk_legacy_common_init();
4605
4606 return r;
4607}
4608
4609int __init omap3430_clk_legacy_init(void)
4610{
4611 int r;
4612
4613 r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4614 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4615 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4616 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4617
4618 omap3_clk_legacy_common_init();
4619 omap3_clk_lock_dpll5();
4620
4621 return r;
4622}
4623
4624int __init omap36xx_clk_legacy_init(void)
4625{
4626 int r;
4627
4628 ti_clk_patch_legacy_clks(omap36xx_clk_patches);
4629 r = ti_clk_register_legacy_clks(omap36xx_clks);
4630 r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
4631 r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
4632 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4633 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4634
4635 omap3_clk_legacy_common_init();
4636 omap3_clk_lock_dpll5();
4637
4638 return r;
4639}
4640
4641int __init am35xx_clk_legacy_init(void)
4642{
4643 int r;
4644
4645 r = ti_clk_register_legacy_clks(am35xx_clks);
4646 r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
4647 r |= ti_clk_register_legacy_clks(omap3xxx_clks);
4648
4649 omap3_clk_legacy_common_init();
4650 omap3_clk_lock_dpll5();
4651
4652 return r;
4653}
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 0d1750a8aea4..383a06e49b09 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -327,7 +327,6 @@ enum {
327 OMAP3_SOC_OMAP3430_ES1, 327 OMAP3_SOC_OMAP3430_ES1,
328 OMAP3_SOC_OMAP3430_ES2_PLUS, 328 OMAP3_SOC_OMAP3430_ES2_PLUS,
329 OMAP3_SOC_OMAP3630, 329 OMAP3_SOC_OMAP3630,
330 OMAP3_SOC_TI81XX,
331}; 330};
332 331
333static int __init omap3xxx_dt_clk_init(int soc_type) 332static int __init omap3xxx_dt_clk_init(int soc_type)
@@ -370,7 +369,7 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
370 (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), 369 (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
371 (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); 370 (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
372 371
373 if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) 372 if (soc_type != OMAP3_SOC_OMAP3430_ES1)
374 omap3_clk_lock_dpll5(); 373 omap3_clk_lock_dpll5();
375 374
376 return 0; 375 return 0;
@@ -390,8 +389,3 @@ int __init am35xx_dt_clk_init(void)
390{ 389{
391 return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX); 390 return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
392} 391}
393
394int __init ti81xx_dt_clk_init(void)
395{
396 return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX);
397}
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 02517a8206bd..4f4c87751db5 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -12,7 +12,7 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/list.h> 14#include <linux/list.h>
15#include <linux/clk-private.h> 15#include <linux/clk.h>
16#include <linux/clkdev.h> 16#include <linux/clkdev.h>
17#include <linux/clk/ti.h> 17#include <linux/clk/ti.h>
18 18
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 5e183993e3ec..14160b223548 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -12,7 +12,7 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/list.h> 14#include <linux/list.h>
15#include <linux/clk-private.h> 15#include <linux/clk.h>
16#include <linux/clkdev.h> 16#include <linux/clkdev.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/clk/ti.h> 18#include <linux/clk/ti.h>
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 62ac8f6e480c..ee32f4deebf4 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -12,7 +12,7 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/list.h> 14#include <linux/list.h>
15#include <linux/clk-private.h> 15#include <linux/clk.h>
16#include <linux/clkdev.h> 16#include <linux/clkdev.h>
17#include <linux/clk/ti.h> 17#include <linux/clk/ti.h>
18 18
diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
new file mode 100644
index 000000000000..9451e651a1ff
--- /dev/null
+++ b/drivers/clk/ti/clk-816x.c
@@ -0,0 +1,53 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License as
4 * published by the Free Software Foundation version 2.
5 *
6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
7 * kind, whether express or implied; without even the implied warranty
8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 */
11
12#include <linux/kernel.h>
13#include <linux/list.h>
14#include <linux/clk-provider.h>
15#include <linux/clk/ti.h>
16
17static struct ti_dt_clk dm816x_clks[] = {
18 DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
19 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
20 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
21 DT_CLK(NULL, "mpu_ck", "mpu_ck"),
22 DT_CLK(NULL, "timer1_fck", "timer1_fck"),
23 DT_CLK(NULL, "timer2_fck", "timer2_fck"),
24 DT_CLK(NULL, "timer3_fck", "timer3_fck"),
25 DT_CLK(NULL, "timer4_fck", "timer4_fck"),
26 DT_CLK(NULL, "timer5_fck", "timer5_fck"),
27 DT_CLK(NULL, "timer6_fck", "timer6_fck"),
28 DT_CLK(NULL, "timer7_fck", "timer7_fck"),
29 DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
30 DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
31 DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
32 DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
33 DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
34 DT_CLK(NULL, "sysclk24_ck", "sysclk24_ck"),
35 DT_CLK("4a100000.ethernet", "sysclk24_ck", "sysclk24_ck"),
36 { .node_name = NULL },
37};
38
39static const char *enable_init_clks[] = {
40 "ddr_pll_clk1",
41 "ddr_pll_clk2",
42 "ddr_pll_clk3",
43};
44
45int __init ti81xx_dt_clk_init(void)
46{
47 ti_dt_clocks_register(dm816x_clks);
48 omap2_clk_disable_autoidle_all();
49 omap2_clk_enable_init_clocks(enable_init_clks,
50 ARRAY_SIZE(enable_init_clks));
51
52 return 0;
53}
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 337abe5909e1..e22b95646e09 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -22,6 +22,8 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/list.h> 23#include <linux/list.h>
24 24
25#include "clock.h"
26
25#undef pr_fmt 27#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 28#define pr_fmt(fmt) "%s: " fmt, __func__
27 29
@@ -183,3 +185,128 @@ void ti_dt_clk_init_retry_clks(void)
183 retries--; 185 retries--;
184 } 186 }
185} 187}
188
189#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
190void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
191{
192 while (*patch) {
193 memcpy((*patch)->patch, *patch, sizeof(**patch));
194 patch++;
195 }
196}
197
198struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
199{
200 struct clk *clk;
201 struct ti_clk_fixed *fixed;
202 struct ti_clk_fixed_factor *fixed_factor;
203 struct clk_hw *clk_hw;
204
205 if (setup->clk)
206 return setup->clk;
207
208 switch (setup->type) {
209 case TI_CLK_FIXED:
210 fixed = setup->data;
211
212 clk = clk_register_fixed_rate(NULL, setup->name, NULL,
213 CLK_IS_ROOT, fixed->frequency);
214 break;
215 case TI_CLK_MUX:
216 clk = ti_clk_register_mux(setup);
217 break;
218 case TI_CLK_DIVIDER:
219 clk = ti_clk_register_divider(setup);
220 break;
221 case TI_CLK_COMPOSITE:
222 clk = ti_clk_register_composite(setup);
223 break;
224 case TI_CLK_FIXED_FACTOR:
225 fixed_factor = setup->data;
226
227 clk = clk_register_fixed_factor(NULL, setup->name,
228 fixed_factor->parent,
229 0, fixed_factor->mult,
230 fixed_factor->div);
231 break;
232 case TI_CLK_GATE:
233 clk = ti_clk_register_gate(setup);
234 break;
235 case TI_CLK_DPLL:
236 clk = ti_clk_register_dpll(setup);
237 break;
238 default:
239 pr_err("bad type for %s!\n", setup->name);
240 clk = ERR_PTR(-EINVAL);
241 }
242
243 if (!IS_ERR(clk)) {
244 setup->clk = clk;
245 if (setup->clkdm_name) {
246 if (__clk_get_flags(clk) & CLK_IS_BASIC) {
247 pr_warn("can't setup clkdm for basic clk %s\n",
248 setup->name);
249 } else {
250 clk_hw = __clk_get_hw(clk);
251 to_clk_hw_omap(clk_hw)->clkdm_name =
252 setup->clkdm_name;
253 omap2_init_clk_clkdm(clk_hw);
254 }
255 }
256 }
257
258 return clk;
259}
260
261int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
262{
263 struct clk *clk;
264 bool retry;
265 struct ti_clk_alias *retry_clk;
266 struct ti_clk_alias *tmp;
267
268 while (clks->clk) {
269 clk = ti_clk_register_clk(clks->clk);
270 if (IS_ERR(clk)) {
271 if (PTR_ERR(clk) == -EAGAIN) {
272 list_add(&clks->link, &retry_list);
273 } else {
274 pr_err("register for %s failed: %ld\n",
275 clks->clk->name, PTR_ERR(clk));
276 return PTR_ERR(clk);
277 }
278 } else {
279 clks->lk.clk = clk;
280 clkdev_add(&clks->lk);
281 }
282 clks++;
283 }
284
285 retry = true;
286
287 while (!list_empty(&retry_list) && retry) {
288 retry = false;
289 list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
290 pr_debug("retry-init: %s\n", retry_clk->clk->name);
291 clk = ti_clk_register_clk(retry_clk->clk);
292 if (IS_ERR(clk)) {
293 if (PTR_ERR(clk) == -EAGAIN) {
294 continue;
295 } else {
296 pr_err("register for %s failed: %ld\n",
297 retry_clk->clk->name,
298 PTR_ERR(clk));
299 return PTR_ERR(clk);
300 }
301 } else {
302 retry = true;
303 retry_clk->lk.clk = clk;
304 clkdev_add(&retry_clk->lk);
305 list_del(&retry_clk->link);
306 }
307 }
308 }
309
310 return 0;
311}
312#endif
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
new file mode 100644
index 000000000000..404158d2d7f8
--- /dev/null
+++ b/drivers/clk/ti/clock.h
@@ -0,0 +1,172 @@
1/*
2 * TI Clock driver internal definitions
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#ifndef __DRIVERS_CLK_TI_CLOCK__
17#define __DRIVERS_CLK_TI_CLOCK__
18
19enum {
20 TI_CLK_FIXED,
21 TI_CLK_MUX,
22 TI_CLK_DIVIDER,
23 TI_CLK_COMPOSITE,
24 TI_CLK_FIXED_FACTOR,
25 TI_CLK_GATE,
26 TI_CLK_DPLL,
27};
28
29/* Global flags */
30#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
31#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
32#define CLKF_SET_RATE_PARENT (1 << 2)
33#define CLKF_OMAP3 (1 << 3)
34#define CLKF_AM35XX (1 << 4)
35
36/* Gate flags */
37#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
38#define CLKF_INTERFACE (1 << 6)
39#define CLKF_SSI (1 << 7)
40#define CLKF_DSS (1 << 8)
41#define CLKF_HSOTGUSB (1 << 9)
42#define CLKF_WAIT (1 << 10)
43#define CLKF_NO_WAIT (1 << 11)
44#define CLKF_HSDIV (1 << 12)
45#define CLKF_CLKDM (1 << 13)
46
47/* DPLL flags */
48#define CLKF_LOW_POWER_STOP (1 << 5)
49#define CLKF_LOCK (1 << 6)
50#define CLKF_LOW_POWER_BYPASS (1 << 7)
51#define CLKF_PER (1 << 8)
52#define CLKF_CORE (1 << 9)
53#define CLKF_J_TYPE (1 << 10)
54
55#define CLK(dev, con, ck) \
56 { \
57 .lk = { \
58 .dev_id = dev, \
59 .con_id = con, \
60 }, \
61 .clk = ck, \
62 }
63
64struct ti_clk {
65 const char *name;
66 const char *clkdm_name;
67 int type;
68 void *data;
69 struct ti_clk *patch;
70 struct clk *clk;
71};
72
73struct ti_clk_alias {
74 struct ti_clk *clk;
75 struct clk_lookup lk;
76 struct list_head link;
77};
78
79struct ti_clk_fixed {
80 u32 frequency;
81 u16 flags;
82};
83
84struct ti_clk_mux {
85 u8 bit_shift;
86 int num_parents;
87 u16 reg;
88 u8 module;
89 const char **parents;
90 u16 flags;
91};
92
93struct ti_clk_divider {
94 const char *parent;
95 u8 bit_shift;
96 u16 max_div;
97 u16 reg;
98 u8 module;
99 int *dividers;
100 int num_dividers;
101 u16 flags;
102};
103
104struct ti_clk_fixed_factor {
105 const char *parent;
106 u16 div;
107 u16 mult;
108 u16 flags;
109};
110
111struct ti_clk_gate {
112 const char *parent;
113 u8 bit_shift;
114 u16 reg;
115 u8 module;
116 u16 flags;
117};
118
119struct ti_clk_composite {
120 struct ti_clk_divider *divider;
121 struct ti_clk_mux *mux;
122 struct ti_clk_gate *gate;
123 u16 flags;
124};
125
126struct ti_clk_clkdm_gate {
127 const char *parent;
128 u16 flags;
129};
130
131struct ti_clk_dpll {
132 int num_parents;
133 u16 control_reg;
134 u16 idlest_reg;
135 u16 autoidle_reg;
136 u16 mult_div1_reg;
137 u8 module;
138 const char **parents;
139 u16 flags;
140 u8 modes;
141 u32 mult_mask;
142 u32 div1_mask;
143 u32 enable_mask;
144 u32 autoidle_mask;
145 u32 freqsel_mask;
146 u32 idlest_mask;
147 u32 dco_mask;
148 u32 sddiv_mask;
149 u16 max_multiplier;
150 u16 max_divider;
151 u8 min_divider;
152 u8 auto_recal_bit;
153 u8 recal_en_bit;
154 u8 recal_st_bit;
155};
156
157struct clk *ti_clk_register_gate(struct ti_clk *setup);
158struct clk *ti_clk_register_interface(struct ti_clk *setup);
159struct clk *ti_clk_register_mux(struct ti_clk *setup);
160struct clk *ti_clk_register_divider(struct ti_clk *setup);
161struct clk *ti_clk_register_composite(struct ti_clk *setup);
162struct clk *ti_clk_register_dpll(struct ti_clk *setup);
163
164struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
165struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
166struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
167
168void ti_clk_patch_legacy_clks(struct ti_clk **patch);
169struct clk *ti_clk_register_clk(struct ti_clk *setup);
170int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
171
172#endif
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 19d8980ba458..3654f61912eb 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -23,6 +23,8 @@
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include <linux/list.h> 24#include <linux/list.h>
25 25
26#include "clock.h"
27
26#undef pr_fmt 28#undef pr_fmt
27#define pr_fmt(fmt) "%s: " fmt, __func__ 29#define pr_fmt(fmt) "%s: " fmt, __func__
28 30
@@ -116,8 +118,46 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
116 118
117#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw) 119#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
118 120
119static void __init ti_clk_register_composite(struct clk_hw *hw, 121#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
120 struct device_node *node) 122struct clk *ti_clk_register_composite(struct ti_clk *setup)
123{
124 struct ti_clk_composite *comp;
125 struct clk_hw *gate;
126 struct clk_hw *mux;
127 struct clk_hw *div;
128 int num_parents = 1;
129 const char **parent_names = NULL;
130 struct clk *clk;
131
132 comp = setup->data;
133
134 div = ti_clk_build_component_div(comp->divider);
135 gate = ti_clk_build_component_gate(comp->gate);
136 mux = ti_clk_build_component_mux(comp->mux);
137
138 if (div)
139 parent_names = &comp->divider->parent;
140
141 if (gate)
142 parent_names = &comp->gate->parent;
143
144 if (mux) {
145 num_parents = comp->mux->num_parents;
146 parent_names = comp->mux->parents;
147 }
148
149 clk = clk_register_composite(NULL, setup->name,
150 parent_names, num_parents, mux,
151 &ti_clk_mux_ops, div,
152 &ti_composite_divider_ops, gate,
153 &ti_composite_gate_ops, 0);
154
155 return clk;
156}
157#endif
158
159static void __init _register_composite(struct clk_hw *hw,
160 struct device_node *node)
121{ 161{
122 struct clk *clk; 162 struct clk *clk;
123 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); 163 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
@@ -136,7 +176,7 @@ static void __init ti_clk_register_composite(struct clk_hw *hw,
136 pr_debug("component %s not ready for %s, retry\n", 176 pr_debug("component %s not ready for %s, retry\n",
137 cclk->comp_nodes[i]->name, node->name); 177 cclk->comp_nodes[i]->name, node->name);
138 if (!ti_clk_retry_init(node, hw, 178 if (!ti_clk_retry_init(node, hw,
139 ti_clk_register_composite)) 179 _register_composite))
140 return; 180 return;
141 181
142 goto cleanup; 182 goto cleanup;
@@ -216,7 +256,7 @@ static void __init of_ti_composite_clk_setup(struct device_node *node)
216 for (i = 0; i < num_clks; i++) 256 for (i = 0; i < num_clks; i++)
217 cclk->comp_nodes[i] = _get_component_node(node, i); 257 cclk->comp_nodes[i] = _get_component_node(node, i);
218 258
219 ti_clk_register_composite(&cclk->hw, node); 259 _register_composite(&cclk->hw, node);
220} 260}
221CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock", 261CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
222 of_ti_composite_clk_setup); 262 of_ti_composite_clk_setup);
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index bff2b5b8ff59..6211893c0980 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include "clock.h"
24 25
25#undef pr_fmt 26#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 27#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -301,6 +302,134 @@ static struct clk *_register_divider(struct device *dev, const char *name,
301} 302}
302 303
303static struct clk_div_table * 304static struct clk_div_table *
305_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
306{
307 int valid_div = 0;
308 struct clk_div_table *table;
309 int i;
310 int div;
311 u32 val;
312 u8 flags;
313
314 if (!setup->num_dividers) {
315 /* Clk divider table not provided, determine min/max divs */
316 flags = setup->flags;
317
318 if (flags & CLKF_INDEX_STARTS_AT_ONE)
319 val = 1;
320 else
321 val = 0;
322
323 div = 1;
324
325 while (div < setup->max_div) {
326 if (flags & CLKF_INDEX_POWER_OF_TWO)
327 div <<= 1;
328 else
329 div++;
330 val++;
331 }
332
333 *width = fls(val);
334
335 return NULL;
336 }
337
338 for (i = 0; i < setup->num_dividers; i++)
339 if (setup->dividers[i])
340 valid_div++;
341
342 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
343 if (!table)
344 return ERR_PTR(-ENOMEM);
345
346 valid_div = 0;
347 *width = 0;
348
349 for (i = 0; i < setup->num_dividers; i++)
350 if (setup->dividers[i]) {
351 table[valid_div].div = setup->dividers[i];
352 table[valid_div].val = i;
353 valid_div++;
354 *width = i;
355 }
356
357 *width = fls(*width);
358
359 return table;
360}
361
362struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
363{
364 struct clk_divider *div;
365 struct clk_omap_reg *reg;
366
367 if (!setup)
368 return NULL;
369
370 div = kzalloc(sizeof(*div), GFP_KERNEL);
371 if (!div)
372 return ERR_PTR(-ENOMEM);
373
374 reg = (struct clk_omap_reg *)&div->reg;
375 reg->index = setup->module;
376 reg->offset = setup->reg;
377
378 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
379 div->flags |= CLK_DIVIDER_ONE_BASED;
380
381 if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
382 div->flags |= CLK_DIVIDER_POWER_OF_TWO;
383
384 div->table = _get_div_table_from_setup(setup, &div->width);
385
386 div->shift = setup->bit_shift;
387
388 return &div->hw;
389}
390
391struct clk *ti_clk_register_divider(struct ti_clk *setup)
392{
393 struct ti_clk_divider *div;
394 struct clk_omap_reg *reg_setup;
395 u32 reg;
396 u8 width;
397 u32 flags = 0;
398 u8 div_flags = 0;
399 struct clk_div_table *table;
400 struct clk *clk;
401
402 div = setup->data;
403
404 reg_setup = (struct clk_omap_reg *)&reg;
405
406 reg_setup->index = div->module;
407 reg_setup->offset = div->reg;
408
409 if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
410 div_flags |= CLK_DIVIDER_ONE_BASED;
411
412 if (div->flags & CLKF_INDEX_POWER_OF_TWO)
413 div_flags |= CLK_DIVIDER_POWER_OF_TWO;
414
415 if (div->flags & CLKF_SET_RATE_PARENT)
416 flags |= CLK_SET_RATE_PARENT;
417
418 table = _get_div_table_from_setup(div, &width);
419 if (IS_ERR(table))
420 return (struct clk *)table;
421
422 clk = _register_divider(NULL, setup->name, div->parent,
423 flags, (void __iomem *)reg, div->bit_shift,
424 width, div_flags, table, NULL);
425
426 if (IS_ERR(clk))
427 kfree(table);
428
429 return clk;
430}
431
432static struct clk_div_table *
304__init ti_clk_get_div_table(struct device_node *node) 433__init ti_clk_get_div_table(struct device_node *node)
305{ 434{
306 struct clk_div_table *table; 435 struct clk_div_table *table;
@@ -455,7 +584,8 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
455 goto cleanup; 584 goto cleanup;
456 585
457 clk = _register_divider(NULL, node->name, parent_name, flags, reg, 586 clk = _register_divider(NULL, node->name, parent_name, flags, reg,
458 shift, width, clk_divider_flags, table, NULL); 587 shift, width, clk_divider_flags, table,
588 NULL);
459 589
460 if (!IS_ERR(clk)) { 590 if (!IS_ERR(clk)) {
461 of_clk_add_provider(node, of_clk_src_simple_get, clk); 591 of_clk_add_provider(node, of_clk_src_simple_get, clk);
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 85ac0dd501de..81dc4698dc41 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include "clock.h"
24 25
25#undef pr_fmt 26#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 27#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -130,7 +131,7 @@ static const struct clk_ops dpll_x2_ck_ops = {
130}; 131};
131 132
132/** 133/**
133 * ti_clk_register_dpll - low level registration of a DPLL clock 134 * _register_dpll - low level registration of a DPLL clock
134 * @hw: hardware clock definition for the clock 135 * @hw: hardware clock definition for the clock
135 * @node: device node for the clock 136 * @node: device node for the clock
136 * 137 *
@@ -138,8 +139,8 @@ static const struct clk_ops dpll_x2_ck_ops = {
138 * clk-bypass is missing), the clock is added to retry list and 139 * clk-bypass is missing), the clock is added to retry list and
139 * the initialization is retried on later stage. 140 * the initialization is retried on later stage.
140 */ 141 */
141static void __init ti_clk_register_dpll(struct clk_hw *hw, 142static void __init _register_dpll(struct clk_hw *hw,
142 struct device_node *node) 143 struct device_node *node)
143{ 144{
144 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 145 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
145 struct dpll_data *dd = clk_hw->dpll_data; 146 struct dpll_data *dd = clk_hw->dpll_data;
@@ -151,7 +152,7 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw,
151 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) { 152 if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
152 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n", 153 pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
153 node->name); 154 node->name);
154 if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll)) 155 if (!ti_clk_retry_init(node, hw, _register_dpll))
155 return; 156 return;
156 157
157 goto cleanup; 158 goto cleanup;
@@ -175,20 +176,118 @@ cleanup:
175 kfree(clk_hw); 176 kfree(clk_hw);
176} 177}
177 178
179#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
180void __iomem *_get_reg(u8 module, u16 offset)
181{
182 u32 reg;
183 struct clk_omap_reg *reg_setup;
184
185 reg_setup = (struct clk_omap_reg *)&reg;
186
187 reg_setup->index = module;
188 reg_setup->offset = offset;
189
190 return (void __iomem *)reg;
191}
192
193struct clk *ti_clk_register_dpll(struct ti_clk *setup)
194{
195 struct clk_hw_omap *clk_hw;
196 struct clk_init_data init = { NULL };
197 struct dpll_data *dd;
198 struct clk *clk;
199 struct ti_clk_dpll *dpll;
200 const struct clk_ops *ops = &omap3_dpll_ck_ops;
201 struct clk *clk_ref;
202 struct clk *clk_bypass;
203
204 dpll = setup->data;
205
206 if (dpll->num_parents < 2)
207 return ERR_PTR(-EINVAL);
208
209 clk_ref = clk_get_sys(NULL, dpll->parents[0]);
210 clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
211
212 if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
213 return ERR_PTR(-EAGAIN);
214
215 dd = kzalloc(sizeof(*dd), GFP_KERNEL);
216 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
217 if (!dd || !clk_hw) {
218 clk = ERR_PTR(-ENOMEM);
219 goto cleanup;
220 }
221
222 clk_hw->dpll_data = dd;
223 clk_hw->ops = &clkhwops_omap3_dpll;
224 clk_hw->hw.init = &init;
225 clk_hw->flags = MEMMAP_ADDRESSING;
226
227 init.name = setup->name;
228 init.ops = ops;
229
230 init.num_parents = dpll->num_parents;
231 init.parent_names = dpll->parents;
232
233 dd->control_reg = _get_reg(dpll->module, dpll->control_reg);
234 dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg);
235 dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg);
236 dd->autoidle_reg = _get_reg(dpll->module, dpll->autoidle_reg);
237
238 dd->modes = dpll->modes;
239 dd->div1_mask = dpll->div1_mask;
240 dd->idlest_mask = dpll->idlest_mask;
241 dd->mult_mask = dpll->mult_mask;
242 dd->autoidle_mask = dpll->autoidle_mask;
243 dd->enable_mask = dpll->enable_mask;
244 dd->sddiv_mask = dpll->sddiv_mask;
245 dd->dco_mask = dpll->dco_mask;
246 dd->max_divider = dpll->max_divider;
247 dd->min_divider = dpll->min_divider;
248 dd->max_multiplier = dpll->max_multiplier;
249 dd->auto_recal_bit = dpll->auto_recal_bit;
250 dd->recal_en_bit = dpll->recal_en_bit;
251 dd->recal_st_bit = dpll->recal_st_bit;
252
253 dd->clk_ref = clk_ref;
254 dd->clk_bypass = clk_bypass;
255
256 if (dpll->flags & CLKF_CORE)
257 ops = &omap3_dpll_core_ck_ops;
258
259 if (dpll->flags & CLKF_PER)
260 ops = &omap3_dpll_per_ck_ops;
261
262 if (dpll->flags & CLKF_J_TYPE)
263 dd->flags |= DPLL_J_TYPE;
264
265 clk = clk_register(NULL, &clk_hw->hw);
266
267 if (!IS_ERR(clk))
268 return clk;
269
270cleanup:
271 kfree(dd);
272 kfree(clk_hw);
273 return clk;
274}
275#endif
276
178#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 277#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
179 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \ 278 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
180 defined(CONFIG_SOC_AM43XX) 279 defined(CONFIG_SOC_AM43XX)
181/** 280/**
182 * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock 281 * _register_dpll_x2 - Registers a DPLLx2 clock
183 * @node: device node for this clock 282 * @node: device node for this clock
184 * @ops: clk_ops for this clock 283 * @ops: clk_ops for this clock
185 * @hw_ops: clk_hw_ops for this clock 284 * @hw_ops: clk_hw_ops for this clock
186 * 285 *
187 * Initializes a DPLL x 2 clock from device tree data. 286 * Initializes a DPLL x 2 clock from device tree data.
188 */ 287 */
189static void ti_clk_register_dpll_x2(struct device_node *node, 288static void _register_dpll_x2(struct device_node *node,
190 const struct clk_ops *ops, 289 const struct clk_ops *ops,
191 const struct clk_hw_omap_ops *hw_ops) 290 const struct clk_hw_omap_ops *hw_ops)
192{ 291{
193 struct clk *clk; 292 struct clk *clk;
194 struct clk_init_data init = { NULL }; 293 struct clk_init_data init = { NULL };
@@ -318,7 +417,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
318 if (dpll_mode) 417 if (dpll_mode)
319 dd->modes = dpll_mode; 418 dd->modes = dpll_mode;
320 419
321 ti_clk_register_dpll(&clk_hw->hw, node); 420 _register_dpll(&clk_hw->hw, node);
322 return; 421 return;
323 422
324cleanup: 423cleanup:
@@ -332,7 +431,7 @@ cleanup:
332 defined(CONFIG_SOC_DRA7XX) 431 defined(CONFIG_SOC_DRA7XX)
333static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) 432static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
334{ 433{
335 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); 434 _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
336} 435}
337CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", 436CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
338 of_ti_omap4_dpll_x2_setup); 437 of_ti_omap4_dpll_x2_setup);
@@ -341,7 +440,7 @@ CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
341#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 440#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
342static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) 441static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
343{ 442{
344 ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL); 443 _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
345} 444}
346CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", 445CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
347 of_ti_am3_dpll_x2_setup); 446 of_ti_am3_dpll_x2_setup);
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
new file mode 100644
index 000000000000..6ef89639a9f6
--- /dev/null
+++ b/drivers/clk/ti/fapll.c
@@ -0,0 +1,410 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License as
4 * published by the Free Software Foundation version 2.
5 *
6 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
7 * kind, whether express or implied; without even the implied warranty
8 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/delay.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/clk/ti.h>
19#include <asm/div64.h>
20
21/* FAPLL Control Register PLL_CTRL */
22#define FAPLL_MAIN_LOCK BIT(7)
23#define FAPLL_MAIN_PLLEN BIT(3)
24#define FAPLL_MAIN_BP BIT(2)
25#define FAPLL_MAIN_LOC_CTL BIT(0)
26
27/* FAPLL powerdown register PWD */
28#define FAPLL_PWD_OFFSET 4
29
30#define MAX_FAPLL_OUTPUTS 7
31#define FAPLL_MAX_RETRIES 1000
32
33#define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
34#define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
35
36/* The bypass bit is inverted on the ddr_pll.. */
37#define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
38
39/*
40 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
41 * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
42 */
43#define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
44#define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
45
46/* Synthesizer divider register */
47#define SYNTH_LDMDIV1 BIT(8)
48
49/* Synthesizer frequency register */
50#define SYNTH_LDFREQ BIT(31)
51
52struct fapll_data {
53 struct clk_hw hw;
54 void __iomem *base;
55 const char *name;
56 struct clk *clk_ref;
57 struct clk *clk_bypass;
58 struct clk_onecell_data outputs;
59 bool bypass_bit_inverted;
60};
61
62struct fapll_synth {
63 struct clk_hw hw;
64 struct fapll_data *fd;
65 int index;
66 void __iomem *freq;
67 void __iomem *div;
68 const char *name;
69 struct clk *clk_pll;
70};
71
72static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
73{
74 u32 v = readl_relaxed(fd->base);
75
76 if (fd->bypass_bit_inverted)
77 return !(v & FAPLL_MAIN_BP);
78 else
79 return !!(v & FAPLL_MAIN_BP);
80}
81
82static int ti_fapll_enable(struct clk_hw *hw)
83{
84 struct fapll_data *fd = to_fapll(hw);
85 u32 v = readl_relaxed(fd->base);
86
87 v |= (1 << FAPLL_MAIN_PLLEN);
88 writel_relaxed(v, fd->base);
89
90 return 0;
91}
92
93static void ti_fapll_disable(struct clk_hw *hw)
94{
95 struct fapll_data *fd = to_fapll(hw);
96 u32 v = readl_relaxed(fd->base);
97
98 v &= ~(1 << FAPLL_MAIN_PLLEN);
99 writel_relaxed(v, fd->base);
100}
101
102static int ti_fapll_is_enabled(struct clk_hw *hw)
103{
104 struct fapll_data *fd = to_fapll(hw);
105 u32 v = readl_relaxed(fd->base);
106
107 return v & (1 << FAPLL_MAIN_PLLEN);
108}
109
110static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate)
112{
113 struct fapll_data *fd = to_fapll(hw);
114 u32 fapll_n, fapll_p, v;
115 long long rate;
116
117 if (ti_fapll_clock_is_bypass(fd))
118 return parent_rate;
119
120 rate = parent_rate;
121
122 /* PLL pre-divider is P and multiplier is N */
123 v = readl_relaxed(fd->base);
124 fapll_p = (v >> 8) & 0xff;
125 if (fapll_p)
126 do_div(rate, fapll_p);
127 fapll_n = v >> 16;
128 if (fapll_n)
129 rate *= fapll_n;
130
131 return rate;
132}
133
134static u8 ti_fapll_get_parent(struct clk_hw *hw)
135{
136 struct fapll_data *fd = to_fapll(hw);
137
138 if (ti_fapll_clock_is_bypass(fd))
139 return 1;
140
141 return 0;
142}
143
144static struct clk_ops ti_fapll_ops = {
145 .enable = ti_fapll_enable,
146 .disable = ti_fapll_disable,
147 .is_enabled = ti_fapll_is_enabled,
148 .recalc_rate = ti_fapll_recalc_rate,
149 .get_parent = ti_fapll_get_parent,
150};
151
152static int ti_fapll_synth_enable(struct clk_hw *hw)
153{
154 struct fapll_synth *synth = to_synth(hw);
155 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
156
157 v &= ~(1 << synth->index);
158 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
159
160 return 0;
161}
162
163static void ti_fapll_synth_disable(struct clk_hw *hw)
164{
165 struct fapll_synth *synth = to_synth(hw);
166 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
167
168 v |= 1 << synth->index;
169 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
170}
171
172static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
173{
174 struct fapll_synth *synth = to_synth(hw);
175 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
176
177 return !(v & (1 << synth->index));
178}
179
180/*
181 * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
182 */
183static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
184 unsigned long parent_rate)
185{
186 struct fapll_synth *synth = to_synth(hw);
187 u32 synth_div_m;
188 long long rate;
189
190 /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
191 if (!synth->div)
192 return 32768;
193
194 /*
195 * PLL in bypass sets the synths in bypass mode too. The PLL rate
196 * can be also be set to 27MHz, so we can't use parent_rate to
197 * check for bypass mode.
198 */
199 if (ti_fapll_clock_is_bypass(synth->fd))
200 return parent_rate;
201
202 rate = parent_rate;
203
204 /*
205 * Synth frequency integer and fractional divider.
206 * Note that the phase output K is 8, so the result needs
207 * to be multiplied by 8.
208 */
209 if (synth->freq) {
210 u32 v, synth_int_div, synth_frac_div, synth_div_freq;
211
212 v = readl_relaxed(synth->freq);
213 synth_int_div = (v >> 24) & 0xf;
214 synth_frac_div = v & 0xffffff;
215 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
216 rate *= 10000000;
217 do_div(rate, synth_div_freq);
218 rate *= 8;
219 }
220
221 /* Synth ost-divider M */
222 synth_div_m = readl_relaxed(synth->div) & 0xff;
223 do_div(rate, synth_div_m);
224
225 return rate;
226}
227
228static struct clk_ops ti_fapll_synt_ops = {
229 .enable = ti_fapll_synth_enable,
230 .disable = ti_fapll_synth_disable,
231 .is_enabled = ti_fapll_synth_is_enabled,
232 .recalc_rate = ti_fapll_synth_recalc_rate,
233};
234
235static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
236 void __iomem *freq,
237 void __iomem *div,
238 int index,
239 const char *name,
240 const char *parent,
241 struct clk *pll_clk)
242{
243 struct clk_init_data *init;
244 struct fapll_synth *synth;
245
246 init = kzalloc(sizeof(*init), GFP_KERNEL);
247 if (!init)
248 return ERR_PTR(-ENOMEM);
249
250 init->ops = &ti_fapll_synt_ops;
251 init->name = name;
252 init->parent_names = &parent;
253 init->num_parents = 1;
254
255 synth = kzalloc(sizeof(*synth), GFP_KERNEL);
256 if (!synth)
257 goto free;
258
259 synth->fd = fd;
260 synth->index = index;
261 synth->freq = freq;
262 synth->div = div;
263 synth->name = name;
264 synth->hw.init = init;
265 synth->clk_pll = pll_clk;
266
267 return clk_register(NULL, &synth->hw);
268
269free:
270 kfree(synth);
271 kfree(init);
272
273 return ERR_PTR(-ENOMEM);
274}
275
276static void __init ti_fapll_setup(struct device_node *node)
277{
278 struct fapll_data *fd;
279 struct clk_init_data *init = NULL;
280 const char *parent_name[2];
281 struct clk *pll_clk;
282 int i;
283
284 fd = kzalloc(sizeof(*fd), GFP_KERNEL);
285 if (!fd)
286 return;
287
288 fd->outputs.clks = kzalloc(sizeof(struct clk *) *
289 MAX_FAPLL_OUTPUTS + 1,
290 GFP_KERNEL);
291 if (!fd->outputs.clks)
292 goto free;
293
294 init = kzalloc(sizeof(*init), GFP_KERNEL);
295 if (!init)
296 goto free;
297
298 init->ops = &ti_fapll_ops;
299 init->name = node->name;
300
301 init->num_parents = of_clk_get_parent_count(node);
302 if (init->num_parents != 2) {
303 pr_err("%s must have two parents\n", node->name);
304 goto free;
305 }
306
307 parent_name[0] = of_clk_get_parent_name(node, 0);
308 parent_name[1] = of_clk_get_parent_name(node, 1);
309 init->parent_names = parent_name;
310
311 fd->clk_ref = of_clk_get(node, 0);
312 if (IS_ERR(fd->clk_ref)) {
313 pr_err("%s could not get clk_ref\n", node->name);
314 goto free;
315 }
316
317 fd->clk_bypass = of_clk_get(node, 1);
318 if (IS_ERR(fd->clk_bypass)) {
319 pr_err("%s could not get clk_bypass\n", node->name);
320 goto free;
321 }
322
323 fd->base = of_iomap(node, 0);
324 if (!fd->base) {
325 pr_err("%s could not get IO base\n", node->name);
326 goto free;
327 }
328
329 if (fapll_is_ddr_pll(fd->base))
330 fd->bypass_bit_inverted = true;
331
332 fd->name = node->name;
333 fd->hw.init = init;
334
335 /* Register the parent PLL */
336 pll_clk = clk_register(NULL, &fd->hw);
337 if (IS_ERR(pll_clk))
338 goto unmap;
339
340 fd->outputs.clks[0] = pll_clk;
341 fd->outputs.clk_num++;
342
343 /*
344 * Set up the child synthesizers starting at index 1 as the
345 * PLL output is at index 0. We need to check the clock-indices
346 * for numbering in case there are holes in the synth mapping,
347 * and then probe the synth register to see if it has a FREQ
348 * register available.
349 */
350 for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
351 const char *output_name;
352 void __iomem *freq, *div;
353 struct clk *synth_clk;
354 int output_instance;
355 u32 v;
356
357 if (of_property_read_string_index(node, "clock-output-names",
358 i, &output_name))
359 continue;
360
361 if (of_property_read_u32_index(node, "clock-indices", i,
362 &output_instance))
363 output_instance = i;
364
365 freq = fd->base + (output_instance * 8);
366 div = freq + 4;
367
368 /* Check for hardwired audio_pll_clk1 */
369 if (is_audio_pll_clk1(freq)) {
370 freq = 0;
371 div = 0;
372 } else {
373 /* Does the synthesizer have a FREQ register? */
374 v = readl_relaxed(freq);
375 if (!v)
376 freq = 0;
377 }
378 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
379 output_name, node->name,
380 pll_clk);
381 if (IS_ERR(synth_clk))
382 continue;
383
384 fd->outputs.clks[output_instance] = synth_clk;
385 fd->outputs.clk_num++;
386
387 clk_register_clkdev(synth_clk, output_name, NULL);
388 }
389
390 /* Register the child synthesizers as the FAPLL outputs */
391 of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
392 /* Add clock alias for the outputs */
393
394 kfree(init);
395
396 return;
397
398unmap:
399 iounmap(fd->base);
400free:
401 if (fd->clk_bypass)
402 clk_put(fd->clk_bypass);
403 if (fd->clk_ref)
404 clk_put(fd->clk_ref);
405 kfree(fd->outputs.clks);
406 kfree(fd);
407 kfree(init);
408}
409
410CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index b326d2797feb..d493307b73f4 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -22,6 +22,8 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24 24
25#include "clock.h"
26
25#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 27#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
26 28
27#undef pr_fmt 29#undef pr_fmt
@@ -90,63 +92,164 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
90 return ret; 92 return ret;
91} 93}
92 94
93static void __init _of_ti_gate_clk_setup(struct device_node *node, 95static struct clk *_register_gate(struct device *dev, const char *name,
94 const struct clk_ops *ops, 96 const char *parent_name, unsigned long flags,
95 const struct clk_hw_omap_ops *hw_ops) 97 void __iomem *reg, u8 bit_idx,
98 u8 clk_gate_flags, const struct clk_ops *ops,
99 const struct clk_hw_omap_ops *hw_ops)
96{ 100{
97 struct clk *clk;
98 struct clk_init_data init = { NULL }; 101 struct clk_init_data init = { NULL };
99 struct clk_hw_omap *clk_hw; 102 struct clk_hw_omap *clk_hw;
100 const char *clk_name = node->name; 103 struct clk *clk;
101 const char *parent_name;
102 u32 val;
103 104
104 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 105 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
105 if (!clk_hw) 106 if (!clk_hw)
106 return; 107 return ERR_PTR(-ENOMEM);
107 108
108 clk_hw->hw.init = &init; 109 clk_hw->hw.init = &init;
109 110
110 init.name = clk_name; 111 init.name = name;
111 init.ops = ops; 112 init.ops = ops;
112 113
113 if (ops != &omap_gate_clkdm_clk_ops) { 114 clk_hw->enable_reg = reg;
114 clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0); 115 clk_hw->enable_bit = bit_idx;
115 if (!clk_hw->enable_reg) 116 clk_hw->ops = hw_ops;
116 goto cleanup;
117 117
118 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 118 clk_hw->flags = MEMMAP_ADDRESSING | clk_gate_flags;
119 clk_hw->enable_bit = val; 119
120 init.parent_names = &parent_name;
121 init.num_parents = 1;
122
123 init.flags = flags;
124
125 clk = clk_register(NULL, &clk_hw->hw);
126
127 if (IS_ERR(clk))
128 kfree(clk_hw);
129
130 return clk;
131}
132
133#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
134struct clk *ti_clk_register_gate(struct ti_clk *setup)
135{
136 const struct clk_ops *ops = &omap_gate_clk_ops;
137 const struct clk_hw_omap_ops *hw_ops = NULL;
138 u32 reg;
139 struct clk_omap_reg *reg_setup;
140 u32 flags = 0;
141 u8 clk_gate_flags = 0;
142 struct ti_clk_gate *gate;
143
144 gate = setup->data;
145
146 if (gate->flags & CLKF_INTERFACE)
147 return ti_clk_register_interface(setup);
148
149 reg_setup = (struct clk_omap_reg *)&reg;
150
151 if (gate->flags & CLKF_SET_RATE_PARENT)
152 flags |= CLK_SET_RATE_PARENT;
153
154 if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
155 clk_gate_flags |= INVERT_ENABLE;
156
157 if (gate->flags & CLKF_HSDIV) {
158 ops = &omap_gate_clk_hsdiv_restore_ops;
159 hw_ops = &clkhwops_wait;
120 } 160 }
121 161
122 clk_hw->ops = hw_ops; 162 if (gate->flags & CLKF_DSS)
163 hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
164
165 if (gate->flags & CLKF_WAIT)
166 hw_ops = &clkhwops_wait;
167
168 if (gate->flags & CLKF_CLKDM)
169 ops = &omap_gate_clkdm_clk_ops;
170
171 if (gate->flags & CLKF_AM35XX)
172 hw_ops = &clkhwops_am35xx_ipss_module_wait;
123 173
124 clk_hw->flags = MEMMAP_ADDRESSING; 174 reg_setup->index = gate->module;
175 reg_setup->offset = gate->reg;
176
177 return _register_gate(NULL, setup->name, gate->parent, flags,
178 (void __iomem *)reg, gate->bit_shift,
179 clk_gate_flags, ops, hw_ops);
180}
181
182struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
183{
184 struct clk_hw_omap *gate;
185 struct clk_omap_reg *reg;
186 const struct clk_hw_omap_ops *ops = &clkhwops_wait;
187
188 if (!setup)
189 return NULL;
190
191 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
192 if (!gate)
193 return ERR_PTR(-ENOMEM);
194
195 reg = (struct clk_omap_reg *)&gate->enable_reg;
196 reg->index = setup->module;
197 reg->offset = setup->reg;
198
199 gate->enable_bit = setup->bit_shift;
200
201 if (setup->flags & CLKF_NO_WAIT)
202 ops = NULL;
203
204 if (setup->flags & CLKF_INTERFACE)
205 ops = &clkhwops_iclk_wait;
206
207 gate->ops = ops;
208 gate->flags = MEMMAP_ADDRESSING;
209
210 return &gate->hw;
211}
212#endif
213
214static void __init _of_ti_gate_clk_setup(struct device_node *node,
215 const struct clk_ops *ops,
216 const struct clk_hw_omap_ops *hw_ops)
217{
218 struct clk *clk;
219 const char *parent_name;
220 void __iomem *reg = NULL;
221 u8 enable_bit = 0;
222 u32 val;
223 u32 flags = 0;
224 u8 clk_gate_flags = 0;
225
226 if (ops != &omap_gate_clkdm_clk_ops) {
227 reg = ti_clk_get_reg_addr(node, 0);
228 if (!reg)
229 return;
230
231 if (!of_property_read_u32(node, "ti,bit-shift", &val))
232 enable_bit = val;
233 }
125 234
126 if (of_clk_get_parent_count(node) != 1) { 235 if (of_clk_get_parent_count(node) != 1) {
127 pr_err("%s must have 1 parent\n", clk_name); 236 pr_err("%s must have 1 parent\n", node->name);
128 goto cleanup; 237 return;
129 } 238 }
130 239
131 parent_name = of_clk_get_parent_name(node, 0); 240 parent_name = of_clk_get_parent_name(node, 0);
132 init.parent_names = &parent_name;
133 init.num_parents = 1;
134 241
135 if (of_property_read_bool(node, "ti,set-rate-parent")) 242 if (of_property_read_bool(node, "ti,set-rate-parent"))
136 init.flags |= CLK_SET_RATE_PARENT; 243 flags |= CLK_SET_RATE_PARENT;
137 244
138 if (of_property_read_bool(node, "ti,set-bit-to-disable")) 245 if (of_property_read_bool(node, "ti,set-bit-to-disable"))
139 clk_hw->flags |= INVERT_ENABLE; 246 clk_gate_flags |= INVERT_ENABLE;
140 247
141 clk = clk_register(NULL, &clk_hw->hw); 248 clk = _register_gate(NULL, node->name, parent_name, flags, reg,
249 enable_bit, clk_gate_flags, ops, hw_ops);
142 250
143 if (!IS_ERR(clk)) { 251 if (!IS_ERR(clk))
144 of_clk_add_provider(node, of_clk_src_simple_get, clk); 252 of_clk_add_provider(node, of_clk_src_simple_get, clk);
145 return;
146 }
147
148cleanup:
149 kfree(clk_hw);
150} 253}
151 254
152static void __init 255static void __init
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 9c3e8c4aaa40..265d91f071c5 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -20,6 +20,7 @@
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/clk/ti.h> 22#include <linux/clk/ti.h>
23#include "clock.h"
23 24
24#undef pr_fmt 25#undef pr_fmt
25#define pr_fmt(fmt) "%s: " fmt, __func__ 26#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -31,53 +32,102 @@ static const struct clk_ops ti_interface_clk_ops = {
31 .is_enabled = &omap2_dflt_clk_is_enabled, 32 .is_enabled = &omap2_dflt_clk_is_enabled,
32}; 33};
33 34
34static void __init _of_ti_interface_clk_setup(struct device_node *node, 35static struct clk *_register_interface(struct device *dev, const char *name,
35 const struct clk_hw_omap_ops *ops) 36 const char *parent_name,
37 void __iomem *reg, u8 bit_idx,
38 const struct clk_hw_omap_ops *ops)
36{ 39{
37 struct clk *clk;
38 struct clk_init_data init = { NULL }; 40 struct clk_init_data init = { NULL };
39 struct clk_hw_omap *clk_hw; 41 struct clk_hw_omap *clk_hw;
40 const char *parent_name; 42 struct clk *clk;
41 u32 val;
42 43
43 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 44 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
44 if (!clk_hw) 45 if (!clk_hw)
45 return; 46 return ERR_PTR(-ENOMEM);
46 47
47 clk_hw->hw.init = &init; 48 clk_hw->hw.init = &init;
48 clk_hw->ops = ops; 49 clk_hw->ops = ops;
49 clk_hw->flags = MEMMAP_ADDRESSING; 50 clk_hw->flags = MEMMAP_ADDRESSING;
51 clk_hw->enable_reg = reg;
52 clk_hw->enable_bit = bit_idx;
50 53
51 clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0); 54 init.name = name;
52 if (!clk_hw->enable_reg)
53 goto cleanup;
54
55 if (!of_property_read_u32(node, "ti,bit-shift", &val))
56 clk_hw->enable_bit = val;
57
58 init.name = node->name;
59 init.ops = &ti_interface_clk_ops; 55 init.ops = &ti_interface_clk_ops;
60 init.flags = 0; 56 init.flags = 0;
61 57
62 parent_name = of_clk_get_parent_name(node, 0);
63 if (!parent_name) {
64 pr_err("%s must have a parent\n", node->name);
65 goto cleanup;
66 }
67
68 init.num_parents = 1; 58 init.num_parents = 1;
69 init.parent_names = &parent_name; 59 init.parent_names = &parent_name;
70 60
71 clk = clk_register(NULL, &clk_hw->hw); 61 clk = clk_register(NULL, &clk_hw->hw);
72 62
73 if (!IS_ERR(clk)) { 63 if (IS_ERR(clk))
74 of_clk_add_provider(node, of_clk_src_simple_get, clk); 64 kfree(clk_hw);
65 else
75 omap2_init_clk_hw_omap_clocks(clk); 66 omap2_init_clk_hw_omap_clocks(clk);
67
68 return clk;
69}
70
71#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
72struct clk *ti_clk_register_interface(struct ti_clk *setup)
73{
74 const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
75 u32 reg;
76 struct clk_omap_reg *reg_setup;
77 struct ti_clk_gate *gate;
78
79 gate = setup->data;
80 reg_setup = (struct clk_omap_reg *)&reg;
81 reg_setup->index = gate->module;
82 reg_setup->offset = gate->reg;
83
84 if (gate->flags & CLKF_NO_WAIT)
85 ops = &clkhwops_iclk;
86
87 if (gate->flags & CLKF_HSOTGUSB)
88 ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
89
90 if (gate->flags & CLKF_DSS)
91 ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
92
93 if (gate->flags & CLKF_SSI)
94 ops = &clkhwops_omap3430es2_iclk_ssi_wait;
95
96 if (gate->flags & CLKF_AM35XX)
97 ops = &clkhwops_am35xx_ipss_wait;
98
99 return _register_interface(NULL, setup->name, gate->parent,
100 (void __iomem *)reg, gate->bit_shift, ops);
101}
102#endif
103
104static void __init _of_ti_interface_clk_setup(struct device_node *node,
105 const struct clk_hw_omap_ops *ops)
106{
107 struct clk *clk;
108 const char *parent_name;
109 void __iomem *reg;
110 u8 enable_bit = 0;
111 u32 val;
112
113 reg = ti_clk_get_reg_addr(node, 0);
114 if (!reg)
115 return;
116
117 if (!of_property_read_u32(node, "ti,bit-shift", &val))
118 enable_bit = val;
119
120 parent_name = of_clk_get_parent_name(node, 0);
121 if (!parent_name) {
122 pr_err("%s must have a parent\n", node->name);
76 return; 123 return;
77 } 124 }
78 125
79cleanup: 126 clk = _register_interface(NULL, node->name, parent_name, reg,
80 kfree(clk_hw); 127 enable_bit, ops);
128
129 if (!IS_ERR(clk))
130 of_clk_add_provider(node, of_clk_src_simple_get, clk);
81} 131}
82 132
83static void __init of_ti_interface_clk_setup(struct device_node *node) 133static void __init of_ti_interface_clk_setup(struct device_node *node)
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index e9d650e51287..728e253606bc 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/ti.h> 23#include <linux/clk/ti.h>
24#include "clock.h"
24 25
25#undef pr_fmt 26#undef pr_fmt
26#define pr_fmt(fmt) "%s: " fmt, __func__ 27#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -144,6 +145,39 @@ static struct clk *_register_mux(struct device *dev, const char *name,
144 return clk; 145 return clk;
145} 146}
146 147
148struct clk *ti_clk_register_mux(struct ti_clk *setup)
149{
150 struct ti_clk_mux *mux;
151 u32 flags;
152 u8 mux_flags = 0;
153 struct clk_omap_reg *reg_setup;
154 u32 reg;
155 u32 mask;
156
157 reg_setup = (struct clk_omap_reg *)&reg;
158
159 mux = setup->data;
160 flags = CLK_SET_RATE_NO_REPARENT;
161
162 mask = mux->num_parents;
163 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
164 mask--;
165
166 mask = (1 << fls(mask)) - 1;
167 reg_setup->index = mux->module;
168 reg_setup->offset = mux->reg;
169
170 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
171 mux_flags |= CLK_MUX_INDEX_ONE;
172
173 if (mux->flags & CLKF_SET_RATE_PARENT)
174 flags |= CLK_SET_RATE_PARENT;
175
176 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
177 flags, (void __iomem *)reg, mux->bit_shift, mask,
178 mux_flags, NULL, NULL);
179}
180
147/** 181/**
148 * of_mux_clk_setup - Setup function for simple mux rate clock 182 * of_mux_clk_setup - Setup function for simple mux rate clock
149 * @node: DT node for the clock 183 * @node: DT node for the clock
@@ -194,8 +228,9 @@ static void of_mux_clk_setup(struct device_node *node)
194 228
195 mask = (1 << fls(mask)) - 1; 229 mask = (1 << fls(mask)) - 1;
196 230
197 clk = _register_mux(NULL, node->name, parent_names, num_parents, flags, 231 clk = _register_mux(NULL, node->name, parent_names, num_parents,
198 reg, shift, mask, clk_mux_flags, NULL, NULL); 232 flags, reg, shift, mask, clk_mux_flags, NULL,
233 NULL);
199 234
200 if (!IS_ERR(clk)) 235 if (!IS_ERR(clk))
201 of_clk_add_provider(node, of_clk_src_simple_get, clk); 236 of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -205,6 +240,37 @@ cleanup:
205} 240}
206CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup); 241CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
207 242
243struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
244{
245 struct clk_mux *mux;
246 struct clk_omap_reg *reg;
247 int num_parents;
248
249 if (!setup)
250 return NULL;
251
252 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
253 if (!mux)
254 return ERR_PTR(-ENOMEM);
255
256 reg = (struct clk_omap_reg *)&mux->reg;
257
258 mux->shift = setup->bit_shift;
259
260 reg->index = setup->module;
261 reg->offset = setup->reg;
262
263 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
264 mux->flags |= CLK_MUX_INDEX_ONE;
265
266 num_parents = setup->num_parents;
267
268 mux->mask = num_parents - 1;
269 mux->mask = (1 << fls(mux->mask)) - 1;
270
271 return &mux->hw;
272}
273
208static void __init of_ti_composite_mux_clk_setup(struct device_node *node) 274static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
209{ 275{
210 struct clk_mux *mux; 276 struct clk_mux *mux;
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
index bd4769a84485..0e950769ed03 100644
--- a/drivers/clk/ux500/clk-prcc.c
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -8,7 +8,6 @@
8 */ 8 */
9 9
10#include <linux/clk-provider.h> 10#include <linux/clk-provider.h>
11#include <linux/clk-private.h>
12#include <linux/slab.h> 11#include <linux/slab.h>
13#include <linux/io.h> 12#include <linux/io.h>
14#include <linux/err.h> 13#include <linux/err.h>
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index e2d63bc47436..bf63c96acb1a 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -8,7 +8,6 @@
8 */ 8 */
9 9
10#include <linux/clk-provider.h> 10#include <linux/clk-provider.h>
11#include <linux/clk-private.h>
12#include <linux/mfd/dbx500-prcmu.h> 11#include <linux/mfd/dbx500-prcmu.h>
13#include <linux/slab.h> 12#include <linux/slab.h>
14#include <linux/io.h> 13#include <linux/io.h>
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 9037bebd69f7..f870aad57711 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -303,6 +303,7 @@ static void __init zynq_clk_setup(struct device_node *np)
303 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], 303 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
304 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 304 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
305 26, 0, &armclk_lock); 305 26, 0, &armclk_lock);
306 clk_prepare_enable(clks[cpu_2x]);
306 307
307 clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 308 clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
308 4 + 2 * tmp); 309 4 + 2 * tmp);
diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc
index 72564b701b4a..7ea24413cee6 100644
--- a/drivers/cpufreq/Kconfig.powerpc
+++ b/drivers/cpufreq/Kconfig.powerpc
@@ -26,7 +26,7 @@ config CPU_FREQ_MAPLE
26config PPC_CORENET_CPUFREQ 26config PPC_CORENET_CPUFREQ
27 tristate "CPU frequency scaling driver for Freescale E500MC SoCs" 27 tristate "CPU frequency scaling driver for Freescale E500MC SoCs"
28 depends on PPC_E500MC && OF && COMMON_CLK 28 depends on PPC_E500MC && OF && COMMON_CLK
29 select CLK_PPC_CORENET 29 select CLK_QORIQ
30 help 30 help
31 This adds the CPUFreq driver support for Freescale e500mc, 31 This adds the CPUFreq driver support for Freescale e500mc,
32 e5500 and e6500 series SoCs which are capable of changing 32 e5500 and e6500 series SoCs which are capable of changing
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 6af0a28ba37d..e8a4218b5726 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -21,8 +21,6 @@
21#include <linux/err.h> 21#include <linux/err.h>
22 22
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/clk/sunxi.h>
25
26#include <linux/gpio.h> 24#include <linux/gpio.h>
27#include <linux/platform_device.h> 25#include <linux/platform_device.h>
28#include <linux/spinlock.h> 26#include <linux/spinlock.h>
@@ -229,6 +227,8 @@ struct sunxi_mmc_host {
229 /* clock management */ 227 /* clock management */
230 struct clk *clk_ahb; 228 struct clk *clk_ahb;
231 struct clk *clk_mmc; 229 struct clk *clk_mmc;
230 struct clk *clk_sample;
231 struct clk *clk_output;
232 232
233 /* irq */ 233 /* irq */
234 spinlock_t lock; 234 spinlock_t lock;
@@ -653,26 +653,31 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
653 653
654 /* determine delays */ 654 /* determine delays */
655 if (rate <= 400000) { 655 if (rate <= 400000) {
656 oclk_dly = 0; 656 oclk_dly = 180;
657 sclk_dly = 7; 657 sclk_dly = 42;
658 } else if (rate <= 25000000) { 658 } else if (rate <= 25000000) {
659 oclk_dly = 0; 659 oclk_dly = 180;
660 sclk_dly = 5; 660 sclk_dly = 75;
661 } else if (rate <= 50000000) { 661 } else if (rate <= 50000000) {
662 if (ios->timing == MMC_TIMING_UHS_DDR50) { 662 if (ios->timing == MMC_TIMING_UHS_DDR50) {
663 oclk_dly = 2; 663 oclk_dly = 60;
664 sclk_dly = 4; 664 sclk_dly = 120;
665 } else { 665 } else {
666 oclk_dly = 3; 666 oclk_dly = 90;
667 sclk_dly = 5; 667 sclk_dly = 150;
668 } 668 }
669 } else if (rate <= 100000000) {
670 oclk_dly = 6;
671 sclk_dly = 24;
672 } else if (rate <= 200000000) {
673 oclk_dly = 3;
674 sclk_dly = 12;
669 } else { 675 } else {
670 /* rate > 50000000 */ 676 return -EINVAL;
671 oclk_dly = 2;
672 sclk_dly = 4;
673 } 677 }
674 678
675 clk_sunxi_mmc_phase_control(host->clk_mmc, sclk_dly, oclk_dly); 679 clk_set_phase(host->clk_sample, sclk_dly);
680 clk_set_phase(host->clk_output, oclk_dly);
676 681
677 return sunxi_mmc_oclk_onoff(host, 1); 682 return sunxi_mmc_oclk_onoff(host, 1);
678} 683}
@@ -913,6 +918,18 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
913 return PTR_ERR(host->clk_mmc); 918 return PTR_ERR(host->clk_mmc);
914 } 919 }
915 920
921 host->clk_output = devm_clk_get(&pdev->dev, "output");
922 if (IS_ERR(host->clk_output)) {
923 dev_err(&pdev->dev, "Could not get output clock\n");
924 return PTR_ERR(host->clk_output);
925 }
926
927 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
928 if (IS_ERR(host->clk_sample)) {
929 dev_err(&pdev->dev, "Could not get sample clock\n");
930 return PTR_ERR(host->clk_sample);
931 }
932
916 host->reset = devm_reset_control_get(&pdev->dev, "ahb"); 933 host->reset = devm_reset_control_get(&pdev->dev, "ahb");
917 934
918 ret = clk_prepare_enable(host->clk_ahb); 935 ret = clk_prepare_enable(host->clk_ahb);
@@ -927,11 +944,23 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
927 goto error_disable_clk_ahb; 944 goto error_disable_clk_ahb;
928 } 945 }
929 946
947 ret = clk_prepare_enable(host->clk_output);
948 if (ret) {
949 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
950 goto error_disable_clk_mmc;
951 }
952
953 ret = clk_prepare_enable(host->clk_sample);
954 if (ret) {
955 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
956 goto error_disable_clk_output;
957 }
958
930 if (!IS_ERR(host->reset)) { 959 if (!IS_ERR(host->reset)) {
931 ret = reset_control_deassert(host->reset); 960 ret = reset_control_deassert(host->reset);
932 if (ret) { 961 if (ret) {
933 dev_err(&pdev->dev, "reset err %d\n", ret); 962 dev_err(&pdev->dev, "reset err %d\n", ret);
934 goto error_disable_clk_mmc; 963 goto error_disable_clk_sample;
935 } 964 }
936 } 965 }
937 966
@@ -950,6 +979,10 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
950error_assert_reset: 979error_assert_reset:
951 if (!IS_ERR(host->reset)) 980 if (!IS_ERR(host->reset))
952 reset_control_assert(host->reset); 981 reset_control_assert(host->reset);
982error_disable_clk_sample:
983 clk_disable_unprepare(host->clk_sample);
984error_disable_clk_output:
985 clk_disable_unprepare(host->clk_output);
953error_disable_clk_mmc: 986error_disable_clk_mmc:
954 clk_disable_unprepare(host->clk_mmc); 987 clk_disable_unprepare(host->clk_mmc);
955error_disable_clk_ahb: 988error_disable_clk_ahb:
diff --git a/include/dt-bindings/clock/alphascale,asm9260.h b/include/dt-bindings/clock/alphascale,asm9260.h
new file mode 100644
index 000000000000..04e8db27daf0
--- /dev/null
+++ b/include/dt-bindings/clock/alphascale,asm9260.h
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_ASM9260_H
15#define _DT_BINDINGS_CLK_ASM9260_H
16
17/* ahb gate */
18#define CLKID_AHB_ROM 0
19#define CLKID_AHB_RAM 1
20#define CLKID_AHB_GPIO 2
21#define CLKID_AHB_MAC 3
22#define CLKID_AHB_EMI 4
23#define CLKID_AHB_USB0 5
24#define CLKID_AHB_USB1 6
25#define CLKID_AHB_DMA0 7
26#define CLKID_AHB_DMA1 8
27#define CLKID_AHB_UART0 9
28#define CLKID_AHB_UART1 10
29#define CLKID_AHB_UART2 11
30#define CLKID_AHB_UART3 12
31#define CLKID_AHB_UART4 13
32#define CLKID_AHB_UART5 14
33#define CLKID_AHB_UART6 15
34#define CLKID_AHB_UART7 16
35#define CLKID_AHB_UART8 17
36#define CLKID_AHB_UART9 18
37#define CLKID_AHB_I2S0 19
38#define CLKID_AHB_I2C0 20
39#define CLKID_AHB_I2C1 21
40#define CLKID_AHB_SSP0 22
41#define CLKID_AHB_IOCONFIG 23
42#define CLKID_AHB_WDT 24
43#define CLKID_AHB_CAN0 25
44#define CLKID_AHB_CAN1 26
45#define CLKID_AHB_MPWM 27
46#define CLKID_AHB_SPI0 28
47#define CLKID_AHB_SPI1 29
48#define CLKID_AHB_QEI 30
49#define CLKID_AHB_QUADSPI0 31
50#define CLKID_AHB_CAMIF 32
51#define CLKID_AHB_LCDIF 33
52#define CLKID_AHB_TIMER0 34
53#define CLKID_AHB_TIMER1 35
54#define CLKID_AHB_TIMER2 36
55#define CLKID_AHB_TIMER3 37
56#define CLKID_AHB_IRQ 38
57#define CLKID_AHB_RTC 39
58#define CLKID_AHB_NAND 40
59#define CLKID_AHB_ADC0 41
60#define CLKID_AHB_LED 42
61#define CLKID_AHB_DAC0 43
62#define CLKID_AHB_LCD 44
63#define CLKID_AHB_I2S1 45
64#define CLKID_AHB_MAC1 46
65
66/* devider */
67#define CLKID_SYS_CPU 47
68#define CLKID_SYS_AHB 48
69#define CLKID_SYS_I2S0M 49
70#define CLKID_SYS_I2S0S 50
71#define CLKID_SYS_I2S1M 51
72#define CLKID_SYS_I2S1S 52
73#define CLKID_SYS_UART0 53
74#define CLKID_SYS_UART1 54
75#define CLKID_SYS_UART2 55
76#define CLKID_SYS_UART3 56
77#define CLKID_SYS_UART4 56
78#define CLKID_SYS_UART5 57
79#define CLKID_SYS_UART6 58
80#define CLKID_SYS_UART7 59
81#define CLKID_SYS_UART8 60
82#define CLKID_SYS_UART9 61
83#define CLKID_SYS_SPI0 62
84#define CLKID_SYS_SPI1 63
85#define CLKID_SYS_QUADSPI 64
86#define CLKID_SYS_SSP0 65
87#define CLKID_SYS_NAND 66
88#define CLKID_SYS_TRACE 67
89#define CLKID_SYS_CAMM 68
90#define CLKID_SYS_WDT 69
91#define CLKID_SYS_CLKOUT 70
92#define CLKID_SYS_MAC 71
93#define CLKID_SYS_LCD 72
94#define CLKID_SYS_ADCANA 73
95
96#define MAX_CLKS 74
97#endif
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c622d0..c4b1676ea674 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
262#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ 262#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 263#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 264#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
265#define CLK_DIV_ACP 456
266#define CLK_DIV_DMC 457
267#define CLK_DIV_C2C 458 /* Exynos4x12 only */
268#define CLK_DIV_GDL 459
269#define CLK_DIV_GDR 460
265 270
266/* must be greater than maximal clock id */ 271/* must be greater than maximal clock id */
267#define CLK_NR_CLKS 456 272#define CLK_NR_CLKS 461
268 273
269#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 274#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b07ae7..e33c75a3c09d 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -17,7 +17,11 @@
17#define DOUT_SCLK_CC_PLL 4 17#define DOUT_SCLK_CC_PLL 4
18#define DOUT_SCLK_MFC_PLL 5 18#define DOUT_SCLK_MFC_PLL 5
19#define DOUT_ACLK_CCORE_133 6 19#define DOUT_ACLK_CCORE_133 6
20#define TOPC_NR_CLK 7 20#define DOUT_ACLK_MSCL_532 7
21#define ACLK_MSCL_532 8
22#define DOUT_SCLK_AUD_PLL 9
23#define FOUT_AUD_PLL 10
24#define TOPC_NR_CLK 11
21 25
22/* TOP0 */ 26/* TOP0 */
23#define DOUT_ACLK_PERIC1 1 27#define DOUT_ACLK_PERIC1 1
@@ -26,7 +30,15 @@
26#define CLK_SCLK_UART1 4 30#define CLK_SCLK_UART1 4
27#define CLK_SCLK_UART2 5 31#define CLK_SCLK_UART2 5
28#define CLK_SCLK_UART3 6 32#define CLK_SCLK_UART3 6
29#define TOP0_NR_CLK 7 33#define CLK_SCLK_SPI0 7
34#define CLK_SCLK_SPI1 8
35#define CLK_SCLK_SPI2 9
36#define CLK_SCLK_SPI3 10
37#define CLK_SCLK_SPI4 11
38#define CLK_SCLK_SPDIF 12
39#define CLK_SCLK_PCM1 13
40#define CLK_SCLK_I2S1 14
41#define TOP0_NR_CLK 15
30 42
31/* TOP1 */ 43/* TOP1 */
32#define DOUT_ACLK_FSYS1_200 1 44#define DOUT_ACLK_FSYS1_200 1
@@ -70,7 +82,23 @@
70#define PCLK_HSI2C6 9 82#define PCLK_HSI2C6 9
71#define PCLK_HSI2C7 10 83#define PCLK_HSI2C7 10
72#define PCLK_HSI2C8 11 84#define PCLK_HSI2C8 11
73#define PERIC1_NR_CLK 12 85#define PCLK_SPI0 12
86#define PCLK_SPI1 13
87#define PCLK_SPI2 14
88#define PCLK_SPI3 15
89#define PCLK_SPI4 16
90#define SCLK_SPI0 17
91#define SCLK_SPI1 18
92#define SCLK_SPI2 19
93#define SCLK_SPI3 20
94#define SCLK_SPI4 21
95#define PCLK_I2S1 22
96#define PCLK_PCM1 23
97#define PCLK_SPDIF 24
98#define SCLK_I2S1 25
99#define SCLK_PCM1 26
100#define SCLK_SPDIF 27
101#define PERIC1_NR_CLK 28
74 102
75/* PERIS */ 103/* PERIS */
76#define PCLK_CHIPID 1 104#define PCLK_CHIPID 1
@@ -82,11 +110,63 @@
82 110
83/* FSYS0 */ 111/* FSYS0 */
84#define ACLK_MMC2 1 112#define ACLK_MMC2 1
85#define FSYS0_NR_CLK 2 113#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
114#define ACLK_USBDRD300 3
115#define SCLK_USBDRD300_SUSPENDCLK 4
116#define SCLK_USBDRD300_REFCLK 5
117#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
118#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
119#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
120#define ACLK_PDMA0 9
121#define ACLK_PDMA1 10
122#define FSYS0_NR_CLK 11
86 123
87/* FSYS1 */ 124/* FSYS1 */
88#define ACLK_MMC1 1 125#define ACLK_MMC1 1
89#define ACLK_MMC0 2 126#define ACLK_MMC0 2
90#define FSYS1_NR_CLK 3 127#define FSYS1_NR_CLK 3
91 128
129/* MSCL */
130#define USERMUX_ACLK_MSCL_532 1
131#define DOUT_PCLK_MSCL 2
132#define ACLK_MSCL_0 3
133#define ACLK_MSCL_1 4
134#define ACLK_JPEG 5
135#define ACLK_G2D 6
136#define ACLK_LH_ASYNC_SI_MSCL_0 7
137#define ACLK_LH_ASYNC_SI_MSCL_1 8
138#define ACLK_AXI2ACEL_BRIDGE 9
139#define ACLK_XIU_MSCLX_0 10
140#define ACLK_XIU_MSCLX_1 11
141#define ACLK_QE_MSCL_0 12
142#define ACLK_QE_MSCL_1 13
143#define ACLK_QE_JPEG 14
144#define ACLK_QE_G2D 15
145#define ACLK_PPMU_MSCL_0 16
146#define ACLK_PPMU_MSCL_1 17
147#define ACLK_MSCLNP_133 18
148#define ACLK_AHB2APB_MSCL0P 19
149#define ACLK_AHB2APB_MSCL1P 20
150
151#define PCLK_MSCL_0 21
152#define PCLK_MSCL_1 22
153#define PCLK_JPEG 23
154#define PCLK_G2D 24
155#define PCLK_QE_MSCL_0 25
156#define PCLK_QE_MSCL_1 26
157#define PCLK_QE_JPEG 27
158#define PCLK_QE_G2D 28
159#define PCLK_PPMU_MSCL_0 29
160#define PCLK_PPMU_MSCL_1 30
161#define PCLK_AXI2ACEL_BRIDGE 31
162#define PCLK_PMU_MSCL 32
163#define MSCL_NR_CLK 33
164
165/* AUD */
166#define SCLK_I2S 1
167#define SCLK_PCM 2
168#define PCLK_I2S 3
169#define PCLK_PCM 4
170#define ACLK_ADMA 5
171#define AUD_NR_CLK 6
92#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 172#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index b857cadb0bd4..04fb29ae30e6 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -238,7 +238,6 @@
238#define PLL0_VOTE 221 238#define PLL0_VOTE 221
239#define PLL3 222 239#define PLL3 222
240#define PLL3_VOTE 223 240#define PLL3_VOTE 223
241#define PLL4 224
242#define PLL4_VOTE 225 241#define PLL4_VOTE 225
243#define PLL8 226 242#define PLL8 226
244#define PLL8_VOTE 227 243#define PLL8_VOTE 227
diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
new file mode 100644
index 000000000000..4e944b85c56d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
15#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SPDIF_SRC 9
27#define SPDIF_CLK 10
28#define AHBIX_CLK 11
29
30#endif
diff --git a/include/dt-bindings/clock/qcom,lcc-msm8960.h b/include/dt-bindings/clock/qcom,lcc-msm8960.h
new file mode 100644
index 000000000000..4fb2aa64d9fe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-msm8960.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
15#define _DT_BINDINGS_CLK_LCC_MSM8960_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SLIMBUS_SRC 9
27#define AUDIO_SLIMBUS_CLK 10
28#define SPS_SLIMBUS_CLK 11
29#define CODEC_I2S_MIC_OSR_SRC 12
30#define CODEC_I2S_MIC_OSR_CLK 13
31#define CODEC_I2S_MIC_DIV_CLK 14
32#define CODEC_I2S_MIC_BIT_DIV_CLK 15
33#define CODEC_I2S_MIC_BIT_CLK 16
34#define SPARE_I2S_MIC_OSR_SRC 17
35#define SPARE_I2S_MIC_OSR_CLK 18
36#define SPARE_I2S_MIC_DIV_CLK 19
37#define SPARE_I2S_MIC_BIT_DIV_CLK 20
38#define SPARE_I2S_MIC_BIT_CLK 21
39#define CODEC_I2S_SPKR_OSR_SRC 22
40#define CODEC_I2S_SPKR_OSR_CLK 23
41#define CODEC_I2S_SPKR_DIV_CLK 24
42#define CODEC_I2S_SPKR_BIT_DIV_CLK 25
43#define CODEC_I2S_SPKR_BIT_CLK 26
44#define SPARE_I2S_SPKR_OSR_SRC 27
45#define SPARE_I2S_SPKR_OSR_CLK 28
46#define SPARE_I2S_SPKR_DIV_CLK 29
47#define SPARE_I2S_SPKR_BIT_DIV_CLK 30
48#define SPARE_I2S_SPKR_BIT_CLK 31
49
50#endif
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
new file mode 100644
index 000000000000..ae2eb17a1658
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -0,0 +1,345 @@
1/*
2 * This header provides constants for binding nvidia,tegra124-car or
3 * nvidia,tegra132-car.
4 *
5 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
6 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
8 * this case, those clocks are assigned IDs above 185 in order to highlight
9 * this issue. Implementations that interpret these clock IDs as bit values
10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
11 * explicitly handle these special cases.
12 *
13 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
14 * above.
15 */
16
17#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
18#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
19
20/* 0 */
21/* 1 */
22/* 2 */
23#define TEGRA124_CLK_ISPB 3
24#define TEGRA124_CLK_RTC 4
25#define TEGRA124_CLK_TIMER 5
26#define TEGRA124_CLK_UARTA 6
27/* 7 (register bit affects uartb and vfir) */
28/* 8 */
29#define TEGRA124_CLK_SDMMC2 9
30/* 10 (register bit affects spdif_in and spdif_out) */
31#define TEGRA124_CLK_I2S1 11
32#define TEGRA124_CLK_I2C1 12
33/* 13 */
34#define TEGRA124_CLK_SDMMC1 14
35#define TEGRA124_CLK_SDMMC4 15
36/* 16 */
37#define TEGRA124_CLK_PWM 17
38#define TEGRA124_CLK_I2S2 18
39/* 20 (register bit affects vi and vi_sensor) */
40/* 21 */
41#define TEGRA124_CLK_USBD 22
42#define TEGRA124_CLK_ISP 23
43/* 26 */
44/* 25 */
45#define TEGRA124_CLK_DISP2 26
46#define TEGRA124_CLK_DISP1 27
47#define TEGRA124_CLK_HOST1X 28
48#define TEGRA124_CLK_VCP 29
49#define TEGRA124_CLK_I2S0 30
50/* 31 */
51
52#define TEGRA124_CLK_MC 32
53/* 33 */
54#define TEGRA124_CLK_APBDMA 34
55/* 35 */
56#define TEGRA124_CLK_KBC 36
57/* 37 */
58/* 38 */
59/* 39 (register bit affects fuse and fuse_burn) */
60#define TEGRA124_CLK_KFUSE 40
61#define TEGRA124_CLK_SBC1 41
62#define TEGRA124_CLK_NOR 42
63/* 43 */
64#define TEGRA124_CLK_SBC2 44
65/* 45 */
66#define TEGRA124_CLK_SBC3 46
67#define TEGRA124_CLK_I2C5 47
68#define TEGRA124_CLK_DSIA 48
69/* 49 */
70#define TEGRA124_CLK_MIPI 50
71#define TEGRA124_CLK_HDMI 51
72#define TEGRA124_CLK_CSI 52
73/* 53 */
74#define TEGRA124_CLK_I2C2 54
75#define TEGRA124_CLK_UARTC 55
76#define TEGRA124_CLK_MIPI_CAL 56
77#define TEGRA124_CLK_EMC 57
78#define TEGRA124_CLK_USB2 58
79#define TEGRA124_CLK_USB3 59
80/* 60 */
81#define TEGRA124_CLK_VDE 61
82#define TEGRA124_CLK_BSEA 62
83#define TEGRA124_CLK_BSEV 63
84
85/* 64 */
86#define TEGRA124_CLK_UARTD 65
87/* 66 */
88#define TEGRA124_CLK_I2C3 67
89#define TEGRA124_CLK_SBC4 68
90#define TEGRA124_CLK_SDMMC3 69
91#define TEGRA124_CLK_PCIE 70
92#define TEGRA124_CLK_OWR 71
93#define TEGRA124_CLK_AFI 72
94#define TEGRA124_CLK_CSITE 73
95/* 74 */
96/* 75 */
97#define TEGRA124_CLK_LA 76
98#define TEGRA124_CLK_TRACE 77
99#define TEGRA124_CLK_SOC_THERM 78
100#define TEGRA124_CLK_DTV 79
101/* 80 */
102#define TEGRA124_CLK_I2CSLOW 81
103#define TEGRA124_CLK_DSIB 82
104#define TEGRA124_CLK_TSEC 83
105/* 84 */
106/* 85 */
107/* 86 */
108/* 87 */
109/* 88 */
110#define TEGRA124_CLK_XUSB_HOST 89
111/* 90 */
112#define TEGRA124_CLK_MSENC 91
113#define TEGRA124_CLK_CSUS 92
114/* 93 */
115/* 94 */
116/* 95 (bit affects xusb_dev and xusb_dev_src) */
117
118/* 96 */
119/* 97 */
120/* 98 */
121#define TEGRA124_CLK_MSELECT 99
122#define TEGRA124_CLK_TSENSOR 100
123#define TEGRA124_CLK_I2S3 101
124#define TEGRA124_CLK_I2S4 102
125#define TEGRA124_CLK_I2C4 103
126#define TEGRA124_CLK_SBC5 104
127#define TEGRA124_CLK_SBC6 105
128#define TEGRA124_CLK_D_AUDIO 106
129#define TEGRA124_CLK_APBIF 107
130#define TEGRA124_CLK_DAM0 108
131#define TEGRA124_CLK_DAM1 109
132#define TEGRA124_CLK_DAM2 110
133#define TEGRA124_CLK_HDA2CODEC_2X 111
134/* 112 */
135#define TEGRA124_CLK_AUDIO0_2X 113
136#define TEGRA124_CLK_AUDIO1_2X 114
137#define TEGRA124_CLK_AUDIO2_2X 115
138#define TEGRA124_CLK_AUDIO3_2X 116
139#define TEGRA124_CLK_AUDIO4_2X 117
140#define TEGRA124_CLK_SPDIF_2X 118
141#define TEGRA124_CLK_ACTMON 119
142#define TEGRA124_CLK_EXTERN1 120
143#define TEGRA124_CLK_EXTERN2 121
144#define TEGRA124_CLK_EXTERN3 122
145#define TEGRA124_CLK_SATA_OOB 123
146#define TEGRA124_CLK_SATA 124
147#define TEGRA124_CLK_HDA 125
148/* 126 */
149#define TEGRA124_CLK_SE 127
150
151#define TEGRA124_CLK_HDA2HDMI 128
152#define TEGRA124_CLK_SATA_COLD 129
153/* 130 */
154/* 131 */
155/* 132 */
156/* 133 */
157/* 134 */
158/* 135 */
159/* 136 */
160/* 137 */
161/* 138 */
162/* 139 */
163/* 140 */
164/* 141 */
165/* 142 */
166/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
167/* xusb_host_src and xusb_ss_src) */
168#define TEGRA124_CLK_CILAB 144
169#define TEGRA124_CLK_CILCD 145
170#define TEGRA124_CLK_CILE 146
171#define TEGRA124_CLK_DSIALP 147
172#define TEGRA124_CLK_DSIBLP 148
173#define TEGRA124_CLK_ENTROPY 149
174#define TEGRA124_CLK_DDS 150
175/* 151 */
176#define TEGRA124_CLK_DP2 152
177#define TEGRA124_CLK_AMX 153
178#define TEGRA124_CLK_ADX 154
179/* 155 (bit affects dfll_ref and dfll_soc) */
180#define TEGRA124_CLK_XUSB_SS 156
181/* 157 */
182/* 158 */
183/* 159 */
184
185/* 160 */
186/* 161 */
187/* 162 */
188/* 163 */
189/* 164 */
190/* 165 */
191#define TEGRA124_CLK_I2C6 166
192/* 167 */
193/* 168 */
194/* 169 */
195/* 170 */
196#define TEGRA124_CLK_VIM2_CLK 171
197/* 172 */
198/* 173 */
199/* 174 */
200/* 175 */
201#define TEGRA124_CLK_HDMI_AUDIO 176
202#define TEGRA124_CLK_CLK72MHZ 177
203#define TEGRA124_CLK_VIC03 178
204/* 179 */
205#define TEGRA124_CLK_ADX1 180
206#define TEGRA124_CLK_DPAUX 181
207#define TEGRA124_CLK_SOR0 182
208/* 183 */
209#define TEGRA124_CLK_GPU 184
210#define TEGRA124_CLK_AMX1 185
211/* 186 */
212/* 187 */
213/* 188 */
214/* 189 */
215/* 190 */
216/* 191 */
217#define TEGRA124_CLK_UARTB 192
218#define TEGRA124_CLK_VFIR 193
219#define TEGRA124_CLK_SPDIF_IN 194
220#define TEGRA124_CLK_SPDIF_OUT 195
221#define TEGRA124_CLK_VI 196
222#define TEGRA124_CLK_VI_SENSOR 197
223#define TEGRA124_CLK_FUSE 198
224#define TEGRA124_CLK_FUSE_BURN 199
225#define TEGRA124_CLK_CLK_32K 200
226#define TEGRA124_CLK_CLK_M 201
227#define TEGRA124_CLK_CLK_M_DIV2 202
228#define TEGRA124_CLK_CLK_M_DIV4 203
229#define TEGRA124_CLK_PLL_REF 204
230#define TEGRA124_CLK_PLL_C 205
231#define TEGRA124_CLK_PLL_C_OUT1 206
232#define TEGRA124_CLK_PLL_C2 207
233#define TEGRA124_CLK_PLL_C3 208
234#define TEGRA124_CLK_PLL_M 209
235#define TEGRA124_CLK_PLL_M_OUT1 210
236#define TEGRA124_CLK_PLL_P 211
237#define TEGRA124_CLK_PLL_P_OUT1 212
238#define TEGRA124_CLK_PLL_P_OUT2 213
239#define TEGRA124_CLK_PLL_P_OUT3 214
240#define TEGRA124_CLK_PLL_P_OUT4 215
241#define TEGRA124_CLK_PLL_A 216
242#define TEGRA124_CLK_PLL_A_OUT0 217
243#define TEGRA124_CLK_PLL_D 218
244#define TEGRA124_CLK_PLL_D_OUT0 219
245#define TEGRA124_CLK_PLL_D2 220
246#define TEGRA124_CLK_PLL_D2_OUT0 221
247#define TEGRA124_CLK_PLL_U 222
248#define TEGRA124_CLK_PLL_U_480M 223
249
250#define TEGRA124_CLK_PLL_U_60M 224
251#define TEGRA124_CLK_PLL_U_48M 225
252#define TEGRA124_CLK_PLL_U_12M 226
253/* 227 */
254/* 228 */
255#define TEGRA124_CLK_PLL_RE_VCO 229
256#define TEGRA124_CLK_PLL_RE_OUT 230
257#define TEGRA124_CLK_PLL_E 231
258#define TEGRA124_CLK_SPDIF_IN_SYNC 232
259#define TEGRA124_CLK_I2S0_SYNC 233
260#define TEGRA124_CLK_I2S1_SYNC 234
261#define TEGRA124_CLK_I2S2_SYNC 235
262#define TEGRA124_CLK_I2S3_SYNC 236
263#define TEGRA124_CLK_I2S4_SYNC 237
264#define TEGRA124_CLK_VIMCLK_SYNC 238
265#define TEGRA124_CLK_AUDIO0 239
266#define TEGRA124_CLK_AUDIO1 240
267#define TEGRA124_CLK_AUDIO2 241
268#define TEGRA124_CLK_AUDIO3 242
269#define TEGRA124_CLK_AUDIO4 243
270#define TEGRA124_CLK_SPDIF 244
271#define TEGRA124_CLK_CLK_OUT_1 245
272#define TEGRA124_CLK_CLK_OUT_2 246
273#define TEGRA124_CLK_CLK_OUT_3 247
274#define TEGRA124_CLK_BLINK 248
275/* 249 */
276/* 250 */
277/* 251 */
278#define TEGRA124_CLK_XUSB_HOST_SRC 252
279#define TEGRA124_CLK_XUSB_FALCON_SRC 253
280#define TEGRA124_CLK_XUSB_FS_SRC 254
281#define TEGRA124_CLK_XUSB_SS_SRC 255
282
283#define TEGRA124_CLK_XUSB_DEV_SRC 256
284#define TEGRA124_CLK_XUSB_DEV 257
285#define TEGRA124_CLK_XUSB_HS_SRC 258
286#define TEGRA124_CLK_SCLK 259
287#define TEGRA124_CLK_HCLK 260
288#define TEGRA124_CLK_PCLK 261
289/* 262 */
290/* 263 */
291#define TEGRA124_CLK_DFLL_REF 264
292#define TEGRA124_CLK_DFLL_SOC 265
293#define TEGRA124_CLK_VI_SENSOR2 266
294#define TEGRA124_CLK_PLL_P_OUT5 267
295#define TEGRA124_CLK_CML0 268
296#define TEGRA124_CLK_CML1 269
297#define TEGRA124_CLK_PLL_C4 270
298#define TEGRA124_CLK_PLL_DP 271
299#define TEGRA124_CLK_PLL_E_MUX 272
300#define TEGRA124_CLK_PLLD_DSI 273
301/* 274 */
302/* 275 */
303/* 276 */
304/* 277 */
305/* 278 */
306/* 279 */
307/* 280 */
308/* 281 */
309/* 282 */
310/* 283 */
311/* 284 */
312/* 285 */
313/* 286 */
314/* 287 */
315
316/* 288 */
317/* 289 */
318/* 290 */
319/* 291 */
320/* 292 */
321/* 293 */
322/* 294 */
323/* 295 */
324/* 296 */
325/* 297 */
326/* 298 */
327/* 299 */
328#define TEGRA124_CLK_AUDIO0_MUX 300
329#define TEGRA124_CLK_AUDIO1_MUX 301
330#define TEGRA124_CLK_AUDIO2_MUX 302
331#define TEGRA124_CLK_AUDIO3_MUX 303
332#define TEGRA124_CLK_AUDIO4_MUX 304
333#define TEGRA124_CLK_SPDIF_MUX 305
334#define TEGRA124_CLK_CLK_OUT_1_MUX 306
335#define TEGRA124_CLK_CLK_OUT_2_MUX 307
336#define TEGRA124_CLK_CLK_OUT_3_MUX 308
337/* 309 */
338/* 310 */
339#define TEGRA124_CLK_SOR0_LVDS 311
340#define TEGRA124_CLK_XUSB_SS_DIV2 312
341
342#define TEGRA124_CLK_PLL_M_UD 313
343#define TEGRA124_CLK_PLL_C_UD 314
344
345#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index af9bc9a3ddbc..2860737f0443 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -1,346 +1,19 @@
1/* 1/*
2 * This header provides constants for binding nvidia,tegra124-car. 2 * This header provides Tegra124-specific constants for binding
3 * 3 * nvidia,tegra124-car.
4 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7 * this case, those clocks are assigned IDs above 185 in order to highlight
8 * this issue. Implementations that interpret these clock IDs as bit values
9 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10 * explicitly handle these special cases.
11 *
12 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
13 * above.
14 */ 4 */
15 5
6#include <dt-bindings/clock/tegra124-car-common.h>
7
16#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H 8#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
17#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H 9#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
18 10
19/* 0 */ 11#define TEGRA124_CLK_PLL_X 227
20/* 1 */ 12#define TEGRA124_CLK_PLL_X_OUT0 228
21/* 2 */
22#define TEGRA124_CLK_ISPB 3
23#define TEGRA124_CLK_RTC 4
24#define TEGRA124_CLK_TIMER 5
25#define TEGRA124_CLK_UARTA 6
26/* 7 (register bit affects uartb and vfir) */
27/* 8 */
28#define TEGRA124_CLK_SDMMC2 9
29/* 10 (register bit affects spdif_in and spdif_out) */
30#define TEGRA124_CLK_I2S1 11
31#define TEGRA124_CLK_I2C1 12
32/* 13 */
33#define TEGRA124_CLK_SDMMC1 14
34#define TEGRA124_CLK_SDMMC4 15
35/* 16 */
36#define TEGRA124_CLK_PWM 17
37#define TEGRA124_CLK_I2S2 18
38/* 20 (register bit affects vi and vi_sensor) */
39/* 21 */
40#define TEGRA124_CLK_USBD 22
41#define TEGRA124_CLK_ISP 23
42/* 26 */
43/* 25 */
44#define TEGRA124_CLK_DISP2 26
45#define TEGRA124_CLK_DISP1 27
46#define TEGRA124_CLK_HOST1X 28
47#define TEGRA124_CLK_VCP 29
48#define TEGRA124_CLK_I2S0 30
49/* 31 */
50
51#define TEGRA124_CLK_MC 32
52/* 33 */
53#define TEGRA124_CLK_APBDMA 34
54/* 35 */
55#define TEGRA124_CLK_KBC 36
56/* 37 */
57/* 38 */
58/* 39 (register bit affects fuse and fuse_burn) */
59#define TEGRA124_CLK_KFUSE 40
60#define TEGRA124_CLK_SBC1 41
61#define TEGRA124_CLK_NOR 42
62/* 43 */
63#define TEGRA124_CLK_SBC2 44
64/* 45 */
65#define TEGRA124_CLK_SBC3 46
66#define TEGRA124_CLK_I2C5 47
67#define TEGRA124_CLK_DSIA 48
68/* 49 */
69#define TEGRA124_CLK_MIPI 50
70#define TEGRA124_CLK_HDMI 51
71#define TEGRA124_CLK_CSI 52
72/* 53 */
73#define TEGRA124_CLK_I2C2 54
74#define TEGRA124_CLK_UARTC 55
75#define TEGRA124_CLK_MIPI_CAL 56
76#define TEGRA124_CLK_EMC 57
77#define TEGRA124_CLK_USB2 58
78#define TEGRA124_CLK_USB3 59
79/* 60 */
80#define TEGRA124_CLK_VDE 61
81#define TEGRA124_CLK_BSEA 62
82#define TEGRA124_CLK_BSEV 63
83
84/* 64 */
85#define TEGRA124_CLK_UARTD 65
86/* 66 */
87#define TEGRA124_CLK_I2C3 67
88#define TEGRA124_CLK_SBC4 68
89#define TEGRA124_CLK_SDMMC3 69
90#define TEGRA124_CLK_PCIE 70
91#define TEGRA124_CLK_OWR 71
92#define TEGRA124_CLK_AFI 72
93#define TEGRA124_CLK_CSITE 73
94/* 74 */
95/* 75 */
96#define TEGRA124_CLK_LA 76
97#define TEGRA124_CLK_TRACE 77
98#define TEGRA124_CLK_SOC_THERM 78
99#define TEGRA124_CLK_DTV 79
100/* 80 */
101#define TEGRA124_CLK_I2CSLOW 81
102#define TEGRA124_CLK_DSIB 82
103#define TEGRA124_CLK_TSEC 83
104/* 84 */
105/* 85 */
106/* 86 */
107/* 87 */
108/* 88 */
109#define TEGRA124_CLK_XUSB_HOST 89
110/* 90 */
111#define TEGRA124_CLK_MSENC 91
112#define TEGRA124_CLK_CSUS 92
113/* 93 */
114/* 94 */
115/* 95 (bit affects xusb_dev and xusb_dev_src) */
116
117/* 96 */
118/* 97 */
119/* 98 */
120#define TEGRA124_CLK_MSELECT 99
121#define TEGRA124_CLK_TSENSOR 100
122#define TEGRA124_CLK_I2S3 101
123#define TEGRA124_CLK_I2S4 102
124#define TEGRA124_CLK_I2C4 103
125#define TEGRA124_CLK_SBC5 104
126#define TEGRA124_CLK_SBC6 105
127#define TEGRA124_CLK_D_AUDIO 106
128#define TEGRA124_CLK_APBIF 107
129#define TEGRA124_CLK_DAM0 108
130#define TEGRA124_CLK_DAM1 109
131#define TEGRA124_CLK_DAM2 110
132#define TEGRA124_CLK_HDA2CODEC_2X 111
133/* 112 */
134#define TEGRA124_CLK_AUDIO0_2X 113
135#define TEGRA124_CLK_AUDIO1_2X 114
136#define TEGRA124_CLK_AUDIO2_2X 115
137#define TEGRA124_CLK_AUDIO3_2X 116
138#define TEGRA124_CLK_AUDIO4_2X 117
139#define TEGRA124_CLK_SPDIF_2X 118
140#define TEGRA124_CLK_ACTMON 119
141#define TEGRA124_CLK_EXTERN1 120
142#define TEGRA124_CLK_EXTERN2 121
143#define TEGRA124_CLK_EXTERN3 122
144#define TEGRA124_CLK_SATA_OOB 123
145#define TEGRA124_CLK_SATA 124
146#define TEGRA124_CLK_HDA 125
147/* 126 */
148#define TEGRA124_CLK_SE 127
149
150#define TEGRA124_CLK_HDA2HDMI 128
151#define TEGRA124_CLK_SATA_COLD 129
152/* 130 */
153/* 131 */
154/* 132 */
155/* 133 */
156/* 134 */
157/* 135 */
158/* 136 */
159/* 137 */
160/* 138 */
161/* 139 */
162/* 140 */
163/* 141 */
164/* 142 */
165/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
166/* xusb_host_src and xusb_ss_src) */
167#define TEGRA124_CLK_CILAB 144
168#define TEGRA124_CLK_CILCD 145
169#define TEGRA124_CLK_CILE 146
170#define TEGRA124_CLK_DSIALP 147
171#define TEGRA124_CLK_DSIBLP 148
172#define TEGRA124_CLK_ENTROPY 149
173#define TEGRA124_CLK_DDS 150
174/* 151 */
175#define TEGRA124_CLK_DP2 152
176#define TEGRA124_CLK_AMX 153
177#define TEGRA124_CLK_ADX 154
178/* 155 (bit affects dfll_ref and dfll_soc) */
179#define TEGRA124_CLK_XUSB_SS 156
180/* 157 */
181/* 158 */
182/* 159 */
183
184/* 160 */
185/* 161 */
186/* 162 */
187/* 163 */
188/* 164 */
189/* 165 */
190#define TEGRA124_CLK_I2C6 166
191/* 167 */
192/* 168 */
193/* 169 */
194/* 170 */
195#define TEGRA124_CLK_VIM2_CLK 171
196/* 172 */
197/* 173 */
198/* 174 */
199/* 175 */
200#define TEGRA124_CLK_HDMI_AUDIO 176
201#define TEGRA124_CLK_CLK72MHZ 177
202#define TEGRA124_CLK_VIC03 178
203/* 179 */
204#define TEGRA124_CLK_ADX1 180
205#define TEGRA124_CLK_DPAUX 181
206#define TEGRA124_CLK_SOR0 182
207/* 183 */
208#define TEGRA124_CLK_GPU 184
209#define TEGRA124_CLK_AMX1 185
210/* 186 */
211/* 187 */
212/* 188 */
213/* 189 */
214/* 190 */
215/* 191 */
216#define TEGRA124_CLK_UARTB 192
217#define TEGRA124_CLK_VFIR 193
218#define TEGRA124_CLK_SPDIF_IN 194
219#define TEGRA124_CLK_SPDIF_OUT 195
220#define TEGRA124_CLK_VI 196
221#define TEGRA124_CLK_VI_SENSOR 197
222#define TEGRA124_CLK_FUSE 198
223#define TEGRA124_CLK_FUSE_BURN 199
224#define TEGRA124_CLK_CLK_32K 200
225#define TEGRA124_CLK_CLK_M 201
226#define TEGRA124_CLK_CLK_M_DIV2 202
227#define TEGRA124_CLK_CLK_M_DIV4 203
228#define TEGRA124_CLK_PLL_REF 204
229#define TEGRA124_CLK_PLL_C 205
230#define TEGRA124_CLK_PLL_C_OUT1 206
231#define TEGRA124_CLK_PLL_C2 207
232#define TEGRA124_CLK_PLL_C3 208
233#define TEGRA124_CLK_PLL_M 209
234#define TEGRA124_CLK_PLL_M_OUT1 210
235#define TEGRA124_CLK_PLL_P 211
236#define TEGRA124_CLK_PLL_P_OUT1 212
237#define TEGRA124_CLK_PLL_P_OUT2 213
238#define TEGRA124_CLK_PLL_P_OUT3 214
239#define TEGRA124_CLK_PLL_P_OUT4 215
240#define TEGRA124_CLK_PLL_A 216
241#define TEGRA124_CLK_PLL_A_OUT0 217
242#define TEGRA124_CLK_PLL_D 218
243#define TEGRA124_CLK_PLL_D_OUT0 219
244#define TEGRA124_CLK_PLL_D2 220
245#define TEGRA124_CLK_PLL_D2_OUT0 221
246#define TEGRA124_CLK_PLL_U 222
247#define TEGRA124_CLK_PLL_U_480M 223
248
249#define TEGRA124_CLK_PLL_U_60M 224
250#define TEGRA124_CLK_PLL_U_48M 225
251#define TEGRA124_CLK_PLL_U_12M 226
252#define TEGRA124_CLK_PLL_X 227
253#define TEGRA124_CLK_PLL_X_OUT0 228
254#define TEGRA124_CLK_PLL_RE_VCO 229
255#define TEGRA124_CLK_PLL_RE_OUT 230
256#define TEGRA124_CLK_PLL_E 231
257#define TEGRA124_CLK_SPDIF_IN_SYNC 232
258#define TEGRA124_CLK_I2S0_SYNC 233
259#define TEGRA124_CLK_I2S1_SYNC 234
260#define TEGRA124_CLK_I2S2_SYNC 235
261#define TEGRA124_CLK_I2S3_SYNC 236
262#define TEGRA124_CLK_I2S4_SYNC 237
263#define TEGRA124_CLK_VIMCLK_SYNC 238
264#define TEGRA124_CLK_AUDIO0 239
265#define TEGRA124_CLK_AUDIO1 240
266#define TEGRA124_CLK_AUDIO2 241
267#define TEGRA124_CLK_AUDIO3 242
268#define TEGRA124_CLK_AUDIO4 243
269#define TEGRA124_CLK_SPDIF 244
270#define TEGRA124_CLK_CLK_OUT_1 245
271#define TEGRA124_CLK_CLK_OUT_2 246
272#define TEGRA124_CLK_CLK_OUT_3 247
273#define TEGRA124_CLK_BLINK 248
274/* 249 */
275/* 250 */
276/* 251 */
277#define TEGRA124_CLK_XUSB_HOST_SRC 252
278#define TEGRA124_CLK_XUSB_FALCON_SRC 253
279#define TEGRA124_CLK_XUSB_FS_SRC 254
280#define TEGRA124_CLK_XUSB_SS_SRC 255
281
282#define TEGRA124_CLK_XUSB_DEV_SRC 256
283#define TEGRA124_CLK_XUSB_DEV 257
284#define TEGRA124_CLK_XUSB_HS_SRC 258
285#define TEGRA124_CLK_SCLK 259
286#define TEGRA124_CLK_HCLK 260
287#define TEGRA124_CLK_PCLK 261
288#define TEGRA124_CLK_CCLK_G 262
289#define TEGRA124_CLK_CCLK_LP 263
290#define TEGRA124_CLK_DFLL_REF 264
291#define TEGRA124_CLK_DFLL_SOC 265
292#define TEGRA124_CLK_VI_SENSOR2 266
293#define TEGRA124_CLK_PLL_P_OUT5 267
294#define TEGRA124_CLK_CML0 268
295#define TEGRA124_CLK_CML1 269
296#define TEGRA124_CLK_PLL_C4 270
297#define TEGRA124_CLK_PLL_DP 271
298#define TEGRA124_CLK_PLL_E_MUX 272
299/* 273 */
300/* 274 */
301/* 275 */
302/* 276 */
303/* 277 */
304/* 278 */
305/* 279 */
306/* 280 */
307/* 281 */
308/* 282 */
309/* 283 */
310/* 284 */
311/* 285 */
312/* 286 */
313/* 287 */
314
315/* 288 */
316/* 289 */
317/* 290 */
318/* 291 */
319/* 292 */
320/* 293 */
321/* 294 */
322/* 295 */
323/* 296 */
324/* 297 */
325/* 298 */
326/* 299 */
327#define TEGRA124_CLK_AUDIO0_MUX 300
328#define TEGRA124_CLK_AUDIO1_MUX 301
329#define TEGRA124_CLK_AUDIO2_MUX 302
330#define TEGRA124_CLK_AUDIO3_MUX 303
331#define TEGRA124_CLK_AUDIO4_MUX 304
332#define TEGRA124_CLK_SPDIF_MUX 305
333#define TEGRA124_CLK_CLK_OUT_1_MUX 306
334#define TEGRA124_CLK_CLK_OUT_2_MUX 307
335#define TEGRA124_CLK_CLK_OUT_3_MUX 308
336#define TEGRA124_CLK_DSIA_MUX 309
337#define TEGRA124_CLK_DSIB_MUX 310
338#define TEGRA124_CLK_SOR0_LVDS 311
339#define TEGRA124_CLK_XUSB_SS_DIV2 312
340 13
341#define TEGRA124_CLK_PLL_M_UD 313 14#define TEGRA124_CLK_CCLK_G 262
342#define TEGRA124_CLK_PLL_C_UD 314 15#define TEGRA124_CLK_CCLK_LP 263
343 16
344#define TEGRA124_CLK_CLK_MAX 315 17#define TEGRA124_CLK_CLK_MAX 315
345 18
346#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ 19#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
deleted file mode 100644
index 0ca5f6046920..000000000000
--- a/include/linux/clk-private.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * linux/include/linux/clk-private.h
3 *
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef __LINUX_CLK_PRIVATE_H
12#define __LINUX_CLK_PRIVATE_H
13
14#include <linux/clk-provider.h>
15#include <linux/kref.h>
16#include <linux/list.h>
17
18/*
19 * WARNING: Do not include clk-private.h from any file that implements struct
20 * clk_ops. Doing so is a layering violation!
21 *
22 * This header exists only to allow for statically initialized clock data. Any
23 * static clock data must be defined in a separate file from the logic that
24 * implements the clock operations for that same data.
25 */
26
27#ifdef CONFIG_COMMON_CLK
28
29struct module;
30
31struct clk {
32 const char *name;
33 const struct clk_ops *ops;
34 struct clk_hw *hw;
35 struct module *owner;
36 struct clk *parent;
37 const char **parent_names;
38 struct clk **parents;
39 u8 num_parents;
40 u8 new_parent_index;
41 unsigned long rate;
42 unsigned long new_rate;
43 struct clk *new_parent;
44 struct clk *new_child;
45 unsigned long flags;
46 unsigned int enable_count;
47 unsigned int prepare_count;
48 unsigned long accuracy;
49 int phase;
50 struct hlist_head children;
51 struct hlist_node child_node;
52 struct hlist_node debug_node;
53 unsigned int notifier_count;
54#ifdef CONFIG_DEBUG_FS
55 struct dentry *dentry;
56#endif
57 struct kref ref;
58};
59
60/*
61 * DOC: Basic clock implementations common to many platforms
62 *
63 * Each basic clock hardware type is comprised of a structure describing the
64 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
65 * unique flags for that hardware type, a registration function and an
66 * alternative macro for static initialization
67 */
68
69#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \
70 _parents) \
71 static struct clk _name = { \
72 .name = #_name, \
73 .ops = &_ops, \
74 .hw = &_name##_hw.hw, \
75 .parent_names = _parent_names, \
76 .num_parents = ARRAY_SIZE(_parent_names), \
77 .parents = _parents, \
78 .flags = _flags | CLK_IS_BASIC, \
79 }
80
81#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
82 _fixed_rate_flags) \
83 static struct clk _name; \
84 static const char *_name##_parent_names[] = {}; \
85 static struct clk_fixed_rate _name##_hw = { \
86 .hw = { \
87 .clk = &_name, \
88 }, \
89 .fixed_rate = _rate, \
90 .flags = _fixed_rate_flags, \
91 }; \
92 DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \
93 _name##_parent_names, NULL);
94
95#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
96 _flags, _reg, _bit_idx, \
97 _gate_flags, _lock) \
98 static struct clk _name; \
99 static const char *_name##_parent_names[] = { \
100 _parent_name, \
101 }; \
102 static struct clk *_name##_parents[] = { \
103 _parent_ptr, \
104 }; \
105 static struct clk_gate _name##_hw = { \
106 .hw = { \
107 .clk = &_name, \
108 }, \
109 .reg = _reg, \
110 .bit_idx = _bit_idx, \
111 .flags = _gate_flags, \
112 .lock = _lock, \
113 }; \
114 DEFINE_CLK(_name, clk_gate_ops, _flags, \
115 _name##_parent_names, _name##_parents);
116
117#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
118 _flags, _reg, _shift, _width, \
119 _divider_flags, _table, _lock) \
120 static struct clk _name; \
121 static const char *_name##_parent_names[] = { \
122 _parent_name, \
123 }; \
124 static struct clk *_name##_parents[] = { \
125 _parent_ptr, \
126 }; \
127 static struct clk_divider _name##_hw = { \
128 .hw = { \
129 .clk = &_name, \
130 }, \
131 .reg = _reg, \
132 .shift = _shift, \
133 .width = _width, \
134 .flags = _divider_flags, \
135 .table = _table, \
136 .lock = _lock, \
137 }; \
138 DEFINE_CLK(_name, clk_divider_ops, _flags, \
139 _name##_parent_names, _name##_parents);
140
141#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
142 _flags, _reg, _shift, _width, \
143 _divider_flags, _lock) \
144 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
145 _flags, _reg, _shift, _width, \
146 _divider_flags, NULL, _lock)
147
148#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
149 _parent_ptr, _flags, _reg, \
150 _shift, _width, _divider_flags, \
151 _table, _lock) \
152 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
153 _flags, _reg, _shift, _width, \
154 _divider_flags, _table, _lock) \
155
156#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
157 _reg, _shift, _width, \
158 _mux_flags, _lock) \
159 static struct clk _name; \
160 static struct clk_mux _name##_hw = { \
161 .hw = { \
162 .clk = &_name, \
163 }, \
164 .reg = _reg, \
165 .shift = _shift, \
166 .mask = BIT(_width) - 1, \
167 .flags = _mux_flags, \
168 .lock = _lock, \
169 }; \
170 DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \
171 _parents);
172
173#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \
174 _parent_ptr, _flags, \
175 _mult, _div) \
176 static struct clk _name; \
177 static const char *_name##_parent_names[] = { \
178 _parent_name, \
179 }; \
180 static struct clk *_name##_parents[] = { \
181 _parent_ptr, \
182 }; \
183 static struct clk_fixed_factor _name##_hw = { \
184 .hw = { \
185 .clk = &_name, \
186 }, \
187 .mult = _mult, \
188 .div = _div, \
189 }; \
190 DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \
191 _name##_parent_names, _name##_parents);
192
193/**
194 * __clk_init - initialize the data structures in a struct clk
195 * @dev: device initializing this clk, placeholder for now
196 * @clk: clk being initialized
197 *
198 * Initializes the lists in struct clk, queries the hardware for the
199 * parent and rate and sets them both.
200 *
201 * Any struct clk passed into __clk_init must have the following members
202 * populated:
203 * .name
204 * .ops
205 * .hw
206 * .parent_names
207 * .num_parents
208 * .flags
209 *
210 * It is not necessary to call clk_register if __clk_init is used directly with
211 * statically initialized clock data.
212 *
213 * Returns 0 on success, otherwise an error code.
214 */
215int __clk_init(struct device *dev, struct clk *clk);
216
217struct clk *__clk_register(struct device *dev, struct clk_hw *hw);
218
219#endif /* CONFIG_COMMON_CLK */
220#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d936409520f8..5591ea71a8d1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -33,6 +33,7 @@
33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
34 34
35struct clk_hw; 35struct clk_hw;
36struct clk_core;
36struct dentry; 37struct dentry;
37 38
38/** 39/**
@@ -174,9 +175,12 @@ struct clk_ops {
174 unsigned long parent_rate); 175 unsigned long parent_rate);
175 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 176 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
176 unsigned long *parent_rate); 177 unsigned long *parent_rate);
177 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 178 long (*determine_rate)(struct clk_hw *hw,
178 unsigned long *best_parent_rate, 179 unsigned long rate,
179 struct clk_hw **best_parent_hw); 180 unsigned long min_rate,
181 unsigned long max_rate,
182 unsigned long *best_parent_rate,
183 struct clk_hw **best_parent_hw);
180 int (*set_parent)(struct clk_hw *hw, u8 index); 184 int (*set_parent)(struct clk_hw *hw, u8 index);
181 u8 (*get_parent)(struct clk_hw *hw); 185 u8 (*get_parent)(struct clk_hw *hw);
182 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 186 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
@@ -216,13 +220,17 @@ struct clk_init_data {
216 * clk_foo and then referenced by the struct clk instance that uses struct 220 * clk_foo and then referenced by the struct clk instance that uses struct
217 * clk_foo's clk_ops 221 * clk_foo's clk_ops
218 * 222 *
219 * @clk: pointer to the struct clk instance that points back to this struct 223 * @core: pointer to the struct clk_core instance that points back to this
220 * clk_hw instance 224 * struct clk_hw instance
225 *
226 * @clk: pointer to the per-user struct clk instance that can be used to call
227 * into the clk API
221 * 228 *
222 * @init: pointer to struct clk_init_data that contains the init data shared 229 * @init: pointer to struct clk_init_data that contains the init data shared
223 * with the common clock framework. 230 * with the common clock framework.
224 */ 231 */
225struct clk_hw { 232struct clk_hw {
233 struct clk_core *core;
226 struct clk *clk; 234 struct clk *clk;
227 const struct clk_init_data *init; 235 const struct clk_init_data *init;
228}; 236};
@@ -294,6 +302,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
294 const char *parent_name, unsigned long flags, 302 const char *parent_name, unsigned long flags,
295 void __iomem *reg, u8 bit_idx, 303 void __iomem *reg, u8 bit_idx,
296 u8 clk_gate_flags, spinlock_t *lock); 304 u8 clk_gate_flags, spinlock_t *lock);
305void clk_unregister_gate(struct clk *clk);
297 306
298struct clk_div_table { 307struct clk_div_table {
299 unsigned int val; 308 unsigned int val;
@@ -352,6 +361,17 @@ struct clk_divider {
352#define CLK_DIVIDER_READ_ONLY BIT(5) 361#define CLK_DIVIDER_READ_ONLY BIT(5)
353 362
354extern const struct clk_ops clk_divider_ops; 363extern const struct clk_ops clk_divider_ops;
364
365unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
366 unsigned int val, const struct clk_div_table *table,
367 unsigned long flags);
368long divider_round_rate(struct clk_hw *hw, unsigned long rate,
369 unsigned long *prate, const struct clk_div_table *table,
370 u8 width, unsigned long flags);
371int divider_get_val(unsigned long rate, unsigned long parent_rate,
372 const struct clk_div_table *table, u8 width,
373 unsigned long flags);
374
355struct clk *clk_register_divider(struct device *dev, const char *name, 375struct clk *clk_register_divider(struct device *dev, const char *name,
356 const char *parent_name, unsigned long flags, 376 const char *parent_name, unsigned long flags,
357 void __iomem *reg, u8 shift, u8 width, 377 void __iomem *reg, u8 shift, u8 width,
@@ -361,6 +381,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
361 void __iomem *reg, u8 shift, u8 width, 381 void __iomem *reg, u8 shift, u8 width,
362 u8 clk_divider_flags, const struct clk_div_table *table, 382 u8 clk_divider_flags, const struct clk_div_table *table,
363 spinlock_t *lock); 383 spinlock_t *lock);
384void clk_unregister_divider(struct clk *clk);
364 385
365/** 386/**
366 * struct clk_mux - multiplexer clock 387 * struct clk_mux - multiplexer clock
@@ -382,6 +403,8 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
382 * register, and mask of mux bits are in higher 16-bit of this register. 403 * register, and mask of mux bits are in higher 16-bit of this register.
383 * While setting the mux bits, higher 16-bit should also be updated to 404 * While setting the mux bits, higher 16-bit should also be updated to
384 * indicate changing mux bits. 405 * indicate changing mux bits.
406 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
407 * frequency.
385 */ 408 */
386struct clk_mux { 409struct clk_mux {
387 struct clk_hw hw; 410 struct clk_hw hw;
@@ -396,7 +419,8 @@ struct clk_mux {
396#define CLK_MUX_INDEX_ONE BIT(0) 419#define CLK_MUX_INDEX_ONE BIT(0)
397#define CLK_MUX_INDEX_BIT BIT(1) 420#define CLK_MUX_INDEX_BIT BIT(1)
398#define CLK_MUX_HIWORD_MASK BIT(2) 421#define CLK_MUX_HIWORD_MASK BIT(2)
399#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 422#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
423#define CLK_MUX_ROUND_CLOSEST BIT(4)
400 424
401extern const struct clk_ops clk_mux_ops; 425extern const struct clk_ops clk_mux_ops;
402extern const struct clk_ops clk_mux_ro_ops; 426extern const struct clk_ops clk_mux_ro_ops;
@@ -411,6 +435,8 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
411 void __iomem *reg, u8 shift, u32 mask, 435 void __iomem *reg, u8 shift, u32 mask,
412 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 436 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
413 437
438void clk_unregister_mux(struct clk *clk);
439
414void of_fixed_factor_clk_setup(struct device_node *node); 440void of_fixed_factor_clk_setup(struct device_node *node);
415 441
416/** 442/**
@@ -550,15 +576,29 @@ bool __clk_is_prepared(struct clk *clk);
550bool __clk_is_enabled(struct clk *clk); 576bool __clk_is_enabled(struct clk *clk);
551struct clk *__clk_lookup(const char *name); 577struct clk *__clk_lookup(const char *name);
552long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 578long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
579 unsigned long min_rate,
580 unsigned long max_rate,
553 unsigned long *best_parent_rate, 581 unsigned long *best_parent_rate,
554 struct clk_hw **best_parent_p); 582 struct clk_hw **best_parent_p);
583unsigned long __clk_determine_rate(struct clk_hw *core,
584 unsigned long rate,
585 unsigned long min_rate,
586 unsigned long max_rate);
587long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
588 unsigned long min_rate,
589 unsigned long max_rate,
590 unsigned long *best_parent_rate,
591 struct clk_hw **best_parent_p);
592
593static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
594{
595 dst->clk = src->clk;
596 dst->core = src->core;
597}
555 598
556/* 599/*
557 * FIXME clock api without lock protection 600 * FIXME clock api without lock protection
558 */ 601 */
559int __clk_prepare(struct clk *clk);
560void __clk_unprepare(struct clk *clk);
561void __clk_reparent(struct clk *clk, struct clk *new_parent);
562unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 602unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
563 603
564struct of_device_id; 604struct of_device_id;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index c7f258a81761..8381bbfbc308 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -302,6 +302,46 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
302int clk_set_rate(struct clk *clk, unsigned long rate); 302int clk_set_rate(struct clk *clk, unsigned long rate);
303 303
304/** 304/**
305 * clk_has_parent - check if a clock is a possible parent for another
306 * @clk: clock source
307 * @parent: parent clock source
308 *
309 * This function can be used in drivers that need to check that a clock can be
310 * the parent of another without actually changing the parent.
311 *
312 * Returns true if @parent is a possible parent for @clk, false otherwise.
313 */
314bool clk_has_parent(struct clk *clk, struct clk *parent);
315
316/**
317 * clk_set_rate_range - set a rate range for a clock source
318 * @clk: clock source
319 * @min: desired minimum clock rate in Hz, inclusive
320 * @max: desired maximum clock rate in Hz, inclusive
321 *
322 * Returns success (0) or negative errno.
323 */
324int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
325
326/**
327 * clk_set_min_rate - set a minimum clock rate for a clock source
328 * @clk: clock source
329 * @rate: desired minimum clock rate in Hz, inclusive
330 *
331 * Returns success (0) or negative errno.
332 */
333int clk_set_min_rate(struct clk *clk, unsigned long rate);
334
335/**
336 * clk_set_max_rate - set a maximum clock rate for a clock source
337 * @clk: clock source
338 * @rate: desired maximum clock rate in Hz, inclusive
339 *
340 * Returns success (0) or negative errno.
341 */
342int clk_set_max_rate(struct clk *clk, unsigned long rate);
343
344/**
305 * clk_set_parent - set the parent clock source for this clock 345 * clk_set_parent - set the parent clock source for this clock
306 * @clk: clock source 346 * @clk: clock source
307 * @parent: parent clock source 347 * @parent: parent clock source
@@ -374,6 +414,11 @@ static inline long clk_round_rate(struct clk *clk, unsigned long rate)
374 return 0; 414 return 0;
375} 415}
376 416
417static inline bool clk_has_parent(struct clk *clk, struct clk *parent)
418{
419 return true;
420}
421
377static inline int clk_set_parent(struct clk *clk, struct clk *parent) 422static inline int clk_set_parent(struct clk *clk, struct clk *parent)
378{ 423{
379 return 0; 424 return 0;
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
deleted file mode 100644
index aed28c4451d9..000000000000
--- a/include/linux/clk/sunxi.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __LINUX_CLK_SUNXI_H_
16#define __LINUX_CLK_SUNXI_H_
17
18#include <linux/clk.h>
19
20void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
21
22#endif
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3ca9fca827a2..19c4208f4752 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,6 +120,4 @@ static inline void tegra_cpu_clock_resume(void)
120} 120}
121#endif 121#endif
122 122
123void tegra_clocks_apply_init_table(void);
124
125#endif /* __LINUX_CLK_TEGRA_H_ */ 123#endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 55ef529a0dbf..67844003493d 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,7 @@
15#ifndef __LINUX_CLK_TI_H__ 15#ifndef __LINUX_CLK_TI_H__
16#define __LINUX_CLK_TI_H__ 16#define __LINUX_CLK_TI_H__
17 17
18#include <linux/clk-provider.h>
18#include <linux/clkdev.h> 19#include <linux/clkdev.h>
19 20
20/** 21/**
@@ -217,6 +218,13 @@ struct ti_dt_clk {
217/* Maximum number of clock memmaps */ 218/* Maximum number of clock memmaps */
218#define CLK_MAX_MEMMAPS 4 219#define CLK_MAX_MEMMAPS 4
219 220
221/* Static memmap indices */
222enum {
223 TI_CLKM_CM = 0,
224 TI_CLKM_PRM,
225 TI_CLKM_SCRM,
226};
227
220typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 228typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
221 229
222/** 230/**
@@ -263,6 +271,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
263 u8 index); 271 u8 index);
264long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 272long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
265 unsigned long rate, 273 unsigned long rate,
274 unsigned long min_rate,
275 unsigned long max_rate,
266 unsigned long *best_parent_rate, 276 unsigned long *best_parent_rate,
267 struct clk_hw **best_parent_clk); 277 struct clk_hw **best_parent_clk);
268unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 278unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
@@ -272,6 +282,8 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
272 unsigned long *parent_rate); 282 unsigned long *parent_rate);
273long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 283long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
274 unsigned long rate, 284 unsigned long rate,
285 unsigned long min_rate,
286 unsigned long max_rate,
275 unsigned long *best_parent_rate, 287 unsigned long *best_parent_rate,
276 struct clk_hw **best_parent_clk); 288 struct clk_hw **best_parent_clk);
277u8 omap2_init_dpll_parent(struct clk_hw *hw); 289u8 omap2_init_dpll_parent(struct clk_hw *hw);
@@ -348,4 +360,17 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
348extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 360extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
349extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 361extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
350 362
363#ifdef CONFIG_ATAGS
364int omap3430_clk_legacy_init(void);
365int omap3430es1_clk_legacy_init(void);
366int omap36xx_clk_legacy_init(void);
367int am35xx_clk_legacy_init(void);
368#else
369static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
370static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
371static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
372static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
373#endif
374
375
351#endif 376#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 09:13:46 -0500