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authorLucas Stach <dev@lynxeye.de>2014-11-03 17:20:04 -0500
committerThierry Reding <treding@nvidia.com>2014-11-13 10:57:48 -0500
commit121a2f6d5f09d929fc663349ba34e248e8d07391 (patch)
tree727bbcdcac97812ab3d7c3fdc2b1f222aeb5ec61
parentf114040e3ea6e07372334ade75d1ee0775c355e1 (diff)
ARM: tegra: Add serial port labels to Tegra124 DT
These labels will be used to provide deterministic numbering of consoles in a later patch. Signed-off-by: Lucas Stach <dev@lynxeye.de> [treding@nvidia.com: drop aliases, reword commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 478c555ebd96..df2b06b29985 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -286,7 +286,7 @@
286 * the APB DMA based serial driver, the comptible is 286 * the APB DMA based serial driver, the comptible is
287 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 287 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
288 */ 288 */
289 serial@0,70006000 { 289 uarta: serial@0,70006000 {
290 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 290 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
291 reg = <0x0 0x70006000 0x0 0x40>; 291 reg = <0x0 0x70006000 0x0 0x40>;
292 reg-shift = <2>; 292 reg-shift = <2>;
@@ -299,7 +299,7 @@
299 status = "disabled"; 299 status = "disabled";
300 }; 300 };
301 301
302 serial@0,70006040 { 302 uartb: serial@0,70006040 {
303 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 303 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
304 reg = <0x0 0x70006040 0x0 0x40>; 304 reg = <0x0 0x70006040 0x0 0x40>;
305 reg-shift = <2>; 305 reg-shift = <2>;
@@ -312,7 +312,7 @@
312 status = "disabled"; 312 status = "disabled";
313 }; 313 };
314 314
315 serial@0,70006200 { 315 uartc: serial@0,70006200 {
316 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 316 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
317 reg = <0x0 0x70006200 0x0 0x40>; 317 reg = <0x0 0x70006200 0x0 0x40>;
318 reg-shift = <2>; 318 reg-shift = <2>;
@@ -325,7 +325,7 @@
325 status = "disabled"; 325 status = "disabled";
326 }; 326 };
327 327
328 serial@0,70006300 { 328 uartd: serial@0,70006300 {
329 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 329 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
330 reg = <0x0 0x70006300 0x0 0x40>; 330 reg = <0x0 0x70006300 0x0 0x40>;
331 reg-shift = <2>; 331 reg-shift = <2>;