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authorBen Skeggs <bskeggs@redhat.com>2011-05-25 04:32:44 -0400
committerBen Skeggs <bskeggs@redhat.com>2011-06-23 01:57:38 -0400
commit0411de854898a2402cf4bd915bed7ec9a6b76f9a (patch)
tree52678d0557377674a78b95211adb36dba1ecde9b
parentf8522fc80f2e0392fc44b069f61721bd25907270 (diff)
drm/nvc0/gr: import and use our own fuc by default
The ability to use NVIDIA's fuc has been retained *temporarily* in order to better debug any issues that may be lingering in our initial attempt at writing this ucode. Once I'm fairly confident we're okay, it'll be removed. There's a number of things not implemented by this fuc currently, but most of it is sets of state that our context setup would not have used anyway. No doubt we'll find out what they're for at some point, and implement it if required. This has been tested on 0xc0/0xc4 thus far, and from what I could tell it worked as well as NVIDIA's. It's also been tested on 0xc1, but even with NVIDIA's fuc that chipset doesn't work correctly with nouveau yet. 0xc3/0xc8/0xce should in theory be supported too, but I don't have the hardware to check that. There's no doubt numerous bugs to squash yet, please report any! Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h1
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.c185
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.fuc400
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grgpc.fuc474
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h483
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grhub.fuc808
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h838
8 files changed, 3157 insertions, 36 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index bdee1a6956e7..7e25f5a6db96 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -119,6 +119,10 @@ MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
119int nouveau_msi; 119int nouveau_msi;
120module_param_named(msi, nouveau_msi, int, 0400); 120module_param_named(msi, nouveau_msi, int, 0400);
121 121
122MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)\n");
123int nouveau_ctxfw;
124module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
125
122int nouveau_fbpercrtc; 126int nouveau_fbpercrtc;
123#if 0 127#if 0
124module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400); 128module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 7136ad34921d..86eb3f40c4f8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -786,6 +786,7 @@ extern int nouveau_override_conntype;
786extern char *nouveau_perflvl; 786extern char *nouveau_perflvl;
787extern int nouveau_perflvl_wr; 787extern int nouveau_perflvl_wr;
788extern int nouveau_msi; 788extern int nouveau_msi;
789extern int nouveau_ctxfw;
789 790
790extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 791extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
791extern int nouveau_pci_resume(struct pci_dev *pdev); 792extern int nouveau_pci_resume(struct pci_dev *pdev);
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index 6c06d6636a3c..c5aa7e7aea0d 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -28,7 +28,34 @@
28 28
29#include "nouveau_drv.h" 29#include "nouveau_drv.h"
30#include "nouveau_mm.h" 30#include "nouveau_mm.h"
31
31#include "nvc0_graph.h" 32#include "nvc0_graph.h"
33#include "nvc0_grhub.fuc.h"
34#include "nvc0_grgpc.fuc.h"
35
36static void
37nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base)
38{
39 NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base,
40 nv_rd32(dev, base + 0x400));
41 NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
42 nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804),
43 nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c));
44 NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
45 nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814),
46 nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c));
47}
48
49static void
50nvc0_graph_ctxctl_debug(struct drm_device *dev)
51{
52 u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff;
53 u32 gpc;
54
55 nvc0_graph_ctxctl_debug_unit(dev, 0x409000);
56 for (gpc = 0; gpc < gpcnr; gpc++)
57 nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000));
58}
32 59
33static int 60static int
34nvc0_graph_load_context(struct nouveau_channel *chan) 61nvc0_graph_load_context(struct nouveau_channel *chan)
@@ -72,13 +99,24 @@ nvc0_graph_construct_context(struct nouveau_channel *chan)
72 if (!ctx) 99 if (!ctx)
73 return -ENOMEM; 100 return -ENOMEM;
74 101
75 nvc0_graph_load_context(chan); 102 if (!nouveau_ctxfw) {
76 103 nv_wr32(dev, 0x409840, 0x80000000);
77 nv_wo32(grch->grctx, 0x1c, 1); 104 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
78 nv_wo32(grch->grctx, 0x20, 0); 105 nv_wr32(dev, 0x409504, 0x00000001);
79 nv_wo32(grch->grctx, 0x28, 0); 106 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
80 nv_wo32(grch->grctx, 0x2c, 0); 107 NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
81 dev_priv->engine.instmem.flush(dev); 108 nvc0_graph_ctxctl_debug(dev);
109 return -EBUSY;
110 }
111 } else {
112 nvc0_graph_load_context(chan);
113
114 nv_wo32(grch->grctx, 0x1c, 1);
115 nv_wo32(grch->grctx, 0x20, 0);
116 nv_wo32(grch->grctx, 0x28, 0);
117 nv_wo32(grch->grctx, 0x2c, 0);
118 dev_priv->engine.instmem.flush(dev);
119 }
82 120
83 ret = nvc0_grctx_generate(chan); 121 ret = nvc0_grctx_generate(chan);
84 if (ret) { 122 if (ret) {
@@ -86,10 +124,21 @@ nvc0_graph_construct_context(struct nouveau_channel *chan)
86 return ret; 124 return ret;
87 } 125 }
88 126
89 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst); 127 if (!nouveau_ctxfw) {
90 if (ret) { 128 nv_wr32(dev, 0x409840, 0x80000000);
91 kfree(ctx); 129 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
92 return ret; 130 nv_wr32(dev, 0x409504, 0x00000002);
131 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
132 NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n");
133 nvc0_graph_ctxctl_debug(dev);
134 return -EBUSY;
135 }
136 } else {
137 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
138 if (ret) {
139 kfree(ctx);
140 return ret;
141 }
93 } 142 }
94 143
95 for (i = 0; i < priv->grctx_size; i += 4) 144 for (i = 0; i < priv->grctx_size; i += 4)
@@ -210,15 +259,20 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
210 for (i = 0; i < priv->grctx_size; i += 4) 259 for (i = 0; i < priv->grctx_size; i += 4)
211 nv_wo32(grctx, i, priv->grctx_vals[i / 4]); 260 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
212 261
213 nv_wo32(grctx, 0xf4, 0); 262 if (!nouveau_ctxfw) {
214 nv_wo32(grctx, 0xf8, 0); 263 nv_wo32(grctx, 0x00, grch->mmio_nr);
215 nv_wo32(grctx, 0x10, grch->mmio_nr); 264 nv_wo32(grctx, 0x04, grch->mmio->linst >> 8);
216 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst)); 265 } else {
217 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst)); 266 nv_wo32(grctx, 0xf4, 0);
218 nv_wo32(grctx, 0x1c, 1); 267 nv_wo32(grctx, 0xf8, 0);
219 nv_wo32(grctx, 0x20, 0); 268 nv_wo32(grctx, 0x10, grch->mmio_nr);
220 nv_wo32(grctx, 0x28, 0); 269 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
221 nv_wo32(grctx, 0x2c, 0); 270 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
271 nv_wo32(grctx, 0x1c, 1);
272 nv_wo32(grctx, 0x20, 0);
273 nv_wo32(grctx, 0x28, 0);
274 nv_wo32(grctx, 0x2c, 0);
275 }
222 pinstmem->flush(dev); 276 pinstmem->flush(dev);
223 return 0; 277 return 0;
224 278
@@ -419,8 +473,51 @@ nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
419static int 473static int
420nvc0_graph_init_ctxctl(struct drm_device *dev) 474nvc0_graph_init_ctxctl(struct drm_device *dev)
421{ 475{
476 struct drm_nouveau_private *dev_priv = dev->dev_private;
422 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR); 477 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
423 u32 r000260; 478 u32 r000260;
479 int i;
480
481 if (!nouveau_ctxfw) {
482 /* load HUB microcode */
483 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
484 nv_wr32(dev, 0x4091c0, 0x01000000);
485 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
486 nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]);
487
488 nv_wr32(dev, 0x409180, 0x01000000);
489 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
490 if ((i & 0x3f) == 0)
491 nv_wr32(dev, 0x409188, i >> 6);
492 nv_wr32(dev, 0x409184, nvc0_grhub_code[i]);
493 }
494
495 /* load GPC microcode */
496 nv_wr32(dev, 0x41a1c0, 0x01000000);
497 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
498 nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]);
499
500 nv_wr32(dev, 0x41a180, 0x01000000);
501 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
502 if ((i & 0x3f) == 0)
503 nv_wr32(dev, 0x41a188, i >> 6);
504 nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]);
505 }
506 nv_wr32(dev, 0x000260, r000260);
507
508 /* start HUB ucode running, it'll init the GPCs */
509 nv_wr32(dev, 0x409800, dev_priv->chipset);
510 nv_wr32(dev, 0x40910c, 0x00000000);
511 nv_wr32(dev, 0x409100, 0x00000002);
512 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
513 NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n");
514 nvc0_graph_ctxctl_debug(dev);
515 return -EBUSY;
516 }
517
518 priv->grctx_size = nv_rd32(dev, 0x409804);
519 return 0;
520 }
424 521
425 /* load fuc microcode */ 522 /* load fuc microcode */
426 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000); 523 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
@@ -528,6 +625,22 @@ nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
528} 625}
529 626
530static void 627static void
628nvc0_graph_ctxctl_isr(struct drm_device *dev)
629{
630 u32 ustat = nv_rd32(dev, 0x409c18);
631
632 if (ustat & 0x00000001)
633 NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n");
634 if (ustat & 0x00080000)
635 NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n");
636 if (ustat & ~0x00080001)
637 NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat);
638
639 nvc0_graph_ctxctl_debug(dev);
640 nv_wr32(dev, 0x409c20, ustat);
641}
642
643static void
531nvc0_graph_isr(struct drm_device *dev) 644nvc0_graph_isr(struct drm_device *dev)
532{ 645{
533 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12; 646 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
@@ -578,11 +691,7 @@ nvc0_graph_isr(struct drm_device *dev)
578 } 691 }
579 692
580 if (stat & 0x00080000) { 693 if (stat & 0x00080000) {
581 u32 ustat = nv_rd32(dev, 0x409c18); 694 nvc0_graph_ctxctl_isr(dev);
582
583 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
584
585 nv_wr32(dev, 0x409c20, ustat);
586 nv_wr32(dev, 0x400100, 0x00080000); 695 nv_wr32(dev, 0x400100, 0x00080000);
587 stat &= ~0x00080000; 696 stat &= ~0x00080000;
588 } 697 }
@@ -651,10 +760,12 @@ nvc0_graph_destroy(struct drm_device *dev, int engine)
651{ 760{
652 struct nvc0_graph_priv *priv = nv_engine(dev, engine); 761 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
653 762
654 nvc0_graph_destroy_fw(&priv->fuc409c); 763 if (nouveau_ctxfw) {
655 nvc0_graph_destroy_fw(&priv->fuc409d); 764 nvc0_graph_destroy_fw(&priv->fuc409c);
656 nvc0_graph_destroy_fw(&priv->fuc41ac); 765 nvc0_graph_destroy_fw(&priv->fuc409d);
657 nvc0_graph_destroy_fw(&priv->fuc41ad); 766 nvc0_graph_destroy_fw(&priv->fuc41ac);
767 nvc0_graph_destroy_fw(&priv->fuc41ad);
768 }
658 769
659 nouveau_irq_unregister(dev, 12); 770 nouveau_irq_unregister(dev, 12);
660 nouveau_irq_unregister(dev, 25); 771 nouveau_irq_unregister(dev, 25);
@@ -698,15 +809,17 @@ nvc0_graph_create(struct drm_device *dev)
698 nouveau_irq_register(dev, 12, nvc0_graph_isr); 809 nouveau_irq_register(dev, 12, nvc0_graph_isr);
699 nouveau_irq_register(dev, 25, nvc0_runk140_isr); 810 nouveau_irq_register(dev, 25, nvc0_runk140_isr);
700 811
701 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) || 812 if (nouveau_ctxfw) {
702 nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) || 813 NV_INFO(dev, "PGRAPH: using external firmware\n");
703 nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) || 814 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
704 nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) { 815 nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
705 ret = 0; 816 nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
706 goto error; 817 nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
818 ret = 0;
819 goto error;
820 }
707 } 821 }
708 822
709
710 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4); 823 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
711 if (ret) 824 if (ret)
712 goto error; 825 goto error;
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.fuc b/drivers/gpu/drm/nouveau/nvc0_graph.fuc
new file mode 100644
index 000000000000..2a4b6dc8f9de
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.fuc
@@ -0,0 +1,400 @@
1/* fuc microcode util functions for nvc0 PGRAPH
2 *
3 * Copyright 2011 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Ben Skeggs
24 */
25
26define(`mmctx_data', `.b32 eval((($2 - 1) << 26) | $1)')
27define(`queue_init', `.skip eval((2 * 4) + ((8 * 4) * 2))')
28
29ifdef(`include_code', `
30// Error codes
31define(`E_BAD_COMMAND', 0x01)
32define(`E_CMD_OVERFLOW', 0x02)
33
34// Util macros to help with debugging ucode hangs etc
35define(`T_WAIT', 0)
36define(`T_MMCTX', 1)
37define(`T_STRWAIT', 2)
38define(`T_STRINIT', 3)
39define(`T_AUTO', 4)
40define(`T_CHAN', 5)
41define(`T_LOAD', 6)
42define(`T_SAVE', 7)
43define(`T_LCHAN', 8)
44define(`T_LCTXH', 9)
45
46define(`trace_set', `
47 mov $r8 0x83c
48 shl b32 $r8 6
49 clear b32 $r9
50 bset $r9 $1
51 iowr I[$r8 + 0x000] $r9 // CC_SCRATCH[7]
52')
53
54define(`trace_clr', `
55 mov $r8 0x85c
56 shl b32 $r8 6
57 clear b32 $r9
58 bset $r9 $1
59 iowr I[$r8 + 0x000] $r9 // CC_SCRATCH[7]
60')
61
62// queue_put - add request to queue
63//
64// In : $r13 queue pointer
65// $r14 command
66// $r15 data
67//
68queue_put:
69 // make sure we have space..
70 ld b32 $r8 D[$r13 + 0x0] // GET
71 ld b32 $r9 D[$r13 + 0x4] // PUT
72 xor $r8 8
73 cmpu b32 $r8 $r9
74 bra ne queue_put_next
75 mov $r15 E_CMD_OVERFLOW
76 call error
77 ret
78
79 // store cmd/data on queue
80 queue_put_next:
81 and $r8 $r9 7
82 shl b32 $r8 3
83 add b32 $r8 $r13
84 add b32 $r8 8
85 st b32 D[$r8 + 0x0] $r14
86 st b32 D[$r8 + 0x4] $r15
87
88 // update PUT
89 add b32 $r9 1
90 and $r9 0xf
91 st b32 D[$r13 + 0x4] $r9
92 ret
93
94// queue_get - fetch request from queue
95//
96// In : $r13 queue pointer
97//
98// Out: $p1 clear on success (data available)
99// $r14 command
100// $r15 data
101//
102queue_get:
103 bset $flags $p1
104 ld b32 $r8 D[$r13 + 0x0] // GET
105 ld b32 $r9 D[$r13 + 0x4] // PUT
106 cmpu b32 $r8 $r9
107 bra e queue_get_done
108 // fetch first cmd/data pair
109 and $r9 $r8 7
110 shl b32 $r9 3
111 add b32 $r9 $r13
112 add b32 $r9 8
113 ld b32 $r14 D[$r9 + 0x0]
114 ld b32 $r15 D[$r9 + 0x4]
115
116 // update GET
117 add b32 $r8 1
118 and $r8 0xf
119 st b32 D[$r13 + 0x0] $r8
120 bclr $flags $p1
121queue_get_done:
122 ret
123
124// nv_rd32 - read 32-bit value from nv register
125//
126// In : $r14 register
127// Out: $r15 value
128//
129nv_rd32:
130 mov $r11 0x728
131 shl b32 $r11 6
132 mov b32 $r12 $r14
133 bset $r12 31 // MMIO_CTRL_PENDING
134 iowr I[$r11 + 0x000] $r12 // MMIO_CTRL
135 nv_rd32_wait:
136 iord $r12 I[$r11 + 0x000]
137 xbit $r12 $r12 31
138 bra ne nv_rd32_wait
139 mov $r10 6 // DONE_MMIO_RD
140 call wait_doneo
141 iord $r15 I[$r11 + 0x100] // MMIO_RDVAL
142 ret
143
144// nv_wr32 - write 32-bit value to nv register
145//
146// In : $r14 register
147// $r15 value
148//
149nv_wr32:
150 mov $r11 0x728
151 shl b32 $r11 6
152 iowr I[$r11 + 0x200] $r15 // MMIO_WRVAL
153 mov b32 $r12 $r14
154 bset $r12 31 // MMIO_CTRL_PENDING
155 bset $r12 30 // MMIO_CTRL_WRITE
156 iowr I[$r11 + 0x000] $r12 // MMIO_CTRL
157 nv_wr32_wait:
158 iord $r12 I[$r11 + 0x000]
159 xbit $r12 $r12 31
160 bra ne nv_wr32_wait
161 ret
162
163// (re)set watchdog timer
164//
165// In : $r15 timeout
166//
167watchdog_reset:
168 mov $r8 0x430
169 shl b32 $r8 6
170 bset $r15 31
171 iowr I[$r8 + 0x000] $r15
172 ret
173
174// clear watchdog timer
175watchdog_clear:
176 mov $r8 0x430
177 shl b32 $r8 6
178 iowr I[$r8 + 0x000] $r0
179 ret
180
181// wait_done{z,o} - wait on FUC_DONE bit to become clear/set
182//
183// In : $r10 bit to wait on
184//
185define(`wait_done', `
186$1:
187 trace_set(T_WAIT);
188 mov $r8 0x818
189 shl b32 $r8 6
190 iowr I[$r8 + 0x000] $r10 // CC_SCRATCH[6] = wait bit
191 wait_done_$1:
192 mov $r8 0x400
193 shl b32 $r8 6
194 iord $r8 I[$r8 + 0x000] // DONE
195 xbit $r8 $r8 $r10
196 bra $2 wait_done_$1
197 trace_clr(T_WAIT)
198 ret
199')
200wait_done(wait_donez, ne)
201wait_done(wait_doneo, e)
202
203// mmctx_size - determine size of a mmio list transfer
204//
205// In : $r14 mmio list head
206// $r15 mmio list tail
207// Out: $r15 transfer size (in bytes)
208//
209mmctx_size:
210 clear b32 $r9
211 nv_mmctx_size_loop:
212 ld b32 $r8 D[$r14]
213 shr b32 $r8 26
214 add b32 $r8 1
215 shl b32 $r8 2
216 add b32 $r9 $r8
217 add b32 $r14 4
218 cmpu b32 $r14 $r15
219 bra ne nv_mmctx_size_loop
220 mov b32 $r15 $r9
221 ret
222
223// mmctx_xfer - execute a list of mmio transfers
224//
225// In : $r10 flags
226// bit 0: direction (0 = save, 1 = load)
227// bit 1: set if first transfer
228// bit 2: set if last transfer
229// $r11 base
230// $r12 mmio list head
231// $r13 mmio list tail
232// $r14 multi_stride
233// $r15 multi_mask
234//
235mmctx_xfer:
236 trace_set(T_MMCTX)
237 mov $r8 0x710
238 shl b32 $r8 6
239 clear b32 $r9
240 or $r11 $r11
241 bra e mmctx_base_disabled
242 iowr I[$r8 + 0x000] $r11 // MMCTX_BASE
243 bset $r9 0 // BASE_EN
244 mmctx_base_disabled:
245 or $r14 $r14
246 bra e mmctx_multi_disabled
247 iowr I[$r8 + 0x200] $r14 // MMCTX_MULTI_STRIDE
248 iowr I[$r8 + 0x300] $r15 // MMCTX_MULTI_MASK
249 bset $r9 1 // MULTI_EN
250 mmctx_multi_disabled:
251 add b32 $r8 0x100
252
253 xbit $r11 $r10 0
254 shl b32 $r11 16 // DIR
255 bset $r11 12 // QLIMIT = 0x10
256 xbit $r14 $r10 1
257 shl b32 $r14 17
258 or $r11 $r14 // START_TRIGGER
259 iowr I[$r8 + 0x000] $r11 // MMCTX_CTRL
260
261 // loop over the mmio list, and send requests to the hw
262 mmctx_exec_loop:
263 // wait for space in mmctx queue
264 mmctx_wait_free:
265 iord $r14 I[$r8 + 0x000] // MMCTX_CTRL
266 and $r14 0x1f
267 bra e mmctx_wait_free
268
269 // queue up an entry
270 ld b32 $r14 D[$r12]
271 or $r14 $r9
272 iowr I[$r8 + 0x300] $r14
273 add b32 $r12 4
274 cmpu b32 $r12 $r13
275 bra ne mmctx_exec_loop
276
277 xbit $r11 $r10 2
278 bra ne mmctx_stop
279 // wait for queue to empty
280 mmctx_fini_wait:
281 iord $r11 I[$r8 + 0x000] // MMCTX_CTRL
282 and $r11 0x1f
283 cmpu b32 $r11 0x10
284 bra ne mmctx_fini_wait
285 mov $r10 2 // DONE_MMCTX
286 call wait_donez
287 bra mmctx_done
288 mmctx_stop:
289 xbit $r11 $r10 0
290 shl b32 $r11 16 // DIR
291 bset $r11 12 // QLIMIT = 0x10
292 bset $r11 18 // STOP_TRIGGER
293 iowr I[$r8 + 0x000] $r11 // MMCTX_CTRL
294 mmctx_stop_wait:
295 // wait for STOP_TRIGGER to clear
296 iord $r11 I[$r8 + 0x000] // MMCTX_CTRL
297 xbit $r11 $r11 18
298 bra ne mmctx_stop_wait
299 mmctx_done:
300 trace_clr(T_MMCTX)
301 ret
302
303// Wait for DONE_STRAND
304//
305strand_wait:
306 push $r10
307 mov $r10 2
308 call wait_donez
309 pop $r10
310 ret
311
312// unknown - call before issuing strand commands
313//
314strand_pre:
315 mov $r8 0x4afc
316 sethi $r8 0x20000
317 mov $r9 0xc
318 iowr I[$r8] $r9
319 call strand_wait
320 ret
321
322// unknown - call after issuing strand commands
323//
324strand_post:
325 mov $r8 0x4afc
326 sethi $r8 0x20000
327 mov $r9 0xd
328 iowr I[$r8] $r9
329 call strand_wait
330 ret
331
332// Selects strand set?!
333//
334// In: $r14 id
335//
336strand_set:
337 mov $r10 0x4ffc
338 sethi $r10 0x20000
339 sub b32 $r11 $r10 0x500
340 mov $r12 0xf
341 iowr I[$r10 + 0x000] $r12 // 0x93c = 0xf
342 mov $r12 0xb
343 iowr I[$r11 + 0x000] $r12 // 0x928 = 0xb
344 call strand_wait
345 iowr I[$r10 + 0x000] $r14 // 0x93c = <id>
346 mov $r12 0xa
347 iowr I[$r11 + 0x000] $r12 // 0x928 = 0xa
348 call strand_wait
349 ret
350
351// Initialise strand context data
352//
353// In : $r15 context base
354// Out: $r15 context size (in bytes)
355//
356// Strandset(?) 3 hardcoded currently
357//
358strand_ctx_init:
359 trace_set(T_STRINIT)
360 call strand_pre
361 mov $r14 3
362 call strand_set
363 mov $r10 0x46fc
364 sethi $r10 0x20000
365 add b32 $r11 $r10 0x400
366 iowr I[$r10 + 0x100] $r0 // STRAND_FIRST_GENE = 0
367 mov $r12 1
368 iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_FIRST_GENE
369 call strand_wait
370 sub b32 $r12 $r0 1
371 iowr I[$r10 + 0x000] $r12 // STRAND_GENE_CNT = 0xffffffff
372 mov $r12 2
373 iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_GENE_CNT
374 call strand_wait
375 call strand_post
376
377 // read the size of each strand, poke the context offset of
378 // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
379 // about it later then.
380 mov $r8 0x880
381 shl b32 $r8 6
382 iord $r9 I[$r8 + 0x000] // STRANDS
383 add b32 $r8 0x2200
384 shr b32 $r14 $r15 8
385 ctx_init_strand_loop:
386 iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE
387 iowr I[$r8 + 0x100] $r14 // STRAND_LOAD_SWBASE
388 iord $r10 I[$r8 + 0x200] // STRAND_SIZE
389 shr b32 $r10 6
390 add b32 $r10 1
391 add b32 $r14 $r10
392 add b32 $r8 4
393 sub b32 $r9 1
394 bra ne ctx_init_strand_loop
395
396 shl b32 $r14 8
397 sub b32 $r15 $r14 $r15
398 trace_clr(T_STRINIT)
399 ret
400')
diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
new file mode 100644
index 000000000000..0ec2add72a76
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
@@ -0,0 +1,474 @@
1/* fuc microcode for nvc0 PGRAPH/GPC
2 *
3 * Copyright 2011 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Ben Skeggs
24 */
25
26/* To build:
27 * m4 nvc0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grgpc.fuc.h
28 */
29
30/* TODO
31 * - bracket certain functions with scratch writes, useful for debugging
32 * - watchdog timer around ctx operations
33 */
34
35.section nvc0_grgpc_data
36include(`nvc0_graph.fuc')
37gpc_id: .b32 0
38gpc_mmio_list_head: .b32 0
39gpc_mmio_list_tail: .b32 0
40
41tpc_count: .b32 0
42tpc_mask: .b32 0
43tpc_mmio_list_head: .b32 0
44tpc_mmio_list_tail: .b32 0
45
46cmd_queue: queue_init
47
48// chipset descriptions
49chipsets:
50.b8 0xc0 0 0 0
51.b16 nvc0_gpc_mmio_head
52.b16 nvc0_gpc_mmio_tail
53.b16 nvc0_tpc_mmio_head
54.b16 nvc0_tpc_mmio_tail
55.b8 0xc1 0 0 0
56.b16 nvc0_gpc_mmio_head
57.b16 nvc1_gpc_mmio_tail
58.b16 nvc0_tpc_mmio_head
59.b16 nvc1_tpc_mmio_tail
60.b8 0xc3 0 0 0
61.b16 nvc0_gpc_mmio_head
62.b16 nvc0_gpc_mmio_tail
63.b16 nvc0_tpc_mmio_head
64.b16 nvc3_tpc_mmio_tail
65.b8 0xc4 0 0 0
66.b16 nvc0_gpc_mmio_head
67.b16 nvc0_gpc_mmio_tail
68.b16 nvc0_tpc_mmio_head
69.b16 nvc3_tpc_mmio_tail
70.b8 0xc8 0 0 0
71.b16 nvc0_gpc_mmio_head
72.b16 nvc0_gpc_mmio_tail
73.b16 nvc0_tpc_mmio_head
74.b16 nvc0_tpc_mmio_tail
75.b8 0xce 0 0 0
76.b16 nvc0_gpc_mmio_head
77.b16 nvc0_gpc_mmio_tail
78.b16 nvc0_tpc_mmio_head
79.b16 nvc3_tpc_mmio_tail
80.b8 0 0 0 0
81
82// GPC mmio lists
83nvc0_gpc_mmio_head:
84mmctx_data(0x000380, 1)
85mmctx_data(0x000400, 6)
86mmctx_data(0x000450, 9)
87mmctx_data(0x000600, 1)
88mmctx_data(0x000684, 1)
89mmctx_data(0x000700, 5)
90mmctx_data(0x000800, 1)
91mmctx_data(0x000808, 3)
92mmctx_data(0x000828, 1)
93mmctx_data(0x000830, 1)
94mmctx_data(0x0008d8, 1)
95mmctx_data(0x0008e0, 1)
96mmctx_data(0x0008e8, 6)
97mmctx_data(0x00091c, 1)
98mmctx_data(0x000924, 3)
99mmctx_data(0x000b00, 1)
100mmctx_data(0x000b08, 6)
101mmctx_data(0x000bb8, 1)
102mmctx_data(0x000c08, 1)
103mmctx_data(0x000c10, 8)
104mmctx_data(0x000c80, 1)
105mmctx_data(0x000c8c, 1)
106mmctx_data(0x001000, 3)
107mmctx_data(0x001014, 1)
108nvc0_gpc_mmio_tail:
109mmctx_data(0x000c6c, 1);
110nvc1_gpc_mmio_tail:
111
112// TPC mmio lists
113nvc0_tpc_mmio_head:
114mmctx_data(0x000018, 1)
115mmctx_data(0x00003c, 1)
116mmctx_data(0x000048, 1)
117mmctx_data(0x000064, 1)
118mmctx_data(0x000088, 1)
119mmctx_data(0x000200, 6)
120mmctx_data(0x00021c, 2)
121mmctx_data(0x000300, 6)
122mmctx_data(0x0003d0, 1)
123mmctx_data(0x0003e0, 2)
124mmctx_data(0x000400, 3)
125mmctx_data(0x000420, 1)
126mmctx_data(0x0004b0, 1)
127mmctx_data(0x0004e8, 1)
128mmctx_data(0x0004f4, 1)
129mmctx_data(0x000520, 2)
130mmctx_data(0x000604, 4)
131mmctx_data(0x000644, 20)
132mmctx_data(0x000698, 1)
133mmctx_data(0x000750, 2)
134nvc0_tpc_mmio_tail:
135mmctx_data(0x000758, 1)
136mmctx_data(0x0002c4, 1)
137mmctx_data(0x0004bc, 1)
138mmctx_data(0x0006e0, 1)
139nvc3_tpc_mmio_tail:
140mmctx_data(0x000544, 1)
141nvc1_tpc_mmio_tail:
142
143
144.section nvc0_grgpc_code
145bra init
146define(`include_code')
147include(`nvc0_graph.fuc')
148
149// reports an exception to the host
150//
151// In: $r15 error code (see nvc0_graph.fuc)
152//
153error:
154 push $r14
155 mov $r14 -0x67ec // 0x9814
156 sethi $r14 0x400000
157 call nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
158 add b32 $r14 0x41c
159 mov $r15 1
160 call nv_wr32 // HUB_CTXCTL_INTR_UP_SET
161 pop $r14
162 ret
163
164// GPC fuc initialisation, executed by triggering ucode start, will
165// fall through to main loop after completion.
166//
167// Input:
168// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
169// CC_SCRATCH[1]: context base
170//
171// Output:
172// CC_SCRATCH[0]:
173// 31:31: set to signal completion
174// CC_SCRATCH[1]:
175// 31:0: GPC context size
176//
177init:
178 clear b32 $r0
179 mov $sp $r0
180
181 // enable fifo access
182 mov $r1 0x1200
183 mov $r2 2
184 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
185
186 // setup i0 handler, and route all interrupts to it
187 mov $r1 ih
188 mov $iv0 $r1
189 mov $r1 0x400
190 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
191
192 // enable fifo interrupt
193 mov $r2 4
194 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
195
196 // enable interrupts
197 bset $flags ie0
198
199 // figure out which GPC we are, and how many TPCs we have
200 mov $r1 0x608
201 shl b32 $r1 6
202 iord $r2 I[$r1 + 0x000] // UNITS
203 mov $r3 1
204 and $r2 0x1f
205 shl b32 $r3 $r2
206 sub b32 $r3 1
207 st b32 D[$r0 + tpc_count] $r2
208 st b32 D[$r0 + tpc_mask] $r3
209 add b32 $r1 0x400
210 iord $r2 I[$r1 + 0x000] // MYINDEX
211 st b32 D[$r0 + gpc_id] $r2
212
213 // find context data for this chipset
214 mov $r2 0x800
215 shl b32 $r2 6
216 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
217 mov $r1 chipsets - 12
218 init_find_chipset:
219 add b32 $r1 12
220 ld b32 $r3 D[$r1 + 0x00]
221 cmpu b32 $r3 $r2
222 bra e init_context
223 cmpu b32 $r3 0
224 bra ne init_find_chipset
225 // unknown chipset
226 ret
227
228 // initialise context base, and size tracking
229 init_context:
230 mov $r2 0x800
231 shl b32 $r2 6
232 iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
233 clear b32 $r3 // track GPC context size here
234
235 // set mmctx base addresses now so we don't have to do it later,
236 // they don't currently ever change
237 mov $r4 0x700
238 shl b32 $r4 6
239 shr b32 $r5 $r2 8
240 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
241 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
242
243 // calculate GPC mmio context size, store the chipset-specific
244 // mmio list pointers somewhere we can get at them later without
245 // re-parsing the chipset list
246 clear b32 $r14
247 clear b32 $r15
248 ld b16 $r14 D[$r1 + 4]
249 ld b16 $r15 D[$r1 + 6]
250 st b16 D[$r0 + gpc_mmio_list_head] $r14
251 st b16 D[$r0 + gpc_mmio_list_tail] $r15
252 call mmctx_size
253 add b32 $r2 $r15
254 add b32 $r3 $r15
255
256 // calculate per-TPC mmio context size, store the list pointers
257 ld b16 $r14 D[$r1 + 8]
258 ld b16 $r15 D[$r1 + 10]
259 st b16 D[$r0 + tpc_mmio_list_head] $r14
260 st b16 D[$r0 + tpc_mmio_list_tail] $r15
261 call mmctx_size
262 ld b32 $r14 D[$r0 + tpc_count]
263 mulu $r14 $r15
264 add b32 $r2 $r14
265 add b32 $r3 $r14
266
267 // round up base/size to 256 byte boundary (for strand SWBASE)
268 add b32 $r4 0x1300
269 shr b32 $r3 2
270 iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
271 shr b32 $r2 8
272 shr b32 $r3 6
273 add b32 $r2 1
274 add b32 $r3 1
275 shl b32 $r2 8
276 shl b32 $r3 8
277
278 // calculate size of strand context data
279 mov b32 $r15 $r2
280 call strand_ctx_init
281 add b32 $r3 $r15
282
283 // save context size, and tell HUB we're done
284 mov $r1 0x800
285 shl b32 $r1 6
286 iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
287 add b32 $r1 0x800
288 clear b32 $r2
289 bset $r2 31
290 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
291
292// Main program loop, very simple, sleeps until woken up by the interrupt
293// handler, pulls a command from the queue and executes its handler
294//
295main:
296 bset $flags $p0
297 sleep $p0
298 mov $r13 cmd_queue
299 call queue_get
300 bra $p1 main
301
302 // 0x0000-0x0003 are all context transfers
303 cmpu b32 $r14 0x04
304 bra nc main_not_ctx_xfer
305 // fetch $flags and mask off $p1/$p2
306 mov $r1 $flags
307 mov $r2 0x0006
308 not b32 $r2
309 and $r1 $r2
310 // set $p1/$p2 according to transfer type
311 shl b32 $r14 1
312 or $r1 $r14
313 mov $flags $r1
314 // transfer context data
315 call ctx_xfer
316 bra main
317
318 main_not_ctx_xfer:
319 shl b32 $r15 $r14 16
320 or $r15 E_BAD_COMMAND
321 call error
322 bra main
323
324// interrupt handler
325ih:
326 push $r8
327 mov $r8 $flags
328 push $r8
329 push $r9
330 push $r10
331 push $r11
332 push $r13
333 push $r14
334 push $r15
335
336 // incoming fifo command?
337 iord $r10 I[$r0 + 0x200] // INTR
338 and $r11 $r10 0x00000004
339 bra e ih_no_fifo
340 // queue incoming fifo command for later processing
341 mov $r11 0x1900
342 mov $r13 cmd_queue
343 iord $r14 I[$r11 + 0x100] // FIFO_CMD
344 iord $r15 I[$r11 + 0x000] // FIFO_DATA
345 call queue_put
346 add b32 $r11 0x400
347 mov $r14 1
348 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
349
350 // ack, and wake up main()
351 ih_no_fifo:
352 iowr I[$r0 + 0x100] $r10 // INTR_ACK
353
354 pop $r15
355 pop $r14
356 pop $r13
357 pop $r11
358 pop $r10
359 pop $r9
360 pop $r8
361 mov $flags $r8
362 pop $r8
363 bclr $flags $p0
364 iret
365
366// Set this GPC's bit in HUB_BAR, used to signal completion of various
367// activities to the HUB fuc
368//
369hub_barrier_done:
370 mov $r15 1
371 ld b32 $r14 D[$r0 + gpc_id]
372 shl b32 $r15 $r14
373 mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
374 sethi $r14 0x400000
375 call nv_wr32
376 ret
377
378// Disables various things, waits a bit, and re-enables them..
379//
380// Not sure how exactly this helps, perhaps "ENABLE" is not such a
381// good description for the bits we turn off? Anyways, without this,
382// funny things happen.
383//
384ctx_redswitch:
385 mov $r14 0x614
386 shl b32 $r14 6
387 mov $r15 0x020
388 iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
389 mov $r15 8
390 ctx_redswitch_delay:
391 sub b32 $r15 1
392 bra ne ctx_redswitch_delay
393 mov $r15 0xa20
394 iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
395 ret
396
397// Transfer GPC context data between GPU and storage area
398//
399// In: $r15 context base address
400// $p1 clear on save, set on load
401// $p2 set if opposite direction done/will be done, so:
402// on save it means: "a load will follow this save"
403// on load it means: "a save preceeded this load"
404//
405ctx_xfer:
406 // set context base address
407 mov $r1 0xa04
408 shl b32 $r1 6
409 iowr I[$r1 + 0x000] $r15// MEM_BASE
410 bra not $p1 ctx_xfer_not_load
411 call ctx_redswitch
412 ctx_xfer_not_load:
413
414 // strands
415 mov $r1 0x4afc
416 sethi $r1 0x20000
417 mov $r2 0xc
418 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
419 call strand_wait
420 mov $r2 0x47fc
421 sethi $r2 0x20000
422 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
423 xbit $r2 $flags $p1
424 add b32 $r2 3
425 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
426
427 // mmio context
428 xbit $r10 $flags $p1 // direction
429 or $r10 2 // first
430 mov $r11 0x0000
431 sethi $r11 0x500000
432 ld b32 $r12 D[$r0 + gpc_id]
433 shl b32 $r12 15
434 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
435 ld b32 $r12 D[$r0 + gpc_mmio_list_head]
436 ld b32 $r13 D[$r0 + gpc_mmio_list_tail]
437 mov $r14 0 // not multi
438 call mmctx_xfer
439
440 // per-TPC mmio context
441 xbit $r10 $flags $p1 // direction
442 or $r10 4 // last
443 mov $r11 0x4000
444 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
445 ld b32 $r12 D[$r0 + gpc_id]
446 shl b32 $r12 15
447 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
448 ld b32 $r12 D[$r0 + tpc_mmio_list_head]
449 ld b32 $r13 D[$r0 + tpc_mmio_list_tail]
450 ld b32 $r15 D[$r0 + tpc_mask]
451 mov $r14 0x800 // stride = 0x800
452 call mmctx_xfer
453
454 // wait for strands to finish
455 call strand_wait
456
457 // if load, or a save without a load following, do some
458 // unknown stuff that's done after finishing a block of
459 // strand commands
460 bra $p1 ctx_xfer_post
461 bra not $p2 ctx_xfer_done
462 ctx_xfer_post:
463 mov $r1 0x4afc
464 sethi $r1 0x20000
465 mov $r2 0xd
466 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
467 call strand_wait
468
469 // mark completion in HUB's barrier
470 ctx_xfer_done:
471 call hub_barrier_done
472 ret
473
474.align 256
diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
new file mode 100644
index 000000000000..1896c898f5ba
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
@@ -0,0 +1,483 @@
1uint32_t nvc0_grgpc_data[] = {
2 0x00000000,
3 0x00000000,
4 0x00000000,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x000000c0,
28 0x011000b0,
29 0x01640114,
30 0x000000c1,
31 0x011400b0,
32 0x01780114,
33 0x000000c3,
34 0x011000b0,
35 0x01740114,
36 0x000000c4,
37 0x011000b0,
38 0x01740114,
39 0x000000c8,
40 0x011000b0,
41 0x01640114,
42 0x000000ce,
43 0x011000b0,
44 0x01740114,
45 0x00000000,
46 0x00000380,
47 0x14000400,
48 0x20000450,
49 0x00000600,
50 0x00000684,
51 0x10000700,
52 0x00000800,
53 0x08000808,
54 0x00000828,
55 0x00000830,
56 0x000008d8,
57 0x000008e0,
58 0x140008e8,
59 0x0000091c,
60 0x08000924,
61 0x00000b00,
62 0x14000b08,
63 0x00000bb8,
64 0x00000c08,
65 0x1c000c10,
66 0x00000c80,
67 0x00000c8c,
68 0x08001000,
69 0x00001014,
70 0x00000c6c,
71 0x00000018,
72 0x0000003c,
73 0x00000048,
74 0x00000064,
75 0x00000088,
76 0x14000200,
77 0x0400021c,
78 0x14000300,
79 0x000003d0,
80 0x040003e0,
81 0x08000400,
82 0x00000420,
83 0x000004b0,
84 0x000004e8,
85 0x000004f4,
86 0x04000520,
87 0x0c000604,
88 0x4c000644,
89 0x00000698,
90 0x04000750,
91 0x00000758,
92 0x000002c4,
93 0x000004bc,
94 0x000006e0,
95 0x00000544,
96};
97
98uint32_t nvc0_grgpc_code[] = {
99 0x03060ef5,
100 0x9800d898,
101 0x86f001d9,
102 0x0489b808,
103 0xf00c1bf4,
104 0x21f502f7,
105 0x00f802ec,
106 0xb60798c4,
107 0x8dbb0384,
108 0x0880b600,
109 0x80008e80,
110 0x90b6018f,
111 0x0f94f001,
112 0xf801d980,
113 0x0131f400,
114 0x9800d898,
115 0x89b801d9,
116 0x210bf404,
117 0xb60789c4,
118 0x9dbb0394,
119 0x0890b600,
120 0x98009e98,
121 0x80b6019f,
122 0x0f84f001,
123 0xf400d880,
124 0x00f80132,
125 0x0728b7f1,
126 0xb906b4b6,
127 0xc9f002ec,
128 0x00bcd01f,
129 0xc800bccf,
130 0x1bf41fcc,
131 0x06a7f0fa,
132 0x010321f5,
133 0xf840bfcf,
134 0x28b7f100,
135 0x06b4b607,
136 0xb980bfd0,
137 0xc9f002ec,
138 0x1ec9f01f,
139 0xcf00bcd0,
140 0xccc800bc,
141 0xfa1bf41f,
142 0x87f100f8,
143 0x84b60430,
144 0x1ff9f006,
145 0xf8008fd0,
146 0x3087f100,
147 0x0684b604,
148 0xf80080d0,
149 0x3c87f100,
150 0x0684b608,
151 0x99f094bd,
152 0x0089d000,
153 0x081887f1,
154 0xd00684b6,
155 0x87f1008a,
156 0x84b60400,
157 0x0088cf06,
158 0xf4888aff,
159 0x87f1f31b,
160 0x84b6085c,
161 0xf094bd06,
162 0x89d00099,
163 0xf100f800,
164 0xb6083c87,
165 0x94bd0684,
166 0xd00099f0,
167 0x87f10089,
168 0x84b60818,
169 0x008ad006,
170 0x040087f1,
171 0xcf0684b6,
172 0x8aff0088,
173 0xf30bf488,
174 0x085c87f1,
175 0xbd0684b6,
176 0x0099f094,
177 0xf80089d0,
178 0x9894bd00,
179 0x85b600e8,
180 0x0180b61a,
181 0xbb0284b6,
182 0xe0b60098,
183 0x04efb804,
184 0xb9eb1bf4,
185 0x00f8029f,
186 0x083c87f1,
187 0xbd0684b6,
188 0x0199f094,
189 0xf10089d0,
190 0xb6071087,
191 0x94bd0684,
192 0xf405bbfd,
193 0x8bd0090b,
194 0x0099f000,
195 0xf405eefd,
196 0x8ed00c0b,
197 0xc08fd080,
198 0xb70199f0,
199 0xc8010080,
200 0xb4b600ab,
201 0x0cb9f010,
202 0xb601aec8,
203 0xbefd11e4,
204 0x008bd005,
205 0xf0008ecf,
206 0x0bf41fe4,
207 0x00ce98fa,
208 0xd005e9fd,
209 0xc0b6c08e,
210 0x04cdb804,
211 0xc8e81bf4,
212 0x1bf402ab,
213 0x008bcf18,
214 0xb01fb4f0,
215 0x1bf410b4,
216 0x02a7f0f7,
217 0xf4c921f4,
218 0xabc81b0e,
219 0x10b4b600,
220 0xf00cb9f0,
221 0x8bd012b9,
222 0x008bcf00,
223 0xf412bbc8,
224 0x87f1fa1b,
225 0x84b6085c,
226 0xf094bd06,
227 0x89d00199,
228 0xf900f800,
229 0x02a7f0a0,
230 0xfcc921f4,
231 0xf100f8a0,
232 0xf04afc87,
233 0x97f00283,
234 0x0089d00c,
235 0x020721f5,
236 0x87f100f8,
237 0x83f04afc,
238 0x0d97f002,
239 0xf50089d0,
240 0xf8020721,
241 0xfca7f100,
242 0x02a3f04f,
243 0x0500aba2,
244 0xd00fc7f0,
245 0xc7f000ac,
246 0x00bcd00b,
247 0x020721f5,
248 0xf000aed0,
249 0xbcd00ac7,
250 0x0721f500,
251 0xf100f802,
252 0xb6083c87,
253 0x94bd0684,
254 0xd00399f0,
255 0x21f50089,
256 0xe7f00213,
257 0x3921f503,
258 0xfca7f102,
259 0x02a3f046,
260 0x0400aba0,
261 0xf040a0d0,
262 0xbcd001c7,
263 0x0721f500,
264 0x010c9202,
265 0xf000acd0,
266 0xbcd002c7,
267 0x0721f500,
268 0x2621f502,
269 0x8087f102,
270 0x0684b608,
271 0xb70089cf,
272 0x95220080,
273 0x8ed008fe,
274 0x408ed000,
275 0xb6808acf,
276 0xa0b606a5,
277 0x00eabb01,
278 0xb60480b6,
279 0x1bf40192,
280 0x08e4b6e8,
281 0xf1f2efbc,
282 0xb6085c87,
283 0x94bd0684,
284 0xd00399f0,
285 0x00f80089,
286 0xe7f1e0f9,
287 0xe3f09814,
288 0x8d21f440,
289 0x041ce0b7,
290 0xf401f7f0,
291 0xe0fc8d21,
292 0x04bd00f8,
293 0xf10004fe,
294 0xf0120017,
295 0x12d00227,
296 0x3e17f100,
297 0x0010fe04,
298 0x040017f1,
299 0xf0c010d0,
300 0x12d00427,
301 0x1031f400,
302 0x060817f1,
303 0xcf0614b6,
304 0x37f00012,
305 0x1f24f001,
306 0xb60432bb,
307 0x02800132,
308 0x04038003,
309 0x040010b7,
310 0x800012cf,
311 0x27f10002,
312 0x24b60800,
313 0x0022cf06,
314 0xb65817f0,
315 0x13980c10,
316 0x0432b800,
317 0xb00b0bf4,
318 0x1bf40034,
319 0xf100f8f1,
320 0xb6080027,
321 0x22cf0624,
322 0xf134bd40,
323 0xb6070047,
324 0x25950644,
325 0x0045d008,
326 0xbd4045d0,
327 0x58f4bde4,
328 0x1f58021e,
329 0x020e4003,
330 0xf5040f40,
331 0xbb013d21,
332 0x3fbb002f,
333 0x041e5800,
334 0x40051f58,
335 0x0f400a0e,
336 0x3d21f50c,
337 0x030e9801,
338 0xbb00effd,
339 0x3ebb002e,
340 0x0040b700,
341 0x0235b613,
342 0xb60043d0,
343 0x35b60825,
344 0x0120b606,
345 0xb60130b6,
346 0x34b60824,
347 0x022fb908,
348 0x026321f5,
349 0xf1003fbb,
350 0xb6080017,
351 0x13d00614,
352 0x0010b740,
353 0xf024bd08,
354 0x12d01f29,
355 0x0031f400,
356 0xf00028f4,
357 0x21f41cd7,
358 0xf401f439,
359 0xf404e4b0,
360 0x81fe1e18,
361 0x0627f001,
362 0x12fd20bd,
363 0x01e4b604,
364 0xfe051efd,
365 0x21f50018,
366 0x0ef404c3,
367 0x10ef94d3,
368 0xf501f5f0,
369 0xf402ec21,
370 0x80f9c60e,
371 0xf90188fe,
372 0xf990f980,
373 0xf9b0f9a0,
374 0xf9e0f9d0,
375 0x800acff0,
376 0xf404abc4,
377 0xb7f11d0b,
378 0xd7f01900,
379 0x40becf1c,
380 0xf400bfcf,
381 0xb0b70421,
382 0xe7f00400,
383 0x00bed001,
384 0xfc400ad0,
385 0xfce0fcf0,
386 0xfcb0fcd0,
387 0xfc90fca0,
388 0x0088fe80,
389 0x32f480fc,
390 0xf001f800,
391 0x0e9801f7,
392 0x04febb00,
393 0x9418e7f1,
394 0xf440e3f0,
395 0x00f88d21,
396 0x0614e7f1,
397 0xf006e4b6,
398 0xefd020f7,
399 0x08f7f000,
400 0xf401f2b6,
401 0xf7f1fd1b,
402 0xefd00a20,
403 0xf100f800,
404 0xb60a0417,
405 0x1fd00614,
406 0x0711f400,
407 0x04a421f5,
408 0x4afc17f1,
409 0xf00213f0,
410 0x12d00c27,
411 0x0721f500,
412 0xfc27f102,
413 0x0223f047,
414 0xf00020d0,
415 0x20b6012c,
416 0x0012d003,
417 0xf001acf0,
418 0xb7f002a5,
419 0x50b3f000,
420 0xb6000c98,
421 0xbcbb0fc4,
422 0x010c9800,
423 0xf0020d98,
424 0x21f500e7,
425 0xacf0015c,
426 0x04a5f001,
427 0x4000b7f1,
428 0x9850b3f0,
429 0xc4b6000c,
430 0x00bcbb0f,
431 0x98050c98,
432 0x0f98060d,
433 0x00e7f104,
434 0x5c21f508,
435 0x0721f501,
436 0x0601f402,
437 0xf11412f4,
438 0xf04afc17,
439 0x27f00213,
440 0x0012d00d,
441 0x020721f5,
442 0x048f21f5,
443 0x000000f8,
444 0x00000000,
445 0x00000000,
446 0x00000000,
447 0x00000000,
448 0x00000000,
449 0x00000000,
450 0x00000000,
451 0x00000000,
452 0x00000000,
453 0x00000000,
454 0x00000000,
455 0x00000000,
456 0x00000000,
457 0x00000000,
458 0x00000000,
459 0x00000000,
460 0x00000000,
461 0x00000000,
462 0x00000000,
463 0x00000000,
464 0x00000000,
465 0x00000000,
466 0x00000000,
467 0x00000000,
468 0x00000000,
469 0x00000000,
470 0x00000000,
471 0x00000000,
472 0x00000000,
473 0x00000000,
474 0x00000000,
475 0x00000000,
476 0x00000000,
477 0x00000000,
478 0x00000000,
479 0x00000000,
480 0x00000000,
481 0x00000000,
482 0x00000000,
483};
diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
new file mode 100644
index 000000000000..a1a599124cf4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc
@@ -0,0 +1,808 @@
1/* fuc microcode for nvc0 PGRAPH/HUB
2 *
3 * Copyright 2011 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Ben Skeggs
24 */
25
26/* To build:
27 * m4 nvc0_grhub.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grhub.fuc.h
28 */
29
30.section nvc0_grhub_data
31include(`nvc0_graph.fuc')
32gpc_count: .b32 0
33rop_count: .b32 0
34cmd_queue: queue_init
35hub_mmio_list_head: .b32 0
36hub_mmio_list_tail: .b32 0
37
38ctx_current: .b32 0
39
40chipsets:
41.b8 0xc0 0 0 0
42.b16 nvc0_hub_mmio_head
43.b16 nvc0_hub_mmio_tail
44.b8 0xc1 0 0 0
45.b16 nvc0_hub_mmio_head
46.b16 nvc1_hub_mmio_tail
47.b8 0xc3 0 0 0
48.b16 nvc0_hub_mmio_head
49.b16 nvc0_hub_mmio_tail
50.b8 0xc4 0 0 0
51.b16 nvc0_hub_mmio_head
52.b16 nvc0_hub_mmio_tail
53.b8 0xc8 0 0 0
54.b16 nvc0_hub_mmio_head
55.b16 nvc0_hub_mmio_tail
56.b8 0xce 0 0 0
57.b16 nvc0_hub_mmio_head
58.b16 nvc0_hub_mmio_tail
59.b8 0 0 0 0
60
61nvc0_hub_mmio_head:
62mmctx_data(0x17e91c, 2)
63mmctx_data(0x400204, 2)
64mmctx_data(0x404004, 11)
65mmctx_data(0x404044, 1)
66mmctx_data(0x404094, 14)
67mmctx_data(0x4040d0, 7)
68mmctx_data(0x4040f8, 1)
69mmctx_data(0x404130, 3)
70mmctx_data(0x404150, 3)
71mmctx_data(0x404164, 2)
72mmctx_data(0x404174, 3)
73mmctx_data(0x404200, 8)
74mmctx_data(0x404404, 14)
75mmctx_data(0x404460, 4)
76mmctx_data(0x404480, 1)
77mmctx_data(0x404498, 1)
78mmctx_data(0x404604, 4)
79mmctx_data(0x404618, 32)
80mmctx_data(0x404698, 21)
81mmctx_data(0x4046f0, 2)
82mmctx_data(0x404700, 22)
83mmctx_data(0x405800, 1)
84mmctx_data(0x405830, 3)
85mmctx_data(0x405854, 1)
86mmctx_data(0x405870, 4)
87mmctx_data(0x405a00, 2)
88mmctx_data(0x405a18, 1)
89mmctx_data(0x406020, 1)
90mmctx_data(0x406028, 4)
91mmctx_data(0x4064a8, 2)
92mmctx_data(0x4064b4, 2)
93mmctx_data(0x407804, 1)
94mmctx_data(0x40780c, 6)
95mmctx_data(0x4078bc, 1)
96mmctx_data(0x408000, 7)
97mmctx_data(0x408064, 1)
98mmctx_data(0x408800, 3)
99mmctx_data(0x408900, 4)
100mmctx_data(0x408980, 1)
101nvc0_hub_mmio_tail:
102mmctx_data(0x4064c0, 2)
103nvc1_hub_mmio_tail:
104
105.align 256
106chan_data:
107chan_mmio_count: .b32 0
108chan_mmio_address: .b32 0
109
110.align 256
111xfer_data: .b32 0
112
113.section nvc0_grhub_code
114bra init
115define(`include_code')
116include(`nvc0_graph.fuc')
117
118// reports an exception to the host
119//
120// In: $r15 error code (see nvc0_graph.fuc)
121//
122error:
123 push $r14
124 mov $r14 0x814
125 shl b32 $r14 6
126 iowr I[$r14 + 0x000] $r15 // CC_SCRATCH[5] = error code
127 mov $r14 0xc1c
128 shl b32 $r14 6
129 mov $r15 1
130 iowr I[$r14 + 0x000] $r15 // INTR_UP_SET
131 pop $r14
132 ret
133
134// HUB fuc initialisation, executed by triggering ucode start, will
135// fall through to main loop after completion.
136//
137// Input:
138// CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
139//
140// Output:
141// CC_SCRATCH[0]:
142// 31:31: set to signal completion
143// CC_SCRATCH[1]:
144// 31:0: total PGRAPH context size
145//
146init:
147 clear b32 $r0
148 mov $sp $r0
149 mov $xdbase $r0
150
151 // enable fifo access
152 mov $r1 0x1200
153 mov $r2 2
154 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
155
156 // setup i0 handler, and route all interrupts to it
157 mov $r1 ih
158 mov $iv0 $r1
159 mov $r1 0x400
160 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
161
162 // route HUB_CHANNEL_SWITCH to fuc interrupt 8
163 mov $r3 0x404
164 shl b32 $r3 6
165 mov $r2 0x2003 // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8
166 iowr I[$r3 + 0x000] $r2
167
168 // not sure what these are, route them because NVIDIA does, and
169 // the IRQ handler will signal the host if we ever get one.. we
170 // may find out if/why we need to handle these if so..
171 //
172 mov $r2 0x2004
173 iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9
174 mov $r2 0x200b
175 iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10
176 mov $r2 0x200c
177 iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15
178
179 // enable all INTR_UP interrupts
180 mov $r2 0xc24
181 shl b32 $r2 6
182 not b32 $r3 $r0
183 iowr I[$r2] $r3
184
185 // enable fifo, ctxsw, 9, 10, 15 interrupts
186 mov $r2 -0x78fc // 0x8704
187 sethi $r2 0
188 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
189
190 // fifo level triggered, rest edge
191 sub b32 $r1 0x100
192 mov $r2 4
193 iowr I[$r1] $r2
194
195 // enable interrupts
196 bset $flags ie0
197
198 // fetch enabled GPC/ROP counts
199 mov $r14 -0x69fc // 0x409604
200 sethi $r14 0x400000
201 call nv_rd32
202 extr $r1 $r15 16:20
203 st b32 D[$r0 + rop_count] $r1
204 and $r15 0x1f
205 st b32 D[$r0 + gpc_count] $r15
206
207 // set BAR_REQMASK to GPC mask
208 mov $r1 1
209 shl b32 $r1 $r15
210 sub b32 $r1 1
211 mov $r2 0x40c
212 shl b32 $r2 6
213 iowr I[$r2 + 0x000] $r1
214 iowr I[$r2 + 0x100] $r1
215
216 // find context data for this chipset
217 mov $r2 0x800
218 shl b32 $r2 6
219 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
220 mov $r15 chipsets - 8
221 init_find_chipset:
222 add b32 $r15 8
223 ld b32 $r3 D[$r15 + 0x00]
224 cmpu b32 $r3 $r2
225 bra e init_context
226 cmpu b32 $r3 0
227 bra ne init_find_chipset
228 // unknown chipset
229 ret
230
231 // context size calculation, reserve first 256 bytes for use by fuc
232 init_context:
233 mov $r1 256
234
235 // calculate size of mmio context data
236 ld b16 $r14 D[$r15 + 4]
237 ld b16 $r15 D[$r15 + 6]
238 sethi $r14 0
239 st b32 D[$r0 + hub_mmio_list_head] $r14
240 st b32 D[$r0 + hub_mmio_list_tail] $r15
241 call mmctx_size
242
243 // set mmctx base addresses now so we don't have to do it later,
244 // they don't (currently) ever change
245 mov $r3 0x700
246 shl b32 $r3 6
247 shr b32 $r4 $r1 8
248 iowr I[$r3 + 0x000] $r4 // MMCTX_SAVE_SWBASE
249 iowr I[$r3 + 0x100] $r4 // MMCTX_LOAD_SWBASE
250 add b32 $r3 0x1300
251 add b32 $r1 $r15
252 shr b32 $r15 2
253 iowr I[$r3 + 0x000] $r15 // MMCTX_LOAD_COUNT, wtf for?!?
254
255 // strands, base offset needs to be aligned to 256 bytes
256 shr b32 $r1 8
257 add b32 $r1 1
258 shl b32 $r1 8
259 mov b32 $r15 $r1
260 call strand_ctx_init
261 add b32 $r1 $r15
262
263 // initialise each GPC in sequence by passing in the offset of its
264 // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
265 // has previously been uploaded by the host) running.
266 //
267 // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
268 // when it has completed, and return the size of its context data
269 // in GPCn_CC_SCRATCH[1]
270 //
271 ld b32 $r3 D[$r0 + gpc_count]
272 mov $r4 0x2000
273 sethi $r4 0x500000
274 init_gpc:
275 // setup, and start GPC ucode running
276 add b32 $r14 $r4 0x804
277 mov b32 $r15 $r1
278 call nv_wr32 // CC_SCRATCH[1] = ctx offset
279 add b32 $r14 $r4 0x800
280 mov b32 $r15 $r2
281 call nv_wr32 // CC_SCRATCH[0] = chipset
282 add b32 $r14 $r4 0x10c
283 clear b32 $r15
284 call nv_wr32
285 add b32 $r14 $r4 0x104
286 call nv_wr32 // ENTRY
287 add b32 $r14 $r4 0x100
288 mov $r15 2 // CTRL_START_TRIGGER
289 call nv_wr32 // CTRL
290
291 // wait for it to complete, and adjust context size
292 add b32 $r14 $r4 0x800
293 init_gpc_wait:
294 call nv_rd32
295 xbit $r15 $r15 31
296 bra e init_gpc_wait
297 add b32 $r14 $r4 0x804
298 call nv_rd32
299 add b32 $r1 $r15
300
301 // next!
302 add b32 $r4 0x8000
303 sub b32 $r3 1
304 bra ne init_gpc
305
306 // save context size, and tell host we're ready
307 mov $r2 0x800
308 shl b32 $r2 6
309 iowr I[$r2 + 0x100] $r1 // CC_SCRATCH[1] = context size
310 add b32 $r2 0x800
311 clear b32 $r1
312 bset $r1 31
313 iowr I[$r2 + 0x000] $r1 // CC_SCRATCH[0] |= 0x80000000
314
315// Main program loop, very simple, sleeps until woken up by the interrupt
316// handler, pulls a command from the queue and executes its handler
317//
318main:
319 // sleep until we have something to do
320 bset $flags $p0
321 sleep $p0
322 mov $r13 cmd_queue
323 call queue_get
324 bra $p1 main
325
326 // context switch, requested by GPU?
327 cmpu b32 $r14 0x4001
328 bra ne main_not_ctx_switch
329 trace_set(T_AUTO)
330 mov $r1 0xb00
331 shl b32 $r1 6
332 iord $r2 I[$r1 + 0x100] // CHAN_NEXT
333 iord $r1 I[$r1 + 0x000] // CHAN_CUR
334
335 xbit $r3 $r1 31
336 bra e chsw_no_prev
337 xbit $r3 $r2 31
338 bra e chsw_prev_no_next
339 push $r2
340 mov b32 $r2 $r1
341 trace_set(T_SAVE)
342 bclr $flags $p1
343 bset $flags $p2
344 call ctx_xfer
345 trace_clr(T_SAVE);
346 pop $r2
347 trace_set(T_LOAD);
348 bset $flags $p1
349 call ctx_xfer
350 trace_clr(T_LOAD);
351 bra chsw_done
352 chsw_prev_no_next:
353 push $r2
354 mov b32 $r2 $r1
355 bclr $flags $p1
356 bclr $flags $p2
357 call ctx_xfer
358 pop $r2
359 mov $r1 0xb00
360 shl b32 $r1 6
361 iowr I[$r1] $r2
362 bra chsw_done
363 chsw_no_prev:
364 xbit $r3 $r2 31
365 bra e chsw_done
366 bset $flags $p1
367 bclr $flags $p2
368 call ctx_xfer
369
370 // ack the context switch request
371 chsw_done:
372 mov $r1 0xb0c
373 shl b32 $r1 6
374 mov $r2 1
375 iowr I[$r1 + 0x000] $r2 // 0x409b0c
376 trace_clr(T_AUTO)
377 bra main
378
379 // request to set current channel? (*not* a context switch)
380 main_not_ctx_switch:
381 cmpu b32 $r14 0x0001
382 bra ne main_not_ctx_chan
383 mov b32 $r2 $r15
384 call ctx_chan
385 bra main_done
386
387 // request to store current channel context?
388 main_not_ctx_chan:
389 cmpu b32 $r14 0x0002
390 bra ne main_not_ctx_save
391 trace_set(T_SAVE)
392 bclr $flags $p1
393 bclr $flags $p2
394 call ctx_xfer
395 trace_clr(T_SAVE)
396 bra main_done
397
398 main_not_ctx_save:
399 shl b32 $r15 $r14 16
400 or $r15 E_BAD_COMMAND
401 call error
402 bra main
403
404 main_done:
405 mov $r1 0x820
406 shl b32 $r1 6
407 clear b32 $r2
408 bset $r2 31
409 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
410 bra main
411
412// interrupt handler
413ih:
414 push $r8
415 mov $r8 $flags
416 push $r8
417 push $r9
418 push $r10
419 push $r11
420 push $r13
421 push $r14
422 push $r15
423
424 // incoming fifo command?
425 iord $r10 I[$r0 + 0x200] // INTR
426 and $r11 $r10 0x00000004
427 bra e ih_no_fifo
428 // queue incoming fifo command for later processing
429 mov $r11 0x1900
430 mov $r13 cmd_queue
431 iord $r14 I[$r11 + 0x100] // FIFO_CMD
432 iord $r15 I[$r11 + 0x000] // FIFO_DATA
433 call queue_put
434 add b32 $r11 0x400
435 mov $r14 1
436 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
437
438 // context switch request?
439 ih_no_fifo:
440 and $r11 $r10 0x00000100
441 bra e ih_no_ctxsw
442 // enqueue a context switch for later processing
443 mov $r13 cmd_queue
444 mov $r14 0x4001
445 call queue_put
446
447 // anything we didn't handle, bring it to the host's attention
448 ih_no_ctxsw:
449 mov $r11 0x104
450 not b32 $r11
451 and $r11 $r10 $r11
452 bra e ih_no_other
453 mov $r10 0xc1c
454 shl b32 $r10 6
455 iowr I[$r10] $r11 // INTR_UP_SET
456
457 // ack, and wake up main()
458 ih_no_other:
459 iowr I[$r0 + 0x100] $r10 // INTR_ACK
460
461 pop $r15
462 pop $r14
463 pop $r13
464 pop $r11
465 pop $r10
466 pop $r9
467 pop $r8
468 mov $flags $r8
469 pop $r8
470 bclr $flags $p0
471 iret
472
473// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
474ctx_4160s:
475 mov $r14 0x4160
476 sethi $r14 0x400000
477 mov $r15 1
478 call nv_wr32
479 ctx_4160s_wait:
480 call nv_rd32
481 xbit $r15 $r15 4
482 bra e ctx_4160s_wait
483 ret
484
485// Without clearing again at end of xfer, some things cause PGRAPH
486// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
487// still function with it set however...
488ctx_4160c:
489 mov $r14 0x4160
490 sethi $r14 0x400000
491 clear b32 $r15
492 call nv_wr32
493 ret
494
495// Again, not real sure
496//
497// In: $r15 value to set 0x404170 to
498//
499ctx_4170s:
500 mov $r14 0x4170
501 sethi $r14 0x400000
502 or $r15 0x10
503 call nv_wr32
504 ret
505
506// Waits for a ctx_4170s() call to complete
507//
508ctx_4170w:
509 mov $r14 0x4170
510 sethi $r14 0x400000
511 call nv_rd32
512 and $r15 0x10
513 bra ne ctx_4170w
514 ret
515
516// Disables various things, waits a bit, and re-enables them..
517//
518// Not sure how exactly this helps, perhaps "ENABLE" is not such a
519// good description for the bits we turn off? Anyways, without this,
520// funny things happen.
521//
522ctx_redswitch:
523 mov $r14 0x614
524 shl b32 $r14 6
525 mov $r15 0x270
526 iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL
527 mov $r15 8
528 ctx_redswitch_delay:
529 sub b32 $r15 1
530 bra ne ctx_redswitch_delay
531 mov $r15 0x770
532 iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL
533 ret
534
535// Not a clue what this is for, except that unless the value is 0x10, the
536// strand context is saved (and presumably restored) incorrectly..
537//
538// In: $r15 value to set to (0x00/0x10 are used)
539//
540ctx_86c:
541 mov $r14 0x86c
542 shl b32 $r14 6
543 iowr I[$r14] $r15 // HUB(0x86c) = val
544 mov $r14 -0x75ec
545 sethi $r14 0x400000
546 call nv_wr32 // ROP(0xa14) = val
547 mov $r14 -0x5794
548 sethi $r14 0x410000
549 call nv_wr32 // GPC(0x86c) = val
550 ret
551
552// ctx_load - load's a channel's ctxctl data, and selects its vm
553//
554// In: $r2 channel address
555//
556ctx_load:
557 trace_set(T_CHAN)
558
559 // switch to channel, somewhat magic in parts..
560 mov $r10 12 // DONE_UNK12
561 call wait_donez
562 mov $r1 0xa24
563 shl b32 $r1 6
564 iowr I[$r1 + 0x000] $r0 // 0x409a24
565 mov $r3 0xb00
566 shl b32 $r3 6
567 iowr I[$r3 + 0x100] $r2 // CHAN_NEXT
568 mov $r1 0xa0c
569 shl b32 $r1 6
570 mov $r4 7
571 iowr I[$r1 + 0x000] $r2 // MEM_CHAN
572 iowr I[$r1 + 0x100] $r4 // MEM_CMD
573 ctx_chan_wait_0:
574 iord $r4 I[$r1 + 0x100]
575 and $r4 0x1f
576 bra ne ctx_chan_wait_0
577 iowr I[$r3 + 0x000] $r2 // CHAN_CUR
578
579 // load channel header, fetch PGRAPH context pointer
580 mov $xtargets $r0
581 bclr $r2 31
582 shl b32 $r2 4
583 add b32 $r2 2
584
585 trace_set(T_LCHAN)
586 mov $r1 0xa04
587 shl b32 $r1 6
588 iowr I[$r1 + 0x000] $r2 // MEM_BASE
589 mov $r1 0xa20
590 shl b32 $r1 6
591 mov $r2 0x0002
592 sethi $r2 0x80000000
593 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram
594 mov $r1 0x10 // chan + 0x0210
595 mov $r2 xfer_data
596 sethi $r2 0x00020000 // 16 bytes
597 xdld $r1 $r2
598 xdwait
599 trace_clr(T_LCHAN)
600
601 // update current context
602 ld b32 $r1 D[$r0 + xfer_data + 4]
603 shl b32 $r1 24
604 ld b32 $r2 D[$r0 + xfer_data + 0]
605 shr b32 $r2 8
606 or $r1 $r2
607 st b32 D[$r0 + ctx_current] $r1
608
609 // set transfer base to start of context, and fetch context header
610 trace_set(T_LCTXH)
611 mov $r2 0xa04
612 shl b32 $r2 6
613 iowr I[$r2 + 0x000] $r1 // MEM_BASE
614 mov $r2 1
615 mov $r1 0xa20
616 shl b32 $r1 6
617 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm
618 mov $r1 chan_data
619 sethi $r1 0x00060000 // 256 bytes
620 xdld $r0 $r1
621 xdwait
622 trace_clr(T_LCTXH)
623
624 trace_clr(T_CHAN)
625 ret
626
627// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
628// the active channel for ctxctl, but not actually transfer
629// any context data. intended for use only during initial
630// context construction.
631//
632// In: $r2 channel address
633//
634ctx_chan:
635 call ctx_4160s
636 call ctx_load
637 mov $r10 12 // DONE_UNK12
638 call wait_donez
639 mov $r1 0xa10
640 shl b32 $r1 6
641 mov $r2 5
642 iowr I[$r1 + 0x000] $r2 // MEM_CMD = 5 (???)
643 ctx_chan_wait:
644 iord $r2 I[$r1 + 0x000]
645 or $r2 $r2
646 bra ne ctx_chan_wait
647 call ctx_4160c
648 ret
649
650// Execute per-context state overrides list
651//
652// Only executed on the first load of a channel. Might want to look into
653// removing this and having the host directly modify the channel's context
654// to change this state... The nouveau DRM already builds this list as
655// it's definitely needed for NVIDIA's, so we may as well use it for now
656//
657// Input: $r1 mmio list length
658//
659ctx_mmio_exec:
660 // set transfer base to be the mmio list
661 ld b32 $r3 D[$r0 + chan_mmio_address]
662 mov $r2 0xa04
663 shl b32 $r2 6
664 iowr I[$r2 + 0x000] $r3 // MEM_BASE
665
666 clear b32 $r3
667 ctx_mmio_loop:
668 // fetch next 256 bytes of mmio list if necessary
669 and $r4 $r3 0xff
670 bra ne ctx_mmio_pull
671 mov $r5 xfer_data
672 sethi $r5 0x00060000 // 256 bytes
673 xdld $r3 $r5
674 xdwait
675
676 // execute a single list entry
677 ctx_mmio_pull:
678 ld b32 $r14 D[$r4 + xfer_data + 0x00]
679 ld b32 $r15 D[$r4 + xfer_data + 0x04]
680 call nv_wr32
681
682 // next!
683 add b32 $r3 8
684 sub b32 $r1 1
685 bra ne ctx_mmio_loop
686
687 // set transfer base back to the current context
688 ctx_mmio_done:
689 ld b32 $r3 D[$r0 + ctx_current]
690 iowr I[$r2 + 0x000] $r3 // MEM_BASE
691
692 // disable the mmio list now, we don't need/want to execute it again
693 st b32 D[$r0 + chan_mmio_count] $r0
694 mov $r1 chan_data
695 sethi $r1 0x00060000 // 256 bytes
696 xdst $r0 $r1
697 xdwait
698 ret
699
700// Transfer HUB context data between GPU and storage area
701//
702// In: $r2 channel address
703// $p1 clear on save, set on load
704// $p2 set if opposite direction done/will be done, so:
705// on save it means: "a load will follow this save"
706// on load it means: "a save preceeded this load"
707//
708ctx_xfer:
709 bra not $p1 ctx_xfer_pre
710 bra $p2 ctx_xfer_pre_load
711 ctx_xfer_pre:
712 mov $r15 0x10
713 call ctx_86c
714 call ctx_4160s
715 bra not $p1 ctx_xfer_exec
716
717 ctx_xfer_pre_load:
718 mov $r15 2
719 call ctx_4170s
720 call ctx_4170w
721 call ctx_redswitch
722 clear b32 $r15
723 call ctx_4170s
724 call ctx_load
725
726 // fetch context pointer, and initiate xfer on all GPCs
727 ctx_xfer_exec:
728 ld b32 $r1 D[$r0 + ctx_current]
729 mov $r2 0x414
730 shl b32 $r2 6
731 iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
732 mov $r14 -0x5b00
733 sethi $r14 0x410000
734 mov b32 $r15 $r1
735 call nv_wr32 // GPC_BCAST_WRCMD_DATA = ctx pointer
736 add b32 $r14 4
737 xbit $r15 $flags $p1
738 xbit $r2 $flags $p2
739 shl b32 $r2 1
740 or $r15 $r2
741 call nv_wr32 // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
742
743 // strands
744 mov $r1 0x4afc
745 sethi $r1 0x20000
746 mov $r2 0xc
747 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
748 call strand_wait
749 mov $r2 0x47fc
750 sethi $r2 0x20000
751 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
752 xbit $r2 $flags $p1
753 add b32 $r2 3
754 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
755
756 // mmio context
757 xbit $r10 $flags $p1 // direction
758 or $r10 6 // first, last
759 mov $r11 0 // base = 0
760 ld b32 $r12 D[$r0 + hub_mmio_list_head]
761 ld b32 $r13 D[$r0 + hub_mmio_list_tail]
762 mov $r14 0 // not multi
763 call mmctx_xfer
764
765 // wait for GPCs to all complete
766 mov $r10 8 // DONE_BAR
767 call wait_doneo
768
769 // wait for strand xfer to complete
770 call strand_wait
771
772 // post-op
773 bra $p1 ctx_xfer_post
774 mov $r10 12 // DONE_UNK12
775 call wait_donez
776 mov $r1 0xa10
777 shl b32 $r1 6
778 mov $r2 5
779 iowr I[$r1] $r2 // MEM_CMD
780 ctx_xfer_post_save_wait:
781 iord $r2 I[$r1]
782 or $r2 $r2
783 bra ne ctx_xfer_post_save_wait
784
785 bra $p2 ctx_xfer_done
786 ctx_xfer_post:
787 mov $r15 2
788 call ctx_4170s
789 clear b32 $r15
790 call ctx_86c
791 call strand_post
792 call ctx_4170w
793 clear b32 $r15
794 call ctx_4170s
795
796 bra not $p1 ctx_xfer_no_post_mmio
797 ld b32 $r1 D[$r0 + chan_mmio_count]
798 or $r1 $r1
799 bra e ctx_xfer_no_post_mmio
800 call ctx_mmio_exec
801
802 ctx_xfer_no_post_mmio:
803 call ctx_4160c
804
805 ctx_xfer_done:
806 ret
807
808.align 256
diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
new file mode 100644
index 000000000000..b3b541b6d044
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
@@ -0,0 +1,838 @@
1uint32_t nvc0_grhub_data[] = {
2 0x00000000,
3 0x00000000,
4 0x00000000,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x000000c0,
26 0x012c0090,
27 0x000000c1,
28 0x01300090,
29 0x000000c3,
30 0x012c0090,
31 0x000000c4,
32 0x012c0090,
33 0x000000c8,
34 0x012c0090,
35 0x000000ce,
36 0x012c0090,
37 0x00000000,
38 0x0417e91c,
39 0x04400204,
40 0x28404004,
41 0x00404044,
42 0x34404094,
43 0x184040d0,
44 0x004040f8,
45 0x08404130,
46 0x08404150,
47 0x04404164,
48 0x08404174,
49 0x1c404200,
50 0x34404404,
51 0x0c404460,
52 0x00404480,
53 0x00404498,
54 0x0c404604,
55 0x7c404618,
56 0x50404698,
57 0x044046f0,
58 0x54404700,
59 0x00405800,
60 0x08405830,
61 0x00405854,
62 0x0c405870,
63 0x04405a00,
64 0x00405a18,
65 0x00406020,
66 0x0c406028,
67 0x044064a8,
68 0x044064b4,
69 0x00407804,
70 0x1440780c,
71 0x004078bc,
72 0x18408000,
73 0x00408064,
74 0x08408800,
75 0x0c408900,
76 0x00408980,
77 0x044064c0,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x00000000,
93 0x00000000,
94 0x00000000,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x00000000,
115 0x00000000,
116 0x00000000,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139 0x00000000,
140 0x00000000,
141 0x00000000,
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195};
196
197uint32_t nvc0_grhub_code[] = {
198 0x03090ef5,
199 0x9800d898,
200 0x86f001d9,
201 0x0489b808,
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838};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 13:34:12 -0500