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authorTony Lindgren <tony@atomide.com>2015-01-28 12:00:49 -0500
committerMichael Turquette <mturquette@linaro.org>2015-02-25 15:06:29 -0500
commit03208cc69fc16a8d46de49f51f49964666e4a694 (patch)
tree08b4a61f707d891c3a3f13e192908361a736a636
parentc517d838eb7d07bbe9507871fab3931deccff539 (diff)
clk: ti: Fix FAPLL parent enable bit handling
Commit 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x") added basic support for the FAPLL on dm818x, but has a bug for the parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3) but the code is doing a shift on it. This means the parent PLL won't get disabled even if all it's child synthesizers are disabled. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
-rw-r--r--drivers/clk/ti/fapll.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 6ef89639a9f6..d21640634adf 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -84,7 +84,7 @@ static int ti_fapll_enable(struct clk_hw *hw)
84 struct fapll_data *fd = to_fapll(hw); 84 struct fapll_data *fd = to_fapll(hw);
85 u32 v = readl_relaxed(fd->base); 85 u32 v = readl_relaxed(fd->base);
86 86
87 v |= (1 << FAPLL_MAIN_PLLEN); 87 v |= FAPLL_MAIN_PLLEN;
88 writel_relaxed(v, fd->base); 88 writel_relaxed(v, fd->base);
89 89
90 return 0; 90 return 0;
@@ -95,7 +95,7 @@ static void ti_fapll_disable(struct clk_hw *hw)
95 struct fapll_data *fd = to_fapll(hw); 95 struct fapll_data *fd = to_fapll(hw);
96 u32 v = readl_relaxed(fd->base); 96 u32 v = readl_relaxed(fd->base);
97 97
98 v &= ~(1 << FAPLL_MAIN_PLLEN); 98 v &= ~FAPLL_MAIN_PLLEN;
99 writel_relaxed(v, fd->base); 99 writel_relaxed(v, fd->base);
100} 100}
101 101
@@ -104,7 +104,7 @@ static int ti_fapll_is_enabled(struct clk_hw *hw)
104 struct fapll_data *fd = to_fapll(hw); 104 struct fapll_data *fd = to_fapll(hw);
105 u32 v = readl_relaxed(fd->base); 105 u32 v = readl_relaxed(fd->base);
106 106
107 return v & (1 << FAPLL_MAIN_PLLEN); 107 return v & FAPLL_MAIN_PLLEN;
108} 108}
109 109
110static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, 110static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,