diff options
author | Tomas Winkler <tomas.winkler@intel.com> | 2008-04-17 19:03:38 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2008-05-07 15:02:11 -0400 |
commit | a693f187facbf25925bbcf201db88c5384468646 (patch) | |
tree | 4db39a08946dc297431034192eaee44d1d7e3cdc | |
parent | fe07aa7acd9ec221d4440a38ffc9a58776cb34bc (diff) |
iwlwifi: define ANA_PLL values in iwl-csr.h
This patch defines ANA_PLL values in iwl-csr.h
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-3945.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 7 |
2 files changed, 6 insertions, 3 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index d3406830c8e3..8464397f7816 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c | |||
@@ -1229,7 +1229,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv) | |||
1229 | iwl3945_power_init_handle(priv); | 1229 | iwl3945_power_init_handle(priv); |
1230 | 1230 | ||
1231 | spin_lock_irqsave(&priv->lock, flags); | 1231 | spin_lock_irqsave(&priv->lock, flags); |
1232 | iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24)); | 1232 | iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL); |
1233 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, | 1233 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
1234 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | 1234 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
1235 | 1235 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index a59f48b02f05..82c7445d2927 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
@@ -95,8 +95,7 @@ | |||
95 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) | 95 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
96 | #define CSR_LED_REG (CSR_BASE+0x094) | 96 | #define CSR_LED_REG (CSR_BASE+0x094) |
97 | 97 | ||
98 | /* Analog phase-lock-loop configuration (3945 only) | 98 | /* Analog phase-lock-loop configuration */ |
99 | * Set bit 24. */ | ||
100 | #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) | 99 | #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) |
101 | /* | 100 | /* |
102 | * Indicates hardware rev, to determine CCK backoff for txpower calculation. | 101 | * Indicates hardware rev, to determine CCK backoff for txpower calculation. |
@@ -219,6 +218,10 @@ | |||
219 | #define CSR_LED_REG_TRUN_ON (0x78) | 218 | #define CSR_LED_REG_TRUN_ON (0x78) |
220 | #define CSR_LED_REG_TRUN_OFF (0x38) | 219 | #define CSR_LED_REG_TRUN_OFF (0x38) |
221 | 220 | ||
221 | /* ANA_PLL */ | ||
222 | #define CSR39_ANA_PLL_CFG_VAL (0x01000000) | ||
223 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) | ||
224 | |||
222 | /*=== HBUS (Host-side Bus) ===*/ | 225 | /*=== HBUS (Host-side Bus) ===*/ |
223 | #define HBUS_BASE (0x400) | 226 | #define HBUS_BASE (0x400) |
224 | /* | 227 | /* |