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authorBen Hutchings <bhutchings@solarflare.com>2009-10-23 04:30:17 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-24 07:27:00 -0400
commit625b451455cebb7120492766c8425b6e808fc209 (patch)
tree363f5124ee89bdb883f63ce6c30e11fb4b3b4035
parent56241ceb9e75fc1a5fb142a754096ad6c6ab19ee (diff)
sfc: Move RX data FIFO thresholds out of struct efx_nic_type
Since there are now separate blocks of code to set the thresholds for each NIC type, it is no longer useful to include them in the NIC type description. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/sfc/falcon.c23
-rw-r--r--drivers/net/sfc/net_driver.h4
2 files changed, 12 insertions, 15 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 4cb98d473c4d..c23e8e2b094a 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -2922,16 +2922,17 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
2922 const unsigned ctrl_xon_thr = 20; 2922 const unsigned ctrl_xon_thr = 20;
2923 const unsigned ctrl_xoff_thr = 25; 2923 const unsigned ctrl_xoff_thr = 25;
2924 /* RX data FIFO thresholds (256-byte units; size varies) */ 2924 /* RX data FIFO thresholds (256-byte units; size varies) */
2925 unsigned data_xon_thr = 2925 int data_xon_thr = rx_xon_thresh_bytes >> 8;
2926 ((rx_xon_thresh_bytes >= 0) ? 2926 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2927 rx_xon_thresh_bytes : efx->type->rx_xon_thresh) >> 8;
2928 unsigned data_xoff_thr =
2929 ((rx_xoff_thresh_bytes >= 0) ?
2930 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh) >> 8;
2931 efx_oword_t reg; 2927 efx_oword_t reg;
2932 2928
2933 falcon_read(efx, &reg, RX_CFG_REG_KER); 2929 falcon_read(efx, &reg, RX_CFG_REG_KER);
2934 if (falcon_rev(efx) <= FALCON_REV_A1) { 2930 if (falcon_rev(efx) <= FALCON_REV_A1) {
2931 /* Data FIFO size is 5.5K */
2932 if (data_xon_thr < 0)
2933 data_xon_thr = 512 >> 8;
2934 if (data_xoff_thr < 0)
2935 data_xoff_thr = 2048 >> 8;
2935 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_A1, 0); 2936 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_A1, 0);
2936 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_A1, huge_buf_size); 2937 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_A1, huge_buf_size);
2937 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_A1, data_xon_thr); 2938 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_A1, data_xon_thr);
@@ -2939,7 +2940,11 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
2939 EFX_SET_OWORD_FIELD(reg, RX_XON_TX_TH_A1, ctrl_xon_thr); 2940 EFX_SET_OWORD_FIELD(reg, RX_XON_TX_TH_A1, ctrl_xon_thr);
2940 EFX_SET_OWORD_FIELD(reg, RX_XOFF_TX_TH_A1, ctrl_xoff_thr); 2941 EFX_SET_OWORD_FIELD(reg, RX_XOFF_TX_TH_A1, ctrl_xoff_thr);
2941 } else { 2942 } else {
2942 /* Register fields moved */ 2943 /* Data FIFO size is 80K; register fields moved */
2944 if (data_xon_thr < 0)
2945 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
2946 if (data_xoff_thr < 0)
2947 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
2943 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_B0, 0); 2948 EFX_SET_OWORD_FIELD(reg, RX_DESC_PUSH_EN_B0, 0);
2944 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_B0, huge_buf_size); 2949 EFX_SET_OWORD_FIELD(reg, RX_USR_BUF_SIZE_B0, huge_buf_size);
2945 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_B0, data_xon_thr); 2950 EFX_SET_OWORD_FIELD(reg, RX_XON_MAC_TH_B0, data_xon_thr);
@@ -3130,8 +3135,6 @@ struct efx_nic_type falcon_a_nic_type = {
3130 .max_dma_mask = FALCON_DMA_MASK, 3135 .max_dma_mask = FALCON_DMA_MASK,
3131 .tx_dma_mask = FALCON_TX_DMA_MASK, 3136 .tx_dma_mask = FALCON_TX_DMA_MASK,
3132 .bug5391_mask = 0xf, 3137 .bug5391_mask = 0xf,
3133 .rx_xoff_thresh = 2048,
3134 .rx_xon_thresh = 512,
3135 .rx_buffer_padding = 0x24, 3138 .rx_buffer_padding = 0x24,
3136 .max_interrupt_mode = EFX_INT_MODE_MSI, 3139 .max_interrupt_mode = EFX_INT_MODE_MSI,
3137 .phys_addr_channels = 4, 3140 .phys_addr_channels = 4,
@@ -3154,8 +3157,6 @@ struct efx_nic_type falcon_b_nic_type = {
3154 .max_dma_mask = FALCON_DMA_MASK, 3157 .max_dma_mask = FALCON_DMA_MASK,
3155 .tx_dma_mask = FALCON_TX_DMA_MASK, 3158 .tx_dma_mask = FALCON_TX_DMA_MASK,
3156 .bug5391_mask = 0, 3159 .bug5391_mask = 0,
3157 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3158 .rx_xon_thresh = 27648, /* ~3*max MTU */
3159 .rx_buffer_padding = 0, 3160 .rx_buffer_padding = 0,
3160 .max_interrupt_mode = EFX_INT_MODE_MSIX, 3161 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3161 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy 3162 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
diff --git a/drivers/net/sfc/net_driver.h b/drivers/net/sfc/net_driver.h
index 298566da638b..479a6fe38318 100644
--- a/drivers/net/sfc/net_driver.h
+++ b/drivers/net/sfc/net_driver.h
@@ -875,8 +875,6 @@ static inline const char *efx_dev_name(struct efx_nic *efx)
875 * @max_dma_mask: Maximum possible DMA mask 875 * @max_dma_mask: Maximum possible DMA mask
876 * @tx_dma_mask: TX DMA mask 876 * @tx_dma_mask: TX DMA mask
877 * @bug5391_mask: Address mask for bug 5391 workaround 877 * @bug5391_mask: Address mask for bug 5391 workaround
878 * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
879 * @rx_xon_thresh: RX FIFO XON watermark (bytes)
880 * @rx_buffer_padding: Padding added to each RX buffer 878 * @rx_buffer_padding: Padding added to each RX buffer
881 * @max_interrupt_mode: Highest capability interrupt mode supported 879 * @max_interrupt_mode: Highest capability interrupt mode supported
882 * from &enum efx_init_mode. 880 * from &enum efx_init_mode.
@@ -899,8 +897,6 @@ struct efx_nic_type {
899 unsigned int tx_dma_mask; 897 unsigned int tx_dma_mask;
900 unsigned bug5391_mask; 898 unsigned bug5391_mask;
901 899
902 int rx_xoff_thresh;
903 int rx_xon_thresh;
904 unsigned int rx_buffer_padding; 900 unsigned int rx_buffer_padding;
905 unsigned int max_interrupt_mode; 901 unsigned int max_interrupt_mode;
906 unsigned int phys_addr_channels; 902 unsigned int phys_addr_channels;