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authorMarc Kleine-Budde <mkl@pengutronix.de>2010-09-28 04:18:34 -0400
committerMarc Kleine-Budde <mkl@pengutronix.de>2010-10-18 05:19:42 -0400
commitd3cd15657516141adce387810be8cb377baf020e (patch)
treef85a4b2ab4b8bd7f532ccf93e56dc1cade87eb6e
parent7e15de3a73899903f33975b1ce57cf59c616d1d9 (diff)
can: mcp251x: write intf only when needed
This patch introduces a variable "clear_intf" that hold the bits that should be cleared. Only read-modify-write register if "clear_intf" is set. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Wolfgang Grandegger <wg@grandegger.com>
-rw-r--r--drivers/net/can/mcp251x.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/net/can/mcp251x.c b/drivers/net/can/mcp251x.c
index 7e2f951002a5..f5e2edd09ce4 100644
--- a/drivers/net/can/mcp251x.c
+++ b/drivers/net/can/mcp251x.c
@@ -125,6 +125,8 @@
125# define CANINTF_TX0IF 0x04 125# define CANINTF_TX0IF 0x04
126# define CANINTF_RX1IF 0x02 126# define CANINTF_RX1IF 0x02
127# define CANINTF_RX0IF 0x01 127# define CANINTF_RX0IF 0x01
128# define CANINTF_ERR_TX \
129 (CANINTF_ERRIF | CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
128#define EFLG 0x2d 130#define EFLG 0x2d
129# define EFLG_EWARN 0x01 131# define EFLG_EWARN 0x01
130# define EFLG_RXWAR 0x02 132# define EFLG_RXWAR 0x02
@@ -769,10 +771,12 @@ static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
769 while (!priv->force_quit) { 771 while (!priv->force_quit) {
770 enum can_state new_state; 772 enum can_state new_state;
771 u8 intf, eflag; 773 u8 intf, eflag;
774 u8 clear_intf = 0;
772 int can_id = 0, data1 = 0; 775 int can_id = 0, data1 = 0;
773 776
774 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); 777 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
775 778
779 /* receive buffer 0 */
776 if (intf & CANINTF_RX0IF) { 780 if (intf & CANINTF_RX0IF) {
777 mcp251x_hw_rx(spi, 0); 781 mcp251x_hw_rx(spi, 0);
778 /* Free one buffer ASAP */ 782 /* Free one buffer ASAP */
@@ -780,10 +784,17 @@ static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
780 0x00); 784 0x00);
781 } 785 }
782 786
783 if (intf & CANINTF_RX1IF) 787 /* receive buffer 1 */
788 if (intf & CANINTF_RX1IF) {
784 mcp251x_hw_rx(spi, 1); 789 mcp251x_hw_rx(spi, 1);
790 clear_intf |= CANINTF_RX1IF;
791 }
785 792
786 mcp251x_write_bits(spi, CANINTF, intf, 0x00); 793 /* any error or tx interrupt we need to clear? */
794 if (intf & CANINTF_ERR_TX)
795 clear_intf |= intf & CANINTF_ERR_TX;
796 if (clear_intf)
797 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
787 798
788 if (eflag) 799 if (eflag)
789 mcp251x_write_bits(spi, EFLG, eflag, 0x00); 800 mcp251x_write_bits(spi, EFLG, eflag, 0x00);