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authorAlex Deucher <alexdeucher@gmail.com>2009-03-06 11:47:54 -0500
committerDave Airlie <airlied@redhat.com>2009-03-13 00:24:16 -0400
commit800b69951174f7de294da575d7e7921041a7e783 (patch)
treecb6208891d5d661e87fe5fde57313ea0b6531f1f
parenta7d13ad0e2c1b0572492fd53ca1a090794e2f8e2 (diff)
drm/radeon: RS600: fix interrupt handling
the checks weren't updated when RS600 support was added. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq.c14
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 1e3b2557a51a..2cb4f32b81d4 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -46,7 +46,7 @@ static int radeon_suspend(struct drm_device *dev, pm_message_t state)
46 drm_radeon_private_t *dev_priv = dev->dev_private; 46 drm_radeon_private_t *dev_priv = dev->dev_private;
47 47
48 /* Disable *all* interrupts */ 48 /* Disable *all* interrupts */
49 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) 49 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
50 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 50 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
51 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 51 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
52 return 0; 52 return 0;
@@ -57,7 +57,7 @@ static int radeon_resume(struct drm_device *dev)
57 drm_radeon_private_t *dev_priv = dev->dev_private; 57 drm_radeon_private_t *dev_priv = dev->dev_private;
58 58
59 /* Restore interrupt registers */ 59 /* Restore interrupt registers */
60 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) 60 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
61 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 61 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
62 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 62 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
63 return 0; 63 return 0;
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index 8289e16419a8..9836c705a952 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -65,7 +65,7 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc)
65{ 65{
66 drm_radeon_private_t *dev_priv = dev->dev_private; 66 drm_radeon_private_t *dev_priv = dev->dev_private;
67 67
68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { 68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
69 switch (crtc) { 69 switch (crtc) {
70 case 0: 70 case 0:
71 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1); 71 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
@@ -100,7 +100,7 @@ void radeon_disable_vblank(struct drm_device *dev, int crtc)
100{ 100{
101 drm_radeon_private_t *dev_priv = dev->dev_private; 101 drm_radeon_private_t *dev_priv = dev->dev_private;
102 102
103 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { 103 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
104 switch (crtc) { 104 switch (crtc) {
105 case 0: 105 case 0:
106 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0); 106 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
@@ -135,7 +135,7 @@ static inline u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r
135 u32 irq_mask = RADEON_SW_INT_TEST; 135 u32 irq_mask = RADEON_SW_INT_TEST;
136 136
137 *r500_disp_int = 0; 137 *r500_disp_int = 0;
138 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { 138 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
139 /* vbl interrupts in a different place */ 139 /* vbl interrupts in a different place */
140 140
141 if (irqs & R500_DISPLAY_INT_STATUS) { 141 if (irqs & R500_DISPLAY_INT_STATUS) {
@@ -202,7 +202,7 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
202 DRM_WAKEUP(&dev_priv->swi_queue); 202 DRM_WAKEUP(&dev_priv->swi_queue);
203 203
204 /* VBLANK interrupt */ 204 /* VBLANK interrupt */
205 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { 205 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
206 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT) 206 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
207 drm_handle_vblank(dev, 0); 207 drm_handle_vblank(dev, 0);
208 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT) 208 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
@@ -265,7 +265,7 @@ u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
265 return -EINVAL; 265 return -EINVAL;
266 } 266 }
267 267
268 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) { 268 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
269 if (crtc == 0) 269 if (crtc == 0)
270 return RADEON_READ(R500_D1CRTC_FRAME_COUNT); 270 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
271 else 271 else
@@ -327,7 +327,7 @@ void radeon_driver_irq_preinstall(struct drm_device * dev)
327 u32 dummy; 327 u32 dummy;
328 328
329 /* Disable *all* interrupts */ 329 /* Disable *all* interrupts */
330 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) 330 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
331 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 331 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
332 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 332 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
333 333
@@ -357,7 +357,7 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
357 if (!dev_priv) 357 if (!dev_priv)
358 return; 358 return;
359 359
360 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) 360 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
361 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 361 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
362 /* Disable *all* interrupts */ 362 /* Disable *all* interrupts */
363 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 363 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);