diff options
author | Kazunori Asayama <asayama@sm.sony.co.jp> | 2007-07-20 15:39:30 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@klappe.arndb.de> | 2007-07-20 15:41:47 -0400 |
commit | 49776d30aea903fb2f9966c8e9b6f23ae5f7c937 (patch) | |
tree | d17073772de1e741960d5f741ce57e9fb6ead5b8 | |
parent | d1450317554d52e0e4a454806c4d05bb2a834f00 (diff) |
[CELL] spufs: Avoid unexpectedly restaring MFC during context save
The current SPU context saving procedure in SPUFS unexpectedly
restarts MFC when halting decrementer, because MFC_CNTL[Dh] is set
without MFC_CNTL[Sm]. This bug causes, for example, saving broken DMA
queues. Here is a patch to fix the problem.
Signed-off-by: Kazunori Asayama <asayama@sm.sony.co.jp>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
-rw-r--r-- | arch/powerpc/platforms/cell/spufs/switch.c | 3 | ||||
-rw-r--r-- | include/asm-powerpc/spu.h | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/cell/spufs/switch.c b/arch/powerpc/platforms/cell/spufs/switch.c index 9c506ba08cdc..827aada391f2 100644 --- a/arch/powerpc/platforms/cell/spufs/switch.c +++ b/arch/powerpc/platforms/cell/spufs/switch.c | |||
@@ -271,7 +271,8 @@ static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu) | |||
271 | * Write MFC_CNTL[Dh] set to a '1' to halt | 271 | * Write MFC_CNTL[Dh] set to a '1' to halt |
272 | * the decrementer. | 272 | * the decrementer. |
273 | */ | 273 | */ |
274 | out_be64(&priv2->mfc_control_RW, MFC_CNTL_DECREMENTER_HALTED); | 274 | out_be64(&priv2->mfc_control_RW, |
275 | MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK); | ||
275 | eieio(); | 276 | eieio(); |
276 | } | 277 | } |
277 | 278 | ||
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h index 42d88a6d2dfd..a034f03b8107 100644 --- a/include/asm-powerpc/spu.h +++ b/include/asm-powerpc/spu.h | |||
@@ -411,6 +411,7 @@ struct spu_priv2 { | |||
411 | #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0) | 411 | #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0) |
412 | #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0) | 412 | #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0) |
413 | #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0) | 413 | #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0) |
414 | #define MFC_CNTL_SUSPEND_MASK (1ull << 4) | ||
414 | #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8) | 415 | #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8) |
415 | #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8) | 416 | #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8) |
416 | #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8) | 417 | #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8) |