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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2010-06-14 02:49:00 -0400
committerIngo Molnar <mingo@elte.hu>2010-09-09 14:46:29 -0400
commit33696fc0d141bbbcb12f75b69608ea83282e3117 (patch)
tree72e08dba377d57eb7dd8c08a937a6de10e8af9c4
parent24cd7f54a0d47e1d5b3de29e2456bfbd2d8447b7 (diff)
perf: Per PMU disable
Changes perf_disable() into perf_pmu_disable(). Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: paulus <paulus@samba.org> Cc: stephane eranian <eranian@googlemail.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Cyrill Gorcunov <gorcunov@gmail.com> Cc: Lin Ming <ming.m.lin@intel.com> Cc: Yanmin <yanmin_zhang@linux.intel.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Cc: David Miller <davem@davemloft.net> Cc: Michael Cree <mcree@orcon.net.nz> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
-rw-r--r--arch/alpha/kernel/perf_event.c30
-rw-r--r--arch/arm/kernel/perf_event.c28
-rw-r--r--arch/powerpc/kernel/perf_event.c24
-rw-r--r--arch/powerpc/kernel/perf_event_fsl_emb.c18
-rw-r--r--arch/sh/kernel/perf_event.c38
-rw-r--r--arch/sparc/kernel/perf_event.c20
-rw-r--r--arch/x86/kernel/cpu/perf_event.c16
-rw-r--r--include/linux/perf_event.h13
-rw-r--r--kernel/perf_event.c31
9 files changed, 119 insertions, 99 deletions
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index 19660b5c298f..3e260731f8e6 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -435,7 +435,7 @@ static int alpha_pmu_enable(struct perf_event *event)
435 * nevertheless we disable the PMCs first to enable a potential 435 * nevertheless we disable the PMCs first to enable a potential
436 * final PMI to occur before we disable interrupts. 436 * final PMI to occur before we disable interrupts.
437 */ 437 */
438 perf_disable(); 438 perf_pmu_disable(event->pmu);
439 local_irq_save(flags); 439 local_irq_save(flags);
440 440
441 /* Default to error to be returned */ 441 /* Default to error to be returned */
@@ -456,7 +456,7 @@ static int alpha_pmu_enable(struct perf_event *event)
456 } 456 }
457 457
458 local_irq_restore(flags); 458 local_irq_restore(flags);
459 perf_enable(); 459 perf_pmu_enable(event->pmu);
460 460
461 return ret; 461 return ret;
462} 462}
@@ -474,7 +474,7 @@ static void alpha_pmu_disable(struct perf_event *event)
474 unsigned long flags; 474 unsigned long flags;
475 int j; 475 int j;
476 476
477 perf_disable(); 477 perf_pmu_disable(event->pmu);
478 local_irq_save(flags); 478 local_irq_save(flags);
479 479
480 for (j = 0; j < cpuc->n_events; j++) { 480 for (j = 0; j < cpuc->n_events; j++) {
@@ -502,7 +502,7 @@ static void alpha_pmu_disable(struct perf_event *event)
502 } 502 }
503 503
504 local_irq_restore(flags); 504 local_irq_restore(flags);
505 perf_enable(); 505 perf_pmu_enable(event->pmu);
506} 506}
507 507
508 508
@@ -668,18 +668,10 @@ static int alpha_pmu_event_init(struct perf_event *event)
668 return err; 668 return err;
669} 669}
670 670
671static struct pmu pmu = {
672 .event_init = alpha_pmu_event_init,
673 .enable = alpha_pmu_enable,
674 .disable = alpha_pmu_disable,
675 .read = alpha_pmu_read,
676 .unthrottle = alpha_pmu_unthrottle,
677};
678
679/* 671/*
680 * Main entry point - enable HW performance counters. 672 * Main entry point - enable HW performance counters.
681 */ 673 */
682void hw_perf_enable(void) 674static void alpha_pmu_pmu_enable(struct pmu *pmu)
683{ 675{
684 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 676 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
685 677
@@ -705,7 +697,7 @@ void hw_perf_enable(void)
705 * Main entry point - disable HW performance counters. 697 * Main entry point - disable HW performance counters.
706 */ 698 */
707 699
708void hw_perf_disable(void) 700static void alpha_pmu_pmu_disable(struct pmu *pmu)
709{ 701{
710 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 702 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
711 703
@@ -718,6 +710,16 @@ void hw_perf_disable(void)
718 wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask); 710 wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask);
719} 711}
720 712
713static struct pmu pmu = {
714 .pmu_enable = alpha_pmu_pmu_enable,
715 .pmu_disable = alpha_pmu_pmu_disable,
716 .event_init = alpha_pmu_event_init,
717 .enable = alpha_pmu_enable,
718 .disable = alpha_pmu_disable,
719 .read = alpha_pmu_read,
720 .unthrottle = alpha_pmu_unthrottle,
721};
722
721 723
722/* 724/*
723 * Main entry point - don't know when this is called but it 725 * Main entry point - don't know when this is called but it
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index afc92c580d18..3343f3f4b973 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -277,7 +277,7 @@ armpmu_enable(struct perf_event *event)
277 int idx; 277 int idx;
278 int err = 0; 278 int err = 0;
279 279
280 perf_disable(); 280 perf_pmu_disable(event->pmu);
281 281
282 /* If we don't have a space for the counter then finish early. */ 282 /* If we don't have a space for the counter then finish early. */
283 idx = armpmu->get_event_idx(cpuc, hwc); 283 idx = armpmu->get_event_idx(cpuc, hwc);
@@ -305,7 +305,7 @@ armpmu_enable(struct perf_event *event)
305 perf_event_update_userpage(event); 305 perf_event_update_userpage(event);
306 306
307out: 307out:
308 perf_enable(); 308 perf_pmu_enable(event->pmu);
309 return err; 309 return err;
310} 310}
311 311
@@ -534,16 +534,7 @@ static int armpmu_event_init(struct perf_event *event)
534 return err; 534 return err;
535} 535}
536 536
537static struct pmu pmu = { 537static void armpmu_pmu_enable(struct pmu *pmu)
538 .event_init = armpmu_event_init,
539 .enable = armpmu_enable,
540 .disable = armpmu_disable,
541 .unthrottle = armpmu_unthrottle,
542 .read = armpmu_read,
543};
544
545void
546hw_perf_enable(void)
547{ 538{
548 /* Enable all of the perf events on hardware. */ 539 /* Enable all of the perf events on hardware. */
549 int idx; 540 int idx;
@@ -564,13 +555,22 @@ hw_perf_enable(void)
564 armpmu->start(); 555 armpmu->start();
565} 556}
566 557
567void 558static void armpmu_pmu_disable(struct pmu *pmu)
568hw_perf_disable(void)
569{ 559{
570 if (armpmu) 560 if (armpmu)
571 armpmu->stop(); 561 armpmu->stop();
572} 562}
573 563
564static struct pmu pmu = {
565 .pmu_enable = armpmu_pmu_enable,
566 .pmu_disable= armpmu_pmu_disable,
567 .event_init = armpmu_event_init,
568 .enable = armpmu_enable,
569 .disable = armpmu_disable,
570 .unthrottle = armpmu_unthrottle,
571 .read = armpmu_read,
572};
573
574/* 574/*
575 * ARMv6 Performance counter handling code. 575 * ARMv6 Performance counter handling code.
576 * 576 *
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index c1408821dbc2..deb84bbcb0e6 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -517,7 +517,7 @@ static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
517 * Disable all events to prevent PMU interrupts and to allow 517 * Disable all events to prevent PMU interrupts and to allow
518 * events to be added or removed. 518 * events to be added or removed.
519 */ 519 */
520void hw_perf_disable(void) 520static void power_pmu_pmu_disable(struct pmu *pmu)
521{ 521{
522 struct cpu_hw_events *cpuhw; 522 struct cpu_hw_events *cpuhw;
523 unsigned long flags; 523 unsigned long flags;
@@ -565,7 +565,7 @@ void hw_perf_disable(void)
565 * If we were previously disabled and events were added, then 565 * If we were previously disabled and events were added, then
566 * put the new config on the PMU. 566 * put the new config on the PMU.
567 */ 567 */
568void hw_perf_enable(void) 568static void power_pmu_pmu_enable(struct pmu *pmu)
569{ 569{
570 struct perf_event *event; 570 struct perf_event *event;
571 struct cpu_hw_events *cpuhw; 571 struct cpu_hw_events *cpuhw;
@@ -735,7 +735,7 @@ static int power_pmu_enable(struct perf_event *event)
735 int ret = -EAGAIN; 735 int ret = -EAGAIN;
736 736
737 local_irq_save(flags); 737 local_irq_save(flags);
738 perf_disable(); 738 perf_pmu_disable(event->pmu);
739 739
740 /* 740 /*
741 * Add the event to the list (if there is room) 741 * Add the event to the list (if there is room)
@@ -769,7 +769,7 @@ nocheck:
769 769
770 ret = 0; 770 ret = 0;
771 out: 771 out:
772 perf_enable(); 772 perf_pmu_enable(event->pmu);
773 local_irq_restore(flags); 773 local_irq_restore(flags);
774 return ret; 774 return ret;
775} 775}
@@ -784,7 +784,7 @@ static void power_pmu_disable(struct perf_event *event)
784 unsigned long flags; 784 unsigned long flags;
785 785
786 local_irq_save(flags); 786 local_irq_save(flags);
787 perf_disable(); 787 perf_pmu_disable(event->pmu);
788 788
789 power_pmu_read(event); 789 power_pmu_read(event);
790 790
@@ -821,7 +821,7 @@ static void power_pmu_disable(struct perf_event *event)
821 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 821 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
822 } 822 }
823 823
824 perf_enable(); 824 perf_pmu_enable(event->pmu);
825 local_irq_restore(flags); 825 local_irq_restore(flags);
826} 826}
827 827
@@ -837,7 +837,7 @@ static void power_pmu_unthrottle(struct perf_event *event)
837 if (!event->hw.idx || !event->hw.sample_period) 837 if (!event->hw.idx || !event->hw.sample_period)
838 return; 838 return;
839 local_irq_save(flags); 839 local_irq_save(flags);
840 perf_disable(); 840 perf_pmu_disable(event->pmu);
841 power_pmu_read(event); 841 power_pmu_read(event);
842 left = event->hw.sample_period; 842 left = event->hw.sample_period;
843 event->hw.last_period = left; 843 event->hw.last_period = left;
@@ -848,7 +848,7 @@ static void power_pmu_unthrottle(struct perf_event *event)
848 local64_set(&event->hw.prev_count, val); 848 local64_set(&event->hw.prev_count, val);
849 local64_set(&event->hw.period_left, left); 849 local64_set(&event->hw.period_left, left);
850 perf_event_update_userpage(event); 850 perf_event_update_userpage(event);
851 perf_enable(); 851 perf_pmu_enable(event->pmu);
852 local_irq_restore(flags); 852 local_irq_restore(flags);
853} 853}
854 854
@@ -861,7 +861,7 @@ void power_pmu_start_txn(struct pmu *pmu)
861{ 861{
862 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 862 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
863 863
864 perf_disable(); 864 perf_pmu_disable(pmu);
865 cpuhw->group_flag |= PERF_EVENT_TXN; 865 cpuhw->group_flag |= PERF_EVENT_TXN;
866 cpuhw->n_txn_start = cpuhw->n_events; 866 cpuhw->n_txn_start = cpuhw->n_events;
867} 867}
@@ -876,7 +876,7 @@ void power_pmu_cancel_txn(struct pmu *pmu)
876 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 876 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
877 877
878 cpuhw->group_flag &= ~PERF_EVENT_TXN; 878 cpuhw->group_flag &= ~PERF_EVENT_TXN;
879 perf_enable(); 879 perf_pmu_enable(pmu);
880} 880}
881 881
882/* 882/*
@@ -903,7 +903,7 @@ int power_pmu_commit_txn(struct pmu *pmu)
903 cpuhw->event[i]->hw.config = cpuhw->events[i]; 903 cpuhw->event[i]->hw.config = cpuhw->events[i];
904 904
905 cpuhw->group_flag &= ~PERF_EVENT_TXN; 905 cpuhw->group_flag &= ~PERF_EVENT_TXN;
906 perf_enable(); 906 perf_pmu_enable(pmu);
907 return 0; 907 return 0;
908} 908}
909 909
@@ -1131,6 +1131,8 @@ static int power_pmu_event_init(struct perf_event *event)
1131} 1131}
1132 1132
1133struct pmu power_pmu = { 1133struct pmu power_pmu = {
1134 .pmu_enable = power_pmu_pmu_enable,
1135 .pmu_disable = power_pmu_pmu_disable,
1134 .event_init = power_pmu_event_init, 1136 .event_init = power_pmu_event_init,
1135 .enable = power_pmu_enable, 1137 .enable = power_pmu_enable,
1136 .disable = power_pmu_disable, 1138 .disable = power_pmu_disable,
diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c
index 9bc84a7fd901..84b1974c628f 100644
--- a/arch/powerpc/kernel/perf_event_fsl_emb.c
+++ b/arch/powerpc/kernel/perf_event_fsl_emb.c
@@ -177,7 +177,7 @@ static void fsl_emb_pmu_read(struct perf_event *event)
177 * Disable all events to prevent PMU interrupts and to allow 177 * Disable all events to prevent PMU interrupts and to allow
178 * events to be added or removed. 178 * events to be added or removed.
179 */ 179 */
180void hw_perf_disable(void) 180static void fsl_emb_pmu_pmu_disable(struct pmu *pmu)
181{ 181{
182 struct cpu_hw_events *cpuhw; 182 struct cpu_hw_events *cpuhw;
183 unsigned long flags; 183 unsigned long flags;
@@ -216,7 +216,7 @@ void hw_perf_disable(void)
216 * If we were previously disabled and events were added, then 216 * If we were previously disabled and events were added, then
217 * put the new config on the PMU. 217 * put the new config on the PMU.
218 */ 218 */
219void hw_perf_enable(void) 219static void fsl_emb_pmu_pmu_enable(struct pmu *pmu)
220{ 220{
221 struct cpu_hw_events *cpuhw; 221 struct cpu_hw_events *cpuhw;
222 unsigned long flags; 222 unsigned long flags;
@@ -271,7 +271,7 @@ static int fsl_emb_pmu_enable(struct perf_event *event)
271 u64 val; 271 u64 val;
272 int i; 272 int i;
273 273
274 perf_disable(); 274 perf_pmu_disable(event->pmu);
275 cpuhw = &get_cpu_var(cpu_hw_events); 275 cpuhw = &get_cpu_var(cpu_hw_events);
276 276
277 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) 277 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED)
@@ -311,7 +311,7 @@ static int fsl_emb_pmu_enable(struct perf_event *event)
311 ret = 0; 311 ret = 0;
312 out: 312 out:
313 put_cpu_var(cpu_hw_events); 313 put_cpu_var(cpu_hw_events);
314 perf_enable(); 314 perf_pmu_enable(event->pmu);
315 return ret; 315 return ret;
316} 316}
317 317
@@ -321,7 +321,7 @@ static void fsl_emb_pmu_disable(struct perf_event *event)
321 struct cpu_hw_events *cpuhw; 321 struct cpu_hw_events *cpuhw;
322 int i = event->hw.idx; 322 int i = event->hw.idx;
323 323
324 perf_disable(); 324 perf_pmu_disable(event->pmu);
325 if (i < 0) 325 if (i < 0)
326 goto out; 326 goto out;
327 327
@@ -349,7 +349,7 @@ static void fsl_emb_pmu_disable(struct perf_event *event)
349 cpuhw->n_events--; 349 cpuhw->n_events--;
350 350
351 out: 351 out:
352 perf_enable(); 352 perf_pmu_enable(event->pmu);
353 put_cpu_var(cpu_hw_events); 353 put_cpu_var(cpu_hw_events);
354} 354}
355 355
@@ -367,7 +367,7 @@ static void fsl_emb_pmu_unthrottle(struct perf_event *event)
367 if (event->hw.idx < 0 || !event->hw.sample_period) 367 if (event->hw.idx < 0 || !event->hw.sample_period)
368 return; 368 return;
369 local_irq_save(flags); 369 local_irq_save(flags);
370 perf_disable(); 370 perf_pmu_disable(event->pmu);
371 fsl_emb_pmu_read(event); 371 fsl_emb_pmu_read(event);
372 left = event->hw.sample_period; 372 left = event->hw.sample_period;
373 event->hw.last_period = left; 373 event->hw.last_period = left;
@@ -378,7 +378,7 @@ static void fsl_emb_pmu_unthrottle(struct perf_event *event)
378 local64_set(&event->hw.prev_count, val); 378 local64_set(&event->hw.prev_count, val);
379 local64_set(&event->hw.period_left, left); 379 local64_set(&event->hw.period_left, left);
380 perf_event_update_userpage(event); 380 perf_event_update_userpage(event);
381 perf_enable(); 381 perf_pmu_enable(event->pmu);
382 local_irq_restore(flags); 382 local_irq_restore(flags);
383} 383}
384 384
@@ -524,6 +524,8 @@ static int fsl_emb_pmu_event_init(struct perf_event *event)
524} 524}
525 525
526static struct pmu fsl_emb_pmu = { 526static struct pmu fsl_emb_pmu = {
527 .pmu_enable = fsl_emb_pmu_pmu_enable,
528 .pmu_disable = fsl_emb_pmu_pmu_disable,
527 .event_init = fsl_emb_pmu_event_init, 529 .event_init = fsl_emb_pmu_event_init,
528 .enable = fsl_emb_pmu_enable, 530 .enable = fsl_emb_pmu_enable,
529 .disable = fsl_emb_pmu_disable, 531 .disable = fsl_emb_pmu_disable,
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index d042989ceb45..4bbe19058a58 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -232,7 +232,7 @@ static int sh_pmu_enable(struct perf_event *event)
232 int idx = hwc->idx; 232 int idx = hwc->idx;
233 int ret = -EAGAIN; 233 int ret = -EAGAIN;
234 234
235 perf_disable(); 235 perf_pmu_disable(event->pmu);
236 236
237 if (test_and_set_bit(idx, cpuc->used_mask)) { 237 if (test_and_set_bit(idx, cpuc->used_mask)) {
238 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); 238 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
@@ -253,7 +253,7 @@ static int sh_pmu_enable(struct perf_event *event)
253 perf_event_update_userpage(event); 253 perf_event_update_userpage(event);
254 ret = 0; 254 ret = 0;
255out: 255out:
256 perf_enable(); 256 perf_pmu_enable(event->pmu);
257 return ret; 257 return ret;
258} 258}
259 259
@@ -285,7 +285,25 @@ static int sh_pmu_event_init(struct perf_event *event)
285 return err; 285 return err;
286} 286}
287 287
288static void sh_pmu_pmu_enable(struct pmu *pmu)
289{
290 if (!sh_pmu_initialized())
291 return;
292
293 sh_pmu->enable_all();
294}
295
296static void sh_pmu_pmu_disable(struct pmu *pmu)
297{
298 if (!sh_pmu_initialized())
299 return;
300
301 sh_pmu->disable_all();
302}
303
288static struct pmu pmu = { 304static struct pmu pmu = {
305 .pmu_enable = sh_pmu_pmu_enable,
306 .pmu_disable = sh_pmu_pmu_disable,
289 .event_init = sh_pmu_event_init, 307 .event_init = sh_pmu_event_init,
290 .enable = sh_pmu_enable, 308 .enable = sh_pmu_enable,
291 .disable = sh_pmu_disable, 309 .disable = sh_pmu_disable,
@@ -316,22 +334,6 @@ sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
316 return NOTIFY_OK; 334 return NOTIFY_OK;
317} 335}
318 336
319void hw_perf_enable(void)
320{
321 if (!sh_pmu_initialized())
322 return;
323
324 sh_pmu->enable_all();
325}
326
327void hw_perf_disable(void)
328{
329 if (!sh_pmu_initialized())
330 return;
331
332 sh_pmu->disable_all();
333}
334
335int __cpuinit register_sh_pmu(struct sh_pmu *pmu) 337int __cpuinit register_sh_pmu(struct sh_pmu *pmu)
336{ 338{
337 if (sh_pmu) 339 if (sh_pmu)
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index d0131deeeaf6..37cae676536c 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -664,7 +664,7 @@ out:
664 return pcr; 664 return pcr;
665} 665}
666 666
667void hw_perf_enable(void) 667static void sparc_pmu_pmu_enable(struct pmu *pmu)
668{ 668{
669 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 669 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
670 u64 pcr; 670 u64 pcr;
@@ -691,7 +691,7 @@ void hw_perf_enable(void)
691 pcr_ops->write(cpuc->pcr); 691 pcr_ops->write(cpuc->pcr);
692} 692}
693 693
694void hw_perf_disable(void) 694static void sparc_pmu_pmu_disable(struct pmu *pmu)
695{ 695{
696 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 696 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
697 u64 val; 697 u64 val;
@@ -718,7 +718,7 @@ static void sparc_pmu_disable(struct perf_event *event)
718 int i; 718 int i;
719 719
720 local_irq_save(flags); 720 local_irq_save(flags);
721 perf_disable(); 721 perf_pmu_disable(event->pmu);
722 722
723 for (i = 0; i < cpuc->n_events; i++) { 723 for (i = 0; i < cpuc->n_events; i++) {
724 if (event == cpuc->event[i]) { 724 if (event == cpuc->event[i]) {
@@ -748,7 +748,7 @@ static void sparc_pmu_disable(struct perf_event *event)
748 } 748 }
749 } 749 }
750 750
751 perf_enable(); 751 perf_pmu_enable(event->pmu);
752 local_irq_restore(flags); 752 local_irq_restore(flags);
753} 753}
754 754
@@ -991,7 +991,7 @@ static int sparc_pmu_enable(struct perf_event *event)
991 unsigned long flags; 991 unsigned long flags;
992 992
993 local_irq_save(flags); 993 local_irq_save(flags);
994 perf_disable(); 994 perf_pmu_disable(event->pmu);
995 995
996 n0 = cpuc->n_events; 996 n0 = cpuc->n_events;
997 if (n0 >= perf_max_events) 997 if (n0 >= perf_max_events)
@@ -1020,7 +1020,7 @@ nocheck:
1020 1020
1021 ret = 0; 1021 ret = 0;
1022out: 1022out:
1023 perf_enable(); 1023 perf_pmu_enable(event->pmu);
1024 local_irq_restore(flags); 1024 local_irq_restore(flags);
1025 return ret; 1025 return ret;
1026} 1026}
@@ -1113,7 +1113,7 @@ static void sparc_pmu_start_txn(struct pmu *pmu)
1113{ 1113{
1114 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1114 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1115 1115
1116 perf_disable(); 1116 perf_pmu_disable(pmu);
1117 cpuhw->group_flag |= PERF_EVENT_TXN; 1117 cpuhw->group_flag |= PERF_EVENT_TXN;
1118} 1118}
1119 1119
@@ -1127,7 +1127,7 @@ static void sparc_pmu_cancel_txn(struct pmu *pmu)
1127 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1127 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1128 1128
1129 cpuhw->group_flag &= ~PERF_EVENT_TXN; 1129 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1130 perf_enable(); 1130 perf_pmu_enable(pmu);
1131} 1131}
1132 1132
1133/* 1133/*
@@ -1151,11 +1151,13 @@ static int sparc_pmu_commit_txn(struct pmu *pmu)
1151 return -EAGAIN; 1151 return -EAGAIN;
1152 1152
1153 cpuc->group_flag &= ~PERF_EVENT_TXN; 1153 cpuc->group_flag &= ~PERF_EVENT_TXN;
1154 perf_enable(); 1154 perf_pmu_enable(pmu);
1155 return 0; 1155 return 0;
1156} 1156}
1157 1157
1158static struct pmu pmu = { 1158static struct pmu pmu = {
1159 .pmu_enable = sparc_pmu_pmu_enable,
1160 .pmu_disable = sparc_pmu_pmu_disable,
1159 .event_init = sparc_pmu_event_init, 1161 .event_init = sparc_pmu_event_init,
1160 .enable = sparc_pmu_enable, 1162 .enable = sparc_pmu_enable,
1161 .disable = sparc_pmu_disable, 1163 .disable = sparc_pmu_disable,
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 846070ce49c3..79705ac45019 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -583,7 +583,7 @@ static void x86_pmu_disable_all(void)
583 } 583 }
584} 584}
585 585
586void hw_perf_disable(void) 586static void x86_pmu_pmu_disable(struct pmu *pmu)
587{ 587{
588 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 588 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
589 589
@@ -803,7 +803,7 @@ static inline int match_prev_assignment(struct hw_perf_event *hwc,
803static int x86_pmu_start(struct perf_event *event); 803static int x86_pmu_start(struct perf_event *event);
804static void x86_pmu_stop(struct perf_event *event); 804static void x86_pmu_stop(struct perf_event *event);
805 805
806void hw_perf_enable(void) 806static void x86_pmu_pmu_enable(struct pmu *pmu)
807{ 807{
808 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 808 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
809 struct perf_event *event; 809 struct perf_event *event;
@@ -969,7 +969,7 @@ static int x86_pmu_enable(struct perf_event *event)
969 969
970 hwc = &event->hw; 970 hwc = &event->hw;
971 971
972 perf_disable(); 972 perf_pmu_disable(event->pmu);
973 n0 = cpuc->n_events; 973 n0 = cpuc->n_events;
974 ret = n = collect_events(cpuc, event, false); 974 ret = n = collect_events(cpuc, event, false);
975 if (ret < 0) 975 if (ret < 0)
@@ -999,7 +999,7 @@ done_collect:
999 999
1000 ret = 0; 1000 ret = 0;
1001out: 1001out:
1002 perf_enable(); 1002 perf_pmu_enable(event->pmu);
1003 return ret; 1003 return ret;
1004} 1004}
1005 1005
@@ -1436,7 +1436,7 @@ static void x86_pmu_start_txn(struct pmu *pmu)
1436{ 1436{
1437 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 1437 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1438 1438
1439 perf_disable(); 1439 perf_pmu_disable(pmu);
1440 cpuc->group_flag |= PERF_EVENT_TXN; 1440 cpuc->group_flag |= PERF_EVENT_TXN;
1441 cpuc->n_txn = 0; 1441 cpuc->n_txn = 0;
1442} 1442}
@@ -1456,7 +1456,7 @@ static void x86_pmu_cancel_txn(struct pmu *pmu)
1456 */ 1456 */
1457 cpuc->n_added -= cpuc->n_txn; 1457 cpuc->n_added -= cpuc->n_txn;
1458 cpuc->n_events -= cpuc->n_txn; 1458 cpuc->n_events -= cpuc->n_txn;
1459 perf_enable(); 1459 perf_pmu_enable(pmu);
1460} 1460}
1461 1461
1462/* 1462/*
@@ -1486,7 +1486,7 @@ static int x86_pmu_commit_txn(struct pmu *pmu)
1486 memcpy(cpuc->assign, assign, n*sizeof(int)); 1486 memcpy(cpuc->assign, assign, n*sizeof(int));
1487 1487
1488 cpuc->group_flag &= ~PERF_EVENT_TXN; 1488 cpuc->group_flag &= ~PERF_EVENT_TXN;
1489 perf_enable(); 1489 perf_pmu_enable(pmu);
1490 return 0; 1490 return 0;
1491} 1491}
1492 1492
@@ -1605,6 +1605,8 @@ int x86_pmu_event_init(struct perf_event *event)
1605} 1605}
1606 1606
1607static struct pmu pmu = { 1607static struct pmu pmu = {
1608 .pmu_enable = x86_pmu_pmu_enable,
1609 .pmu_disable = x86_pmu_pmu_disable,
1608 .event_init = x86_pmu_event_init, 1610 .event_init = x86_pmu_event_init,
1609 .enable = x86_pmu_enable, 1611 .enable = x86_pmu_enable,
1610 .disable = x86_pmu_disable, 1612 .disable = x86_pmu_disable,
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 243286a8ded7..6abf103fb7f8 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -563,6 +563,11 @@ struct perf_event;
563struct pmu { 563struct pmu {
564 struct list_head entry; 564 struct list_head entry;
565 565
566 int *pmu_disable_count;
567
568 void (*pmu_enable) (struct pmu *pmu);
569 void (*pmu_disable) (struct pmu *pmu);
570
566 /* 571 /*
567 * Should return -ENOENT when the @event doesn't match this PMU. 572 * Should return -ENOENT when the @event doesn't match this PMU.
568 */ 573 */
@@ -868,10 +873,8 @@ extern void perf_event_free_task(struct task_struct *task);
868extern void set_perf_event_pending(void); 873extern void set_perf_event_pending(void);
869extern void perf_event_do_pending(void); 874extern void perf_event_do_pending(void);
870extern void perf_event_print_debug(void); 875extern void perf_event_print_debug(void);
871extern void __perf_disable(void); 876extern void perf_pmu_disable(struct pmu *pmu);
872extern bool __perf_enable(void); 877extern void perf_pmu_enable(struct pmu *pmu);
873extern void perf_disable(void);
874extern void perf_enable(void);
875extern int perf_event_task_disable(void); 878extern int perf_event_task_disable(void);
876extern int perf_event_task_enable(void); 879extern int perf_event_task_enable(void);
877extern void perf_event_update_userpage(struct perf_event *event); 880extern void perf_event_update_userpage(struct perf_event *event);
@@ -1056,8 +1059,6 @@ static inline void perf_event_exit_task(struct task_struct *child) { }
1056static inline void perf_event_free_task(struct task_struct *task) { } 1059static inline void perf_event_free_task(struct task_struct *task) { }
1057static inline void perf_event_do_pending(void) { } 1060static inline void perf_event_do_pending(void) { }
1058static inline void perf_event_print_debug(void) { } 1061static inline void perf_event_print_debug(void) { }
1059static inline void perf_disable(void) { }
1060static inline void perf_enable(void) { }
1061static inline int perf_event_task_disable(void) { return -EINVAL; } 1062static inline int perf_event_task_disable(void) { return -EINVAL; }
1062static inline int perf_event_task_enable(void) { return -EINVAL; } 1063static inline int perf_event_task_enable(void) { return -EINVAL; }
1063 1064
diff --git a/kernel/perf_event.c b/kernel/perf_event.c
index 9a98ce953561..5ed0c06765bb 100644
--- a/kernel/perf_event.c
+++ b/kernel/perf_event.c
@@ -71,23 +71,20 @@ static atomic64_t perf_event_id;
71 */ 71 */
72static DEFINE_SPINLOCK(perf_resource_lock); 72static DEFINE_SPINLOCK(perf_resource_lock);
73 73
74void __weak hw_perf_disable(void) { barrier(); }
75void __weak hw_perf_enable(void) { barrier(); }
76
77void __weak perf_event_print_debug(void) { } 74void __weak perf_event_print_debug(void) { }
78 75
79static DEFINE_PER_CPU(int, perf_disable_count); 76void perf_pmu_disable(struct pmu *pmu)
80
81void perf_disable(void)
82{ 77{
83 if (!__get_cpu_var(perf_disable_count)++) 78 int *count = this_cpu_ptr(pmu->pmu_disable_count);
84 hw_perf_disable(); 79 if (!(*count)++)
80 pmu->pmu_disable(pmu);
85} 81}
86 82
87void perf_enable(void) 83void perf_pmu_enable(struct pmu *pmu)
88{ 84{
89 if (!--__get_cpu_var(perf_disable_count)) 85 int *count = this_cpu_ptr(pmu->pmu_disable_count);
90 hw_perf_enable(); 86 if (!--(*count))
87 pmu->pmu_enable(pmu);
91} 88}
92 89
93static void get_ctx(struct perf_event_context *ctx) 90static void get_ctx(struct perf_event_context *ctx)
@@ -4970,11 +4967,19 @@ static struct srcu_struct pmus_srcu;
4970 4967
4971int perf_pmu_register(struct pmu *pmu) 4968int perf_pmu_register(struct pmu *pmu)
4972{ 4969{
4970 int ret;
4971
4973 mutex_lock(&pmus_lock); 4972 mutex_lock(&pmus_lock);
4973 ret = -ENOMEM;
4974 pmu->pmu_disable_count = alloc_percpu(int);
4975 if (!pmu->pmu_disable_count)
4976 goto unlock;
4974 list_add_rcu(&pmu->entry, &pmus); 4977 list_add_rcu(&pmu->entry, &pmus);
4978 ret = 0;
4979unlock:
4975 mutex_unlock(&pmus_lock); 4980 mutex_unlock(&pmus_lock);
4976 4981
4977 return 0; 4982 return ret;
4978} 4983}
4979 4984
4980void perf_pmu_unregister(struct pmu *pmu) 4985void perf_pmu_unregister(struct pmu *pmu)
@@ -4984,6 +4989,8 @@ void perf_pmu_unregister(struct pmu *pmu)
4984 mutex_unlock(&pmus_lock); 4989 mutex_unlock(&pmus_lock);
4985 4990
4986 synchronize_srcu(&pmus_srcu); 4991 synchronize_srcu(&pmus_srcu);
4992
4993 free_percpu(pmu->pmu_disable_count);
4987} 4994}
4988 4995
4989struct pmu *perf_init_event(struct perf_event *event) 4996struct pmu *perf_init_event(struct perf_event *event)
ting out all code part that were * deprecated and also styling related comments. * Grant Grundler : For helping me get rid of some Architecture * dependent code. * Christopher Hellwig : Some more 2.6 specific issues in the driver. * * The module loadable parameters that are supported by the driver and a brief * explaination of all the variables. * rx_ring_num : This can be used to program the number of receive rings used * in the driver. * rx_ring_sz: This defines the number of descriptors each ring can have. This * is also an array of size 8. * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver. * tx_fifo_len: This too is an array of 8. Each element defines the number of * Tx descriptors that can be associated with each corresponding FIFO. ************************************************************************/ #include <linux/config.h> #include <linux/module.h> #include <linux/types.h> #include <linux/errno.h> #include <linux/ioport.h> #include <linux/pci.h> #include <linux/dma-mapping.h> #include <linux/kernel.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/stddef.h> #include <linux/ioctl.h> #include <linux/timex.h> #include <linux/sched.h> #include <linux/ethtool.h> #include <linux/version.h> #include <linux/workqueue.h> #include <linux/if_vlan.h> #include <asm/system.h> #include <asm/uaccess.h> #include <asm/io.h> /* local include */ #include "s2io.h" #include "s2io-regs.h" #define DRV_VERSION "Version 2.0.9.1" /* S2io Driver name & version. */ static char s2io_driver_name[] = "Neterion"; static char s2io_driver_version[] = DRV_VERSION; static inline int RXD_IS_UP2DT(RxD_t *rxdp) { int ret; ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) && (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK)); return ret; } /* * Cards with following subsystem_id have a link state indication * problem, 600B, 600C, 600D, 640B, 640C and 640D. * macro below identifies these cards given the subsystem_id. */ #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \ (dev_type == XFRAME_I_DEVICE) ? \ ((((subid >= 0x600B) && (subid <= 0x600D)) || \ ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ ADAPTER_STATUS_RMAC_LOCAL_FAULT))) #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status)) #define PANIC 1 #define LOW 2 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring) { int level = 0; mac_info_t *mac_control; mac_control = &sp->mac_control; if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) { level = LOW; if (rxb_size <= MAX_RXDS_PER_BLOCK) { level = PANIC; } } return level; } /* Ethtool related variables and Macros. */ static char s2io_gstrings[][ETH_GSTRING_LEN] = { "Register test\t(offline)", "Eeprom test\t(offline)", "Link test\t(online)", "RLDRAM test\t(offline)", "BIST Test\t(offline)" }; static char ethtool_stats_keys[][ETH_GSTRING_LEN] = { {"tmac_frms"}, {"tmac_data_octets"}, {"tmac_drop_frms"}, {"tmac_mcst_frms"}, {"tmac_bcst_frms"}, {"tmac_pause_ctrl_frms"}, {"tmac_any_err_frms"}, {"tmac_vld_ip_octets"}, {"tmac_vld_ip"}, {"tmac_drop_ip"}, {"tmac_icmp"}, {"tmac_rst_tcp"}, {"tmac_tcp"}, {"tmac_udp"}, {"rmac_vld_frms"}, {"rmac_data_octets"}, {"rmac_fcs_err_frms"}, {"rmac_drop_frms"}, {"rmac_vld_mcst_frms"}, {"rmac_vld_bcst_frms"}, {"rmac_in_rng_len_err_frms"}, {"rmac_long_frms"}, {"rmac_pause_ctrl_frms"}, {"rmac_discarded_frms"}, {"rmac_usized_frms"}, {"rmac_osized_frms"}, {"rmac_frag_frms"}, {"rmac_jabber_frms"}, {"rmac_ip"}, {"rmac_ip_octets"}, {"rmac_hdr_err_ip"}, {"rmac_drop_ip"}, {"rmac_icmp"}, {"rmac_tcp"}, {"rmac_udp"}, {"rmac_err_drp_udp"}, {"rmac_pause_cnt"}, {"rmac_accepted_ip"}, {"rmac_err_tcp"}, {"\n DRIVER STATISTICS"}, {"single_bit_ecc_errs"}, {"double_bit_ecc_errs"}, }; #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN #define S2IO_TIMER_CONF(timer, handle, arg, exp) \ init_timer(&timer); \ timer.function = handle; \ timer.data = (unsigned long) arg; \ mod_timer(&timer, (jiffies + exp)) \ /* Add the vlan */ static void s2io_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) { nic_t *nic = dev->priv; unsigned long flags; spin_lock_irqsave(&nic->tx_lock, flags); nic->vlgrp = grp; spin_unlock_irqrestore(&nic->tx_lock, flags); } /* Unregister the vlan */ static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid) { nic_t *nic = dev->priv; unsigned long flags; spin_lock_irqsave(&nic->tx_lock, flags); if (nic->vlgrp) nic->vlgrp->vlan_devices[vid] = NULL; spin_unlock_irqrestore(&nic->tx_lock, flags); } /* * Constants to be programmed into the Xena's registers, to configure * the XAUI. */ #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL #define END_SIGN 0x0 static u64 herc_act_dtx_cfg[] = { /* Set address */ 0x8000051536750000ULL, 0x80000515367500E0ULL, /* Write data */ 0x8000051536750004ULL, 0x80000515367500E4ULL, /* Set address */ 0x80010515003F0000ULL, 0x80010515003F00E0ULL, /* Write data */ 0x80010515003F0004ULL, 0x80010515003F00E4ULL, /* Set address */ 0x801205150D440000ULL, 0x801205150D4400E0ULL, /* Write data */ 0x801205150D440004ULL, 0x801205150D4400E4ULL, /* Set address */ 0x80020515F2100000ULL, 0x80020515F21000E0ULL, /* Write data */ 0x80020515F2100004ULL, 0x80020515F21000E4ULL, /* Done */ END_SIGN }; static u64 xena_mdio_cfg[] = { /* Reset PMA PLL */ 0xC001010000000000ULL, 0xC0010100000000E0ULL, 0xC0010100008000E4ULL, /* Remove Reset from PMA PLL */ 0xC001010000000000ULL, 0xC0010100000000E0ULL, 0xC0010100000000E4ULL, END_SIGN }; static u64 xena_dtx_cfg[] = { 0x8000051500000000ULL, 0x80000515000000E0ULL, 0x80000515D93500E4ULL, 0x8001051500000000ULL, 0x80010515000000E0ULL, 0x80010515001E00E4ULL, 0x8002051500000000ULL, 0x80020515000000E0ULL, 0x80020515F21000E4ULL, /* Set PADLOOPBACKN */ 0x8002051500000000ULL, 0x80020515000000E0ULL, 0x80020515B20000E4ULL, 0x8003051500000000ULL, 0x80030515000000E0ULL, 0x80030515B20000E4ULL, 0x8004051500000000ULL, 0x80040515000000E0ULL, 0x80040515B20000E4ULL, 0x8005051500000000ULL, 0x80050515000000E0ULL, 0x80050515B20000E4ULL, SWITCH_SIGN, /* Remove PADLOOPBACKN */ 0x8002051500000000ULL, 0x80020515000000E0ULL, 0x80020515F20000E4ULL, 0x8003051500000000ULL, 0x80030515000000E0ULL, 0x80030515F20000E4ULL, 0x8004051500000000ULL, 0x80040515000000E0ULL, 0x80040515F20000E4ULL, 0x8005051500000000ULL, 0x80050515000000E0ULL, 0x80050515F20000E4ULL, END_SIGN }; /* * Constants for Fixing the MacAddress problem seen mostly on * Alpha machines. */ static u64 fix_mac[] = { 0x0060000000000000ULL, 0x0060600000000000ULL, 0x0040600000000000ULL, 0x0000600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0060600000000000ULL, 0x0020600000000000ULL, 0x0000600000000000ULL, 0x0040600000000000ULL, 0x0060600000000000ULL, END_SIGN }; /* Module Loadable parameters. */ static unsigned int tx_fifo_num = 1; static unsigned int tx_fifo_len[MAX_TX_FIFOS] = {[0 ...(MAX_TX_FIFOS - 1)] = 0 }; static unsigned int rx_ring_num = 1; static unsigned int rx_ring_sz[MAX_RX_RINGS] = {[0 ...(MAX_RX_RINGS - 1)] = 0 }; static unsigned int rts_frm_len[MAX_RX_RINGS] = {[0 ...(MAX_RX_RINGS - 1)] = 0 }; static unsigned int use_continuous_tx_intrs = 1; static unsigned int rmac_pause_time = 65535; static unsigned int mc_pause_threshold_q0q3 = 187; static unsigned int mc_pause_threshold_q4q7 = 187; static unsigned int shared_splits; static unsigned int tmac_util_period = 5; static unsigned int rmac_util_period = 5; static unsigned int bimodal = 0; #ifndef CONFIG_S2IO_NAPI static unsigned int indicate_max_pkts; #endif /* Frequency of Rx desc syncs expressed as power of 2 */ static unsigned int rxsync_frequency = 3; /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */ static unsigned int intr_type = 0; /* * S2IO device table. * This table lists all the devices that this driver supports. */ static struct pci_device_id s2io_tbl[] __devinitdata = { {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN, PCI_ANY_ID, PCI_ANY_ID}, {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, PCI_ANY_ID, PCI_ANY_ID}, {0,} }; MODULE_DEVICE_TABLE(pci, s2io_tbl); static struct pci_driver s2io_driver = { .name = "S2IO", .id_table = s2io_tbl, .probe = s2io_init_nic, .remove = __devexit_p(s2io_rem_nic), }; /* A simplifier macro used both by init and free shared_mem Fns(). */ #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each) /** * init_shared_mem - Allocation and Initialization of Memory * @nic: Device private variable. * Description: The function allocates all the memory areas shared * between the NIC and the driver. This includes Tx descriptors, * Rx descriptors and the statistics block. */ static int init_shared_mem(struct s2io_nic *nic) { u32 size; void *tmp_v_addr, *tmp_v_addr_next; dma_addr_t tmp_p_addr, tmp_p_addr_next; RxD_block_t *pre_rxd_blk = NULL; int i, j, blk_cnt, rx_sz, tx_sz; int lst_size, lst_per_page; struct net_device *dev = nic->dev; #ifdef CONFIG_2BUFF_MODE unsigned long tmp; buffAdd_t *ba; #endif mac_info_t *mac_control; struct config_param *config; mac_control = &nic->mac_control; config = &nic->config; /* Allocation and initialization of TXDLs in FIOFs */ size = 0; for (i = 0; i < config->tx_fifo_num; i++) { size += config->tx_cfg[i].fifo_len; } if (size > MAX_AVAILABLE_TXDS) { DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ", __FUNCTION__); DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size); return FAILURE; } lst_size = (sizeof(TxD_t) * config->max_txds); tx_sz = lst_size * size; lst_per_page = PAGE_SIZE / lst_size; for (i = 0; i < config->tx_fifo_num; i++) { int fifo_len = config->tx_cfg[i].fifo_len; int list_holder_size = fifo_len * sizeof(list_info_hold_t); mac_control->fifos[i].list_info = kmalloc(list_holder_size, GFP_KERNEL); if (!mac_control->fifos[i].list_info) { DBG_PRINT(ERR_DBG, "Malloc failed for list_info\n"); return -ENOMEM; } memset(mac_control->fifos[i].list_info, 0, list_holder_size); } for (i = 0; i < config->tx_fifo_num; i++) { int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, lst_per_page); mac_control->fifos[i].tx_curr_put_info.offset = 0; mac_control->fifos[i].tx_curr_put_info.fifo_len = config->tx_cfg[i].fifo_len - 1; mac_control->fifos[i].tx_curr_get_info.offset = 0; mac_control->fifos[i].tx_curr_get_info.fifo_len = config->tx_cfg[i].fifo_len - 1; mac_control->fifos[i].fifo_no = i; mac_control->fifos[i].nic = nic; mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 1; for (j = 0; j < page_num; j++) { int k = 0; dma_addr_t tmp_p; void *tmp_v; tmp_v = pci_alloc_consistent(nic->pdev, PAGE_SIZE, &tmp_p); if (!tmp_v) { DBG_PRINT(ERR_DBG, "pci_alloc_consistent "); DBG_PRINT(ERR_DBG, "failed for TxDL\n"); return -ENOMEM; } /* If we got a zero DMA address(can happen on * certain platforms like PPC), reallocate. * Store virtual address of page we don't want, * to be freed later. */ if (!tmp_p) { mac_control->zerodma_virt_addr = tmp_v; DBG_PRINT(INIT_DBG, "%s: Zero DMA address for TxDL. ", dev->name); DBG_PRINT(INIT_DBG, "Virtual address %p\n", tmp_v); tmp_v = pci_alloc_consistent(nic->pdev, PAGE_SIZE, &tmp_p); if (!tmp_v) { DBG_PRINT(ERR_DBG, "pci_alloc_consistent "); DBG_PRINT(ERR_DBG, "failed for TxDL\n"); return -ENOMEM; } } while (k < lst_per_page) { int l = (j * lst_per_page) + k; if (l == config->tx_cfg[i].fifo_len) break; mac_control->fifos[i].list_info[l].list_virt_addr = tmp_v + (k * lst_size); mac_control->fifos[i].list_info[l].list_phy_addr = tmp_p + (k * lst_size); k++; } } } /* Allocation and initialization of RXDs in Rings */ size = 0; for (i = 0; i < config->rx_ring_num; i++) { if (config->rx_cfg[i].num_rxd % (MAX_RXDS_PER_BLOCK + 1)) { DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name); DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i); DBG_PRINT(ERR_DBG, "RxDs per Block"); return FAILURE; } size += config->rx_cfg[i].num_rxd; mac_control->rings[i].block_count = config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count; } size = (size * (sizeof(RxD_t))); rx_sz = size; for (i = 0; i < config->rx_ring_num; i++) { mac_control->rings[i].rx_curr_get_info.block_index = 0; mac_control->rings[i].rx_curr_get_info.offset = 0; mac_control->rings[i].rx_curr_get_info.ring_len = config->rx_cfg[i].num_rxd - 1; mac_control->rings[i].rx_curr_put_info.block_index = 0; mac_control->rings[i].rx_curr_put_info.offset = 0; mac_control->rings[i].rx_curr_put_info.ring_len = config->rx_cfg[i].num_rxd - 1; mac_control->rings[i].nic = nic; mac_control->rings[i].ring_no = i; blk_cnt = config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); /* Allocating all the Rx blocks */ for (j = 0; j < blk_cnt; j++) { #ifndef CONFIG_2BUFF_MODE size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t)); #else size = SIZE_OF_BLOCK; #endif tmp_v_addr = pci_alloc_consistent(nic->pdev, size, &tmp_p_addr); if (tmp_v_addr == NULL) { /* * In case of failure, free_shared_mem() * is called, which should free any * memory that was alloced till the * failure happened. */ mac_control->rings[i].rx_blocks[j].block_virt_addr = tmp_v_addr; return -ENOMEM; } memset(tmp_v_addr, 0, size); mac_control->rings[i].rx_blocks[j].block_virt_addr = tmp_v_addr; mac_control->rings[i].rx_blocks[j].block_dma_addr = tmp_p_addr; } /* Interlinking all Rx Blocks */ for (j = 0; j < blk_cnt; j++) { tmp_v_addr = mac_control->rings[i].rx_blocks[j].block_virt_addr; tmp_v_addr_next = mac_control->rings[i].rx_blocks[(j + 1) % blk_cnt].block_virt_addr; tmp_p_addr = mac_control->rings[i].rx_blocks[j].block_dma_addr; tmp_p_addr_next = mac_control->rings[i].rx_blocks[(j + 1) % blk_cnt].block_dma_addr; pre_rxd_blk = (RxD_block_t *) tmp_v_addr; pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD * marker. */ #ifndef CONFIG_2BUFF_MODE pre_rxd_blk->reserved_2_pNext_RxD_block = (unsigned long) tmp_v_addr_next; #endif pre_rxd_blk->pNext_RxD_Blk_physical = (u64) tmp_p_addr_next; } } #ifdef CONFIG_2BUFF_MODE /* * Allocation of Storages for buffer addresses in 2BUFF mode * and the buffers as well. */ for (i = 0; i < config->rx_ring_num; i++) { blk_cnt = config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt), GFP_KERNEL); if (!mac_control->rings[i].ba) return -ENOMEM; for (j = 0; j < blk_cnt; j++) { int k = 0; mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) * (MAX_RXDS_PER_BLOCK + 1)), GFP_KERNEL); if (!mac_control->rings[i].ba[j]) return -ENOMEM; while (k != MAX_RXDS_PER_BLOCK) { ba = &mac_control->rings[i].ba[j][k]; ba->ba_0_org = (void *) kmalloc (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL); if (!ba->ba_0_org) return -ENOMEM; tmp = (unsigned long) ba->ba_0_org; tmp += ALIGN_SIZE; tmp &= ~((unsigned long) ALIGN_SIZE); ba->ba_0 = (void *) tmp; ba->ba_1_org = (void *) kmalloc (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL); if (!ba->ba_1_org) return -ENOMEM; tmp = (unsigned long) ba->ba_1_org; tmp += ALIGN_SIZE; tmp &= ~((unsigned long) ALIGN_SIZE); ba->ba_1 = (void *) tmp; k++; } } } #endif /* Allocation and initialization of Statistics block */ size = sizeof(StatInfo_t); mac_control->stats_mem = pci_alloc_consistent (nic->pdev, size, &mac_control->stats_mem_phy); if (!mac_control->stats_mem) { /* * In case of failure, free_shared_mem() is called, which * should free any memory that was alloced till the * failure happened. */ return -ENOMEM; } mac_control->stats_mem_sz = size; tmp_v_addr = mac_control->stats_mem; mac_control->stats_info = (StatInfo_t *) tmp_v_addr; memset(tmp_v_addr, 0, size); DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name, (unsigned long long) tmp_p_addr); return SUCCESS; } /** * free_shared_mem - Free the allocated Memory * @nic: Device private variable. * Description: This function is to free all memory locations allocated by * the init_shared_mem() function and return it to the kernel. */ static void free_shared_mem(struct s2io_nic *nic) { int i, j, blk_cnt, size; void *tmp_v_addr; dma_addr_t tmp_p_addr; mac_info_t *mac_control; struct config_param *config; int lst_size, lst_per_page; struct net_device *dev = nic->dev; if (!nic) return; mac_control = &nic->mac_control; config = &nic->config; lst_size = (sizeof(TxD_t) * config->max_txds); lst_per_page = PAGE_SIZE / lst_size; for (i = 0; i < config->tx_fifo_num; i++) { int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, lst_per_page); for (j = 0; j < page_num; j++) { int mem_blks = (j * lst_per_page); if (!mac_control->fifos[i].list_info) return; if (!mac_control->fifos[i].list_info[mem_blks]. list_virt_addr) break; pci_free_consistent(nic->pdev, PAGE_SIZE, mac_control->fifos[i]. list_info[mem_blks]. list_virt_addr, mac_control->fifos[i]. list_info[mem_blks]. list_phy_addr); } /* If we got a zero DMA address during allocation, * free the page now */ if (mac_control->zerodma_virt_addr) { pci_free_consistent(nic->pdev, PAGE_SIZE, mac_control->zerodma_virt_addr, (dma_addr_t)0); DBG_PRINT(INIT_DBG, "%s: Freeing TxDL with zero DMA addr. ", dev->name); DBG_PRINT(INIT_DBG, "Virtual address %p\n", mac_control->zerodma_virt_addr); } kfree(mac_control->fifos[i].list_info); } #ifndef CONFIG_2BUFF_MODE size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t)); #else size = SIZE_OF_BLOCK; #endif for (i = 0; i < config->rx_ring_num; i++) { blk_cnt = mac_control->rings[i].block_count; for (j = 0; j < blk_cnt; j++) { tmp_v_addr = mac_control->rings[i].rx_blocks[j]. block_virt_addr; tmp_p_addr = mac_control->rings[i].rx_blocks[j]. block_dma_addr; if (tmp_v_addr == NULL) break; pci_free_consistent(nic->pdev, size, tmp_v_addr, tmp_p_addr); } } #ifdef CONFIG_2BUFF_MODE /* Freeing buffer storage addresses in 2BUFF mode. */ for (i = 0; i < config->rx_ring_num; i++) { blk_cnt = config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); for (j = 0; j < blk_cnt; j++) { int k = 0; if (!mac_control->rings[i].ba[j]) continue; while (k != MAX_RXDS_PER_BLOCK) { buffAdd_t *ba = &mac_control->rings[i].ba[j][k]; kfree(ba->ba_0_org); kfree(ba->ba_1_org); k++; } kfree(mac_control->rings[i].ba[j]); } kfree(mac_control->rings[i].ba); } #endif if (mac_control->stats_mem) { pci_free_consistent(nic->pdev, mac_control->stats_mem_sz, mac_control->stats_mem, mac_control->stats_mem_phy); } } /** * s2io_verify_pci_mode - */ static int s2io_verify_pci_mode(nic_t *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0; int mode; val64 = readq(&bar0->pci_mode); mode = (u8)GET_PCI_MODE(val64); if ( val64 & PCI_MODE_UNKNOWN_MODE) return -1; /* Unknown PCI mode */ return mode; } /** * s2io_print_pci_mode - */ static int s2io_print_pci_mode(nic_t *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0; int mode; struct config_param *config = &nic->config; val64 = readq(&bar0->pci_mode); mode = (u8)GET_PCI_MODE(val64); if ( val64 & PCI_MODE_UNKNOWN_MODE) return -1; /* Unknown PCI mode */ if (val64 & PCI_MODE_32_BITS) { DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name); } else { DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name); } switch(mode) { case PCI_MODE_PCI_33: DBG_PRINT(ERR_DBG, "33MHz PCI bus\n"); config->bus_speed = 33; break; case PCI_MODE_PCI_66: DBG_PRINT(ERR_DBG, "66MHz PCI bus\n"); config->bus_speed = 133; break; case PCI_MODE_PCIX_M1_66: DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n"); config->bus_speed = 133; /* Herc doubles the clock rate */ break; case PCI_MODE_PCIX_M1_100: DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n"); config->bus_speed = 200; break; case PCI_MODE_PCIX_M1_133: DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n"); config->bus_speed = 266; break; case PCI_MODE_PCIX_M2_66: DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n"); config->bus_speed = 133; break; case PCI_MODE_PCIX_M2_100: DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n"); config->bus_speed = 200; break; case PCI_MODE_PCIX_M2_133: DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n"); config->bus_speed = 266; break; default: return -1; /* Unsupported bus speed */ } return mode; } /** * init_nic - Initialization of hardware * @nic: device peivate variable * Description: The function sequentially configures every block * of the H/W from their reset values. * Return Value: SUCCESS on success and * '-1' on failure (endian settings incorrect). */ static int init_nic(struct s2io_nic *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; struct net_device *dev = nic->dev; register u64 val64 = 0; void __iomem *add; u32 time; int i, j; mac_info_t *mac_control; struct config_param *config; int mdio_cnt = 0, dtx_cnt = 0; unsigned long long mem_share; int mem_size; mac_control = &nic->mac_control; config = &nic->config; /* to set the swapper controle on the card */ if(s2io_set_swapper(nic)) { DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n"); return -1; } /* * Herc requires EOI to be removed from reset before XGXS, so.. */ if (nic->device_type & XFRAME_II_DEVICE) { val64 = 0xA500000000ULL; writeq(val64, &bar0->sw_reset); msleep(500); val64 = readq(&bar0->sw_reset); } /* Remove XGXS from reset state */ val64 = 0; writeq(val64, &bar0->sw_reset); msleep(500); val64 = readq(&bar0->sw_reset); /* Enable Receiving broadcasts */ add = &bar0->mac_cfg; val64 = readq(&bar0->mac_cfg); val64 |= MAC_RMAC_BCAST_ENABLE; writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) val64, add); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64 >> 32), (add + 4)); /* Read registers in all blocks */ val64 = readq(&bar0->mac_int_mask); val64 = readq(&bar0->mc_int_mask); val64 = readq(&bar0->xgxs_int_mask); /* Set MTU */ val64 = dev->mtu; writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); /* * Configuring the XAUI Interface of Xena. * *************************************** * To Configure the Xena's XAUI, one has to write a series * of 64 bit values into two registers in a particular * sequence. Hence a macro 'SWITCH_SIGN' has been defined * which will be defined in the array of configuration values * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places * to switch writing from one regsiter to another. We continue * writing these values until we encounter the 'END_SIGN' macro. * For example, After making a series of 21 writes into * dtx_control register the 'SWITCH_SIGN' appears and hence we * start writing into mdio_control until we encounter END_SIGN. */ if (nic->device_type & XFRAME_II_DEVICE) { while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt], &bar0->dtx_control, UF); if (dtx_cnt & 0x1) msleep(1); /* Necessary!! */ dtx_cnt++; } } else { while (1) { dtx_cfg: while (xena_dtx_cfg[dtx_cnt] != END_SIGN) { if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) { dtx_cnt++; goto mdio_cfg; } SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt], &bar0->dtx_control, UF); val64 = readq(&bar0->dtx_control); dtx_cnt++; } mdio_cfg: while (xena_mdio_cfg[mdio_cnt] != END_SIGN) { if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) { mdio_cnt++; goto dtx_cfg; } SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt], &bar0->mdio_control, UF); val64 = readq(&bar0->mdio_control); mdio_cnt++; } if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) && (xena_mdio_cfg[mdio_cnt] == END_SIGN)) { break; } else { goto dtx_cfg; } } } /* Tx DMA Initialization */ val64 = 0; writeq(val64, &bar0->tx_fifo_partition_0); writeq(val64, &bar0->tx_fifo_partition_1); writeq(val64, &bar0->tx_fifo_partition_2); writeq(val64, &bar0->tx_fifo_partition_3); for (i = 0, j = 0; i < config->tx_fifo_num; i++) { val64 |= vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19), 13) | vBIT(config->tx_cfg[i].fifo_priority, ((i * 32) + 5), 3); if (i == (config->tx_fifo_num - 1)) { if (i % 2 == 0) i++; } switch (i) { case 1: writeq(val64, &bar0->tx_fifo_partition_0); val64 = 0; break; case 3: writeq(val64, &bar0->tx_fifo_partition_1); val64 = 0; break; case 5: writeq(val64, &bar0->tx_fifo_partition_2); val64 = 0; break; case 7: writeq(val64, &bar0->tx_fifo_partition_3); break; } } /* Enable Tx FIFO partition 0. */ val64 = readq(&bar0->tx_fifo_partition_0); val64 |= BIT(0); /* To enable the FIFO partition. */ writeq(val64, &bar0->tx_fifo_partition_0); /* * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug * SXE-008 TRANSMIT DMA ARBITRATION ISSUE. */ if ((nic->device_type == XFRAME_I_DEVICE) && (get_xena_rev_id(nic->pdev) < 4)) writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); val64 = readq(&bar0->tx_fifo_partition_0); DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n", &bar0->tx_fifo_partition_0, (unsigned long long) val64); /* * Initialization of Tx_PA_CONFIG register to ignore packet * integrity checking. */ val64 = readq(&bar0->tx_pa_cfg); val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI | TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR; writeq(val64, &bar0->tx_pa_cfg); /* Rx DMA intialization. */ val64 = 0; for (i = 0; i < config->rx_ring_num; i++) { val64 |= vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)), 3); } writeq(val64, &bar0->rx_queue_priority); /* * Allocating equal share of memory to all the * configured Rings. */ val64 = 0; if (nic->device_type & XFRAME_II_DEVICE) mem_size = 32; else mem_size = 64; for (i = 0; i < config->rx_ring_num; i++) { switch (i) { case 0: mem_share = (mem_size / config->rx_ring_num + mem_size % config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); continue; case 1: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); continue; case 2: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); continue; case 3: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); continue; case 4: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); continue; case 5: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); continue; case 6: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); continue; case 7: mem_share = (mem_size / config->rx_ring_num); val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); continue; } } writeq(val64, &bar0->rx_queue_cfg); /* * Filling Tx round robin registers * as per the number of FIFOs */ switch (config->tx_fifo_num) { case 1: val64 = 0x0000000000000000ULL; writeq(val64, &bar0->tx_w_round_robin_0); writeq(val64, &bar0->tx_w_round_robin_1); writeq(val64, &bar0->tx_w_round_robin_2); writeq(val64, &bar0->tx_w_round_robin_3); writeq(val64, &bar0->tx_w_round_robin_4); break; case 2: val64 = 0x0000010000010000ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0100000100000100ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0001000001000001ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0000010000010000ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0100000000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 3: val64 = 0x0001000102000001ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0001020000010001ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0200000100010200ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0001000102000001ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0001020000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 4: val64 = 0x0001020300010200ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0100000102030001ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0200010000010203ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0001020001000001ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0203000100000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 5: val64 = 0x0001000203000102ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0001000203000102ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0001000000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 6: val64 = 0x0001020304000102ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0304050001020001ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0203000100000102ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0304000102030405ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0001000200000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 7: val64 = 0x0001020001020300ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0102030400010203ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0405060001020001ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0304050000010200ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0102030000000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; case 8: val64 = 0x0001020300040105ULL; writeq(val64, &bar0->tx_w_round_robin_0); val64 = 0x0200030106000204ULL; writeq(val64, &bar0->tx_w_round_robin_1); val64 = 0x0103000502010007ULL; writeq(val64, &bar0->tx_w_round_robin_2); val64 = 0x0304010002060500ULL; writeq(val64, &bar0->tx_w_round_robin_3); val64 = 0x0103020400000000ULL; writeq(val64, &bar0->tx_w_round_robin_4); break; } /* Filling the Rx round robin registers as per the * number of Rings and steering based on QoS. */ switch (config->rx_ring_num) { case 1: val64 = 0x8080808080808080ULL; writeq(val64, &bar0->rts_qos_steering); break; case 2: val64 = 0x0000010000010000ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0100000100000100ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0001000001000001ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0000010000010000ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0100000000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080808040404040ULL; writeq(val64, &bar0->rts_qos_steering); break; case 3: val64 = 0x0001000102000001ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0001020000010001ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0200000100010200ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0001000102000001ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0001020000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080804040402020ULL; writeq(val64, &bar0->rts_qos_steering); break; case 4: val64 = 0x0001020300010200ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0100000102030001ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0200010000010203ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0001020001000001ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0203000100000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080404020201010ULL; writeq(val64, &bar0->rts_qos_steering); break; case 5: val64 = 0x0001000203000102ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0001000203000102ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0001020001030004ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0001000000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080404020201008ULL; writeq(val64, &bar0->rts_qos_steering); break; case 6: val64 = 0x0001020304000102ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0304050001020001ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0203000100000102ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0304000102030405ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0001000200000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080404020100804ULL; writeq(val64, &bar0->rts_qos_steering); break; case 7: val64 = 0x0001020001020300ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0102030400010203ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0405060001020001ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0304050000010200ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0102030000000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8080402010080402ULL; writeq(val64, &bar0->rts_qos_steering); break; case 8: val64 = 0x0001020300040105ULL; writeq(val64, &bar0->rx_w_round_robin_0); val64 = 0x0200030106000204ULL; writeq(val64, &bar0->rx_w_round_robin_1); val64 = 0x0103000502010007ULL; writeq(val64, &bar0->rx_w_round_robin_2); val64 = 0x0304010002060500ULL; writeq(val64, &bar0->rx_w_round_robin_3); val64 = 0x0103020400000000ULL; writeq(val64, &bar0->rx_w_round_robin_4); val64 = 0x8040201008040201ULL; writeq(val64, &bar0->rts_qos_steering); break; } /* UDP Fix */ val64 = 0; for (i = 0; i < 8; i++) writeq(val64, &bar0->rts_frm_len_n[i]); /* Set the default rts frame length for the rings configured */ val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); for (i = 0 ; i < config->rx_ring_num ; i++) writeq(val64, &bar0->rts_frm_len_n[i]); /* Set the frame length for the configured rings * desired by the user */ for (i = 0; i < config->rx_ring_num; i++) { /* If rts_frm_len[i] == 0 then it is assumed that user not * specified frame length steering. * If the user provides the frame length then program * the rts_frm_len register for those values or else * leave it as it is. */ if (rts_frm_len[i] != 0) { writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]), &bar0->rts_frm_len_n[i]); } } /* Program statistics memory */ writeq(mac_control->stats_mem_phy, &bar0->stat_addr); if (nic->device_type == XFRAME_II_DEVICE) { val64 = STAT_BC(0x320); writeq(val64, &bar0->stat_byte_cnt); } /* * Initializing the sampling rate for the device to calculate the * bandwidth utilization. */ val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) | MAC_RX_LINK_UTIL_VAL(rmac_util_period); writeq(val64, &bar0->mac_link_util); /* * Initializing the Transmit and Receive Traffic Interrupt * Scheme. */ /* * TTI Initialization. Default Tx timer gets us about * 250 interrupts per sec. Continuous interrupts are enabled * by default. */ if (nic->device_type == XFRAME_II_DEVICE) { int count = (nic->config.bus_speed * 125)/2; val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); } else { val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); } val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | TTI_DATA1_MEM_TX_URNG_B(0x10) | TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN; if (use_continuous_tx_intrs) val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; writeq(val64, &bar0->tti_data1_mem); val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | TTI_DATA2_MEM_TX_UFC_B(0x20) | TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80); writeq(val64, &bar0->tti_data2_mem); val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; writeq(val64, &bar0->tti_command_mem); /* * Once the operation completes, the Strobe bit of the command * register will be reset. We poll for this particular condition * We wait for a maximum of 500ms for the operation to complete, * if it's not complete by then we return error. */ time = 0; while (TRUE) { val64 = readq(&bar0->tti_command_mem); if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { break; } if (time > 10) { DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n", dev->name); return -1; } msleep(50); time++; } if (nic->config.bimodal) { int k = 0; for (k = 0; k < config->rx_ring_num; k++) { val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; val64 |= TTI_CMD_MEM_OFFSET(0x38+k); writeq(val64, &bar0->tti_command_mem); /* * Once the operation completes, the Strobe bit of the command * register will be reset. We poll for this particular condition * We wait for a maximum of 500ms for the operation to complete, * if it's not complete by then we return error. */ time = 0; while (TRUE) { val64 = readq(&bar0->tti_command_mem); if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { break; } if (time > 10) { DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n", dev->name); return -1; } time++; msleep(50); } } } else { /* RTI Initialization */ if (nic->device_type == XFRAME_II_DEVICE) { /* * Programmed to generate Apprx 500 Intrs per * second */ int count = (nic->config.bus_speed * 125)/4; val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); } else { val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); } val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | RTI_DATA1_MEM_RX_URNG_B(0x10) | RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN; writeq(val64, &bar0->rti_data1_mem); val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | RTI_DATA2_MEM_RX_UFC_B(0x2) ; if (nic->intr_type == MSI_X) val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \ RTI_DATA2_MEM_RX_UFC_D(0x40)); else val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \ RTI_DATA2_MEM_RX_UFC_D(0x80)); writeq(val64, &bar0->rti_data2_mem); for (i = 0; i < config->rx_ring_num; i++) { val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD | RTI_CMD_MEM_OFFSET(i); writeq(val64, &bar0->rti_command_mem); /* * Once the operation completes, the Strobe bit of the * command register will be reset. We poll for this * particular condition. We wait for a maximum of 500ms * for the operation to complete, if it's not complete * by then we return error. */ time = 0; while (TRUE) { val64 = readq(&bar0->rti_command_mem); if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) { break; } if (time > 10) { DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n", dev->name); return -1; } time++; msleep(50); } } } /* * Initializing proper values as Pause threshold into all * the 8 Queues on Rx side. */ writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); /* Disable RMAC PAD STRIPPING */ add = &bar0->mac_cfg; val64 = readq(&bar0->mac_cfg); val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64), add); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64 >> 32), (add + 4)); val64 = readq(&bar0->mac_cfg); /* * Set the time value to be inserted in the pause frame * generated by xena. */ val64 = readq(&bar0->rmac_pause_cfg); val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff)); val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); writeq(val64, &bar0->rmac_pause_cfg); /* * Set the Threshold Limit for Generating the pause frame * If the amount of data in any Queue exceeds ratio of * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256 * pause frame is generated */ val64 = 0; for (i = 0; i < 4; i++) { val64 |= (((u64) 0xFF00 | nic->mac_control. mc_pause_threshold_q0q3) << (i * 2 * 8)); } writeq(val64, &bar0->mc_pause_thresh_q0q3); val64 = 0; for (i = 0; i < 4; i++) { val64 |= (((u64) 0xFF00 | nic->mac_control. mc_pause_threshold_q4q7) << (i * 2 * 8)); } writeq(val64, &bar0->mc_pause_thresh_q4q7); /* * TxDMA will stop Read request if the number of read split has * exceeded the limit pointed by shared_splits */ val64 = readq(&bar0->pic_control); val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); writeq(val64, &bar0->pic_control); /* * Programming the Herc to split every write transaction * that does not start on an ADB to reduce disconnects. */ if (nic->device_type == XFRAME_II_DEVICE) { val64 = WREQ_SPLIT_MASK_SET_MASK(255); writeq(val64, &bar0->wreq_split_mask); } /* Setting Link stability period to 64 ms */ if (nic->device_type == XFRAME_II_DEVICE) { val64 = MISC_LINK_STABILITY_PRD(3); writeq(val64, &bar0->misc_control); } return SUCCESS; } #define LINK_UP_DOWN_INTERRUPT 1 #define MAC_RMAC_ERR_TIMER 2 int s2io_link_fault_indication(nic_t *nic) { if (nic->intr_type != INTA) return MAC_RMAC_ERR_TIMER; if (nic->device_type == XFRAME_II_DEVICE) return LINK_UP_DOWN_INTERRUPT; else return MAC_RMAC_ERR_TIMER; } /** * en_dis_able_nic_intrs - Enable or Disable the interrupts * @nic: device private variable, * @mask: A mask indicating which Intr block must be modified and, * @flag: A flag indicating whether to enable or disable the Intrs. * Description: This function will either disable or enable the interrupts * depending on the flag argument. The mask argument can be used to * enable/disable any Intr block. * Return Value: NONE. */ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0, temp64 = 0; /* Top level interrupt classification */ /* PIC Interrupts */ if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) { /* Enable PIC Intrs in the general intr mask register */ val64 = TXPIC_INT_M | PIC_RX_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * If Hercules adapter enable GPIO otherwise * disabled all PCIX, Flash, MDIO, IIC and GPIO * interrupts for now. * TODO */ if (s2io_link_fault_indication(nic) == LINK_UP_DOWN_INTERRUPT ) { temp64 = readq(&bar0->pic_int_mask); temp64 &= ~((u64) PIC_INT_GPIO); writeq(temp64, &bar0->pic_int_mask); temp64 = readq(&bar0->gpio_int_mask); temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP); writeq(temp64, &bar0->gpio_int_mask); } else { writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); } /* * No MSI Support is available presently, so TTI and * RTI interrupts are also disabled. */ } else if (flag == DISABLE_INTRS) { /* * Disable PIC Intrs in the general * intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* DMA Interrupts */ /* Enabling/Disabling Tx DMA interrupts */ if (mask & TX_DMA_INTR) { /* Enable TxDMA Intrs in the general intr mask register */ val64 = TXDMA_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * Keep all interrupts other than PFC interrupt * and PCC interrupt disabled in DMA level. */ val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M | TXDMA_PCC_INT_M); writeq(val64, &bar0->txdma_int_mask); /* * Enable only the MISC error 1 interrupt in PFC block */ val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1); writeq(val64, &bar0->pfc_err_mask); /* * Enable only the FB_ECC error interrupt in PCC block */ val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR); writeq(val64, &bar0->pcc_err_mask); } else if (flag == DISABLE_INTRS) { /* * Disable TxDMA Intrs in the general intr mask * register */ writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask); writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Enabling/Disabling Rx DMA interrupts */ if (mask & RX_DMA_INTR) { /* Enable RxDMA Intrs in the general intr mask register */ val64 = RXDMA_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * All RxDMA block interrupts are disabled for now * TODO */ writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); } else if (flag == DISABLE_INTRS) { /* * Disable RxDMA Intrs in the general intr mask * register */ writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* MAC Interrupts */ /* Enabling/Disabling MAC interrupts */ if (mask & (TX_MAC_INTR | RX_MAC_INTR)) { val64 = TXMAC_INT_M | RXMAC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * All MAC block error interrupts are disabled for now * TODO */ } else if (flag == DISABLE_INTRS) { /* * Disable MAC Intrs in the general intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask); writeq(DISABLE_ALL_INTRS, &bar0->mac_rmac_err_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* XGXS Interrupts */ if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) { val64 = TXXGXS_INT_M | RXXGXS_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * All XGXS block error interrupts are disabled for now * TODO */ writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); } else if (flag == DISABLE_INTRS) { /* * Disable MC Intrs in the general intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Memory Controller(MC) interrupts */ if (mask & MC_INTR) { val64 = MC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * Enable all MC Intrs. */ writeq(0x0, &bar0->mc_int_mask); writeq(0x0, &bar0->mc_err_mask); } else if (flag == DISABLE_INTRS) { /* * Disable MC Intrs in the general intr mask register */ writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Tx traffic interrupts */ if (mask & TX_TRAFFIC_INTR) { val64 = TXTRAFFIC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* * Enable all the Tx side interrupts * writing 0 Enables all 64 TX interrupt levels */ writeq(0x0, &bar0->tx_traffic_mask); } else if (flag == DISABLE_INTRS) { /* * Disable Tx Traffic Intrs in the general intr mask * register. */ writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } /* Rx traffic interrupts */ if (mask & RX_TRAFFIC_INTR) { val64 = RXTRAFFIC_INT_M; if (flag == ENABLE_INTRS) { temp64 = readq(&bar0->general_int_mask); temp64 &= ~((u64) val64); writeq(temp64, &bar0->general_int_mask); /* writing 0 Enables all 8 RX interrupt levels */ writeq(0x0, &bar0->rx_traffic_mask); } else if (flag == DISABLE_INTRS) { /* * Disable Rx Traffic Intrs in the general intr mask * register. */ writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); temp64 = readq(&bar0->general_int_mask); val64 |= temp64; writeq(val64, &bar0->general_int_mask); } } } static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc) { int ret = 0; if (flag == FALSE) { if ((!herc && (rev_id >= 4)) || herc) { if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) && ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT)) { ret = 1; } }else { if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT)) { ret = 1; } } } else { if ((!herc && (rev_id >= 4)) || herc) { if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == ADAPTER_STATUS_RMAC_PCC_IDLE) && (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT))) { ret = 1; } } else { if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == ADAPTER_STATUS_RC_PRC_QUIESCENT))) { ret = 1; } } } return ret; } /** * verify_xena_quiescence - Checks whether the H/W is ready * @val64 : Value read from adapter status register. * @flag : indicates if the adapter enable bit was ever written once * before. * Description: Returns whether the H/W is ready to go or not. Depending * on whether adapter enable bit was written or not the comparison * differs and the calling function passes the input argument flag to * indicate this. * Return: 1 If xena is quiescence * 0 If Xena is not quiescence */ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag) { int ret = 0, herc; u64 tmp64 = ~((u64) val64); int rev_id = get_xena_rev_id(sp->pdev); herc = (sp->device_type == XFRAME_II_DEVICE); if (! (tmp64 & (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY | ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | ADAPTER_STATUS_P_PLL_LOCK))) { ret = check_prc_pcc_state(val64, flag, rev_id, herc); } return ret; } /** * fix_mac_address - Fix for Mac addr problem on Alpha platforms * @sp: Pointer to device specifc structure * Description : * New procedure to clear mac address reading problems on Alpha platforms * */ void fix_mac_address(nic_t * sp) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64; int i = 0; while (fix_mac[i] != END_SIGN) { writeq(fix_mac[i++], &bar0->gpio_control); udelay(10); val64 = readq(&bar0->gpio_control); } } /** * start_nic - Turns the device on * @nic : device private variable. * Description: * This function actually turns the device on. Before this function is * called,all Registers are configured from their reset states * and shared memory is allocated but the NIC is still quiescent. On * calling this function, the device interrupts are cleared and the NIC is * literally switched on by writing into the adapter control register. * Return Value: * SUCCESS on success and -1 on failure. */ static int start_nic(struct s2io_nic *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; struct net_device *dev = nic->dev; register u64 val64 = 0; u16 interruptible; u16 subid, i; mac_info_t *mac_control; struct config_param *config; mac_control = &nic->mac_control; config = &nic->config; /* PRC Initialization and configuration */ for (i = 0; i < config->rx_ring_num; i++) { writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr, &bar0->prc_rxd0_n[i]); val64 = readq(&bar0->prc_ctrl_n[i]); if (nic->config.bimodal) val64 |= PRC_CTRL_BIMODAL_INTERRUPT; #ifndef CONFIG_2BUFF_MODE val64 |= PRC_CTRL_RC_ENABLED; #else val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; #endif writeq(val64, &bar0->prc_ctrl_n[i]); } #ifdef CONFIG_2BUFF_MODE /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */ val64 = readq(&bar0->rx_pa_cfg); val64 |= RX_PA_CFG_IGNORE_L2_ERR; writeq(val64, &bar0->rx_pa_cfg); #endif /* * Enabling MC-RLDRAM. After enabling the device, we timeout * for around 100ms, which is approximately the time required * for the device to be ready for operation. */ val64 = readq(&bar0->mc_rldram_mrs); val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); val64 = readq(&bar0->mc_rldram_mrs); msleep(100); /* Delay by around 100 ms. */ /* Enabling ECC Protection. */ val64 = readq(&bar0->adapter_control); val64 &= ~ADAPTER_ECC_EN; writeq(val64, &bar0->adapter_control); /* * Clearing any possible Link state change interrupts that * could have popped up just before Enabling the card. */ val64 = readq(&bar0->mac_rmac_err_reg); if (val64) writeq(val64, &bar0->mac_rmac_err_reg); /* * Verify if the device is ready to be enabled, if so enable * it. */ val64 = readq(&bar0->adapter_status); if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) { DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", (unsigned long long) val64); return FAILURE; } /* Enable select interrupts */ if (nic->intr_type != INTA) en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS); else { interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; interruptible |= TX_PIC_INTR | RX_PIC_INTR; interruptible |= TX_MAC_INTR | RX_MAC_INTR; en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS); } /* * With some switches, link might be already up at this point. * Because of this weird behavior, when we enable laser, * we may not get link. We need to handle this. We cannot * figure out which switch is misbehaving. So we are forced to * make a global change. */ /* Enabling Laser. */ val64 = readq(&bar0->adapter_control); val64 |= ADAPTER_EOI_TX_ON; writeq(val64, &bar0->adapter_control); /* SXE-002: Initialize link and activity LED */ subid = nic->pdev->subsystem_device; if (((subid & 0xFF) >= 0x07) && (nic->device_type == XFRAME_I_DEVICE)) { val64 = readq(&bar0->gpio_control); val64 |= 0x0000800000000000ULL; writeq(val64, &bar0->gpio_control); val64 = 0x0411040400000000ULL; writeq(val64, (void __iomem *)bar0 + 0x2700); } /* * Don't see link state interrupts on certain switches, so * directly scheduling a link state task from here. */ schedule_work(&nic->set_link_task); return SUCCESS; } /** * free_tx_buffers - Free all queued Tx buffers * @nic : device private variable. * Description: * Free all queued Tx buffers. * Return Value: void */ static void free_tx_buffers(struct s2io_nic *nic) { struct net_device *dev = nic->dev; struct sk_buff *skb; TxD_t *txdp; int i, j; mac_info_t *mac_control; struct config_param *config; int cnt = 0, frg_cnt; mac_control = &nic->mac_control; config = &nic->config; for (i = 0; i < config->tx_fifo_num; i++) { for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) { txdp = (TxD_t *) mac_control->fifos[i].list_info[j]. list_virt_addr; skb = (struct sk_buff *) ((unsigned long) txdp-> Host_Control); if (skb == NULL) { memset(txdp, 0, sizeof(TxD_t) * config->max_txds); continue; } frg_cnt = skb_shinfo(skb)->nr_frags; pci_unmap_single(nic->pdev, (dma_addr_t) txdp->Buffer_Pointer, skb->len - skb->data_len, PCI_DMA_TODEVICE); if (frg_cnt) { TxD_t *temp; temp = txdp; txdp++; for (j = 0; j < frg_cnt; j++, txdp++) { skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; pci_unmap_page(nic->pdev, (dma_addr_t) txdp-> Buffer_Pointer, frag->size, PCI_DMA_TODEVICE); } txdp = temp; } dev_kfree_skb(skb); memset(txdp, 0, sizeof(TxD_t) * config->max_txds); cnt++; } DBG_PRINT(INTR_DBG, "%s:forcibly freeing %d skbs on FIFO%d\n", dev->name, cnt, i); mac_control->fifos[i].tx_curr_get_info.offset = 0; mac_control->fifos[i].tx_curr_put_info.offset = 0; } } /** * stop_nic - To stop the nic * @nic ; device private variable. * Description: * This function does exactly the opposite of what the start_nic() * function does. This function is called to stop the device. * Return Value: * void. */ static void stop_nic(struct s2io_nic *nic) { XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0; u16 interruptible, i; mac_info_t *mac_control; struct config_param *config; mac_control = &nic->mac_control; config = &nic->config; /* Disable all interrupts */ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; interruptible |= TX_PIC_INTR | RX_PIC_INTR; interruptible |= TX_MAC_INTR | RX_MAC_INTR; en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS); /* Disable PRCs */ for (i = 0; i < config->rx_ring_num; i++) { val64 = readq(&bar0->prc_ctrl_n[i]); val64 &= ~((u64) PRC_CTRL_RC_ENABLED); writeq(val64, &bar0->prc_ctrl_n[i]); } } /** * fill_rx_buffers - Allocates the Rx side skbs * @nic: device private variable * @ring_no: ring number * Description: * The function allocates Rx side skbs and puts the physical * address of these buffers into the RxD buffer pointers, so that the NIC * can DMA the received frame into these locations. * The NIC supports 3 receive modes, viz * 1. single buffer, * 2. three buffer and * 3. Five buffer modes. * Each mode defines how many fragments the received frame will be split * up into by the NIC. The frame is split into L3 header, L4 Header, * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself * is split into 3 fragments. As of now only single buffer mode is * supported. * Return Value: * SUCCESS on success or an appropriate -ve value on failure. */ int fill_rx_buffers(struct s2io_nic *nic, int ring_no) { struct net_device *dev = nic->dev; struct sk_buff *skb; RxD_t *rxdp; int off, off1, size, block_no, block_no1; int offset, offset1; u32 alloc_tab = 0; u32 alloc_cnt; mac_info_t *mac_control; struct config_param *config; #ifdef CONFIG_2BUFF_MODE RxD_t *rxdpnext; int nextblk; u64 tmp; buffAdd_t *ba; dma_addr_t rxdpphys; #endif #ifndef CONFIG_S2IO_NAPI unsigned long flags; #endif RxD_t *first_rxdp = NULL; mac_control = &nic->mac_control; config = &nic->config; alloc_cnt = mac_control->rings[ring_no].pkt_cnt - atomic_read(&nic->rx_bufs_left[ring_no]); size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + HEADER_802_2_SIZE + HEADER_SNAP_SIZE; while (alloc_tab < alloc_cnt) { block_no = mac_control->rings[ring_no].rx_curr_put_info. block_index; block_no1 = mac_control->rings[ring_no].rx_curr_get_info. block_index; off = mac_control->rings[ring_no].rx_curr_put_info.offset; off1 = mac_control->rings[ring_no].rx_curr_get_info.offset; #ifndef CONFIG_2BUFF_MODE offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off; offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1; #else offset = block_no * (MAX_RXDS_PER_BLOCK) + off; offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1; #endif rxdp = mac_control->rings[ring_no].rx_blocks[block_no]. block_virt_addr + off; if ((offset == offset1) && (rxdp->Host_Control)) { DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name); DBG_PRINT(INTR_DBG, " info equated\n"); goto end; } #ifndef CONFIG_2BUFF_MODE if (rxdp->Control_1 == END_OF_BLOCK) { mac_control->rings[ring_no].rx_curr_put_info. block_index++; mac_control->rings[ring_no].rx_curr_put_info. block_index %= mac_control->rings[ring_no].block_count; block_no = mac_control->rings[ring_no].rx_curr_put_info. block_index; off++; off %= (MAX_RXDS_PER_BLOCK + 1); mac_control->rings[ring_no].rx_curr_put_info.offset = off; rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2); DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", dev->name, rxdp); } #ifndef CONFIG_S2IO_NAPI spin_lock_irqsave(&nic->put_lock, flags); mac_control->rings[ring_no].put_pos = (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off; spin_unlock_irqrestore(&nic->put_lock, flags); #endif #else if (rxdp->Host_Control == END_OF_BLOCK) { mac_control->rings[ring_no].rx_curr_put_info. block_index++; mac_control->rings[ring_no].rx_curr_put_info.block_index %= mac_control->rings[ring_no].block_count; block_no = mac_control->rings[ring_no].rx_curr_put_info .block_index; off = 0; DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n", dev->name, block_no, (unsigned long long) rxdp->Control_1); mac_control->rings[ring_no].rx_curr_put_info.offset = off; rxdp = mac_control->rings[ring_no].rx_blocks[block_no]. block_virt_addr; } #ifndef CONFIG_S2IO_NAPI spin_lock_irqsave(&nic->put_lock, flags); mac_control->rings[ring_no].put_pos = (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off; spin_unlock_irqrestore(&nic->put_lock, flags); #endif #endif #ifndef CONFIG_2BUFF_MODE if (rxdp->Control_1 & RXD_OWN_XENA) #else if (rxdp->Control_2 & BIT(0)) #endif { mac_control->rings[ring_no].rx_curr_put_info. offset = off; goto end; } #ifdef CONFIG_2BUFF_MODE /* * RxDs Spanning cache lines will be replenished only * if the succeeding RxD is also owned by Host. It * will always be the ((8*i)+3) and ((8*i)+6) * descriptors for the 48 byte descriptor. The offending * decsriptor is of-course the 3rd descriptor. */ rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no]. block_dma_addr + (off * sizeof(RxD_t)); if (((u64) (rxdpphys)) % 128 > 80) { rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no]. block_virt_addr + (off + 1); if (rxdpnext->Host_Control == END_OF_BLOCK) { nextblk = (block_no + 1) % (mac_control->rings[ring_no].block_count); rxdpnext = mac_control->rings[ring_no].rx_blocks [nextblk].block_virt_addr; } if (rxdpnext->Control_2 & BIT(0)) goto end; } #endif #ifndef CONFIG_2BUFF_MODE skb = dev_alloc_skb(size + NET_IP_ALIGN); #else skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE + BUF0_LEN + 4); #endif if (!skb) { DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name); DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n"); if (first_rxdp) { wmb(); first_rxdp->Control_1 |= RXD_OWN_XENA; } return -ENOMEM; } #ifndef CONFIG_2BUFF_MODE skb_reserve(skb, NET_IP_ALIGN); memset(rxdp, 0, sizeof(RxD_t)); rxdp->Buffer0_ptr = pci_map_single (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE); rxdp->Control_2 &= (~MASK_BUFFER0_SIZE); rxdp->Control_2 |= SET_BUFFER0_SIZE(size); rxdp->Host_Control = (unsigned long) (skb); if (alloc_tab & ((1 << rxsync_frequency) - 1)) rxdp->Control_1 |= RXD_OWN_XENA; off++; off %= (MAX_RXDS_PER_BLOCK + 1); mac_control->rings[ring_no].rx_curr_put_info.offset = off; #else ba = &mac_control->rings[ring_no].ba[block_no][off]; skb_reserve(skb, BUF0_LEN); tmp = ((unsigned long) skb->data & ALIGN_SIZE); if (tmp) skb_reserve(skb, (ALIGN_SIZE + 1) - tmp); memset(rxdp, 0, sizeof(RxD_t)); rxdp->Buffer2_ptr = pci_map_single (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4, PCI_DMA_FROMDEVICE); rxdp->Buffer0_ptr = pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN, PCI_DMA_FROMDEVICE); rxdp->Buffer1_ptr = pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN, PCI_DMA_FROMDEVICE); rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4); rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN); rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */ rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */ rxdp->Host_Control = (u64) ((unsigned long) (skb)); if (alloc_tab & ((1 << rxsync_frequency) - 1)) rxdp->Control_1 |= RXD_OWN_XENA; off++; mac_control->rings[ring_no].rx_curr_put_info.offset = off; #endif rxdp->Control_2 |= SET_RXD_MARKER; if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) { if (first_rxdp) { wmb(); first_rxdp->Control_1 |= RXD_OWN_XENA; } first_rxdp = rxdp; } atomic_inc(&nic->rx_bufs_left[ring_no]); alloc_tab++; } end: /* Transfer ownership of first descriptor to adapter just before * exiting. Before that, use memory barrier so that ownership * and other fields are seen by adapter correctly. */ if (first_rxdp) { wmb(); first_rxdp->Control_1 |= RXD_OWN_XENA; } return SUCCESS; } /** * free_rx_buffers - Frees all Rx buffers * @sp: device private variable. * Description: * This function will free all Rx buffers allocated by host. * Return Value: * NONE. */ static void free_rx_buffers(struct s2io_nic *sp) { struct net_device *dev = sp->dev; int i, j, blk = 0, off, buf_cnt = 0; RxD_t *rxdp; struct sk_buff *skb; mac_info_t *mac_control; struct config_param *config; #ifdef CONFIG_2BUFF_MODE buffAdd_t *ba; #endif mac_control = &sp->mac_control; config = &sp->config; for (i = 0; i < config->rx_ring_num; i++) { for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) { off = j % (MAX_RXDS_PER_BLOCK + 1); rxdp = mac_control->rings[i].rx_blocks[blk]. block_virt_addr + off; #ifndef CONFIG_2BUFF_MODE if (rxdp->Control_1 == END_OF_BLOCK) { rxdp = (RxD_t *) ((unsigned long) rxdp-> Control_2); j++; blk++; } #else if (rxdp->Host_Control == END_OF_BLOCK) { blk++; continue; } #endif if (!(rxdp->Control_1 & RXD_OWN_XENA)) { memset(rxdp, 0, sizeof(RxD_t)); continue; } skb = (struct sk_buff *) ((unsigned long) rxdp-> Host_Control); if (skb) { #ifndef CONFIG_2BUFF_MODE pci_unmap_single(sp->pdev, (dma_addr_t) rxdp->Buffer0_ptr, dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + HEADER_802_2_SIZE + HEADER_SNAP_SIZE, PCI_DMA_FROMDEVICE); #else ba = &mac_control->rings[i].ba[blk][off]; pci_unmap_single(sp->pdev, (dma_addr_t) rxdp->Buffer0_ptr, BUF0_LEN, PCI_DMA_FROMDEVICE); pci_unmap_single(sp->pdev, (dma_addr_t) rxdp->Buffer1_ptr, BUF1_LEN, PCI_DMA_FROMDEVICE); pci_unmap_single(sp->pdev, (dma_addr_t) rxdp->Buffer2_ptr, dev->mtu + BUF0_LEN + 4, PCI_DMA_FROMDEVICE); #endif dev_kfree_skb(skb); atomic_dec(&sp->rx_bufs_left[i]); buf_cnt++; } memset(rxdp, 0, sizeof(RxD_t)); } mac_control->rings[i].rx_curr_put_info.block_index = 0; mac_control->rings[i].rx_curr_get_info.block_index = 0; mac_control->rings[i].rx_curr_put_info.offset = 0; mac_control->rings[i].rx_curr_get_info.offset = 0; atomic_set(&sp->rx_bufs_left[i], 0); DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n", dev->name, buf_cnt, i); } } /** * s2io_poll - Rx interrupt handler for NAPI support * @dev : pointer to the device structure. * @budget : The number of packets that were budgeted to be processed * during one pass through the 'Poll" function. * Description: * Comes into picture only if NAPI support has been incorporated. It does * the same thing that rx_intr_handler does, but not in a interrupt context * also It will process only a given number of packets. * Return value: * 0 on success and 1 if there are No Rx packets to be processed. */ #if defined(CONFIG_S2IO_NAPI) static int s2io_poll(struct net_device *dev, int *budget) { nic_t *nic = dev->priv; int pkt_cnt = 0, org_pkts_to_process; mac_info_t *mac_control; struct config_param *config; XENA_dev_config_t __iomem *bar0 = nic->bar0; u64 val64; int i; atomic_inc(&nic->isr_cnt); mac_control = &nic->mac_control; config = &nic->config; nic->pkts_to_process = *budget; if (nic->pkts_to_process > dev->quota) nic->pkts_to_process = dev->quota; org_pkts_to_process = nic->pkts_to_process; val64 = readq(&bar0->rx_traffic_int); writeq(val64, &bar0->rx_traffic_int); for (i = 0; i < config->rx_ring_num; i++) { rx_intr_handler(&mac_control->rings[i]); pkt_cnt = org_pkts_to_process - nic->pkts_to_process; if (!nic->pkts_to_process) { /* Quota for the current iteration has been met */ goto no_rx; } } if (!pkt_cnt) pkt_cnt = 1; dev->quota -= pkt_cnt; *budget -= pkt_cnt; netif_rx_complete(dev); for (i = 0; i < config->rx_ring_num; i++) { if (fill_rx_buffers(nic, i) == -ENOMEM) { DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name); DBG_PRINT(ERR_DBG, " in Rx Poll!!\n"); break; } } /* Re enable the Rx interrupts. */ en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS); atomic_dec(&nic->isr_cnt); return 0; no_rx: dev->quota -= pkt_cnt; *budget -= pkt_cnt; for (i = 0; i < config->rx_ring_num; i++) { if (fill_rx_buffers(nic, i) == -ENOMEM) { DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name); DBG_PRINT(ERR_DBG, " in Rx Poll!!\n"); break; } } atomic_dec(&nic->isr_cnt); return 1; } #endif /** * rx_intr_handler - Rx interrupt handler * @nic: device private variable. * Description: * If the interrupt is because of a received frame or if the * receive ring contains fresh as yet un-processed frames,this function is * called. It picks out the RxD at which place the last Rx processing had * stopped and sends the skb to the OSM's Rx handler and then increments * the offset. * Return Value: * NONE. */ static void rx_intr_handler(ring_info_t *ring_data) { nic_t *nic = ring_data->nic; struct net_device *dev = (struct net_device *) nic->dev; int get_block, get_offset, put_block, put_offset, ring_bufs; rx_curr_get_info_t get_info, put_info; RxD_t *rxdp; struct sk_buff *skb; #ifndef CONFIG_S2IO_NAPI int pkt_cnt = 0; #endif spin_lock(&nic->rx_lock); if (atomic_read(&nic->card_state) == CARD_DOWN) { DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n", __FUNCTION__, dev->name); spin_unlock(&nic->rx_lock); return; } get_info = ring_data->rx_curr_get_info; get_block = get_info.block_index; put_info = ring_data->rx_curr_put_info; put_block = put_info.block_index; ring_bufs = get_info.ring_len+1; rxdp = ring_data->rx_blocks[get_block].block_virt_addr + get_info.offset; get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) + get_info.offset; #ifndef CONFIG_S2IO_NAPI spin_lock(&nic->put_lock); put_offset = ring_data->put_pos; spin_unlock(&nic->put_lock); #else put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) + put_info.offset; #endif while (RXD_IS_UP2DT(rxdp) && (((get_offset + 1) % ring_bufs) != put_offset)) { skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control); if (skb == NULL) { DBG_PRINT(ERR_DBG, "%s: The skb is ", dev->name); DBG_PRINT(ERR_DBG, "Null in Rx Intr\n"); spin_unlock(&nic->rx_lock); return; } #ifndef CONFIG_2BUFF_MODE pci_unmap_single(nic->pdev, (dma_addr_t) rxdp->Buffer0_ptr, dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + HEADER_802_2_SIZE + HEADER_SNAP_SIZE, PCI_DMA_FROMDEVICE); #else pci_unmap_single(nic->pdev, (dma_addr_t) rxdp->Buffer0_ptr, BUF0_LEN, PCI_DMA_FROMDEVICE); pci_unmap_single(nic->pdev, (dma_addr_t) rxdp->Buffer1_ptr, BUF1_LEN, PCI_DMA_FROMDEVICE); pci_unmap_single(nic->pdev, (dma_addr_t) rxdp->Buffer2_ptr, dev->mtu + BUF0_LEN + 4, PCI_DMA_FROMDEVICE); #endif rx_osm_handler(ring_data, rxdp); get_info.offset++; ring_data->rx_curr_get_info.offset = get_info.offset; rxdp = ring_data->rx_blocks[get_block].block_virt_addr + get_info.offset; if (get_info.offset && (!(get_info.offset % MAX_RXDS_PER_BLOCK))) { get_info.offset = 0; ring_data->rx_curr_get_info.offset = get_info.offset; get_block++; get_block %= ring_data->block_count; ring_data->rx_curr_get_info.block_index = get_block; rxdp = ring_data->rx_blocks[get_block].block_virt_addr; } get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) + get_info.offset; #ifdef CONFIG_S2IO_NAPI nic->pkts_to_process -= 1; if (!nic->pkts_to_process) break; #else pkt_cnt++; if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts)) break; #endif } spin_unlock(&nic->rx_lock); } /** * tx_intr_handler - Transmit interrupt handler * @nic : device private variable * Description: * If an interrupt was raised to indicate DMA complete of the * Tx packet, this function is called. It identifies the last TxD * whose buffer was freed and frees all skbs whose data have already * DMA'ed into the NICs internal memory. * Return Value: * NONE */ static void tx_intr_handler(fifo_info_t *fifo_data) { nic_t *nic = fifo_data->nic; struct net_device *dev = (struct net_device *) nic->dev; tx_curr_get_info_t get_info, put_info; struct sk_buff *skb; TxD_t *txdlp; u16 j, frg_cnt; get_info = fifo_data->tx_curr_get_info; put_info = fifo_data->tx_curr_put_info; txdlp = (TxD_t *) fifo_data->list_info[get_info.offset]. list_virt_addr; while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && (get_info.offset != put_info.offset) && (txdlp->Host_Control)) { /* Check for TxD errors */ if (txdlp->Control_1 & TXD_T_CODE) { unsigned long long err; err = txdlp->Control_1 & TXD_T_CODE; if ((err >> 48) == 0xA) { DBG_PRINT(TX_DBG, "TxD returned due \ to loss of link\n"); } else { DBG_PRINT(ERR_DBG, "***TxD error \ %llx\n", err); } } skb = (struct sk_buff *) ((unsigned long) txdlp->Host_Control); if (skb == NULL) { DBG_PRINT(ERR_DBG, "%s: Null skb ", __FUNCTION__); DBG_PRINT(ERR_DBG, "in Tx Free Intr\n"); return; } frg_cnt = skb_shinfo(skb)->nr_frags; nic->tx_pkt_count++; pci_unmap_single(nic->pdev, (dma_addr_t) txdlp->Buffer_Pointer, skb->len - skb->data_len, PCI_DMA_TODEVICE); if (frg_cnt) { TxD_t *temp; temp = txdlp; txdlp++; for (j = 0; j < frg_cnt; j++, txdlp++) { skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; if (!txdlp->Buffer_Pointer) break; pci_unmap_page(nic->pdev, (dma_addr_t) txdlp-> Buffer_Pointer, frag->size, PCI_DMA_TODEVICE); } txdlp = temp; } memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds)); /* Updating the statistics block */ nic->stats.tx_bytes += skb->len; dev_kfree_skb_irq(skb); get_info.offset++; get_info.offset %= get_info.fifo_len + 1; txdlp = (TxD_t *) fifo_data->list_info [get_info.offset].list_virt_addr; fifo_data->tx_curr_get_info.offset = get_info.offset; } spin_lock(&nic->tx_lock); if (netif_queue_stopped(dev)) netif_wake_queue(dev); spin_unlock(&nic->tx_lock); } /** * alarm_intr_handler - Alarm Interrrupt handler * @nic: device private variable * Description: If the interrupt was neither because of Rx packet or Tx * complete, this function is called. If the interrupt was to indicate * a loss of link, the OSM link status handler is invoked for any other * alarm interrupt the block that raised the interrupt is displayed * and a H/W reset is issued. * Return Value: * NONE */ static void alarm_intr_handler(struct s2io_nic *nic) { struct net_device *dev = (struct net_device *) nic->dev; XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64 = 0, err_reg = 0; /* Handling link status change error Intr */ if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) { err_reg = readq(&bar0->mac_rmac_err_reg); writeq(err_reg, &bar0->mac_rmac_err_reg); if (err_reg & RMAC_LINK_STATE_CHANGE_INT) { schedule_work(&nic->set_link_task); } } /* Handling Ecc errors */ val64 = readq(&bar0->mc_err_reg); writeq(val64, &bar0->mc_err_reg); if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) { if (val64 & MC_ERR_REG_ECC_ALL_DBL) { nic->mac_control.stats_info->sw_stat. double_ecc_errs++; DBG_PRINT(INIT_DBG, "%s: Device indicates ", dev->name); DBG_PRINT(INIT_DBG, "double ECC error!!\n"); if (nic->device_type != XFRAME_II_DEVICE) { /* Reset XframeI only if critical error */ if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 | MC_ERR_REG_MIRI_ECC_DB_ERR_1)) { netif_stop_queue(dev); schedule_work(&nic->rst_timer_task); } } } else { nic->mac_control.stats_info->sw_stat. single_ecc_errs++; } } /* In case of a serious error, the device will be Reset. */ val64 = readq(&bar0->serr_source); if (val64 & SERR_SOURCE_ANY) { DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name); DBG_PRINT(ERR_DBG, "serious error %llx!!\n", (unsigned long long)val64); netif_stop_queue(dev); schedule_work(&nic->rst_timer_task); } /* * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC * Error occurs, the adapter will be recycled by disabling the * adapter enable bit and enabling it again after the device * becomes Quiescent. */ val64 = readq(&bar0->pcc_err_reg); writeq(val64, &bar0->pcc_err_reg); if (val64 & PCC_FB_ECC_DB_ERR) { u64 ac = readq(&bar0->adapter_control); ac &= ~(ADAPTER_CNTL_EN); writeq(ac, &bar0->adapter_control); ac = readq(&bar0->adapter_control); schedule_work(&nic->set_link_task); } /* Other type of interrupts are not being handled now, TODO */ } /** * wait_for_cmd_complete - waits for a command to complete. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * Description: Function that waits for a command to Write into RMAC * ADDR DATA registers to be completed and returns either success or * error depending on whether the command was complete or not. * Return value: * SUCCESS on success and FAILURE on failure. */ int wait_for_cmd_complete(nic_t * sp) { XENA_dev_config_t __iomem *bar0 = sp->bar0; int ret = FAILURE, cnt = 0; u64 val64; while (TRUE) { val64 = readq(&bar0->rmac_addr_cmd_mem); if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) { ret = SUCCESS; break; } msleep(50); if (cnt++ > 10) break; } return ret; } /** * s2io_reset - Resets the card. * @sp : private member of the device structure. * Description: Function to Reset the card. This function then also * restores the previously saved PCI configuration space registers as * the card reset also resets the configuration space. * Return value: * void. */ void s2io_reset(nic_t * sp) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64; u16 subid, pci_cmd; /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); val64 = SW_RESET_ALL; writeq(val64, &bar0->sw_reset); /* * At this stage, if the PCI write is indeed completed, the * card is reset and so is the PCI Config space of the device. * So a read cannot be issued at this stage on any of the * registers to ensure the write into "sw_reset" register * has gone through. * Question: Is there any system call that will explicitly force * all the write commands still pending on the bus to be pushed * through? * As of now I'am just giving a 250ms delay and hoping that the * PCI write to sw_reset register is done by this time. */ msleep(250); /* Restore the PCI state saved during initialization. */ pci_restore_state(sp->pdev); pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd); s2io_init_pci(sp); msleep(250); /* Set swapper to enable I/O register access */ s2io_set_swapper(sp); /* Restore the MSIX table entries from local variables */ restore_xmsi_data(sp); /* Clear certain PCI/PCI-X fields after reset */ if (sp->device_type == XFRAME_II_DEVICE) { /* Clear parity err detect bit */ pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000); /* Clearing PCIX Ecc status register */ pci_write_config_dword(sp->pdev, 0x68, 0x7C); /* Clearing PCI_STATUS error reflected here */ writeq(BIT(62), &bar0->txpic_int_reg); } /* Reset device statistics maintained by OS */ memset(&sp->stats, 0, sizeof (struct net_device_stats)); /* SXE-002: Configure link and activity LED to turn it off */ subid = sp->pdev->subsystem_device; if (((subid & 0xFF) >= 0x07) && (sp->device_type == XFRAME_I_DEVICE)) { val64 = readq(&bar0->gpio_control); val64 |= 0x0000800000000000ULL; writeq(val64, &bar0->gpio_control); val64 = 0x0411040400000000ULL; writeq(val64, (void __iomem *)bar0 + 0x2700); } /* * Clear spurious ECC interrupts that would have occured on * XFRAME II cards after reset. */ if (sp->device_type == XFRAME_II_DEVICE) { val64 = readq(&bar0->pcc_err_reg); writeq(val64, &bar0->pcc_err_reg); } sp->device_enabled_once = FALSE; } /** * s2io_set_swapper - to set the swapper controle on the card * @sp : private member of the device structure, * pointer to the s2io_nic structure. * Description: Function to set the swapper control on the card * correctly depending on the 'endianness' of the system. * Return value: * SUCCESS on success and FAILURE on failure. */ int s2io_set_swapper(nic_t * sp) { struct net_device *dev = sp->dev; XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64, valt, valr; /* * Set proper endian settings and verify the same by reading * the PIF Feed-back register. */ val64 = readq(&bar0->pif_rd_swapper_fb); if (val64 != 0x0123456789ABCDEFULL) { int i = 0; u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */ 0x8100008181000081ULL, /* FE=1, SE=0 */ 0x4200004242000042ULL, /* FE=0, SE=1 */ 0}; /* FE=0, SE=0 */ while(i<4) { writeq(value[i], &bar0->swapper_ctrl); val64 = readq(&bar0->pif_rd_swapper_fb); if (val64 == 0x0123456789ABCDEFULL) break; i++; } if (i == 4) { DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ", dev->name); DBG_PRINT(ERR_DBG, "feedback read %llx\n", (unsigned long long) val64); return FAILURE; } valr = value[i]; } else { valr = readq(&bar0->swapper_ctrl); } valt = 0x0123456789ABCDEFULL; writeq(valt, &bar0->xmsi_address); val64 = readq(&bar0->xmsi_address); if(val64 != valt) { int i = 0; u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */ 0x0081810000818100ULL, /* FE=1, SE=0 */ 0x0042420000424200ULL, /* FE=0, SE=1 */ 0}; /* FE=0, SE=0 */ while(i<4) { writeq((value[i] | valr), &bar0->swapper_ctrl); writeq(valt, &bar0->xmsi_address); val64 = readq(&bar0->xmsi_address); if(val64 == valt) break; i++; } if(i == 4) { unsigned long long x = val64; DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr "); DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x); return FAILURE; } } val64 = readq(&bar0->swapper_ctrl); val64 &= 0xFFFF000000000000ULL; #ifdef __BIG_ENDIAN /* * The device by default set to a big endian format, so a * big endian driver need not set anything. */ val64 |= (SWAPPER_CTRL_TXP_FE | SWAPPER_CTRL_TXP_SE | SWAPPER_CTRL_TXD_R_FE | SWAPPER_CTRL_TXD_W_FE | SWAPPER_CTRL_TXF_R_FE | SWAPPER_CTRL_RXD_R_FE | SWAPPER_CTRL_RXD_W_FE | SWAPPER_CTRL_RXF_W_FE | SWAPPER_CTRL_XMSI_FE | SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); if (sp->intr_type == INTA) val64 |= SWAPPER_CTRL_XMSI_SE; writeq(val64, &bar0->swapper_ctrl); #else /* * Initially we enable all bits to make it accessible by the * driver, then we selectively enable only those bits that * we want to set. */ val64 |= (SWAPPER_CTRL_TXP_FE | SWAPPER_CTRL_TXP_SE | SWAPPER_CTRL_TXD_R_FE | SWAPPER_CTRL_TXD_R_SE | SWAPPER_CTRL_TXD_W_FE | SWAPPER_CTRL_TXD_W_SE | SWAPPER_CTRL_TXF_R_FE | SWAPPER_CTRL_RXD_R_FE | SWAPPER_CTRL_RXD_R_SE | SWAPPER_CTRL_RXD_W_FE | SWAPPER_CTRL_RXD_W_SE | SWAPPER_CTRL_RXF_W_FE | SWAPPER_CTRL_XMSI_FE | SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); if (sp->intr_type == INTA) val64 |= SWAPPER_CTRL_XMSI_SE; writeq(val64, &bar0->swapper_ctrl); #endif val64 = readq(&bar0->swapper_ctrl); /* * Verifying if endian settings are accurate by reading a * feedback register. */ val64 = readq(&bar0->pif_rd_swapper_fb); if (val64 != 0x0123456789ABCDEFULL) { /* Endian settings are incorrect, calls for another dekko. */ DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ", dev->name); DBG_PRINT(ERR_DBG, "feedback read %llx\n", (unsigned long long) val64); return FAILURE; } return SUCCESS; } int wait_for_msix_trans(nic_t *nic, int i) { XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; u64 val64; int ret = 0, cnt = 0; do { val64 = readq(&bar0->xmsi_access); if (!(val64 & BIT(15))) break; mdelay(1); cnt++; } while(cnt < 5); if (cnt == 5) { DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i); ret = 1; } return ret; } void restore_xmsi_data(nic_t *nic) { XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; u64 val64; int i; for (i=0; i< MAX_REQUESTED_MSI_X; i++) { writeq(nic->msix_info[i].addr, &bar0->xmsi_address); writeq(nic->msix_info[i].data, &bar0->xmsi_data); val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6)); writeq(val64, &bar0->xmsi_access); if (wait_for_msix_trans(nic, i)) { DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__); continue; } } } void store_xmsi_data(nic_t *nic) { XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; u64 val64, addr, data; int i; /* Store and display */ for (i=0; i< MAX_REQUESTED_MSI_X; i++) { val64 = (BIT(15) | vBIT(i, 26, 6)); writeq(val64, &bar0->xmsi_access); if (wait_for_msix_trans(nic, i)) { DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__); continue; } addr = readq(&bar0->xmsi_address); data = readq(&bar0->xmsi_data); if (addr && data) { nic->msix_info[i].addr = addr; nic->msix_info[i].data = data; } } } int s2io_enable_msi(nic_t *nic) { XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; u16 msi_ctrl, msg_val; struct config_param *config = &nic->config; struct net_device *dev = nic->dev; u64 val64, tx_mat, rx_mat; int i, err; val64 = readq(&bar0->pic_control); val64 &= ~BIT(1); writeq(val64, &bar0->pic_control); err = pci_enable_msi(nic->pdev); if (err) { DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n", nic->dev->name); return err; } /* * Enable MSI and use MSI-1 in stead of the standard MSI-0 * for interrupt handling. */ pci_read_config_word(nic->pdev, 0x4c, &msg_val); msg_val ^= 0x1; pci_write_config_word(nic->pdev, 0x4c, msg_val); pci_read_config_word(nic->pdev, 0x4c, &msg_val); pci_read_config_word(nic->pdev, 0x42, &msi_ctrl); msi_ctrl |= 0x10; pci_write_config_word(nic->pdev, 0x42, msi_ctrl); /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */ tx_mat = readq(&bar0->tx_mat0_n[0]); for (i=0; i<config->tx_fifo_num; i++) { tx_mat |= TX_MAT_SET(i, 1); } writeq(tx_mat, &bar0->tx_mat0_n[0]); rx_mat = readq(&bar0->rx_mat); for (i=0; i<config->rx_ring_num; i++) { rx_mat |= RX_MAT_SET(i, 1); } writeq(rx_mat, &bar0->rx_mat); dev->irq = nic->pdev->irq; return 0; } int s2io_enable_msi_x(nic_t *nic) { XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; u64 tx_mat, rx_mat; u16 msi_control; /* Temp variable */ int ret, i, j, msix_indx = 1; nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry), GFP_KERNEL); if (nic->entries == NULL) { DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__); return -ENOMEM; } memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry)); nic->s2io_entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry), GFP_KERNEL); if (nic->s2io_entries == NULL) { DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__); kfree(nic->entries); return -ENOMEM; } memset(nic->s2io_entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry)); for (i=0; i< MAX_REQUESTED_MSI_X; i++) { nic->entries[i].entry = i; nic->s2io_entries[i].entry = i; nic->s2io_entries[i].arg = NULL; nic->s2io_entries[i].in_use = 0; } tx_mat = readq(&bar0->tx_mat0_n[0]); for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) { tx_mat |= TX_MAT_SET(i, msix_indx); nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i]; nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE; nic->s2io_entries[msix_indx].in_use = MSIX_FLG; } writeq(tx_mat, &bar0->tx_mat0_n[0]); if (!nic->config.bimodal) { rx_mat = readq(&bar0->rx_mat); for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) { rx_mat |= RX_MAT_SET(j, msix_indx); nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j]; nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE; nic->s2io_entries[msix_indx].in_use = MSIX_FLG; } writeq(rx_mat, &bar0->rx_mat); } else { tx_mat = readq(&bar0->tx_mat0_n[7]); for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) { tx_mat |= TX_MAT_SET(i, msix_indx); nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j]; nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE; nic->s2io_entries[msix_indx].in_use = MSIX_FLG; } writeq(tx_mat, &bar0->tx_mat0_n[7]); } ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X); if (ret) { DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name); kfree(nic->entries); kfree(nic->s2io_entries); nic->entries = NULL; nic->s2io_entries = NULL; return -ENOMEM; } /* * To enable MSI-X, MSI also needs to be enabled, due to a bug * in the herc NIC. (Temp change, needs to be removed later) */ pci_read_config_word(nic->pdev, 0x42, &msi_control); msi_control |= 0x1; /* Enable MSI */ pci_write_config_word(nic->pdev, 0x42, msi_control); return 0; } /* ********************************************************* * * Functions defined below concern the OS part of the driver * * ********************************************************* */ /** * s2io_open - open entry point of the driver * @dev : pointer to the device structure. * Description: * This function is the open entry point of the driver. It mainly calls a * function to allocate Rx buffers and inserts them into the buffer * descriptors and then enables the Rx part of the NIC. * Return value: * 0 on success and an appropriate (-)ve integer as defined in errno.h * file on failure. */ int s2io_open(struct net_device *dev) { nic_t *sp = dev->priv; int err = 0; int i; u16 msi_control; /* Temp variable */ /* * Make sure you have link off by default every time * Nic is initialized */ netif_carrier_off(dev); sp->last_link_state = 0; /* Initialize H/W and enable interrupts */ if (s2io_card_up(sp)) { DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", dev->name); err = -ENODEV; goto hw_init_failed; } /* Store the values of the MSIX table in the nic_t structure */ store_xmsi_data(sp); /* After proper initialization of H/W, register ISR */ if (sp->intr_type == MSI) { err = request_irq((int) sp->pdev->irq, s2io_msi_handle, SA_SHIRQ, sp->name, dev); if (err) { DBG_PRINT(ERR_DBG, "%s: MSI registration \ failed\n", dev->name); goto isr_registration_failed; } } if (sp->intr_type == MSI_X) { for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) { if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) { sprintf(sp->desc1, "%s:MSI-X-%d-TX", dev->name, i); err = request_irq(sp->entries[i].vector, s2io_msix_fifo_handle, 0, sp->desc1, sp->s2io_entries[i].arg); DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1, sp->msix_info[i].addr); } else { sprintf(sp->desc2, "%s:MSI-X-%d-RX", dev->name, i); err = request_irq(sp->entries[i].vector, s2io_msix_ring_handle, 0, sp->desc2, sp->s2io_entries[i].arg); DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2, sp->msix_info[i].addr); } if (err) { DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \ failed\n", dev->name, i); DBG_PRINT(ERR_DBG, "Returned: %d\n", err); goto isr_registration_failed; } sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS; } } if (sp->intr_type == INTA) { err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ, sp->name, dev); if (err) { DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n", dev->name); goto isr_registration_failed; } } if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) { DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n"); err = -ENODEV; goto setting_mac_address_failed; } netif_start_queue(dev); return 0; setting_mac_address_failed: if (sp->intr_type != MSI_X) free_irq(sp->pdev->irq, dev); isr_registration_failed: del_timer_sync(&sp->alarm_timer); if (sp->intr_type == MSI_X) { if (sp->device_type == XFRAME_II_DEVICE) { for (i=1; (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS); i++) { int vector = sp->entries[i].vector; void *arg = sp->s2io_entries[i].arg; free_irq(vector, arg); } pci_disable_msix(sp->pdev); /* Temp */ pci_read_config_word(sp->pdev, 0x42, &msi_control); msi_control &= 0xFFFE; /* Disable MSI */ pci_write_config_word(sp->pdev, 0x42, msi_control); } } else if (sp->intr_type == MSI) pci_disable_msi(sp->pdev); s2io_reset(sp); hw_init_failed: if (sp->intr_type == MSI_X) { if (sp->entries) kfree(sp->entries); if (sp->s2io_entries) kfree(sp->s2io_entries); } return err; } /** * s2io_close -close entry point of the driver * @dev : device pointer. * Description: * This is the stop entry point of the driver. It needs to undo exactly * whatever was done by the open entry point,thus it's usually referred to * as the close function.Among other things this function mainly stops the * Rx side of the NIC and frees all the Rx buffers in the Rx rings. * Return value: * 0 on success and an appropriate (-)ve integer as defined in errno.h * file on failure. */ int s2io_close(struct net_device *dev) { nic_t *sp = dev->priv; int i; u16 msi_control; flush_scheduled_work(); netif_stop_queue(dev); /* Reset card, kill tasklet and free Tx and Rx buffers. */ s2io_card_down(sp); if (sp->intr_type == MSI_X) { if (sp->device_type == XFRAME_II_DEVICE) { for (i=1; (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS); i++) { int vector = sp->entries[i].vector; void *arg = sp->s2io_entries[i].arg; free_irq(vector, arg); } pci_read_config_word(sp->pdev, 0x42, &msi_control); msi_control &= 0xFFFE; /* Disable MSI */ pci_write_config_word(sp->pdev, 0x42, msi_control); pci_disable_msix(sp->pdev); } } else { free_irq(sp->pdev->irq, dev); if (sp->intr_type == MSI) pci_disable_msi(sp->pdev); } sp->device_close_flag = TRUE; /* Device is shut down. */ return 0; } /** * s2io_xmit - Tx entry point of te driver * @skb : the socket buffer containing the Tx data. * @dev : device pointer. * Description : * This function is the Tx entry point of the driver. S2IO NIC supports * certain protocol assist features on Tx side, namely CSO, S/G, LSO. * NOTE: when device cant queue the pkt,just the trans_start variable will * not be upadted. * Return value: * 0 on success & 1 on failure. */ int s2io_xmit(struct sk_buff *skb, struct net_device *dev) { nic_t *sp = dev->priv; u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off; register u64 val64; TxD_t *txdp; TxFIFO_element_t __iomem *tx_fifo; unsigned long flags; #ifdef NETIF_F_TSO int mss; #endif u16 vlan_tag = 0; int vlan_priority = 0; mac_info_t *mac_control; struct config_param *config; mac_control = &sp->mac_control; config = &sp->config; DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name); spin_lock_irqsave(&sp->tx_lock, flags); if (atomic_read(&sp->card_state) == CARD_DOWN) { DBG_PRINT(TX_DBG, "%s: Card going down for reset\n", dev->name); spin_unlock_irqrestore(&sp->tx_lock, flags); dev_kfree_skb(skb); return 0; } queue = 0; /* Get Fifo number to Transmit based on vlan priority */ if (sp->vlgrp && vlan_tx_tag_present(skb)) { vlan_tag = vlan_tx_tag_get(skb); vlan_priority = vlan_tag >> 13; queue = config->fifo_mapping[vlan_priority]; } put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset; get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset; txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off]. list_virt_addr; queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1; /* Avoid "put" pointer going beyond "get" pointer */ if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) { DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n"); netif_stop_queue(dev); dev_kfree_skb(skb); spin_unlock_irqrestore(&sp->tx_lock, flags); return 0; } /* A buffer with no data will be dropped */ if (!skb->len) { DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name); dev_kfree_skb(skb); spin_unlock_irqrestore(&sp->tx_lock, flags); return 0; } #ifdef NETIF_F_TSO mss = skb_shinfo(skb)->tso_size; if (mss) { txdp->Control_1 |= TXD_TCP_LSO_EN; txdp->Control_1 |= TXD_TCP_LSO_MSS(mss); } #endif frg_cnt = skb_shinfo(skb)->nr_frags; frg_len = skb->len - skb->data_len; txdp->Buffer_Pointer = pci_map_single (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE); txdp->Host_Control = (unsigned long) skb; if (skb->ip_summed == CHECKSUM_HW) { txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN | TXD_TX_CKO_UDP_EN); } txdp->Control_2 |= config->tx_intr_type; if (sp->vlgrp && vlan_tx_tag_present(skb)) { txdp->Control_2 |= TXD_VLAN_ENABLE; txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag); } txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) | TXD_GATHER_CODE_FIRST); txdp->Control_1 |= TXD_LIST_OWN_XENA; /* For fragmented SKB. */ for (i = 0; i < frg_cnt; i++) { skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; /* A '0' length fragment will be ignored */ if (!frag->size) continue; txdp++; txdp->Buffer_Pointer = (u64) pci_map_page (sp->pdev, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE); txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size); } txdp->Control_1 |= TXD_GATHER_CODE_LAST; tx_fifo = mac_control->tx_FIFO_start[queue]; val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr; writeq(val64, &tx_fifo->TxDL_Pointer); val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | TX_FIFO_LAST_LIST); #ifdef NETIF_F_TSO if (mss) val64 |= TX_FIFO_SPECIAL_FUNC; #endif writeq(val64, &tx_fifo->List_Control); mmiowb(); put_off++; put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1; mac_control->fifos[queue].tx_curr_put_info.offset = put_off; /* Avoid "put" pointer going beyond "get" pointer */ if (((put_off + 1) % queue_len) == get_off) { DBG_PRINT(TX_DBG, "No free TxDs for xmit, Put: 0x%x Get:0x%x\n", put_off, get_off); netif_stop_queue(dev); } dev->trans_start = jiffies; spin_unlock_irqrestore(&sp->tx_lock, flags); return 0; } static void s2io_alarm_handle(unsigned long data) { nic_t *sp = (nic_t *)data; alarm_intr_handler(sp); mod_timer(&sp->alarm_timer, jiffies + HZ / 2); } static irqreturn_t s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs) { struct net_device *dev = (struct net_device *) dev_id; nic_t *sp = dev->priv; int i; int ret; mac_info_t *mac_control; struct config_param *config; atomic_inc(&sp->isr_cnt); mac_control = &sp->mac_control; config = &sp->config; DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__); /* If Intr is because of Rx Traffic */ for (i = 0; i < config->rx_ring_num; i++) rx_intr_handler(&mac_control->rings[i]); /* If Intr is because of Tx Traffic */ for (i = 0; i < config->tx_fifo_num; i++) tx_intr_handler(&mac_control->fifos[i]); /* * If the Rx buffer count is below the panic threshold then * reallocate the buffers from the interrupt handler itself, * else schedule a tasklet to reallocate the buffers. */ for (i = 0; i < config->rx_ring_num; i++) { int rxb_size = atomic_read(&sp->rx_bufs_left[i]); int level = rx_buffer_level(sp, rxb_size, i); if ((level == PANIC) && (!TASKLET_IN_USE)) { DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name); DBG_PRINT(INTR_DBG, "PANIC levels\n"); if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) { DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name); DBG_PRINT(ERR_DBG, " in ISR!!\n"); clear_bit(0, (&sp->tasklet_status)); atomic_dec(&sp->isr_cnt); return IRQ_HANDLED; } clear_bit(0, (&sp->tasklet_status)); } else if (level == LOW) { tasklet_schedule(&sp->task); } } atomic_dec(&sp->isr_cnt); return IRQ_HANDLED; } static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs) { ring_info_t *ring = (ring_info_t *)dev_id; nic_t *sp = ring->nic; int rxb_size, level, rng_n; atomic_inc(&sp->isr_cnt); rx_intr_handler(ring); rng_n = ring->ring_no; rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]); level = rx_buffer_level(sp, rxb_size, rng_n); if ((level == PANIC) && (!TASKLET_IN_USE)) { int ret; DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__); DBG_PRINT(INTR_DBG, "PANIC levels\n"); if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) { DBG_PRINT(ERR_DBG, "Out of memory in %s", __FUNCTION__); clear_bit(0, (&sp->tasklet_status)); return IRQ_HANDLED; } clear_bit(0, (&sp->tasklet_status)); } else if (level == LOW) { tasklet_schedule(&sp->task); } atomic_dec(&sp->isr_cnt); return IRQ_HANDLED; } static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs) { fifo_info_t *fifo = (fifo_info_t *)dev_id; nic_t *sp = fifo->nic; atomic_inc(&sp->isr_cnt); tx_intr_handler(fifo); atomic_dec(&sp->isr_cnt); return IRQ_HANDLED; } static void s2io_txpic_intr_handle(nic_t *sp) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64; val64 = readq(&bar0->pic_int_status); if (val64 & PIC_INT_GPIO) { val64 = readq(&bar0->gpio_int_reg); if ((val64 & GPIO_INT_REG_LINK_DOWN) && (val64 & GPIO_INT_REG_LINK_UP)) { val64 |= GPIO_INT_REG_LINK_DOWN; val64 |= GPIO_INT_REG_LINK_UP; writeq(val64, &bar0->gpio_int_reg); goto masking; } if (((sp->last_link_state == LINK_UP) && (val64 & GPIO_INT_REG_LINK_DOWN)) || ((sp->last_link_state == LINK_DOWN) && (val64 & GPIO_INT_REG_LINK_UP))) { val64 = readq(&bar0->gpio_int_mask); val64 |= GPIO_INT_MASK_LINK_DOWN; val64 |= GPIO_INT_MASK_LINK_UP; writeq(val64, &bar0->gpio_int_mask); s2io_set_link((unsigned long)sp); } masking: if (sp->last_link_state == LINK_UP) { /*enable down interrupt */ val64 = readq(&bar0->gpio_int_mask); /* unmasks link down intr */ val64 &= ~GPIO_INT_MASK_LINK_DOWN; /* masks link up intr */ val64 |= GPIO_INT_MASK_LINK_UP; writeq(val64, &bar0->gpio_int_mask); } else { /*enable UP Interrupt */ val64 = readq(&bar0->gpio_int_mask); /* unmasks link up interrupt */ val64 &= ~GPIO_INT_MASK_LINK_UP; /* masks link down interrupt */ val64 |= GPIO_INT_MASK_LINK_DOWN; writeq(val64, &bar0->gpio_int_mask); } } } /** * s2io_isr - ISR handler of the device . * @irq: the irq of the device. * @dev_id: a void pointer to the dev structure of the NIC. * @pt_regs: pointer to the registers pushed on the stack. * Description: This function is the ISR handler of the device. It * identifies the reason for the interrupt and calls the relevant * service routines. As a contongency measure, this ISR allocates the * recv buffers, if their numbers are below the panic value which is * presently set to 25% of the original number of rcv buffers allocated. * Return value: * IRQ_HANDLED: will be returned if IRQ was handled by this routine * IRQ_NONE: will be returned if interrupt is not from our device */ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs) { struct net_device *dev = (struct net_device *) dev_id; nic_t *sp = dev->priv; XENA_dev_config_t __iomem *bar0 = sp->bar0; int i; u64 reason = 0, val64; mac_info_t *mac_control; struct config_param *config; atomic_inc(&sp->isr_cnt); mac_control = &sp->mac_control; config = &sp->config; /* * Identify the cause for interrupt and call the appropriate * interrupt handler. Causes for the interrupt could be; * 1. Rx of packet. * 2. Tx complete. * 3. Link down. * 4. Error in any functional blocks of the NIC. */ reason = readq(&bar0->general_int_status); if (!reason) { /* The interrupt was not raised by Xena. */ atomic_dec(&sp->isr_cnt); return IRQ_NONE; } #ifdef CONFIG_S2IO_NAPI if (reason & GEN_INTR_RXTRAFFIC) { if (netif_rx_schedule_prep(dev)) { en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR, DISABLE_INTRS); __netif_rx_schedule(dev); } } #else /* If Intr is because of Rx Traffic */ if (reason & GEN_INTR_RXTRAFFIC) { /* * rx_traffic_int reg is an R1 register, writing all 1's * will ensure that the actual interrupt causing bit get's * cleared and hence a read can be avoided. */ val64 = 0xFFFFFFFFFFFFFFFFULL; writeq(val64, &bar0->rx_traffic_int); for (i = 0; i < config->rx_ring_num; i++) { rx_intr_handler(&mac_control->rings[i]); } } #endif /* If Intr is because of Tx Traffic */ if (reason & GEN_INTR_TXTRAFFIC) { /* * tx_traffic_int reg is an R1 register, writing all 1's * will ensure that the actual interrupt causing bit get's * cleared and hence a read can be avoided. */ val64 = 0xFFFFFFFFFFFFFFFFULL; writeq(val64, &bar0->tx_traffic_int); for (i = 0; i < config->tx_fifo_num; i++) tx_intr_handler(&mac_control->fifos[i]); } if (reason & GEN_INTR_TXPIC) s2io_txpic_intr_handle(sp); /* * If the Rx buffer count is below the panic threshold then * reallocate the buffers from the interrupt handler itself, * else schedule a tasklet to reallocate the buffers. */ #ifndef CONFIG_S2IO_NAPI for (i = 0; i < config->rx_ring_num; i++) { int ret; int rxb_size = atomic_read(&sp->rx_bufs_left[i]); int level = rx_buffer_level(sp, rxb_size, i); if ((level == PANIC) && (!TASKLET_IN_USE)) { DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name); DBG_PRINT(INTR_DBG, "PANIC levels\n"); if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) { DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name); DBG_PRINT(ERR_DBG, " in ISR!!\n"); clear_bit(0, (&sp->tasklet_status)); atomic_dec(&sp->isr_cnt); return IRQ_HANDLED; } clear_bit(0, (&sp->tasklet_status)); } else if (level == LOW) { tasklet_schedule(&sp->task); } } #endif atomic_dec(&sp->isr_cnt); return IRQ_HANDLED; } /** * s2io_updt_stats - */ static void s2io_updt_stats(nic_t *sp) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64; int cnt = 0; if (atomic_read(&sp->card_state) == CARD_UP) { /* Apprx 30us on a 133 MHz bus */ val64 = SET_UPDT_CLICKS(10) | STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN; writeq(val64, &bar0->stat_cfg); do { udelay(100); val64 = readq(&bar0->stat_cfg); if (!(val64 & BIT(0))) break; cnt++; if (cnt == 5) break; /* Updt failed */ } while(1); } } /** * s2io_get_stats - Updates the device statistics structure. * @dev : pointer to the device structure. * Description: * This function updates the device statistics structure in the s2io_nic * structure and returns a pointer to the same. * Return value: * pointer to the updated net_device_stats structure. */ struct net_device_stats *s2io_get_stats(struct net_device *dev) { nic_t *sp = dev->priv; mac_info_t *mac_control; struct config_param *config; mac_control = &sp->mac_control; config = &sp->config; /* Configure Stats for immediate updt */ s2io_updt_stats(sp); sp->stats.tx_packets = le32_to_cpu(mac_control->stats_info->tmac_frms); sp->stats.tx_errors = le32_to_cpu(mac_control->stats_info->tmac_any_err_frms); sp->stats.rx_errors = le32_to_cpu(mac_control->stats_info->rmac_drop_frms); sp->stats.multicast = le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms); sp->stats.rx_length_errors = le32_to_cpu(mac_control->stats_info->rmac_long_frms); return (&sp->stats); } /** * s2io_set_multicast - entry point for multicast address enable/disable. * @dev : pointer to the device structure * Description: * This function is a driver entry point which gets called by the kernel * whenever multicast addresses must be enabled/disabled. This also gets * called to set/reset promiscuous mode. Depending on the deivce flag, we * determine, if multicast address must be enabled or if promiscuous mode * is to be disabled etc. * Return value: * void. */ static void s2io_set_multicast(struct net_device *dev) { int i, j, prev_cnt; struct dev_mc_list *mclist; nic_t *sp = dev->priv; XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = 0xfeffffffffffULL; u64 dis_addr = 0xffffffffffffULL, mac_addr = 0; void __iomem *add; if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) { /* Enable all Multicast addresses */ writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac), &bar0->rmac_addr_data0_mem); writeq(RMAC_ADDR_DATA1_MEM_MASK(mask), &bar0->rmac_addr_data1_mem); val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET); writeq(val64, &bar0->rmac_addr_cmd_mem); /* Wait till command completes */ wait_for_cmd_complete(sp); sp->m_cast_flg = 1; sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET; } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) { /* Disable all Multicast addresses */ writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), &bar0->rmac_addr_data0_mem); writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0), &bar0->rmac_addr_data1_mem); val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); writeq(val64, &bar0->rmac_addr_cmd_mem); /* Wait till command completes */ wait_for_cmd_complete(sp); sp->m_cast_flg = 0; sp->all_multi_pos = 0; } if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) { /* Put the NIC into promiscuous mode */ add = &bar0->mac_cfg; val64 = readq(&bar0->mac_cfg); val64 |= MAC_CFG_RMAC_PROM_ENABLE; writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) val64, add); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64 >> 32), (add + 4)); val64 = readq(&bar0->mac_cfg); sp->promisc_flg = 1; DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n", dev->name); } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) { /* Remove the NIC from promiscuous mode */ add = &bar0->mac_cfg; val64 = readq(&bar0->mac_cfg); val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) val64, add); writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); writel((u32) (val64 >> 32), (add + 4)); val64 = readq(&bar0->mac_cfg); sp->promisc_flg = 0; DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name); } /* Update individual M_CAST address list */ if ((!sp->m_cast_flg) && dev->mc_count) { if (dev->mc_count > (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) { DBG_PRINT(ERR_DBG, "%s: No more Rx filters ", dev->name); DBG_PRINT(ERR_DBG, "can be added, please enable "); DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n"); return; } prev_cnt = sp->mc_addr_count; sp->mc_addr_count = dev->mc_count; /* Clear out the previous list of Mc in the H/W. */ for (i = 0; i < prev_cnt; i++) { writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), &bar0->rmac_addr_data0_mem); writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), &bar0->rmac_addr_data1_mem); val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | RMAC_ADDR_CMD_MEM_OFFSET (MAC_MC_ADDR_START_OFFSET + i); writeq(val64, &bar0->rmac_addr_cmd_mem); /* Wait for command completes */ if (wait_for_cmd_complete(sp)) { DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name); DBG_PRINT(ERR_DBG, "Multicasts failed\n"); return; } } /* Create the new Rx filter list and update the same in H/W. */ for (i = 0, mclist = dev->mc_list; i < dev->mc_count; i++, mclist = mclist->next) { memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr, ETH_ALEN); for (j = 0; j < ETH_ALEN; j++) { mac_addr |= mclist->dmi_addr[j]; mac_addr <<= 8; } mac_addr >>= 8; writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), &bar0->rmac_addr_data0_mem); writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), &bar0->rmac_addr_data1_mem); val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | RMAC_ADDR_CMD_MEM_OFFSET (i + MAC_MC_ADDR_START_OFFSET); writeq(val64, &bar0->rmac_addr_cmd_mem); /* Wait for command completes */ if (wait_for_cmd_complete(sp)) { DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name); DBG_PRINT(ERR_DBG, "Multicasts failed\n"); return; } } } } /** * s2io_set_mac_addr - Programs the Xframe mac address * @dev : pointer to the device structure. * @addr: a uchar pointer to the new mac address which is to be set. * Description : This procedure will program the Xframe to receive * frames with new Mac Address * Return value: SUCCESS on success and an appropriate (-)ve integer * as defined in errno.h file on failure. */ int s2io_set_mac_addr(struct net_device *dev, u8 * addr) { nic_t *sp = dev->priv; XENA_dev_config_t __iomem *bar0 = sp->bar0; register u64 val64, mac_addr = 0; int i; /* * Set the new MAC address as the new unicast filter and reflect this * change on the device address registered with the OS. It will be * at offset 0. */ for (i = 0; i < ETH_ALEN; i++) { mac_addr <<= 8; mac_addr |= addr[i]; } writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), &bar0->rmac_addr_data0_mem); val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | RMAC_ADDR_CMD_MEM_OFFSET(0); writeq(val64, &bar0->rmac_addr_cmd_mem); /* Wait till command completes */ if (wait_for_cmd_complete(sp)) { DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name); return FAILURE; } return SUCCESS; } /** * s2io_ethtool_sset - Sets different link parameters. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @info: pointer to the structure with parameters given by ethtool to set * link information. * Description: * The function sets different link parameters provided by the user onto * the NIC. * Return value: * 0 on success. */ static int s2io_ethtool_sset(struct net_device *dev, struct ethtool_cmd *info) { nic_t *sp = dev->priv; if ((info->autoneg == AUTONEG_ENABLE) || (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL)) return -EINVAL; else { s2io_close(sp->dev); s2io_open(sp->dev); } return 0; } /** * s2io_ethtol_gset - Return link specific information. * @sp : private member of the device structure, pointer to the * s2io_nic structure. * @info : pointer to the structure with parameters given by ethtool * to return link information. * Description: * Returns link specific information like speed, duplex etc.. to ethtool. * Return value : * return 0 on success. */ static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info) { nic_t *sp = dev->priv; info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); info->port = PORT_FIBRE; /* info->transceiver?? TODO */ if (netif_carrier_ok(sp->dev)) { info->speed = 10000; info->duplex = DUPLEX_FULL; } else { info->speed = -1; info->duplex = -1; } info->autoneg = AUTONEG_DISABLE; return 0; } /** * s2io_ethtool_gdrvinfo - Returns driver specific information. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @info : pointer to the structure with parameters given by ethtool to * return driver information. * Description: * Returns driver specefic information like name, version etc.. to ethtool. * Return value: * void */ static void s2io_ethtool_gdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) { nic_t *sp = dev->priv; strncpy(info->driver, s2io_driver_name, sizeof(info->driver)); strncpy(info->version, s2io_driver_version, sizeof(info->version)); strncpy(info->fw_version, "", sizeof(info->fw_version)); strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info)); info->regdump_len = XENA_REG_SPACE; info->eedump_len = XENA_EEPROM_SPACE; info->testinfo_len = S2IO_TEST_LEN; info->n_stats = S2IO_STAT_LEN; } /** * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer. * @sp: private member of the device structure, which is a pointer to the * s2io_nic structure. * @regs : pointer to the structure with parameters given by ethtool for * dumping the registers. * @reg_space: The input argumnet into which all the registers are dumped. * Description: * Dumps the entire register space of xFrame NIC into the user given * buffer area. * Return value : * void . */ static void s2io_ethtool_gregs(struct net_device *dev, struct ethtool_regs *regs, void *space) { int i; u64 reg; u8 *reg_space = (u8 *) space; nic_t *sp = dev->priv; regs->len = XENA_REG_SPACE; regs->version = sp->pdev->subsystem_device; for (i = 0; i < regs->len; i += 8) { reg = readq(sp->bar0 + i); memcpy((reg_space + i), &reg, 8); } } /** * s2io_phy_id - timer function that alternates adapter LED. * @data : address of the private member of the device structure, which * is a pointer to the s2io_nic structure, provided as an u32. * Description: This is actually the timer function that alternates the * adapter LED bit of the adapter control bit to set/reset every time on * invocation. The timer is set for 1/2 a second, hence tha NIC blinks * once every second. */ static void s2io_phy_id(unsigned long data) { nic_t *sp = (nic_t *) data; XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64 = 0; u16 subid; subid = sp->pdev->subsystem_device; if ((sp->device_type == XFRAME_II_DEVICE) || ((subid & 0xFF) >= 0x07)) { val64 = readq(&bar0->gpio_control); val64 ^= GPIO_CTRL_GPIO_0; writeq(val64, &bar0->gpio_control); } else { val64 = readq(&bar0->adapter_control); val64 ^= ADAPTER_LED_ON; writeq(val64, &bar0->adapter_control); } mod_timer(&sp->id_timer, jiffies + HZ / 2); } /** * s2io_ethtool_idnic - To physically identify the nic on the system. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @id : pointer to the structure with identification parameters given by * ethtool. * Description: Used to physically identify the NIC on the system. * The Link LED will blink for a time specified by the user for * identification. * NOTE: The Link has to be Up to be able to blink the LED. Hence * identification is possible only if it's link is up. * Return value: * int , returns 0 on success */ static int s2io_ethtool_idnic(struct net_device *dev, u32 data) { u64 val64 = 0, last_gpio_ctrl_val; nic_t *sp = dev->priv; XENA_dev_config_t __iomem *bar0 = sp->bar0; u16 subid; subid = sp->pdev->subsystem_device; last_gpio_ctrl_val = readq(&bar0->gpio_control); if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) { val64 = readq(&bar0->adapter_control); if (!(val64 & ADAPTER_CNTL_EN)) { printk(KERN_ERR "Adapter Link down, cannot blink LED\n"); return -EFAULT; } } if (sp->id_timer.function == NULL) { init_timer(&sp->id_timer); sp->id_timer.function = s2io_phy_id; sp->id_timer.data = (unsigned long) sp; } mod_timer(&sp->id_timer, jiffies); if (data) msleep_interruptible(data * HZ); else msleep_interruptible(MAX_FLICKER_TIME); del_timer_sync(&sp->id_timer); if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) { writeq(last_gpio_ctrl_val, &bar0->gpio_control); last_gpio_ctrl_val = readq(&bar0->gpio_control); } return 0; } /** * s2io_ethtool_getpause_data -Pause frame frame generation and reception. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @ep : pointer to the structure with pause parameters given by ethtool. * Description: * Returns the Pause frame generation and reception capability of the NIC. * Return value: * void */ static void s2io_ethtool_getpause_data(struct net_device *dev, struct ethtool_pauseparam *ep) { u64 val64; nic_t *sp = dev->priv; XENA_dev_config_t __iomem *bar0 = sp->bar0; val64 = readq(&bar0->rmac_pause_cfg); if (val64 & RMAC_PAUSE_GEN_ENABLE) ep->tx_pause = TRUE; if (val64 & RMAC_PAUSE_RX_ENABLE) ep->rx_pause = TRUE; ep->autoneg = FALSE; } /** * s2io_ethtool_setpause_data - set/reset pause frame generation. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @ep : pointer to the structure with pause parameters given by ethtool. * Description: * It can be used to set or reset Pause frame generation or reception * support of the NIC. * Return value: * int, returns 0 on Success */ static int s2io_ethtool_setpause_data(struct net_device *dev, struct ethtool_pauseparam *ep) { u64 val64; nic_t *sp = dev->priv; XENA_dev_config_t __iomem *bar0 = sp->bar0; val64 = readq(&bar0->rmac_pause_cfg); if (ep->tx_pause) val64 |= RMAC_PAUSE_GEN_ENABLE; else val64 &= ~RMAC_PAUSE_GEN_ENABLE; if (ep->rx_pause) val64 |= RMAC_PAUSE_RX_ENABLE; else val64 &= ~RMAC_PAUSE_RX_ENABLE; writeq(val64, &bar0->rmac_pause_cfg); return 0; } /** * read_eeprom - reads 4 bytes of data from user given offset. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @off : offset at which the data must be written * @data : Its an output parameter where the data read at the given * offset is stored. * Description: * Will read 4 bytes of data from the user given offset and return the * read data. * NOTE: Will allow to read only part of the EEPROM visible through the * I2C bus. * Return value: * -1 on failure and 0 on success. */ #define S2IO_DEV_ID 5 static int read_eeprom(nic_t * sp, int off, u64 * data) { int ret = -1; u32 exit_cnt = 0; u64 val64; XENA_dev_config_t __iomem *bar0 = sp->bar0; if (sp->device_type == XFRAME_I_DEVICE) { val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ | I2C_CONTROL_CNTL_START; SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); while (exit_cnt < 5) { val64 = readq(&bar0->i2c_control); if (I2C_CONTROL_CNTL_END(val64)) { *data = I2C_CONTROL_GET_DATA(val64); ret = 0; break; } msleep(50); exit_cnt++; } } if (sp->device_type == XFRAME_II_DEVICE) { val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | SPI_CONTROL_BYTECNT(0x3) | SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off); SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); val64 |= SPI_CONTROL_REQ; SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); while (exit_cnt < 5) { val64 = readq(&bar0->spi_control); if (val64 & SPI_CONTROL_NACK) { ret = 1; break; } else if (val64 & SPI_CONTROL_DONE) { *data = readq(&bar0->spi_data); *data &= 0xffffff; ret = 0; break; } msleep(50); exit_cnt++; } } return ret; } /** * write_eeprom - actually writes the relevant part of the data value. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @off : offset at which the data must be written * @data : The data that is to be written * @cnt : Number of bytes of the data that are actually to be written into * the Eeprom. (max of 3) * Description: * Actually writes the relevant part of the data value into the Eeprom * through the I2C bus. * Return value: * 0 on success, -1 on failure. */ static int write_eeprom(nic_t * sp, int off, u64 data, int cnt) { int exit_cnt = 0, ret = -1; u64 val64; XENA_dev_config_t __iomem *bar0 = sp->bar0; if (sp->device_type == XFRAME_I_DEVICE) { val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) | I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) | I2C_CONTROL_CNTL_START; SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); while (exit_cnt < 5) { val64 = readq(&bar0->i2c_control); if (I2C_CONTROL_CNTL_END(val64)) { if (!(val64 & I2C_CONTROL_NACK)) ret = 0; break; } msleep(50); exit_cnt++; } } if (sp->device_type == XFRAME_II_DEVICE) { int write_cnt = (cnt == 8) ? 0 : cnt; writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data); val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | SPI_CONTROL_BYTECNT(write_cnt) | SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off); SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); val64 |= SPI_CONTROL_REQ; SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); while (exit_cnt < 5) { val64 = readq(&bar0->spi_control); if (val64 & SPI_CONTROL_NACK) { ret = 1; break; } else if (val64 & SPI_CONTROL_DONE) { ret = 0; break; } msleep(50); exit_cnt++; } } return ret; } /** * s2io_ethtool_geeprom - reads the value stored in the Eeprom. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @eeprom : pointer to the user level structure provided by ethtool, * containing all relevant information. * @data_buf : user defined value to be written into Eeprom. * Description: Reads the values stored in the Eeprom at given offset * for a given length. Stores these values int the input argument data * buffer 'data_buf' and returns these to the caller (ethtool.) * Return value: * int 0 on success */ static int s2io_ethtool_geeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 * data_buf) { u32 i, valid; u64 data; nic_t *sp = dev->priv; eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16); if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE)) eeprom->len = XENA_EEPROM_SPACE - eeprom->offset; for (i = 0; i < eeprom->len; i += 4) { if (read_eeprom(sp, (eeprom->offset + i), &data)) { DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n"); return -EFAULT; } valid = INV(data); memcpy((data_buf + i), &valid, 4); } return 0; } /** * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @eeprom : pointer to the user level structure provided by ethtool, * containing all relevant information. * @data_buf ; user defined value to be written into Eeprom. * Description: * Tries to write the user provided value in the Eeprom, at the offset * given by the user. * Return value: * 0 on success, -EFAULT on failure. */ static int s2io_ethtool_seeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 * data_buf) { int len = eeprom->len, cnt = 0; u64 valid = 0, data; nic_t *sp = dev->priv; if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) { DBG_PRINT(ERR_DBG, "ETHTOOL_WRITE_EEPROM Err: Magic value "); DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n", eeprom->magic); return -EFAULT; } while (len) { data = (u32) data_buf[cnt] & 0x000000FF; if (data) { valid = (u32) (data << 24); } else valid = data; if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) { DBG_PRINT(ERR_DBG, "ETHTOOL_WRITE_EEPROM Err: Cannot "); DBG_PRINT(ERR_DBG, "write into the specified offset\n"); return -EFAULT; } cnt++; len--; } return 0; } /** * s2io_register_test - reads and writes into all clock domains. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @data : variable that returns the result of each of the test conducted b * by the driver. * Description: * Read and write into all clock domains. The NIC has 3 clock domains, * see that registers in all the three regions are accessible. * Return value: * 0 on success. */ static int s2io_register_test(nic_t * sp, uint64_t * data) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64 = 0, exp_val; int fail = 0; val64 = readq(&bar0->pif_rd_swapper_fb); if (val64 != 0x123456789abcdefULL) { fail = 1; DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n"); } val64 = readq(&bar0->rmac_pause_cfg); if (val64 != 0xc000ffff00000000ULL) { fail = 1; DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n"); } val64 = readq(&bar0->rx_queue_cfg); if (sp->device_type == XFRAME_II_DEVICE) exp_val = 0x0404040404040404ULL; else exp_val = 0x0808080808080808ULL; if (val64 != exp_val) { fail = 1; DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n"); } val64 = readq(&bar0->xgxs_efifo_cfg); if (val64 != 0x000000001923141EULL) { fail = 1; DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n"); } val64 = 0x5A5A5A5A5A5A5A5AULL; writeq(val64, &bar0->xmsi_data); val64 = readq(&bar0->xmsi_data); if (val64 != 0x5A5A5A5A5A5A5A5AULL) { fail = 1; DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n"); } val64 = 0xA5A5A5A5A5A5A5A5ULL; writeq(val64, &bar0->xmsi_data); val64 = readq(&bar0->xmsi_data); if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { fail = 1; DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n"); } *data = fail; return fail; } /** * s2io_eeprom_test - to verify that EEprom in the xena can be programmed. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @data:variable that returns the result of each of the test conducted by * the driver. * Description: * Verify that EEPROM in the xena can be programmed using I2C_CONTROL * register. * Return value: * 0 on success. */ static int s2io_eeprom_test(nic_t * sp, uint64_t * data) { int fail = 0; u64 ret_data, org_4F0, org_7F0; u8 saved_4F0 = 0, saved_7F0 = 0; struct net_device *dev = sp->dev; /* Test Write Error at offset 0 */ /* Note that SPI interface allows write access to all areas * of EEPROM. Hence doing all negative testing only for Xframe I. */ if (sp->device_type == XFRAME_I_DEVICE) if (!write_eeprom(sp, 0, 0, 3)) fail = 1; /* Save current values at offsets 0x4F0 and 0x7F0 */ if (!read_eeprom(sp, 0x4F0, &org_4F0)) saved_4F0 = 1; if (!read_eeprom(sp, 0x7F0, &org_7F0)) saved_7F0 = 1; /* Test Write at offset 4f0 */ if (write_eeprom(sp, 0x4F0, 0x012345, 3)) fail = 1; if (read_eeprom(sp, 0x4F0, &ret_data)) fail = 1; if (ret_data != 0x012345) { DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data); fail = 1; } /* Reset the EEPROM data go FFFF */ write_eeprom(sp, 0x4F0, 0xFFFFFF, 3); /* Test Write Request Error at offset 0x7c */ if (sp->device_type == XFRAME_I_DEVICE) if (!write_eeprom(sp, 0x07C, 0, 3)) fail = 1; /* Test Write Request at offset 0x7f0 */ if (write_eeprom(sp, 0x7F0, 0x012345, 3)) fail = 1; if (read_eeprom(sp, 0x7F0, &ret_data)) fail = 1; if (ret_data != 0x012345) { DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. Data written %llx Data read %llx\n", dev->name, (u64)0x12345, ret_data); fail = 1; } /* Reset the EEPROM data go FFFF */ write_eeprom(sp, 0x7F0, 0xFFFFFF, 3); if (sp->device_type == XFRAME_I_DEVICE) { /* Test Write Error at offset 0x80 */ if (!write_eeprom(sp, 0x080, 0, 3)) fail = 1; /* Test Write Error at offset 0xfc */ if (!write_eeprom(sp, 0x0FC, 0, 3)) fail = 1; /* Test Write Error at offset 0x100 */ if (!write_eeprom(sp, 0x100, 0, 3)) fail = 1; /* Test Write Error at offset 4ec */ if (!write_eeprom(sp, 0x4EC, 0, 3)) fail = 1; } /* Restore values at offsets 0x4F0 and 0x7F0 */ if (saved_4F0) write_eeprom(sp, 0x4F0, org_4F0, 3); if (saved_7F0) write_eeprom(sp, 0x7F0, org_7F0, 3); *data = fail; return fail; } /** * s2io_bist_test - invokes the MemBist test of the card . * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @data:variable that returns the result of each of the test conducted by * the driver. * Description: * This invokes the MemBist test of the card. We give around * 2 secs time for the Test to complete. If it's still not complete * within this peiod, we consider that the test failed. * Return value: * 0 on success and -1 on failure. */ static int s2io_bist_test(nic_t * sp, uint64_t * data) { u8 bist = 0; int cnt = 0, ret = -1; pci_read_config_byte(sp->pdev, PCI_BIST, &bist); bist |= PCI_BIST_START; pci_write_config_word(sp->pdev, PCI_BIST, bist); while (cnt < 20) { pci_read_config_byte(sp->pdev, PCI_BIST, &bist); if (!(bist & PCI_BIST_START)) { *data = (bist & PCI_BIST_CODE_MASK); ret = 0; break; } msleep(100); cnt++; } return ret; } /** * s2io-link_test - verifies the link state of the nic * @sp ; private member of the device structure, which is a pointer to the * s2io_nic structure. * @data: variable that returns the result of each of the test conducted by * the driver. * Description: * The function verifies the link state of the NIC and updates the input * argument 'data' appropriately. * Return value: * 0 on success. */ static int s2io_link_test(nic_t * sp, uint64_t * data) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64; val64 = readq(&bar0->adapter_status); if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT) *data = 1; return 0; } /** * s2io_rldram_test - offline test for access to the RldRam chip on the NIC * @sp - private member of the device structure, which is a pointer to the * s2io_nic structure. * @data - variable that returns the result of each of the test * conducted by the driver. * Description: * This is one of the offline test that tests the read and write * access to the RldRam chip on the NIC. * Return value: * 0 on success. */ static int s2io_rldram_test(nic_t * sp, uint64_t * data) { XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64; int cnt, iteration = 0, test_fail = 0; val64 = readq(&bar0->adapter_control); val64 &= ~ADAPTER_ECC_EN; writeq(val64, &bar0->adapter_control); val64 = readq(&bar0->mc_rldram_test_ctrl); val64 |= MC_RLDRAM_TEST_MODE; SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); val64 = readq(&bar0->mc_rldram_mrs); val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); val64 |= MC_RLDRAM_MRS_ENABLE; SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); while (iteration < 2) { val64 = 0x55555555aaaa0000ULL; if (iteration == 1) { val64 ^= 0xFFFFFFFFFFFF0000ULL; } writeq(val64, &bar0->mc_rldram_test_d0); val64 = 0xaaaa5a5555550000ULL; if (iteration == 1) { val64 ^= 0xFFFFFFFFFFFF0000ULL; } writeq(val64, &bar0->mc_rldram_test_d1); val64 = 0x55aaaaaaaa5a0000ULL; if (iteration == 1) { val64 ^= 0xFFFFFFFFFFFF0000ULL; } writeq(val64, &bar0->mc_rldram_test_d2); val64 = (u64) (0x0000003ffffe0100ULL); writeq(val64, &bar0->mc_rldram_test_add); val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE | MC_RLDRAM_TEST_GO; SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); for (cnt = 0; cnt < 5; cnt++) { val64 = readq(&bar0->mc_rldram_test_ctrl); if (val64 & MC_RLDRAM_TEST_DONE) break; msleep(200); } if (cnt == 5) break; val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO; SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); for (cnt = 0; cnt < 5; cnt++) { val64 = readq(&bar0->mc_rldram_test_ctrl); if (val64 & MC_RLDRAM_TEST_DONE) break; msleep(500); } if (cnt == 5) break; val64 = readq(&bar0->mc_rldram_test_ctrl); if (!(val64 & MC_RLDRAM_TEST_PASS)) test_fail = 1; iteration++; } *data = test_fail; /* Bring the adapter out of test mode */ SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF); return test_fail; } /** * s2io_ethtool_test - conducts 6 tsets to determine the health of card. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. * @ethtest : pointer to a ethtool command specific structure that will be * returned to the user. * @data : variable that returns the result of each of the test * conducted by the driver. * Description: * This function conducts 6 tests ( 4 offline and 2 online) to determine * the health of the card. * Return value: * void */ static void s2io_ethtool_test(struct net_device *dev, struct ethtool_test *ethtest, uint64_t * data) { nic_t *sp = dev->priv; int orig_state = netif_running(sp->dev); if (ethtest->flags == ETH_TEST_FL_OFFLINE) { /* Offline Tests. */ if (orig_state) s2io_close(sp->dev); if (s2io_register_test(sp, &data[0])) ethtest->flags |= ETH_TEST_FL_FAILED; s2io_reset(sp); if (s2io_rldram_test(sp, &data[3])) ethtest->flags |= ETH_TEST_FL_FAILED; s2io_reset(sp); if (s2io_eeprom_test(sp, &data[1])) ethtest->flags |= ETH_TEST_FL_FAILED; if (s2io_bist_test(sp, &data[4])) ethtest->flags |= ETH_TEST_FL_FAILED; if (orig_state) s2io_open(sp->dev); data[2] = 0; } else { /* Online Tests. */ if (!orig_state) { DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n", dev->name); data[0] = -1; data[1] = -1; data[2] = -1; data[3] = -1; data[4] = -1; } if (s2io_link_test(sp, &data[2])) ethtest->flags |= ETH_TEST_FL_FAILED; data[0] = 0; data[1] = 0; data[3] = 0; data[4] = 0; } } static void s2io_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 * tmp_stats) { int i = 0; nic_t *sp = dev->priv; StatInfo_t *stat_info = sp->mac_control.stats_info; s2io_updt_stats(sp); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 | le32_to_cpu(stat_info->tmac_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 | le32_to_cpu(stat_info->tmac_data_octets); tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 | le32_to_cpu(stat_info->tmac_mcst_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 | le32_to_cpu(stat_info->tmac_bcst_frms); tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 | le32_to_cpu(stat_info->tmac_any_err_frms); tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 | le32_to_cpu(stat_info->tmac_vld_ip); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 | le32_to_cpu(stat_info->tmac_drop_ip); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 | le32_to_cpu(stat_info->tmac_icmp); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 | le32_to_cpu(stat_info->tmac_rst_tcp); tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 | le32_to_cpu(stat_info->tmac_udp); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_vld_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 | le32_to_cpu(stat_info->rmac_data_octets); tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms); tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_vld_mcst_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_vld_bcst_frms); tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms); tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms); tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_discarded_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_usized_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_osized_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_frag_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 | le32_to_cpu(stat_info->rmac_jabber_frms); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 | le32_to_cpu(stat_info->rmac_ip); tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets); tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 | le32_to_cpu(stat_info->rmac_drop_ip); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 | le32_to_cpu(stat_info->rmac_icmp); tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 | le32_to_cpu(stat_info->rmac_udp); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 | le32_to_cpu(stat_info->rmac_err_drp_udp); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 | le32_to_cpu(stat_info->rmac_pause_cnt); tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 | le32_to_cpu(stat_info->rmac_accepted_ip); tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp); tmp_stats[i++] = 0; tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs; tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs; } int s2io_ethtool_get_regs_len(struct net_device *dev) { return (XENA_REG_SPACE); } u32 s2io_ethtool_get_rx_csum(struct net_device * dev) { nic_t *sp = dev->priv; return (sp->rx_csum); } int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data) { nic_t *sp = dev->priv; if (data) sp->rx_csum = 1; else sp->rx_csum = 0; return 0; } int s2io_get_eeprom_len(struct net_device *dev) { return (XENA_EEPROM_SPACE); } int s2io_ethtool_self_test_count(struct net_device *dev) { return (S2IO_TEST_LEN); } void s2io_ethtool_get_strings(struct net_device *dev, u32 stringset, u8 * data) { switch (stringset) { case ETH_SS_TEST: memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN); break; case ETH_SS_STATS: memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys)); } } static int s2io_ethtool_get_stats_count(struct net_device *dev) { return (S2IO_STAT_LEN); } int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) { if (data) dev->features |= NETIF_F_IP_CSUM; else dev->features &= ~NETIF_F_IP_CSUM; return 0; } static struct ethtool_ops netdev_ethtool_ops = { .get_settings = s2io_ethtool_gset, .set_settings = s2io_ethtool_sset, .get_drvinfo = s2io_ethtool_gdrvinfo, .get_regs_len = s2io_ethtool_get_regs_len, .get_regs = s2io_ethtool_gregs, .get_link = ethtool_op_get_link, .get_eeprom_len = s2io_get_eeprom_len, .get_eeprom = s2io_ethtool_geeprom, .set_eeprom = s2io_ethtool_seeprom, .get_pauseparam = s2io_ethtool_getpause_data, .set_pauseparam = s2io_ethtool_setpause_data, .get_rx_csum = s2io_ethtool_get_rx_csum, .set_rx_csum = s2io_ethtool_set_rx_csum, .get_tx_csum = ethtool_op_get_tx_csum, .set_tx_csum = s2io_ethtool_op_set_tx_csum, .get_sg = ethtool_op_get_sg, .set_sg = ethtool_op_set_sg, #ifdef NETIF_F_TSO .get_tso = ethtool_op_get_tso, .set_tso = ethtool_op_set_tso, #endif .self_test_count = s2io_ethtool_self_test_count, .self_test = s2io_ethtool_test, .get_strings = s2io_ethtool_get_strings, .phys_id = s2io_ethtool_idnic, .get_stats_count = s2io_ethtool_get_stats_count, .get_ethtool_stats = s2io_get_ethtool_stats }; /** * s2io_ioctl - Entry point for the Ioctl * @dev : Device pointer. * @ifr : An IOCTL specefic structure, that can contain a pointer to * a proprietary structure used to pass information to the driver. * @cmd : This is used to distinguish between the different commands that * can be passed to the IOCTL functions. * Description: * Currently there are no special functionality supported in IOCTL, hence * function always return EOPNOTSUPPORTED */ int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { return -EOPNOTSUPP; } /** * s2io_change_mtu - entry point to change MTU size for the device. * @dev : device pointer. * @new_mtu : the new MTU size for the device. * Description: A driver entry point to change MTU size for the device. * Before changing the MTU the device must be stopped. * Return value: * 0 on success and an appropriate (-)ve integer as defined in errno.h * file on failure. */ int s2io_change_mtu(struct net_device *dev, int new_mtu) { nic_t *sp = dev->priv; if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) { DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name); return -EPERM; } dev->mtu = new_mtu; if (netif_running(dev)) { s2io_card_down(sp); netif_stop_queue(dev); if (s2io_card_up(sp)) { DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", __FUNCTION__); } if (netif_queue_stopped(dev)) netif_wake_queue(dev); } else { /* Device is down */ XENA_dev_config_t __iomem *bar0 = sp->bar0; u64 val64 = new_mtu; writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); } return 0; } /** * s2io_tasklet - Bottom half of the ISR. * @dev_adr : address of the device structure in dma_addr_t format. * Description: * This is the tasklet or the bottom half of the ISR. This is * an extension of the ISR which is scheduled by the scheduler to be run * when the load on the CPU is low. All low priority tasks of the ISR can * be pushed into the tasklet. For now the tasklet is used only to * replenish the Rx buffers in the Rx buffer descriptors. * Return value: * void. */ static void s2io_tasklet(unsigned long dev_addr) { struct net_device *dev = (struct net_device *) dev_addr; nic_t *sp = dev->priv; int i, ret; mac_info_t *mac_control; struct config_param *config; mac_control = &sp->mac_control; config = &sp->config; if (!TASKLET_IN_USE) { for (i = 0; i < config->rx_ring_num; i++) { ret = fill_rx_buffers(sp, i); if (ret == -ENOMEM) { DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name); DBG_PRINT(ERR_DBG, "memory in tasklet\n"); break; } else if (ret == -EFILL) { DBG_PRINT(ERR_DBG, "%s: Rx Ring %d is full\n", dev->name, i); break; } } clear_bit(0, (&sp->tasklet_status)); } } /** * s2io_set_link - Set the LInk status * @data: long pointer to device private structue * Description: Sets the link status for the adapter */ static void s2io_set_link(unsigned long data) { nic_t *nic = (nic_t *) data; struct net_device *dev = nic->dev; XENA_dev_config_t __iomem *bar0 = nic->bar0; register u64 val64; u16 subid; if (test_and_set_bit(0, &(nic->link_state))) { /* The card is being reset, no point doing anything */ return; } subid = nic->pdev->subsystem_device; if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) { /* * Allow a small delay for the NICs self initiated * cleanup to complete. */ msleep(100); } val64 = readq(&bar0->adapter_status); if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) { if (LINK_IS_UP(val64)) { val64 = readq(&bar0->adapter_control); val64 |= ADAPTER_CNTL_EN; writeq(val64, &bar0->adapter_control); if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, subid)) { val64 = readq(&bar0->gpio_control); val64 |= GPIO_CTRL_GPIO_0; writeq(val64, &bar0->gpio_control); val64 = readq(&bar0->gpio_control); } else { val64 |= ADAPTER_LED_ON; writeq(val64, &bar0->adapter_control); } if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) { val64 = readq(&bar0->adapter_status); if (!LINK_IS_UP(val64)) { DBG_PRINT(ERR_DBG, "%s:", dev->name); DBG_PRINT(ERR_DBG, " Link down"); DBG_PRINT(ERR_DBG, "after "); DBG_PRINT(ERR_DBG, "enabling "); DBG_PRINT(ERR_DBG, "device \n"); } } if (nic->device_enabled_once == FALSE) { nic->device_enabled_once = TRUE; } s2io_link(nic, LINK_UP); } else { if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, subid)) { val64 = readq(&bar0->gpio_control); val64 &= ~GPIO_CTRL_GPIO_0; writeq(val64, &bar0->gpio_control); val64 = readq(&bar0->gpio_control); } s2io_link(nic, LINK_DOWN); } } else { /* NIC is not Quiescent. */ DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);