diff options
| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-31 23:41:53 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-31 23:41:53 -0400 |
| commit | d6dd9e93c7531fa31370e27d053a3940d8d662fb (patch) | |
| tree | afab573031b3f0b9bbe5e417a890f7cae09a7224 | |
| parent | dd9cd6d4351076c78bb8c0f9146d1904b481fdbb (diff) | |
| parent | b4b2917cc8babe8eaf4bc133bca31b11ed7dac13 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (50 commits)
[MIPS] Add smp_call_function_single()
[MIPS] thread_info.h: kmalloc + memset conversion to kzalloc
[MIPS] Kexec: Fix several 64-bit bugs.
[MIPS] Kexec: Fix several warnings.
[MIPS] DDB5477: Remove support
[MIPS] Fulong: Remove unneeded header file
[MIPS] Cobalt: Enable UART on RaQ1
[MIPS] Remove unused GROUP_TOSHIBA_NAMES
[MIPS] remove some duplicate includes
[MIPS] Oprofile: Fix rm9000 performance counter handler
[MIPS] Use -Werror on subdirectories which build cleanly.
[MIPS] Yosemite: Fix warning.
[MIPS] PMON: Fix cpustart declaration.
[MIPS] Yosemite: Only build ll_ht_smp_irq_handler() if HYPERTRANSPORT.
[MIPS] Yosemite: Fix build error due to undeclared titan_mailbox_irq().
[MIPS] Yosemite: Don't declare titan_mailbox_irq() as asmlinkage.
[MIPS] Yosemite: Fix warnings in i2c-yoesmite by deleting the unused code.
[MIPS] Delete unused arch/mips/gt64120/common/
[MIPS] Fix build warning in unaligned load/store emulator.
[MIPS] IP32: Don't ignore request_irq's return value.
...
175 files changed, 836 insertions, 6779 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 1e3aeccd7322..3b404b7dfa39 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
| @@ -15,29 +15,6 @@ choice | |||
| 15 | prompt "System type" | 15 | prompt "System type" |
| 16 | default SGI_IP22 | 16 | default SGI_IP22 |
| 17 | 17 | ||
| 18 | config LEMOTE_FULONG | ||
| 19 | bool "Lemote Fulong mini-PC" | ||
| 20 | select ARCH_SPARSEMEM_ENABLE | ||
| 21 | select SYS_HAS_CPU_LOONGSON2 | ||
| 22 | select DMA_NONCOHERENT | ||
| 23 | select BOOT_ELF32 | ||
| 24 | select BOARD_SCACHE | ||
| 25 | select HAVE_STD_PC_SERIAL_PORT | ||
| 26 | select HW_HAS_PCI | ||
| 27 | select I8259 | ||
| 28 | select ISA | ||
| 29 | select IRQ_CPU | ||
| 30 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 31 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 32 | select SYS_SUPPORTS_LITTLE_ENDIAN | ||
| 33 | select SYS_SUPPORTS_HIGHMEM | ||
| 34 | select SYS_HAS_EARLY_PRINTK | ||
| 35 | select GENERIC_HARDIRQS_NO__DO_IRQ | ||
| 36 | select CPU_HAS_WB | ||
| 37 | help | ||
| 38 | Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and | ||
| 39 | an FPGA northbridge | ||
| 40 | |||
| 41 | config MACH_ALCHEMY | 18 | config MACH_ALCHEMY |
| 42 | bool "Alchemy processor based machines" | 19 | bool "Alchemy processor based machines" |
| 43 | 20 | ||
| @@ -131,6 +108,29 @@ config MACH_JAZZ | |||
| 131 | Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and | 108 | Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and |
| 132 | Olivetti M700-10 workstations. | 109 | Olivetti M700-10 workstations. |
| 133 | 110 | ||
| 111 | config LEMOTE_FULONG | ||
| 112 | bool "Lemote Fulong mini-PC" | ||
| 113 | select ARCH_SPARSEMEM_ENABLE | ||
| 114 | select SYS_HAS_CPU_LOONGSON2 | ||
| 115 | select DMA_NONCOHERENT | ||
| 116 | select BOOT_ELF32 | ||
| 117 | select BOARD_SCACHE | ||
| 118 | select HAVE_STD_PC_SERIAL_PORT | ||
| 119 | select HW_HAS_PCI | ||
| 120 | select I8259 | ||
| 121 | select ISA | ||
| 122 | select IRQ_CPU | ||
| 123 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 124 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 125 | select SYS_SUPPORTS_LITTLE_ENDIAN | ||
| 126 | select SYS_SUPPORTS_HIGHMEM | ||
| 127 | select SYS_HAS_EARLY_PRINTK | ||
| 128 | select GENERIC_HARDIRQS_NO__DO_IRQ | ||
| 129 | select CPU_HAS_WB | ||
| 130 | help | ||
| 131 | Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and | ||
| 132 | an FPGA northbridge | ||
| 133 | |||
| 134 | config MIPS_ATLAS | 134 | config MIPS_ATLAS |
| 135 | bool "MIPS Atlas board" | 135 | bool "MIPS Atlas board" |
| 136 | select BOOT_ELF32 | 136 | select BOOT_ELF32 |
| @@ -210,27 +210,6 @@ config MIPS_SEAD | |||
| 210 | This enables support for the MIPS Technologies SEAD evaluation | 210 | This enables support for the MIPS Technologies SEAD evaluation |
| 211 | board. | 211 | board. |
| 212 | 212 | ||
| 213 | config WR_PPMC | ||
| 214 | bool "Wind River PPMC board" | ||
| 215 | select IRQ_CPU | ||
| 216 | select BOOT_ELF32 | ||
| 217 | select DMA_NONCOHERENT | ||
| 218 | select HW_HAS_PCI | ||
| 219 | select PCI_GT64XXX_PCI0 | ||
| 220 | select SWAP_IO_SPACE | ||
| 221 | select SYS_HAS_CPU_MIPS32_R1 | ||
| 222 | select SYS_HAS_CPU_MIPS32_R2 | ||
| 223 | select SYS_HAS_CPU_MIPS64_R1 | ||
| 224 | select SYS_HAS_CPU_NEVADA | ||
| 225 | select SYS_HAS_CPU_RM7000 | ||
| 226 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 227 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 228 | select SYS_SUPPORTS_BIG_ENDIAN | ||
| 229 | select SYS_SUPPORTS_LITTLE_ENDIAN | ||
| 230 | help | ||
| 231 | This enables support for the Wind River MIPS32 4KC PPMC evaluation | ||
| 232 | board, which is based on GT64120 bridge chip. | ||
| 233 | |||
| 234 | config MIPS_SIM | 213 | config MIPS_SIM |
| 235 | bool 'MIPS simulator (MIPSsim)' | 214 | bool 'MIPS simulator (MIPSsim)' |
| 236 | select DMA_NONCOHERENT | 215 | select DMA_NONCOHERENT |
| @@ -248,23 +227,24 @@ config MIPS_SIM | |||
| 248 | This option enables support for MIPS Technologies MIPSsim software | 227 | This option enables support for MIPS Technologies MIPSsim software |
| 249 | emulator. | 228 | emulator. |
| 250 | 229 | ||
| 251 | config MOMENCO_OCELOT | 230 | config MARKEINS |
| 252 | bool "Momentum Ocelot board" | 231 | bool "NEC EMMA2RH Mark-eins" |
| 253 | select DMA_NONCOHERENT | 232 | select DMA_NONCOHERENT |
| 254 | select HW_HAS_PCI | 233 | select HW_HAS_PCI |
| 255 | select IRQ_CPU | 234 | select IRQ_CPU |
| 256 | select IRQ_CPU_RM7K | ||
| 257 | select PCI_GT64XXX_PCI0 | ||
| 258 | select RM7000_CPU_SCACHE | ||
| 259 | select SWAP_IO_SPACE | 235 | select SWAP_IO_SPACE |
| 260 | select SYS_HAS_CPU_RM7000 | ||
| 261 | select SYS_SUPPORTS_32BIT_KERNEL | 236 | select SYS_SUPPORTS_32BIT_KERNEL |
| 262 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 263 | select SYS_SUPPORTS_BIG_ENDIAN | 237 | select SYS_SUPPORTS_BIG_ENDIAN |
| 264 | select SYS_SUPPORTS_KGDB | 238 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 239 | select SYS_HAS_CPU_R5000 | ||
| 265 | help | 240 | help |
| 266 | The Ocelot is a MIPS-based Single Board Computer (SBC) made by | 241 | This enables support for the R5432-based NEC Mark-eins |
| 267 | Momentum Computer <http://www.momenco.com/>. | 242 | boards with R5500 CPU. |
| 243 | |||
| 244 | config MACH_VR41XX | ||
| 245 | bool "NEC VR4100 series based machines" | ||
| 246 | select SYS_HAS_CPU_VR41XX | ||
| 247 | select GENERIC_HARDIRQS_NO__DO_IRQ | ||
| 268 | 248 | ||
| 269 | config PNX8550_JBS | 249 | config PNX8550_JBS |
| 270 | bool "Philips PNX8550 based JBS board" | 250 | bool "Philips PNX8550 based JBS board" |
| @@ -276,31 +256,6 @@ config PNX8550_STB810 | |||
| 276 | select PNX8550 | 256 | select PNX8550 |
| 277 | select SYS_SUPPORTS_LITTLE_ENDIAN | 257 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 278 | 258 | ||
| 279 | config DDB5477 | ||
| 280 | bool "NEC DDB Vrc-5477" | ||
| 281 | select DDB5XXX_COMMON | ||
| 282 | select DMA_NONCOHERENT | ||
| 283 | select HW_HAS_PCI | ||
| 284 | select I8259 | ||
| 285 | select IRQ_CPU | ||
| 286 | select SYS_HAS_CPU_R5432 | ||
| 287 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 288 | select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL | ||
| 289 | select SYS_SUPPORTS_KGDB | ||
| 290 | select SYS_SUPPORTS_KGDB | ||
| 291 | select SYS_SUPPORTS_LITTLE_ENDIAN | ||
| 292 | help | ||
| 293 | This enables support for the R5432-based NEC DDB Vrc-5477, | ||
| 294 | or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. | ||
| 295 | |||
| 296 | Features : kernel debugging, serial terminal, NFS root fs, on-board | ||
| 297 | ether port USB, AC97, PCI, etc. | ||
| 298 | |||
| 299 | config MACH_VR41XX | ||
| 300 | bool "NEC VR4100 series based machines" | ||
| 301 | select SYS_HAS_CPU_VR41XX | ||
| 302 | select GENERIC_HARDIRQS_NO__DO_IRQ | ||
| 303 | |||
| 304 | config PMC_MSP | 259 | config PMC_MSP |
| 305 | bool "PMC-Sierra MSP chipsets" | 260 | bool "PMC-Sierra MSP chipsets" |
| 306 | depends on EXPERIMENTAL | 261 | depends on EXPERIMENTAL |
| @@ -367,20 +322,6 @@ config QEMU | |||
| 367 | simulate actual MIPS hardware platforms. More information on Qemu | 322 | simulate actual MIPS hardware platforms. More information on Qemu |
| 368 | can be found at http://www.linux-mips.org/wiki/Qemu. | 323 | can be found at http://www.linux-mips.org/wiki/Qemu. |
| 369 | 324 | ||
| 370 | config MARKEINS | ||
| 371 | bool "NEC EMMA2RH Mark-eins" | ||
| 372 | select DMA_NONCOHERENT | ||
| 373 | select HW_HAS_PCI | ||
| 374 | select IRQ_CPU | ||
| 375 | select SWAP_IO_SPACE | ||
| 376 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 377 | select SYS_SUPPORTS_BIG_ENDIAN | ||
| 378 | select SYS_SUPPORTS_LITTLE_ENDIAN | ||
| 379 | select SYS_HAS_CPU_R5000 | ||
| 380 | help | ||
| 381 | This enables support for the R5432-based NEC Mark-eins | ||
| 382 | boards with R5500 CPU. | ||
| 383 | |||
| 384 | config SGI_IP22 | 325 | config SGI_IP22 |
| 385 | bool "SGI IP22 (Indy/Indigo2)" | 326 | bool "SGI IP22 (Indy/Indigo2)" |
| 386 | select ARC | 327 | select ARC |
| @@ -443,41 +384,38 @@ config SGI_IP32 | |||
| 443 | help | 384 | help |
| 444 | If you want this kernel to run on SGI O2 workstation, say Y here. | 385 | If you want this kernel to run on SGI O2 workstation, say Y here. |
| 445 | 386 | ||
| 446 | config SIBYTE_BIGSUR | 387 | config SIBYTE_CRHINE |
| 447 | bool "Sibyte BCM91480B-BigSur" | 388 | bool "Sibyte BCM91120C-CRhine" |
| 389 | depends on EXPERIMENTAL | ||
| 448 | select BOOT_ELF32 | 390 | select BOOT_ELF32 |
| 449 | select DMA_COHERENT | 391 | select DMA_COHERENT |
| 450 | select NR_CPUS_DEFAULT_4 | 392 | select SIBYTE_BCM1120 |
| 451 | select PCI_DOMAINS | ||
| 452 | select SIBYTE_BCM1x80 | ||
| 453 | select SWAP_IO_SPACE | 393 | select SWAP_IO_SPACE |
| 454 | select SYS_HAS_CPU_SB1 | 394 | select SYS_HAS_CPU_SB1 |
| 455 | select SYS_SUPPORTS_BIG_ENDIAN | 395 | select SYS_SUPPORTS_BIG_ENDIAN |
| 456 | select SYS_SUPPORTS_LITTLE_ENDIAN | 396 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 457 | 397 | ||
| 458 | config SIBYTE_SWARM | 398 | config SIBYTE_CARMEL |
| 459 | bool "Sibyte BCM91250A-SWARM" | 399 | bool "Sibyte BCM91120x-Carmel" |
| 400 | depends on EXPERIMENTAL | ||
| 460 | select BOOT_ELF32 | 401 | select BOOT_ELF32 |
| 461 | select DMA_COHERENT | 402 | select DMA_COHERENT |
| 462 | select NR_CPUS_DEFAULT_2 | 403 | select SIBYTE_BCM1120 |
| 463 | select SIBYTE_SB1250 | ||
| 464 | select SWAP_IO_SPACE | 404 | select SWAP_IO_SPACE |
| 465 | select SYS_HAS_CPU_SB1 | 405 | select SYS_HAS_CPU_SB1 |
| 466 | select SYS_SUPPORTS_BIG_ENDIAN | 406 | select SYS_SUPPORTS_BIG_ENDIAN |
| 467 | select SYS_SUPPORTS_HIGHMEM | ||
| 468 | select SYS_SUPPORTS_KGDB | ||
| 469 | select SYS_SUPPORTS_LITTLE_ENDIAN | 407 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 470 | 408 | ||
| 471 | config SIBYTE_SENTOSA | 409 | config SIBYTE_CRHONE |
| 472 | bool "Sibyte BCM91250E-Sentosa" | 410 | bool "Sibyte BCM91125C-CRhone" |
| 473 | depends on EXPERIMENTAL | 411 | depends on EXPERIMENTAL |
| 474 | select BOOT_ELF32 | 412 | select BOOT_ELF32 |
| 475 | select DMA_COHERENT | 413 | select DMA_COHERENT |
| 476 | select NR_CPUS_DEFAULT_2 | 414 | select SIBYTE_BCM1125 |
| 477 | select SIBYTE_SB1250 | ||
| 478 | select SWAP_IO_SPACE | 415 | select SWAP_IO_SPACE |
| 479 | select SYS_HAS_CPU_SB1 | 416 | select SYS_HAS_CPU_SB1 |
| 480 | select SYS_SUPPORTS_BIG_ENDIAN | 417 | select SYS_SUPPORTS_BIG_ENDIAN |
| 418 | select SYS_SUPPORTS_HIGHMEM | ||
| 481 | select SYS_SUPPORTS_LITTLE_ENDIAN | 419 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 482 | 420 | ||
| 483 | config SIBYTE_RHONE | 421 | config SIBYTE_RHONE |
| @@ -491,19 +429,21 @@ config SIBYTE_RHONE | |||
| 491 | select SYS_SUPPORTS_BIG_ENDIAN | 429 | select SYS_SUPPORTS_BIG_ENDIAN |
| 492 | select SYS_SUPPORTS_LITTLE_ENDIAN | 430 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 493 | 431 | ||
| 494 | config SIBYTE_CARMEL | 432 | config SIBYTE_SWARM |
| 495 | bool "Sibyte BCM91120x-Carmel" | 433 | bool "Sibyte BCM91250A-SWARM" |
| 496 | depends on EXPERIMENTAL | ||
| 497 | select BOOT_ELF32 | 434 | select BOOT_ELF32 |
| 498 | select DMA_COHERENT | 435 | select DMA_COHERENT |
| 499 | select SIBYTE_BCM1120 | 436 | select NR_CPUS_DEFAULT_2 |
| 437 | select SIBYTE_SB1250 | ||
| 500 | select SWAP_IO_SPACE | 438 | select SWAP_IO_SPACE |
| 501 | select SYS_HAS_CPU_SB1 | 439 | select SYS_HAS_CPU_SB1 |
| 502 | select SYS_SUPPORTS_BIG_ENDIAN | 440 | select SYS_SUPPORTS_BIG_ENDIAN |
| 441 | select SYS_SUPPORTS_HIGHMEM | ||
| 442 | select SYS_SUPPORTS_KGDB | ||
| 503 | select SYS_SUPPORTS_LITTLE_ENDIAN | 443 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 504 | 444 | ||
| 505 | config SIBYTE_PTSWARM | 445 | config SIBYTE_LITTLESUR |
| 506 | bool "Sibyte BCM91250PT-PTSWARM" | 446 | bool "Sibyte BCM91250C2-LittleSur" |
| 507 | depends on EXPERIMENTAL | 447 | depends on EXPERIMENTAL |
| 508 | select BOOT_ELF32 | 448 | select BOOT_ELF32 |
| 509 | select DMA_COHERENT | 449 | select DMA_COHERENT |
| @@ -515,8 +455,8 @@ config SIBYTE_PTSWARM | |||
| 515 | select SYS_SUPPORTS_HIGHMEM | 455 | select SYS_SUPPORTS_HIGHMEM |
| 516 | select SYS_SUPPORTS_LITTLE_ENDIAN | 456 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 517 | 457 | ||
| 518 | config SIBYTE_LITTLESUR | 458 | config SIBYTE_SENTOSA |
| 519 | bool "Sibyte BCM91250C2-LittleSur" | 459 | bool "Sibyte BCM91250E-Sentosa" |
| 520 | depends on EXPERIMENTAL | 460 | depends on EXPERIMENTAL |
| 521 | select BOOT_ELF32 | 461 | select BOOT_ELF32 |
| 522 | select DMA_COHERENT | 462 | select DMA_COHERENT |
| @@ -525,30 +465,31 @@ config SIBYTE_LITTLESUR | |||
| 525 | select SWAP_IO_SPACE | 465 | select SWAP_IO_SPACE |
| 526 | select SYS_HAS_CPU_SB1 | 466 | select SYS_HAS_CPU_SB1 |
| 527 | select SYS_SUPPORTS_BIG_ENDIAN | 467 | select SYS_SUPPORTS_BIG_ENDIAN |
| 528 | select SYS_SUPPORTS_HIGHMEM | ||
| 529 | select SYS_SUPPORTS_LITTLE_ENDIAN | 468 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 530 | 469 | ||
| 531 | config SIBYTE_CRHINE | 470 | config SIBYTE_PTSWARM |
| 532 | bool "Sibyte BCM91120C-CRhine" | 471 | bool "Sibyte BCM91250PT-PTSWARM" |
| 533 | depends on EXPERIMENTAL | 472 | depends on EXPERIMENTAL |
| 534 | select BOOT_ELF32 | 473 | select BOOT_ELF32 |
| 535 | select DMA_COHERENT | 474 | select DMA_COHERENT |
| 536 | select SIBYTE_BCM1120 | 475 | select NR_CPUS_DEFAULT_2 |
| 476 | select SIBYTE_SB1250 | ||
| 537 | select SWAP_IO_SPACE | 477 | select SWAP_IO_SPACE |
| 538 | select SYS_HAS_CPU_SB1 | 478 | select SYS_HAS_CPU_SB1 |
| 539 | select SYS_SUPPORTS_BIG_ENDIAN | 479 | select SYS_SUPPORTS_BIG_ENDIAN |
| 480 | select SYS_SUPPORTS_HIGHMEM | ||
| 540 | select SYS_SUPPORTS_LITTLE_ENDIAN | 481 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 541 | 482 | ||
| 542 | config SIBYTE_CRHONE | 483 | config SIBYTE_BIGSUR |
| 543 | bool "Sibyte BCM91125C-CRhone" | 484 | bool "Sibyte BCM91480B-BigSur" |
| 544 | depends on EXPERIMENTAL | ||
| 545 | select BOOT_ELF32 | 485 | select BOOT_ELF32 |
| 546 | select DMA_COHERENT | 486 | select DMA_COHERENT |
| 547 | select SIBYTE_BCM1125 | 487 | select NR_CPUS_DEFAULT_4 |
| 488 | select PCI_DOMAINS | ||
| 489 | select SIBYTE_BCM1x80 | ||
| 548 | select SWAP_IO_SPACE | 490 | select SWAP_IO_SPACE |
| 549 | select SYS_HAS_CPU_SB1 | 491 | select SYS_HAS_CPU_SB1 |
| 550 | select SYS_SUPPORTS_BIG_ENDIAN | 492 | select SYS_SUPPORTS_BIG_ENDIAN |
| 551 | select SYS_SUPPORTS_HIGHMEM | ||
| 552 | select SYS_SUPPORTS_LITTLE_ENDIAN | 493 | select SYS_SUPPORTS_LITTLE_ENDIAN |
| 553 | 494 | ||
| 554 | config SNI_RM | 495 | config SNI_RM |
| @@ -595,7 +536,7 @@ config TOSHIBA_JMR3927 | |||
| 595 | select GENERIC_HARDIRQS_NO__DO_IRQ | 536 | select GENERIC_HARDIRQS_NO__DO_IRQ |
| 596 | 537 | ||
| 597 | config TOSHIBA_RBTX4927 | 538 | config TOSHIBA_RBTX4927 |
| 598 | bool "Toshiba TBTX49[23]7 board" | 539 | bool "Toshiba RBTX49[23]7 board" |
| 599 | select DMA_NONCOHERENT | 540 | select DMA_NONCOHERENT |
| 600 | select HAS_TXX9_SERIAL | 541 | select HAS_TXX9_SERIAL |
| 601 | select HW_HAS_PCI | 542 | select HW_HAS_PCI |
| @@ -632,10 +573,30 @@ config TOSHIBA_RBTX4938 | |||
| 632 | This Toshiba board is based on the TX4938 processor. Say Y here to | 573 | This Toshiba board is based on the TX4938 processor. Say Y here to |
| 633 | support this machine type | 574 | support this machine type |
| 634 | 575 | ||
| 576 | config WR_PPMC | ||
| 577 | bool "Wind River PPMC board" | ||
| 578 | select IRQ_CPU | ||
| 579 | select BOOT_ELF32 | ||
| 580 | select DMA_NONCOHERENT | ||
| 581 | select HW_HAS_PCI | ||
| 582 | select PCI_GT64XXX_PCI0 | ||
| 583 | select SWAP_IO_SPACE | ||
| 584 | select SYS_HAS_CPU_MIPS32_R1 | ||
| 585 | select SYS_HAS_CPU_MIPS32_R2 | ||
| 586 | select SYS_HAS_CPU_MIPS64_R1 | ||
| 587 | select SYS_HAS_CPU_NEVADA | ||
| 588 | select SYS_HAS_CPU_RM7000 | ||
| 589 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 590 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 591 | select SYS_SUPPORTS_BIG_ENDIAN | ||
| 592 | select SYS_SUPPORTS_LITTLE_ENDIAN | ||
| 593 | help | ||
| 594 | This enables support for the Wind River MIPS32 4KC PPMC evaluation | ||
| 595 | board, which is based on GT64120 bridge chip. | ||
| 596 | |||
| 635 | endchoice | 597 | endchoice |
| 636 | 598 | ||
| 637 | source "arch/mips/au1000/Kconfig" | 599 | source "arch/mips/au1000/Kconfig" |
| 638 | source "arch/mips/ddb5xxx/Kconfig" | ||
| 639 | source "arch/mips/jazz/Kconfig" | 600 | source "arch/mips/jazz/Kconfig" |
| 640 | source "arch/mips/pmc-sierra/Kconfig" | 601 | source "arch/mips/pmc-sierra/Kconfig" |
| 641 | source "arch/mips/sgi-ip27/Kconfig" | 602 | source "arch/mips/sgi-ip27/Kconfig" |
| @@ -807,10 +768,6 @@ config IRQ_MSP_SLP | |||
| 807 | config IRQ_MSP_CIC | 768 | config IRQ_MSP_CIC |
| 808 | bool | 769 | bool |
| 809 | 770 | ||
| 810 | config DDB5XXX_COMMON | ||
| 811 | bool | ||
| 812 | select SYS_SUPPORTS_KGDB | ||
| 813 | |||
| 814 | config MIPS_BOARDS_GEN | 771 | config MIPS_BOARDS_GEN |
| 815 | bool | 772 | bool |
| 816 | 773 | ||
| @@ -1377,17 +1334,6 @@ config MIPS_MT_SMTC | |||
| 1377 | This is a kernel model which is known a SMTC or lately has been | 1334 | This is a kernel model which is known a SMTC or lately has been |
| 1378 | marketesed into SMVP. | 1335 | marketesed into SMVP. |
| 1379 | 1336 | ||
| 1380 | config MIPS_VPE_LOADER | ||
| 1381 | bool "VPE loader support." | ||
| 1382 | depends on SYS_SUPPORTS_MULTITHREADING | ||
| 1383 | select CPU_MIPSR2_IRQ_VI | ||
| 1384 | select CPU_MIPSR2_IRQ_EI | ||
| 1385 | select CPU_MIPSR2_SRS | ||
| 1386 | select MIPS_MT | ||
| 1387 | help | ||
| 1388 | Includes a loader for loading an elf relocatable object | ||
| 1389 | onto another VPE and running it. | ||
| 1390 | |||
| 1391 | endchoice | 1337 | endchoice |
| 1392 | 1338 | ||
| 1393 | config MIPS_MT | 1339 | config MIPS_MT |
| @@ -1398,8 +1344,19 @@ config SYS_SUPPORTS_MULTITHREADING | |||
| 1398 | 1344 | ||
| 1399 | config MIPS_MT_FPAFF | 1345 | config MIPS_MT_FPAFF |
| 1400 | bool "Dynamic FPU affinity for FP-intensive threads" | 1346 | bool "Dynamic FPU affinity for FP-intensive threads" |
| 1401 | depends on MIPS_MT | ||
| 1402 | default y | 1347 | default y |
| 1348 | depends on MIPS_MT_SMP || MIPS_MT_SMTC | ||
| 1349 | |||
| 1350 | config MIPS_VPE_LOADER | ||
| 1351 | bool "VPE loader support." | ||
| 1352 | depends on SYS_SUPPORTS_MULTITHREADING | ||
| 1353 | select CPU_MIPSR2_IRQ_VI | ||
| 1354 | select CPU_MIPSR2_IRQ_EI | ||
| 1355 | select CPU_MIPSR2_SRS | ||
| 1356 | select MIPS_MT | ||
| 1357 | help | ||
| 1358 | Includes a loader for loading an elf relocatable object | ||
| 1359 | onto another VPE and running it. | ||
| 1403 | 1360 | ||
| 1404 | config MIPS_MT_SMTC_INSTANT_REPLAY | 1361 | config MIPS_MT_SMTC_INSTANT_REPLAY |
| 1405 | bool "Low-latency Dispatch of Deferred SMTC IPIs" | 1362 | bool "Low-latency Dispatch of Deferred SMTC IPIs" |
| @@ -1772,7 +1729,7 @@ config KEXEC | |||
| 1772 | 1729 | ||
| 1773 | config SECCOMP | 1730 | config SECCOMP |
| 1774 | bool "Enable seccomp to safely compute untrusted bytecode" | 1731 | bool "Enable seccomp to safely compute untrusted bytecode" |
| 1775 | depends on PROC_FS && BROKEN | 1732 | depends on PROC_FS |
| 1776 | default y | 1733 | default y |
| 1777 | help | 1734 | help |
| 1778 | This kernel feature is useful for number crunching applications | 1735 | This kernel feature is useful for number crunching applications |
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a9a987a06daf..32c1c8fb6f98 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile | |||
| @@ -67,6 +67,8 @@ cflags-y += $(call cc-option,-msym32) | |||
| 67 | endif | 67 | endif |
| 68 | endif | 68 | endif |
| 69 | 69 | ||
| 70 | all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) | ||
| 71 | all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) | ||
| 70 | 72 | ||
| 71 | # | 73 | # |
| 72 | # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel | 74 | # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel |
| @@ -309,6 +311,7 @@ core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ | |||
| 309 | cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas | 311 | cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas |
| 310 | cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips | 312 | cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips |
| 311 | load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 | 313 | load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 |
| 314 | all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec | ||
| 312 | 315 | ||
| 313 | # | 316 | # |
| 314 | # MIPS Malta board | 317 | # MIPS Malta board |
| @@ -316,6 +319,7 @@ load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 | |||
| 316 | core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ | 319 | core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ |
| 317 | cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips | 320 | cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips |
| 318 | load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 | 321 | load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 |
| 322 | all-$(CONFIG_MIPS_MALTA) := vmlinux.srec | ||
| 319 | 323 | ||
| 320 | # | 324 | # |
| 321 | # MIPS SEAD board | 325 | # MIPS SEAD board |
| @@ -323,6 +327,7 @@ load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 | |||
| 323 | core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ | 327 | core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ |
| 324 | cflags-$(CONFIG_MIPS_SEAD) += -Iinclude/asm-mips/mach-mips | 328 | cflags-$(CONFIG_MIPS_SEAD) += -Iinclude/asm-mips/mach-mips |
| 325 | load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 | 329 | load-$(CONFIG_MIPS_SEAD) += 0xffffffff80100000 |
| 330 | all-$(CONFIG_MIPS_SEAD) := vmlinux.srec | ||
| 326 | 331 | ||
| 327 | # | 332 | # |
| 328 | # MIPS SIM | 333 | # MIPS SIM |
| @@ -332,17 +337,6 @@ cflags-$(CONFIG_MIPS_SIM) += -Iinclude/asm-mips/mach-mipssim | |||
| 332 | load-$(CONFIG_MIPS_SIM) += 0x80100000 | 337 | load-$(CONFIG_MIPS_SIM) += 0x80100000 |
| 333 | 338 | ||
| 334 | # | 339 | # |
| 335 | # Momentum Ocelot board | ||
| 336 | # | ||
| 337 | # The Ocelot setup.o must be linked early - it does the ioremap() for the | ||
| 338 | # mips_io_port_base. | ||
| 339 | # | ||
| 340 | core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \ | ||
| 341 | arch/mips/gt64120/momenco_ocelot/ | ||
| 342 | cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot | ||
| 343 | load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 | ||
| 344 | |||
| 345 | # | ||
| 346 | # PMC-Sierra MSP SOCs | 340 | # PMC-Sierra MSP SOCs |
| 347 | # | 341 | # |
| 348 | core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/ | 342 | core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/ |
| @@ -363,6 +357,7 @@ load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 | |||
| 363 | core-$(CONFIG_QEMU) += arch/mips/qemu/ | 357 | core-$(CONFIG_QEMU) += arch/mips/qemu/ |
| 364 | cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu | 358 | cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu |
| 365 | load-$(CONFIG_QEMU) += 0xffffffff80010000 | 359 | load-$(CONFIG_QEMU) += 0xffffffff80010000 |
| 360 | all-$(CONFIG_QEMU) := vmlinux.bin | ||
| 366 | 361 | ||
| 367 | # | 362 | # |
| 368 | # Basler eXcite | 363 | # Basler eXcite |
| @@ -372,17 +367,6 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite | |||
| 372 | load-$(CONFIG_BASLER_EXCITE) += 0x80100000 | 367 | load-$(CONFIG_BASLER_EXCITE) += 0x80100000 |
| 373 | 368 | ||
| 374 | # | 369 | # |
| 375 | # NEC DDB | ||
| 376 | # | ||
| 377 | core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ | ||
| 378 | |||
| 379 | # | ||
| 380 | # NEC DDB Vrc-5477 | ||
| 381 | # | ||
| 382 | core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ | ||
| 383 | load-$(CONFIG_DDB5477) += 0xffffffff80100000 | ||
| 384 | |||
| 385 | # | ||
| 386 | # Common VR41xx | 370 | # Common VR41xx |
| 387 | # | 371 | # |
| 388 | core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ | 372 | core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ |
| @@ -554,6 +538,7 @@ load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 | |||
| 554 | core-$(CONFIG_SNI_RM) += arch/mips/sni/ | 538 | core-$(CONFIG_SNI_RM) += arch/mips/sni/ |
| 555 | cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm | 539 | cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm |
| 556 | load-$(CONFIG_SNI_RM) += 0xffffffff80600000 | 540 | load-$(CONFIG_SNI_RM) += 0xffffffff80600000 |
| 541 | all-$(CONFIG_SNI_RM) := vmlinux.ecoff | ||
| 557 | 542 | ||
| 558 | # | 543 | # |
| 559 | # Toshiba JMR-TX3927 board | 544 | # Toshiba JMR-TX3927 board |
| @@ -647,33 +632,7 @@ vmlinux.64: vmlinux | |||
| 647 | 632 | ||
| 648 | makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) | 633 | makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) |
| 649 | 634 | ||
| 650 | ifdef CONFIG_BOOT_ELF32 | 635 | all: $(all-y) |
| 651 | all: $(vmlinux-32) | ||
| 652 | endif | ||
| 653 | |||
| 654 | ifdef CONFIG_BOOT_ELF64 | ||
| 655 | all: $(vmlinux-64) | ||
| 656 | endif | ||
| 657 | |||
| 658 | ifdef CONFIG_MIPS_ATLAS | ||
| 659 | all: vmlinux.srec | ||
| 660 | endif | ||
| 661 | |||
| 662 | ifdef CONFIG_MIPS_MALTA | ||
| 663 | all: vmlinux.srec | ||
| 664 | endif | ||
| 665 | |||
| 666 | ifdef CONFIG_MIPS_SEAD | ||
| 667 | all: vmlinux.srec | ||
| 668 | endif | ||
| 669 | |||
| 670 | ifdef CONFIG_QEMU | ||
| 671 | all: vmlinux.bin | ||
| 672 | endif | ||
| 673 | |||
| 674 | ifdef CONFIG_SNI_RM | ||
| 675 | all: vmlinux.ecoff | ||
| 676 | endif | ||
| 677 | 636 | ||
| 678 | vmlinux.bin: $(vmlinux-32) | 637 | vmlinux.bin: $(vmlinux-32) |
| 679 | +@$(call makeboot,$@) | 638 | +@$(call makeboot,$@) |
| @@ -700,6 +659,14 @@ endif | |||
| 700 | archclean: | 659 | archclean: |
| 701 | @$(MAKE) $(clean)=arch/mips/boot | 660 | @$(MAKE) $(clean)=arch/mips/boot |
| 702 | 661 | ||
| 662 | define archhelp | ||
| 663 | echo ' vmlinux.ecoff - ECOFF boot image' | ||
| 664 | echo ' vmlinux.bin - Raw binary boot image' | ||
| 665 | echo ' vmlinux.srec - SREC boot image' | ||
| 666 | echo | ||
| 667 | echo ' These will be default as apropriate for a configured platform.' | ||
| 668 | endef | ||
| 669 | |||
| 703 | CLEAN_FILES += vmlinux.32 \ | 670 | CLEAN_FILES += vmlinux.32 \ |
| 704 | vmlinux.64 \ | 671 | vmlinux.64 \ |
| 705 | vmlinux.ecoff | 672 | vmlinux.ecoff |
diff --git a/arch/mips/arc/file.c b/arch/mips/arc/file.c index a43425b3c838..cb0127cf5bc1 100644 --- a/arch/mips/arc/file.c +++ b/arch/mips/arc/file.c | |||
| @@ -13,63 +13,63 @@ | |||
| 13 | #include <asm/arc/types.h> | 13 | #include <asm/arc/types.h> |
| 14 | #include <asm/sgialib.h> | 14 | #include <asm/sgialib.h> |
| 15 | 15 | ||
| 16 | LONG __init | 16 | LONG |
| 17 | ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer, | 17 | ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer, |
| 18 | ULONG N, ULONG *Count) | 18 | ULONG N, ULONG *Count) |
| 19 | { | 19 | { |
| 20 | return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count); | 20 | return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count); |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | LONG __init | 23 | LONG |
| 24 | ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID) | 24 | ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID) |
| 25 | { | 25 | { |
| 26 | return ARC_CALL3(open, Path, OpenMode, FileID); | 26 | return ARC_CALL3(open, Path, OpenMode, FileID); |
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | LONG __init | 29 | LONG |
| 30 | ArcClose(ULONG FileID) | 30 | ArcClose(ULONG FileID) |
| 31 | { | 31 | { |
| 32 | return ARC_CALL1(close, FileID); | 32 | return ARC_CALL1(close, FileID); |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | LONG __init | 35 | LONG |
| 36 | ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) | 36 | ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) |
| 37 | { | 37 | { |
| 38 | return ARC_CALL4(read, FileID, Buffer, N, Count); | 38 | return ARC_CALL4(read, FileID, Buffer, N, Count); |
| 39 | } | 39 | } |
| 40 | 40 | ||
| 41 | LONG __init | 41 | LONG |
| 42 | ArcGetReadStatus(ULONG FileID) | 42 | ArcGetReadStatus(ULONG FileID) |
| 43 | { | 43 | { |
| 44 | return ARC_CALL1(get_rstatus, FileID); | 44 | return ARC_CALL1(get_rstatus, FileID); |
| 45 | } | 45 | } |
| 46 | 46 | ||
| 47 | LONG __init | 47 | LONG |
| 48 | ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) | 48 | ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) |
| 49 | { | 49 | { |
| 50 | return ARC_CALL4(write, FileID, Buffer, N, Count); | 50 | return ARC_CALL4(write, FileID, Buffer, N, Count); |
| 51 | } | 51 | } |
| 52 | 52 | ||
| 53 | LONG __init | 53 | LONG |
| 54 | ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode) | 54 | ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode) |
| 55 | { | 55 | { |
| 56 | return ARC_CALL3(seek, FileID, Position, SeekMode); | 56 | return ARC_CALL3(seek, FileID, Position, SeekMode); |
| 57 | } | 57 | } |
| 58 | 58 | ||
| 59 | LONG __init | 59 | LONG |
| 60 | ArcMount(char *name, enum linux_mountops op) | 60 | ArcMount(char *name, enum linux_mountops op) |
| 61 | { | 61 | { |
| 62 | return ARC_CALL2(mount, name, op); | 62 | return ARC_CALL2(mount, name, op); |
| 63 | } | 63 | } |
| 64 | 64 | ||
| 65 | LONG __init | 65 | LONG |
| 66 | ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information) | 66 | ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information) |
| 67 | { | 67 | { |
| 68 | return ARC_CALL2(get_finfo, FileID, Information); | 68 | return ARC_CALL2(get_finfo, FileID, Information); |
| 69 | } | 69 | } |
| 70 | 70 | ||
| 71 | LONG __init ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, | 71 | LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, |
| 72 | ULONG AttributeMask) | 72 | ULONG AttributeMask) |
| 73 | { | 73 | { |
| 74 | return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask); | 74 | return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask); |
| 75 | } | 75 | } |
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile index 4c35525edb4f..90e2d7a46e8e 100644 --- a/arch/mips/au1000/common/Makefile +++ b/arch/mips/au1000/common/Makefile | |||
| @@ -12,3 +12,5 @@ obj-y += prom.o irq.o puts.o time.o reset.o \ | |||
| 12 | 12 | ||
| 13 | obj-$(CONFIG_KGDB) += dbg_io.o | 13 | obj-$(CONFIG_KGDB) += dbg_io.o |
| 14 | obj-$(CONFIG_PCI) += pci.o | 14 | obj-$(CONFIG_PCI) += pci.o |
| 15 | |||
| 16 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile index 0dc84417bf49..2a209d74f0b4 100644 --- a/arch/mips/boot/Makefile +++ b/arch/mips/boot/Makefile | |||
| @@ -42,10 +42,6 @@ vmlinux.srec: $(VMLINUX) | |||
| 42 | $(obj)/addinitrd: $(obj)/addinitrd.c | 42 | $(obj)/addinitrd: $(obj)/addinitrd.c |
| 43 | $(HOSTCC) -o $@ $^ | 43 | $(HOSTCC) -o $@ $^ |
| 44 | 44 | ||
| 45 | archhelp: | ||
| 46 | @echo '* vmlinux.ecoff - ECOFF boot image' | ||
| 47 | @echo '* vmlinux.srec - SREC boot image' | ||
| 48 | |||
| 49 | clean-files += addinitrd \ | 45 | clean-files += addinitrd \ |
| 50 | elf2ecoff \ | 46 | elf2ecoff \ |
| 51 | vmlinux.bin \ | 47 | vmlinux.bin \ |
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index c292f80a8c74..a043f93f7d08 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile | |||
| @@ -7,3 +7,5 @@ obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o | |||
| 7 | obj-$(CONFIG_PCI) += pci.o | 7 | obj-$(CONFIG_PCI) += pci.o |
| 8 | obj-$(CONFIG_EARLY_PRINTK) += console.o | 8 | obj-$(CONFIG_EARLY_PRINTK) += console.o |
| 9 | obj-$(CONFIG_MTD_PHYSMAP) += mtd.o | 9 | obj-$(CONFIG_MTD_PHYSMAP) += mtd.o |
| 10 | |||
| 11 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c index c27116599a5f..08e739704cc9 100644 --- a/arch/mips/cobalt/serial.c +++ b/arch/mips/cobalt/serial.c | |||
| @@ -55,9 +55,9 @@ static __init int cobalt_uart_add(void) | |||
| 55 | int retval; | 55 | int retval; |
| 56 | 56 | ||
| 57 | /* | 57 | /* |
| 58 | * Cobalt Qube1 and RAQ1 have no UART. | 58 | * Cobalt Qube1 has no UART. |
| 59 | */ | 59 | */ |
| 60 | if (cobalt_board_id <= COBALT_BRD_ID_RAQ1) | 60 | if (cobalt_board_id == COBALT_BRD_ID_QUBE1) |
| 61 | return 0; | 61 | return 0; |
| 62 | 62 | ||
| 63 | pdev = platform_device_alloc("serial8250", -1); | 63 | pdev = platform_device_alloc("serial8250", -1); |
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig index 129e2c961fec..62bcc887f2ca 100644 --- a/arch/mips/configs/atlas_defconfig +++ b/arch/mips/configs/atlas_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_MIPS_ATLAS=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index dc3e1bf4e42e..67a80f4c7d87 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 4c7031222e64..4dc3197e2e9f 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | CONFIG_MACH_VR41XX=y | 38 | CONFIG_MACH_VR41XX=y |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index c8c05785a86d..6d6a01b9a817 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig | |||
| @@ -18,10 +18,8 @@ CONFIG_MIPS_COBALT=y | |||
| 18 | # CONFIG_MIPS_SEAD is not set | 18 | # CONFIG_MIPS_SEAD is not set |
| 19 | # CONFIG_WR_PPMC is not set | 19 | # CONFIG_WR_PPMC is not set |
| 20 | # CONFIG_MIPS_SIM is not set | 20 | # CONFIG_MIPS_SIM is not set |
| 21 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 22 | # CONFIG_PNX8550_JBS is not set | 21 | # CONFIG_PNX8550_JBS is not set |
| 23 | # CONFIG_PNX8550_STB810 is not set | 22 | # CONFIG_PNX8550_STB810 is not set |
| 24 | # CONFIG_DDB5477 is not set | ||
| 25 | # CONFIG_MACH_VR41XX is not set | 23 | # CONFIG_MACH_VR41XX is not set |
| 26 | # CONFIG_PMC_YOSEMITE is not set | 24 | # CONFIG_PMC_YOSEMITE is not set |
| 27 | # CONFIG_QEMU is not set | 25 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index ec60beb888b2..885b633647e9 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1000=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index f3c25f08bfad..e3c3a07e8a7c 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1100=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 6d400befbacc..9aa7c3ebfa3f 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1200=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 82aea6e08823..99240668bca1 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1500=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index 82697714a9e3..19992f76c60d 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_DB1550=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig deleted file mode 100644 index a42ab9ae7d4b..000000000000 --- a/arch/mips/configs/ddb5477_defconfig +++ /dev/null | |||
| @@ -1,990 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.20 | ||
| 4 | # Tue Feb 20 21:47:28 2007 | ||
| 5 | # | ||
| 6 | CONFIG_MIPS=y | ||
| 7 | |||
| 8 | # | ||
| 9 | # Machine selection | ||
| 10 | # | ||
| 11 | CONFIG_ZONE_DMA=y | ||
| 12 | # CONFIG_MIPS_MTX1 is not set | ||
| 13 | # CONFIG_MIPS_BOSPORUS is not set | ||
| 14 | # CONFIG_MIPS_PB1000 is not set | ||
| 15 | # CONFIG_MIPS_PB1100 is not set | ||
| 16 | # CONFIG_MIPS_PB1500 is not set | ||
| 17 | # CONFIG_MIPS_PB1550 is not set | ||
| 18 | # CONFIG_MIPS_PB1200 is not set | ||
| 19 | # CONFIG_MIPS_DB1000 is not set | ||
| 20 | # CONFIG_MIPS_DB1100 is not set | ||
| 21 | # CONFIG_MIPS_DB1500 is not set | ||
| 22 | # CONFIG_MIPS_DB1550 is not set | ||
| 23 | # CONFIG_MIPS_DB1200 is not set | ||
| 24 | # CONFIG_MIPS_MIRAGE is not set | ||
| 25 | # CONFIG_BASLER_EXCITE is not set | ||
| 26 | # CONFIG_MIPS_COBALT is not set | ||
| 27 | # CONFIG_MACH_DECSTATION is not set | ||
| 28 | # CONFIG_MACH_JAZZ is not set | ||
| 29 | # CONFIG_MIPS_ATLAS is not set | ||
| 30 | # CONFIG_MIPS_MALTA is not set | ||
| 31 | # CONFIG_MIPS_SEAD is not set | ||
| 32 | # CONFIG_WR_PPMC is not set | ||
| 33 | # CONFIG_MIPS_SIM is not set | ||
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | ||
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | ||
| 38 | # CONFIG_PNX8550_JBS is not set | ||
| 39 | # CONFIG_PNX8550_STB810 is not set | ||
| 40 | CONFIG_DDB5477=y | ||
| 41 | # CONFIG_MACH_VR41XX is not set | ||
| 42 | # CONFIG_PMC_YOSEMITE is not set | ||
| 43 | # CONFIG_QEMU is not set | ||
| 44 | # CONFIG_MARKEINS is not set | ||
| 45 | # CONFIG_SGI_IP22 is not set | ||
| 46 | # CONFIG_SGI_IP27 is not set | ||
| 47 | # CONFIG_SGI_IP32 is not set | ||
| 48 | # CONFIG_SIBYTE_BIGSUR is not set | ||
| 49 | # CONFIG_SIBYTE_SWARM is not set | ||
| 50 | # CONFIG_SIBYTE_SENTOSA is not set | ||
| 51 | # CONFIG_SIBYTE_RHONE is not set | ||
| 52 | # CONFIG_SIBYTE_CARMEL is not set | ||
| 53 | # CONFIG_SIBYTE_PTSWARM is not set | ||
| 54 | # CONFIG_SIBYTE_LITTLESUR is not set | ||
| 55 | # CONFIG_SIBYTE_CRHINE is not set | ||
| 56 | # CONFIG_SIBYTE_CRHONE is not set | ||
| 57 | # CONFIG_SNI_RM is not set | ||
| 58 | # CONFIG_TOSHIBA_JMR3927 is not set | ||
| 59 | # CONFIG_TOSHIBA_RBTX4927 is not set | ||
| 60 | # CONFIG_TOSHIBA_RBTX4938 is not set | ||
| 61 | CONFIG_DDB5477_BUS_FREQUENCY=0 | ||
| 62 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 63 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 64 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 65 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
| 66 | CONFIG_GENERIC_HWEIGHT=y | ||
| 67 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 68 | CONFIG_GENERIC_TIME=y | ||
| 69 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | ||
| 70 | # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set | ||
| 71 | CONFIG_DMA_NONCOHERENT=y | ||
| 72 | CONFIG_DMA_NEED_PCI_MAP_STATE=y | ||
| 73 | CONFIG_I8259=y | ||
| 74 | # CONFIG_CPU_BIG_ENDIAN is not set | ||
| 75 | CONFIG_CPU_LITTLE_ENDIAN=y | ||
| 76 | CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y | ||
| 77 | CONFIG_IRQ_CPU=y | ||
| 78 | CONFIG_DDB5XXX_COMMON=y | ||
| 79 | CONFIG_MIPS_L1_CACHE_SHIFT=5 | ||
| 80 | |||
| 81 | # | ||
| 82 | # CPU selection | ||
| 83 | # | ||
| 84 | # CONFIG_CPU_MIPS32_R1 is not set | ||
| 85 | # CONFIG_CPU_MIPS32_R2 is not set | ||
| 86 | # CONFIG_CPU_MIPS64_R1 is not set | ||
| 87 | # CONFIG_CPU_MIPS64_R2 is not set | ||
| 88 | # CONFIG_CPU_R3000 is not set | ||
| 89 | # CONFIG_CPU_TX39XX is not set | ||
| 90 | # CONFIG_CPU_VR41XX is not set | ||
| 91 | # CONFIG_CPU_R4300 is not set | ||
| 92 | # CONFIG_CPU_R4X00 is not set | ||
| 93 | # CONFIG_CPU_TX49XX is not set | ||
| 94 | # CONFIG_CPU_R5000 is not set | ||
| 95 | CONFIG_CPU_R5432=y | ||
| 96 | # CONFIG_CPU_R6000 is not set | ||
| 97 | # CONFIG_CPU_NEVADA is not set | ||
| 98 | # CONFIG_CPU_R8000 is not set | ||
| 99 | # CONFIG_CPU_R10000 is not set | ||
| 100 | # CONFIG_CPU_RM7000 is not set | ||
| 101 | # CONFIG_CPU_RM9000 is not set | ||
| 102 | # CONFIG_CPU_SB1 is not set | ||
| 103 | CONFIG_SYS_HAS_CPU_R5432=y | ||
| 104 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y | ||
| 105 | CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y | ||
| 106 | CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y | ||
| 107 | CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y | ||
| 108 | |||
| 109 | # | ||
| 110 | # Kernel type | ||
| 111 | # | ||
| 112 | CONFIG_32BIT=y | ||
| 113 | # CONFIG_64BIT is not set | ||
| 114 | CONFIG_PAGE_SIZE_4KB=y | ||
| 115 | # CONFIG_PAGE_SIZE_8KB is not set | ||
| 116 | # CONFIG_PAGE_SIZE_16KB is not set | ||
| 117 | # CONFIG_PAGE_SIZE_64KB is not set | ||
| 118 | CONFIG_MIPS_MT_DISABLED=y | ||
| 119 | # CONFIG_MIPS_MT_SMP is not set | ||
| 120 | # CONFIG_MIPS_MT_SMTC is not set | ||
| 121 | # CONFIG_MIPS_VPE_LOADER is not set | ||
| 122 | CONFIG_CPU_HAS_LLSC=y | ||
| 123 | CONFIG_CPU_HAS_SYNC=y | ||
| 124 | CONFIG_GENERIC_HARDIRQS=y | ||
| 125 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 126 | CONFIG_ARCH_FLATMEM_ENABLE=y | ||
| 127 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 128 | CONFIG_FLATMEM_MANUAL=y | ||
| 129 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 130 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 131 | CONFIG_FLATMEM=y | ||
| 132 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 133 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 134 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 135 | # CONFIG_RESOURCES_64BIT is not set | ||
| 136 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 137 | # CONFIG_HZ_48 is not set | ||
| 138 | # CONFIG_HZ_100 is not set | ||
| 139 | # CONFIG_HZ_128 is not set | ||
| 140 | # CONFIG_HZ_250 is not set | ||
| 141 | # CONFIG_HZ_256 is not set | ||
| 142 | CONFIG_HZ_1000=y | ||
| 143 | # CONFIG_HZ_1024 is not set | ||
| 144 | CONFIG_SYS_SUPPORTS_ARBIT_HZ=y | ||
| 145 | CONFIG_HZ=1000 | ||
| 146 | CONFIG_PREEMPT_NONE=y | ||
| 147 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 148 | # CONFIG_PREEMPT is not set | ||
| 149 | # CONFIG_KEXEC is not set | ||
| 150 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 151 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 152 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 153 | |||
| 154 | # | ||
| 155 | # Code maturity level options | ||
| 156 | # | ||
| 157 | CONFIG_EXPERIMENTAL=y | ||
| 158 | CONFIG_BROKEN_ON_SMP=y | ||
| 159 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 160 | |||
| 161 | # | ||
| 162 | # General setup | ||
| 163 | # | ||
| 164 | CONFIG_LOCALVERSION="" | ||
| 165 | CONFIG_LOCALVERSION_AUTO=y | ||
| 166 | CONFIG_SWAP=y | ||
| 167 | CONFIG_SYSVIPC=y | ||
| 168 | # CONFIG_IPC_NS is not set | ||
| 169 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 170 | # CONFIG_POSIX_MQUEUE is not set | ||
| 171 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 172 | # CONFIG_TASKSTATS is not set | ||
| 173 | # CONFIG_UTS_NS is not set | ||
| 174 | # CONFIG_AUDIT is not set | ||
| 175 | # CONFIG_IKCONFIG is not set | ||
| 176 | CONFIG_SYSFS_DEPRECATED=y | ||
| 177 | CONFIG_RELAY=y | ||
| 178 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 179 | CONFIG_SYSCTL=y | ||
| 180 | CONFIG_EMBEDDED=y | ||
| 181 | CONFIG_SYSCTL_SYSCALL=y | ||
| 182 | CONFIG_KALLSYMS=y | ||
| 183 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 184 | CONFIG_HOTPLUG=y | ||
| 185 | CONFIG_PRINTK=y | ||
| 186 | CONFIG_BUG=y | ||
| 187 | CONFIG_ELF_CORE=y | ||
| 188 | CONFIG_BASE_FULL=y | ||
| 189 | CONFIG_FUTEX=y | ||
| 190 | CONFIG_EPOLL=y | ||
| 191 | CONFIG_SHMEM=y | ||
| 192 | CONFIG_SLAB=y | ||
| 193 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 194 | CONFIG_RT_MUTEXES=y | ||
| 195 | # CONFIG_TINY_SHMEM is not set | ||
| 196 | CONFIG_BASE_SMALL=0 | ||
| 197 | # CONFIG_SLOB is not set | ||
| 198 | |||
| 199 | # | ||
| 200 | # Loadable module support | ||
| 201 | # | ||
| 202 | # CONFIG_MODULES is not set | ||
| 203 | |||
| 204 | # | ||
| 205 | # Block layer | ||
| 206 | # | ||
| 207 | CONFIG_BLOCK=y | ||
| 208 | # CONFIG_LBD is not set | ||
| 209 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 210 | # CONFIG_LSF is not set | ||
| 211 | |||
| 212 | # | ||
| 213 | # IO Schedulers | ||
| 214 | # | ||
| 215 | CONFIG_IOSCHED_NOOP=y | ||
| 216 | CONFIG_IOSCHED_AS=y | ||
| 217 | CONFIG_IOSCHED_DEADLINE=y | ||
| 218 | CONFIG_IOSCHED_CFQ=y | ||
| 219 | CONFIG_DEFAULT_AS=y | ||
| 220 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 221 | # CONFIG_DEFAULT_CFQ is not set | ||
| 222 | # CONFIG_DEFAULT_NOOP is not set | ||
| 223 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 224 | |||
| 225 | # | ||
| 226 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) | ||
| 227 | # | ||
| 228 | CONFIG_HW_HAS_PCI=y | ||
| 229 | CONFIG_PCI=y | ||
| 230 | CONFIG_MMU=y | ||
| 231 | |||
| 232 | # | ||
| 233 | # PCCARD (PCMCIA/CardBus) support | ||
| 234 | # | ||
| 235 | # CONFIG_PCCARD is not set | ||
| 236 | |||
| 237 | # | ||
| 238 | # PCI Hotplug Support | ||
| 239 | # | ||
| 240 | # CONFIG_HOTPLUG_PCI is not set | ||
| 241 | |||
| 242 | # | ||
| 243 | # Executable file formats | ||
| 244 | # | ||
| 245 | CONFIG_BINFMT_ELF=y | ||
| 246 | # CONFIG_BINFMT_MISC is not set | ||
| 247 | CONFIG_TRAD_SIGNALS=y | ||
| 248 | |||
| 249 | # | ||
| 250 | # Power management options | ||
| 251 | # | ||
| 252 | CONFIG_PM=y | ||
| 253 | # CONFIG_PM_LEGACY is not set | ||
| 254 | # CONFIG_PM_DEBUG is not set | ||
| 255 | # CONFIG_PM_SYSFS_DEPRECATED is not set | ||
| 256 | |||
| 257 | # | ||
| 258 | # Networking | ||
| 259 | # | ||
| 260 | CONFIG_NET=y | ||
| 261 | |||
| 262 | # | ||
| 263 | # Networking options | ||
| 264 | # | ||
| 265 | # CONFIG_NETDEBUG is not set | ||
| 266 | CONFIG_PACKET=y | ||
| 267 | # CONFIG_PACKET_MMAP is not set | ||
| 268 | CONFIG_UNIX=y | ||
| 269 | CONFIG_XFRM=y | ||
| 270 | CONFIG_XFRM_USER=y | ||
| 271 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 272 | CONFIG_XFRM_MIGRATE=y | ||
| 273 | CONFIG_NET_KEY=y | ||
| 274 | CONFIG_NET_KEY_MIGRATE=y | ||
| 275 | CONFIG_INET=y | ||
| 276 | # CONFIG_IP_MULTICAST is not set | ||
| 277 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 278 | CONFIG_IP_FIB_HASH=y | ||
| 279 | CONFIG_IP_PNP=y | ||
| 280 | # CONFIG_IP_PNP_DHCP is not set | ||
| 281 | CONFIG_IP_PNP_BOOTP=y | ||
| 282 | # CONFIG_IP_PNP_RARP is not set | ||
| 283 | # CONFIG_NET_IPIP is not set | ||
| 284 | # CONFIG_NET_IPGRE is not set | ||
| 285 | # CONFIG_ARPD is not set | ||
| 286 | # CONFIG_SYN_COOKIES is not set | ||
| 287 | # CONFIG_INET_AH is not set | ||
| 288 | # CONFIG_INET_ESP is not set | ||
| 289 | # CONFIG_INET_IPCOMP is not set | ||
| 290 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 291 | # CONFIG_INET_TUNNEL is not set | ||
| 292 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 293 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 294 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 295 | CONFIG_INET_DIAG=y | ||
| 296 | CONFIG_INET_TCP_DIAG=y | ||
| 297 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 298 | CONFIG_TCP_CONG_CUBIC=y | ||
| 299 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 300 | CONFIG_TCP_MD5SIG=y | ||
| 301 | # CONFIG_IPV6 is not set | ||
| 302 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 303 | # CONFIG_INET6_TUNNEL is not set | ||
| 304 | CONFIG_NETWORK_SECMARK=y | ||
| 305 | # CONFIG_NETFILTER is not set | ||
| 306 | |||
| 307 | # | ||
| 308 | # DCCP Configuration (EXPERIMENTAL) | ||
| 309 | # | ||
| 310 | # CONFIG_IP_DCCP is not set | ||
| 311 | |||
| 312 | # | ||
| 313 | # SCTP Configuration (EXPERIMENTAL) | ||
| 314 | # | ||
| 315 | # CONFIG_IP_SCTP is not set | ||
| 316 | |||
| 317 | # | ||
| 318 | # TIPC Configuration (EXPERIMENTAL) | ||
| 319 | # | ||
| 320 | # CONFIG_TIPC is not set | ||
| 321 | # CONFIG_ATM is not set | ||
| 322 | # CONFIG_BRIDGE is not set | ||
| 323 | # CONFIG_VLAN_8021Q is not set | ||
| 324 | # CONFIG_DECNET is not set | ||
| 325 | # CONFIG_LLC2 is not set | ||
| 326 | # CONFIG_IPX is not set | ||
| 327 | # CONFIG_ATALK is not set | ||
| 328 | # CONFIG_X25 is not set | ||
| 329 | # CONFIG_LAPB is not set | ||
| 330 | # CONFIG_ECONET is not set | ||
| 331 | # CONFIG_WAN_ROUTER is not set | ||
| 332 | |||
| 333 | # | ||
| 334 | # QoS and/or fair queueing | ||
| 335 | # | ||
| 336 | # CONFIG_NET_SCHED is not set | ||
| 337 | |||
| 338 | # | ||
| 339 | # Network testing | ||
| 340 | # | ||
| 341 | # CONFIG_NET_PKTGEN is not set | ||
| 342 | # CONFIG_HAMRADIO is not set | ||
| 343 | # CONFIG_IRDA is not set | ||
| 344 | # CONFIG_BT is not set | ||
| 345 | CONFIG_IEEE80211=y | ||
| 346 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 347 | CONFIG_IEEE80211_CRYPT_WEP=y | ||
| 348 | CONFIG_IEEE80211_CRYPT_CCMP=y | ||
| 349 | CONFIG_IEEE80211_SOFTMAC=y | ||
| 350 | # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set | ||
| 351 | CONFIG_WIRELESS_EXT=y | ||
| 352 | |||
| 353 | # | ||
| 354 | # Device Drivers | ||
| 355 | # | ||
| 356 | |||
| 357 | # | ||
| 358 | # Generic Driver Options | ||
| 359 | # | ||
| 360 | CONFIG_STANDALONE=y | ||
| 361 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 362 | CONFIG_FW_LOADER=y | ||
| 363 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 364 | |||
| 365 | # | ||
| 366 | # Connector - unified userspace <-> kernelspace linker | ||
| 367 | # | ||
| 368 | CONFIG_CONNECTOR=y | ||
| 369 | CONFIG_PROC_EVENTS=y | ||
| 370 | |||
| 371 | # | ||
| 372 | # Memory Technology Devices (MTD) | ||
| 373 | # | ||
| 374 | # CONFIG_MTD is not set | ||
| 375 | |||
| 376 | # | ||
| 377 | # Parallel port support | ||
| 378 | # | ||
| 379 | # CONFIG_PARPORT is not set | ||
| 380 | |||
| 381 | # | ||
| 382 | # Plug and Play support | ||
| 383 | # | ||
| 384 | # CONFIG_PNPACPI is not set | ||
| 385 | |||
| 386 | # | ||
| 387 | # Block devices | ||
| 388 | # | ||
| 389 | # CONFIG_BLK_CPQ_DA is not set | ||
| 390 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
| 391 | # CONFIG_BLK_DEV_DAC960 is not set | ||
| 392 | # CONFIG_BLK_DEV_UMEM is not set | ||
| 393 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 394 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 395 | # CONFIG_BLK_DEV_NBD is not set | ||
| 396 | # CONFIG_BLK_DEV_SX8 is not set | ||
| 397 | # CONFIG_BLK_DEV_RAM is not set | ||
| 398 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 399 | CONFIG_CDROM_PKTCDVD=y | ||
| 400 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | ||
| 401 | # CONFIG_CDROM_PKTCDVD_WCACHE is not set | ||
| 402 | CONFIG_ATA_OVER_ETH=y | ||
| 403 | |||
| 404 | # | ||
| 405 | # Misc devices | ||
| 406 | # | ||
| 407 | CONFIG_SGI_IOC4=y | ||
| 408 | # CONFIG_TIFM_CORE is not set | ||
| 409 | |||
| 410 | # | ||
| 411 | # ATA/ATAPI/MFM/RLL support | ||
| 412 | # | ||
| 413 | # CONFIG_IDE is not set | ||
| 414 | |||
| 415 | # | ||
| 416 | # SCSI device support | ||
| 417 | # | ||
| 418 | CONFIG_RAID_ATTRS=y | ||
| 419 | # CONFIG_SCSI is not set | ||
| 420 | # CONFIG_SCSI_NETLINK is not set | ||
| 421 | |||
| 422 | # | ||
| 423 | # Serial ATA (prod) and Parallel ATA (experimental) drivers | ||
| 424 | # | ||
| 425 | # CONFIG_ATA is not set | ||
| 426 | |||
| 427 | # | ||
| 428 | # Multi-device support (RAID and LVM) | ||
| 429 | # | ||
| 430 | # CONFIG_MD is not set | ||
| 431 | |||
| 432 | # | ||
| 433 | # Fusion MPT device support | ||
| 434 | # | ||
| 435 | # CONFIG_FUSION is not set | ||
| 436 | |||
| 437 | # | ||
| 438 | # IEEE 1394 (FireWire) support | ||
| 439 | # | ||
| 440 | # CONFIG_IEEE1394 is not set | ||
| 441 | |||
| 442 | # | ||
| 443 | # I2O device support | ||
| 444 | # | ||
| 445 | # CONFIG_I2O is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Network device support | ||
| 449 | # | ||
| 450 | CONFIG_NETDEVICES=y | ||
| 451 | # CONFIG_DUMMY is not set | ||
| 452 | # CONFIG_BONDING is not set | ||
| 453 | # CONFIG_EQUALIZER is not set | ||
| 454 | # CONFIG_TUN is not set | ||
| 455 | |||
| 456 | # | ||
| 457 | # ARCnet devices | ||
| 458 | # | ||
| 459 | # CONFIG_ARCNET is not set | ||
| 460 | |||
| 461 | # | ||
| 462 | # PHY device support | ||
| 463 | # | ||
| 464 | CONFIG_PHYLIB=y | ||
| 465 | |||
| 466 | # | ||
| 467 | # MII PHY device drivers | ||
| 468 | # | ||
| 469 | CONFIG_MARVELL_PHY=y | ||
| 470 | CONFIG_DAVICOM_PHY=y | ||
| 471 | CONFIG_QSEMI_PHY=y | ||
| 472 | CONFIG_LXT_PHY=y | ||
| 473 | CONFIG_CICADA_PHY=y | ||
| 474 | CONFIG_VITESSE_PHY=y | ||
| 475 | CONFIG_SMSC_PHY=y | ||
| 476 | # CONFIG_BROADCOM_PHY is not set | ||
| 477 | # CONFIG_FIXED_PHY is not set | ||
| 478 | |||
| 479 | # | ||
| 480 | # Ethernet (10 or 100Mbit) | ||
| 481 | # | ||
| 482 | CONFIG_NET_ETHERNET=y | ||
| 483 | CONFIG_MII=y | ||
| 484 | # CONFIG_HAPPYMEAL is not set | ||
| 485 | # CONFIG_SUNGEM is not set | ||
| 486 | # CONFIG_CASSINI is not set | ||
| 487 | # CONFIG_NET_VENDOR_3COM is not set | ||
| 488 | # CONFIG_DM9000 is not set | ||
| 489 | |||
| 490 | # | ||
| 491 | # Tulip family network device support | ||
| 492 | # | ||
| 493 | # CONFIG_NET_TULIP is not set | ||
| 494 | # CONFIG_HP100 is not set | ||
| 495 | CONFIG_NET_PCI=y | ||
| 496 | CONFIG_PCNET32=y | ||
| 497 | # CONFIG_PCNET32_NAPI is not set | ||
| 498 | # CONFIG_AMD8111_ETH is not set | ||
| 499 | # CONFIG_ADAPTEC_STARFIRE is not set | ||
| 500 | # CONFIG_B44 is not set | ||
| 501 | # CONFIG_FORCEDETH is not set | ||
| 502 | # CONFIG_DGRS is not set | ||
| 503 | # CONFIG_EEPRO100 is not set | ||
| 504 | # CONFIG_E100 is not set | ||
| 505 | # CONFIG_FEALNX is not set | ||
| 506 | # CONFIG_NATSEMI is not set | ||
| 507 | # CONFIG_NE2K_PCI is not set | ||
| 508 | # CONFIG_8139CP is not set | ||
| 509 | # CONFIG_8139TOO is not set | ||
| 510 | # CONFIG_SIS900 is not set | ||
| 511 | # CONFIG_EPIC100 is not set | ||
| 512 | # CONFIG_SUNDANCE is not set | ||
| 513 | # CONFIG_TLAN is not set | ||
| 514 | # CONFIG_VIA_RHINE is not set | ||
| 515 | # CONFIG_SC92031 is not set | ||
| 516 | |||
| 517 | # | ||
| 518 | # Ethernet (1000 Mbit) | ||
| 519 | # | ||
| 520 | # CONFIG_ACENIC is not set | ||
| 521 | # CONFIG_DL2K is not set | ||
| 522 | # CONFIG_E1000 is not set | ||
| 523 | # CONFIG_NS83820 is not set | ||
| 524 | # CONFIG_HAMACHI is not set | ||
| 525 | # CONFIG_YELLOWFIN is not set | ||
| 526 | # CONFIG_R8169 is not set | ||
| 527 | # CONFIG_SIS190 is not set | ||
| 528 | # CONFIG_SKGE is not set | ||
| 529 | # CONFIG_SKY2 is not set | ||
| 530 | # CONFIG_SK98LIN is not set | ||
| 531 | # CONFIG_VIA_VELOCITY is not set | ||
| 532 | # CONFIG_TIGON3 is not set | ||
| 533 | # CONFIG_BNX2 is not set | ||
| 534 | CONFIG_QLA3XXX=y | ||
| 535 | # CONFIG_ATL1 is not set | ||
| 536 | |||
| 537 | # | ||
| 538 | # Ethernet (10000 Mbit) | ||
| 539 | # | ||
| 540 | # CONFIG_CHELSIO_T1 is not set | ||
| 541 | CONFIG_CHELSIO_T3=y | ||
| 542 | # CONFIG_IXGB is not set | ||
| 543 | # CONFIG_S2IO is not set | ||
| 544 | # CONFIG_MYRI10GE is not set | ||
| 545 | CONFIG_NETXEN_NIC=y | ||
| 546 | |||
| 547 | # | ||
| 548 | # Token Ring devices | ||
| 549 | # | ||
| 550 | # CONFIG_TR is not set | ||
| 551 | |||
| 552 | # | ||
| 553 | # Wireless LAN (non-hamradio) | ||
| 554 | # | ||
| 555 | # CONFIG_NET_RADIO is not set | ||
| 556 | |||
| 557 | # | ||
| 558 | # Wan interfaces | ||
| 559 | # | ||
| 560 | # CONFIG_WAN is not set | ||
| 561 | # CONFIG_FDDI is not set | ||
| 562 | # CONFIG_HIPPI is not set | ||
| 563 | # CONFIG_PPP is not set | ||
| 564 | # CONFIG_SLIP is not set | ||
| 565 | # CONFIG_SHAPER is not set | ||
| 566 | # CONFIG_NETCONSOLE is not set | ||
| 567 | # CONFIG_NETPOLL is not set | ||
| 568 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 569 | |||
| 570 | # | ||
| 571 | # ISDN subsystem | ||
| 572 | # | ||
| 573 | # CONFIG_ISDN is not set | ||
| 574 | |||
| 575 | # | ||
| 576 | # Telephony Support | ||
| 577 | # | ||
| 578 | # CONFIG_PHONE is not set | ||
| 579 | |||
| 580 | # | ||
| 581 | # Input device support | ||
| 582 | # | ||
| 583 | CONFIG_INPUT=y | ||
| 584 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 585 | |||
| 586 | # | ||
| 587 | # Userland interfaces | ||
| 588 | # | ||
| 589 | CONFIG_INPUT_MOUSEDEV=y | ||
| 590 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 591 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 592 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 593 | # CONFIG_INPUT_JOYDEV is not set | ||
| 594 | # CONFIG_INPUT_TSDEV is not set | ||
| 595 | # CONFIG_INPUT_EVDEV is not set | ||
| 596 | # CONFIG_INPUT_EVBUG is not set | ||
| 597 | |||
| 598 | # | ||
| 599 | # Input Device Drivers | ||
| 600 | # | ||
| 601 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 602 | # CONFIG_INPUT_MOUSE is not set | ||
| 603 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 604 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 605 | # CONFIG_INPUT_MISC is not set | ||
| 606 | |||
| 607 | # | ||
| 608 | # Hardware I/O ports | ||
| 609 | # | ||
| 610 | CONFIG_SERIO=y | ||
| 611 | # CONFIG_SERIO_I8042 is not set | ||
| 612 | CONFIG_SERIO_SERPORT=y | ||
| 613 | # CONFIG_SERIO_PCIPS2 is not set | ||
| 614 | # CONFIG_SERIO_LIBPS2 is not set | ||
| 615 | CONFIG_SERIO_RAW=y | ||
| 616 | # CONFIG_GAMEPORT is not set | ||
| 617 | |||
| 618 | # | ||
| 619 | # Character devices | ||
| 620 | # | ||
| 621 | CONFIG_VT=y | ||
| 622 | CONFIG_VT_CONSOLE=y | ||
| 623 | CONFIG_HW_CONSOLE=y | ||
| 624 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 625 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 626 | |||
| 627 | # | ||
| 628 | # Serial drivers | ||
| 629 | # | ||
| 630 | CONFIG_SERIAL_8250=y | ||
| 631 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 632 | CONFIG_SERIAL_8250_PCI=y | ||
| 633 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
| 634 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 635 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 636 | |||
| 637 | # | ||
| 638 | # Non-8250 serial port support | ||
| 639 | # | ||
| 640 | CONFIG_SERIAL_CORE=y | ||
| 641 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 642 | # CONFIG_SERIAL_JSM is not set | ||
| 643 | CONFIG_UNIX98_PTYS=y | ||
| 644 | CONFIG_LEGACY_PTYS=y | ||
| 645 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 646 | |||
| 647 | # | ||
| 648 | # IPMI | ||
| 649 | # | ||
| 650 | # CONFIG_IPMI_HANDLER is not set | ||
| 651 | |||
| 652 | # | ||
| 653 | # Watchdog Cards | ||
| 654 | # | ||
| 655 | # CONFIG_WATCHDOG is not set | ||
| 656 | # CONFIG_HW_RANDOM is not set | ||
| 657 | # CONFIG_RTC is not set | ||
| 658 | # CONFIG_GEN_RTC is not set | ||
| 659 | # CONFIG_DTLK is not set | ||
| 660 | # CONFIG_R3964 is not set | ||
| 661 | # CONFIG_APPLICOM is not set | ||
| 662 | # CONFIG_DRM is not set | ||
| 663 | # CONFIG_RAW_DRIVER is not set | ||
| 664 | |||
| 665 | # | ||
| 666 | # TPM devices | ||
| 667 | # | ||
| 668 | # CONFIG_TCG_TPM is not set | ||
| 669 | |||
| 670 | # | ||
| 671 | # I2C support | ||
| 672 | # | ||
| 673 | # CONFIG_I2C is not set | ||
| 674 | |||
| 675 | # | ||
| 676 | # SPI support | ||
| 677 | # | ||
| 678 | # CONFIG_SPI is not set | ||
| 679 | # CONFIG_SPI_MASTER is not set | ||
| 680 | |||
| 681 | # | ||
| 682 | # Dallas's 1-wire bus | ||
| 683 | # | ||
| 684 | # CONFIG_W1 is not set | ||
| 685 | |||
| 686 | # | ||
| 687 | # Hardware Monitoring support | ||
| 688 | # | ||
| 689 | # CONFIG_HWMON is not set | ||
| 690 | # CONFIG_HWMON_VID is not set | ||
| 691 | |||
| 692 | # | ||
| 693 | # Multimedia devices | ||
| 694 | # | ||
| 695 | # CONFIG_VIDEO_DEV is not set | ||
| 696 | |||
| 697 | # | ||
| 698 | # Digital Video Broadcasting Devices | ||
| 699 | # | ||
| 700 | # CONFIG_DVB is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # Graphics support | ||
| 704 | # | ||
| 705 | # CONFIG_FIRMWARE_EDID is not set | ||
| 706 | # CONFIG_FB is not set | ||
| 707 | |||
| 708 | # | ||
| 709 | # Console display driver support | ||
| 710 | # | ||
| 711 | # CONFIG_VGA_CONSOLE is not set | ||
| 712 | CONFIG_DUMMY_CONSOLE=y | ||
| 713 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 714 | |||
| 715 | # | ||
| 716 | # Sound | ||
| 717 | # | ||
| 718 | # CONFIG_SOUND is not set | ||
| 719 | |||
| 720 | # | ||
| 721 | # HID Devices | ||
| 722 | # | ||
| 723 | # CONFIG_HID is not set | ||
| 724 | |||
| 725 | # | ||
| 726 | # USB support | ||
| 727 | # | ||
| 728 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 729 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 730 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 731 | # CONFIG_USB is not set | ||
| 732 | |||
| 733 | # | ||
| 734 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 735 | # | ||
| 736 | |||
| 737 | # | ||
| 738 | # USB Gadget Support | ||
| 739 | # | ||
| 740 | # CONFIG_USB_GADGET is not set | ||
| 741 | |||
| 742 | # | ||
| 743 | # MMC/SD Card support | ||
| 744 | # | ||
| 745 | # CONFIG_MMC is not set | ||
| 746 | |||
| 747 | # | ||
| 748 | # LED devices | ||
| 749 | # | ||
| 750 | # CONFIG_NEW_LEDS is not set | ||
| 751 | |||
| 752 | # | ||
| 753 | # LED drivers | ||
| 754 | # | ||
| 755 | |||
| 756 | # | ||
| 757 | # LED Triggers | ||
| 758 | # | ||
| 759 | |||
| 760 | # | ||
| 761 | # InfiniBand support | ||
| 762 | # | ||
| 763 | # CONFIG_INFINIBAND is not set | ||
| 764 | |||
| 765 | # | ||
| 766 | # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) | ||
| 767 | # | ||
| 768 | |||
| 769 | # | ||
| 770 | # Real Time Clock | ||
| 771 | # | ||
| 772 | # CONFIG_RTC_CLASS is not set | ||
| 773 | |||
| 774 | # | ||
| 775 | # DMA Engine support | ||
| 776 | # | ||
| 777 | # CONFIG_DMA_ENGINE is not set | ||
| 778 | |||
| 779 | # | ||
| 780 | # DMA Clients | ||
| 781 | # | ||
| 782 | |||
| 783 | # | ||
| 784 | # DMA Devices | ||
| 785 | # | ||
| 786 | |||
| 787 | # | ||
| 788 | # Auxiliary Display support | ||
| 789 | # | ||
| 790 | |||
| 791 | # | ||
| 792 | # Virtualization | ||
| 793 | # | ||
| 794 | |||
| 795 | # | ||
| 796 | # File systems | ||
| 797 | # | ||
| 798 | CONFIG_EXT2_FS=y | ||
| 799 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 800 | # CONFIG_EXT2_FS_XIP is not set | ||
| 801 | # CONFIG_EXT3_FS is not set | ||
| 802 | # CONFIG_EXT4DEV_FS is not set | ||
| 803 | # CONFIG_REISERFS_FS is not set | ||
| 804 | # CONFIG_JFS_FS is not set | ||
| 805 | # CONFIG_FS_POSIX_ACL is not set | ||
| 806 | # CONFIG_XFS_FS is not set | ||
| 807 | # CONFIG_GFS2_FS is not set | ||
| 808 | # CONFIG_OCFS2_FS is not set | ||
| 809 | # CONFIG_MINIX_FS is not set | ||
| 810 | # CONFIG_ROMFS_FS is not set | ||
| 811 | CONFIG_INOTIFY=y | ||
| 812 | CONFIG_INOTIFY_USER=y | ||
| 813 | # CONFIG_QUOTA is not set | ||
| 814 | CONFIG_DNOTIFY=y | ||
| 815 | CONFIG_AUTOFS_FS=y | ||
| 816 | CONFIG_AUTOFS4_FS=y | ||
| 817 | CONFIG_FUSE_FS=y | ||
| 818 | |||
| 819 | # | ||
| 820 | # CD-ROM/DVD Filesystems | ||
| 821 | # | ||
| 822 | # CONFIG_ISO9660_FS is not set | ||
| 823 | # CONFIG_UDF_FS is not set | ||
| 824 | |||
| 825 | # | ||
| 826 | # DOS/FAT/NT Filesystems | ||
| 827 | # | ||
| 828 | # CONFIG_MSDOS_FS is not set | ||
| 829 | # CONFIG_VFAT_FS is not set | ||
| 830 | # CONFIG_NTFS_FS is not set | ||
| 831 | |||
| 832 | # | ||
| 833 | # Pseudo filesystems | ||
| 834 | # | ||
| 835 | CONFIG_PROC_FS=y | ||
| 836 | CONFIG_PROC_KCORE=y | ||
| 837 | CONFIG_PROC_SYSCTL=y | ||
| 838 | CONFIG_SYSFS=y | ||
| 839 | # CONFIG_TMPFS is not set | ||
| 840 | # CONFIG_HUGETLB_PAGE is not set | ||
| 841 | CONFIG_RAMFS=y | ||
| 842 | CONFIG_CONFIGFS_FS=y | ||
| 843 | |||
| 844 | # | ||
| 845 | # Miscellaneous filesystems | ||
| 846 | # | ||
| 847 | # CONFIG_ADFS_FS is not set | ||
| 848 | # CONFIG_AFFS_FS is not set | ||
| 849 | # CONFIG_ECRYPT_FS is not set | ||
| 850 | # CONFIG_HFS_FS is not set | ||
| 851 | # CONFIG_HFSPLUS_FS is not set | ||
| 852 | # CONFIG_BEFS_FS is not set | ||
| 853 | # CONFIG_BFS_FS is not set | ||
| 854 | # CONFIG_EFS_FS is not set | ||
| 855 | # CONFIG_CRAMFS is not set | ||
| 856 | # CONFIG_VXFS_FS is not set | ||
| 857 | # CONFIG_HPFS_FS is not set | ||
| 858 | # CONFIG_QNX4FS_FS is not set | ||
| 859 | # CONFIG_SYSV_FS is not set | ||
| 860 | # CONFIG_UFS_FS is not set | ||
| 861 | |||
| 862 | # | ||
| 863 | # Network File Systems | ||
| 864 | # | ||
| 865 | CONFIG_NFS_FS=y | ||
| 866 | # CONFIG_NFS_V3 is not set | ||
| 867 | # CONFIG_NFS_V4 is not set | ||
| 868 | # CONFIG_NFS_DIRECTIO is not set | ||
| 869 | CONFIG_NFSD=y | ||
| 870 | # CONFIG_NFSD_V3 is not set | ||
| 871 | # CONFIG_NFSD_TCP is not set | ||
| 872 | CONFIG_ROOT_NFS=y | ||
| 873 | CONFIG_LOCKD=y | ||
| 874 | CONFIG_EXPORTFS=y | ||
| 875 | CONFIG_NFS_COMMON=y | ||
| 876 | CONFIG_SUNRPC=y | ||
| 877 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 878 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 879 | # CONFIG_SMB_FS is not set | ||
| 880 | # CONFIG_CIFS is not set | ||
| 881 | # CONFIG_NCP_FS is not set | ||
| 882 | # CONFIG_CODA_FS is not set | ||
| 883 | # CONFIG_AFS_FS is not set | ||
| 884 | # CONFIG_9P_FS is not set | ||
| 885 | |||
| 886 | # | ||
| 887 | # Partition Types | ||
| 888 | # | ||
| 889 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 890 | CONFIG_MSDOS_PARTITION=y | ||
| 891 | |||
| 892 | # | ||
| 893 | # Native Language Support | ||
| 894 | # | ||
| 895 | # CONFIG_NLS is not set | ||
| 896 | |||
| 897 | # | ||
| 898 | # Distributed Lock Manager | ||
| 899 | # | ||
| 900 | CONFIG_DLM=y | ||
| 901 | CONFIG_DLM_TCP=y | ||
| 902 | # CONFIG_DLM_SCTP is not set | ||
| 903 | # CONFIG_DLM_DEBUG is not set | ||
| 904 | |||
| 905 | # | ||
| 906 | # Profiling support | ||
| 907 | # | ||
| 908 | # CONFIG_PROFILING is not set | ||
| 909 | |||
| 910 | # | ||
| 911 | # Kernel hacking | ||
| 912 | # | ||
| 913 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 914 | # CONFIG_PRINTK_TIME is not set | ||
| 915 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 916 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 917 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 918 | # CONFIG_DEBUG_FS is not set | ||
| 919 | # CONFIG_HEADERS_CHECK is not set | ||
| 920 | # CONFIG_DEBUG_KERNEL is not set | ||
| 921 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 922 | CONFIG_CROSSCOMPILE=y | ||
| 923 | CONFIG_CMDLINE="ip=any" | ||
| 924 | CONFIG_SYS_SUPPORTS_KGDB=y | ||
| 925 | |||
| 926 | # | ||
| 927 | # Security options | ||
| 928 | # | ||
| 929 | CONFIG_KEYS=y | ||
| 930 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | ||
| 931 | # CONFIG_SECURITY is not set | ||
| 932 | |||
| 933 | # | ||
| 934 | # Cryptographic options | ||
| 935 | # | ||
| 936 | CONFIG_CRYPTO=y | ||
| 937 | CONFIG_CRYPTO_ALGAPI=y | ||
| 938 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 939 | CONFIG_CRYPTO_HASH=y | ||
| 940 | CONFIG_CRYPTO_MANAGER=y | ||
| 941 | CONFIG_CRYPTO_HMAC=y | ||
| 942 | CONFIG_CRYPTO_XCBC=y | ||
| 943 | CONFIG_CRYPTO_NULL=y | ||
| 944 | CONFIG_CRYPTO_MD4=y | ||
| 945 | CONFIG_CRYPTO_MD5=y | ||
| 946 | CONFIG_CRYPTO_SHA1=y | ||
| 947 | CONFIG_CRYPTO_SHA256=y | ||
| 948 | CONFIG_CRYPTO_SHA512=y | ||
| 949 | CONFIG_CRYPTO_WP512=y | ||
| 950 | CONFIG_CRYPTO_TGR192=y | ||
| 951 | CONFIG_CRYPTO_GF128MUL=y | ||
| 952 | CONFIG_CRYPTO_ECB=y | ||
| 953 | CONFIG_CRYPTO_CBC=y | ||
| 954 | CONFIG_CRYPTO_PCBC=y | ||
| 955 | CONFIG_CRYPTO_LRW=y | ||
| 956 | CONFIG_CRYPTO_DES=y | ||
| 957 | CONFIG_CRYPTO_FCRYPT=y | ||
| 958 | CONFIG_CRYPTO_BLOWFISH=y | ||
| 959 | CONFIG_CRYPTO_TWOFISH=y | ||
| 960 | CONFIG_CRYPTO_TWOFISH_COMMON=y | ||
| 961 | CONFIG_CRYPTO_SERPENT=y | ||
| 962 | CONFIG_CRYPTO_AES=y | ||
| 963 | CONFIG_CRYPTO_CAST5=y | ||
| 964 | CONFIG_CRYPTO_CAST6=y | ||
| 965 | CONFIG_CRYPTO_TEA=y | ||
| 966 | CONFIG_CRYPTO_ARC4=y | ||
| 967 | CONFIG_CRYPTO_KHAZAD=y | ||
| 968 | CONFIG_CRYPTO_ANUBIS=y | ||
| 969 | CONFIG_CRYPTO_DEFLATE=y | ||
| 970 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 971 | CONFIG_CRYPTO_CRC32C=y | ||
| 972 | CONFIG_CRYPTO_CAMELLIA=y | ||
| 973 | |||
| 974 | # | ||
| 975 | # Hardware crypto devices | ||
| 976 | # | ||
| 977 | |||
| 978 | # | ||
| 979 | # Library routines | ||
| 980 | # | ||
| 981 | CONFIG_BITREVERSE=y | ||
| 982 | # CONFIG_CRC_CCITT is not set | ||
| 983 | CONFIG_CRC16=y | ||
| 984 | CONFIG_CRC32=y | ||
| 985 | CONFIG_LIBCRC32C=y | ||
| 986 | CONFIG_ZLIB_INFLATE=y | ||
| 987 | CONFIG_ZLIB_DEFLATE=y | ||
| 988 | CONFIG_PLIST=y | ||
| 989 | CONFIG_HAS_IOMEM=y | ||
| 990 | CONFIG_HAS_IOPORT=y | ||
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index d6e3fffbc80d..2fb350432669 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_MACH_DECSTATION=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 78f5004fb721..5467d750b6eb 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | CONFIG_MACH_VR41XX=y | 38 | CONFIG_MACH_VR41XX=y |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index b29bff0f56c3..d73d965f7615 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 69810592aa6b..17a866057fd4 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_BASLER_EXCITE=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 6ab94d8cf08b..4ef39a0527cc 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig | |||
| @@ -19,10 +19,8 @@ CONFIG_LEMOTE_FULONG=y | |||
| 19 | # CONFIG_MIPS_SEAD is not set | 19 | # CONFIG_MIPS_SEAD is not set |
| 20 | # CONFIG_WR_PPMC is not set | 20 | # CONFIG_WR_PPMC is not set |
| 21 | # CONFIG_MIPS_SIM is not set | 21 | # CONFIG_MIPS_SIM is not set |
| 22 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 23 | # CONFIG_PNX8550_JBS is not set | 22 | # CONFIG_PNX8550_JBS is not set |
| 24 | # CONFIG_PNX8550_STB810 is not set | 23 | # CONFIG_PNX8550_STB810 is not set |
| 25 | # CONFIG_DDB5477 is not set | ||
| 26 | # CONFIG_MACH_VR41XX is not set | 24 | # CONFIG_MACH_VR41XX is not set |
| 27 | # CONFIG_PMC_YOSEMITE is not set | 25 | # CONFIG_PMC_YOSEMITE is not set |
| 28 | # CONFIG_QEMU is not set | 26 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index 405c9f505a77..934d8a008936 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index a9dcbcf563cb..eb35f7518d06 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index a040459bec11..47f49b60c5d6 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index 8a0b4ac5283d..fa655e247ecc 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_MACH_JAZZ=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 9a25e770abd8..95a72d2750ef 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 546cb243fd09..fbfa5685887c 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_MIPS_MALTA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 6abad6f88313..86dcb7464353 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | CONFIG_MIPS_SIM=y | 33 | CONFIG_MIPS_SIM=y |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 4981ce425d82..239810b6c88d 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | CONFIG_MACH_VR41XX=y | 38 | CONFIG_MACH_VR41XX=y |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index adca5f7ba533..69278999c9a2 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | CONFIG_PMC_MSP=y | 39 | CONFIG_PMC_MSP=y |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig deleted file mode 100644 index e1db1fb80cd0..000000000000 --- a/arch/mips/configs/ocelot_defconfig +++ /dev/null | |||
| @@ -1,919 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.20 | ||
| 4 | # Tue Feb 20 21:47:36 2007 | ||
| 5 | # | ||
| 6 | CONFIG_MIPS=y | ||
| 7 | |||
| 8 | # | ||
| 9 | # Machine selection | ||
| 10 | # | ||
| 11 | CONFIG_ZONE_DMA=y | ||
| 12 | # CONFIG_MIPS_MTX1 is not set | ||
| 13 | # CONFIG_MIPS_BOSPORUS is not set | ||
| 14 | # CONFIG_MIPS_PB1000 is not set | ||
| 15 | # CONFIG_MIPS_PB1100 is not set | ||
| 16 | # CONFIG_MIPS_PB1500 is not set | ||
| 17 | # CONFIG_MIPS_PB1550 is not set | ||
| 18 | # CONFIG_MIPS_PB1200 is not set | ||
| 19 | # CONFIG_MIPS_DB1000 is not set | ||
| 20 | # CONFIG_MIPS_DB1100 is not set | ||
| 21 | # CONFIG_MIPS_DB1500 is not set | ||
| 22 | # CONFIG_MIPS_DB1550 is not set | ||
| 23 | # CONFIG_MIPS_DB1200 is not set | ||
| 24 | # CONFIG_MIPS_MIRAGE is not set | ||
| 25 | # CONFIG_BASLER_EXCITE is not set | ||
| 26 | # CONFIG_MIPS_COBALT is not set | ||
| 27 | # CONFIG_MACH_DECSTATION is not set | ||
| 28 | # CONFIG_MACH_JAZZ is not set | ||
| 29 | # CONFIG_MIPS_ATLAS is not set | ||
| 30 | # CONFIG_MIPS_MALTA is not set | ||
| 31 | # CONFIG_MIPS_SEAD is not set | ||
| 32 | # CONFIG_WR_PPMC is not set | ||
| 33 | # CONFIG_MIPS_SIM is not set | ||
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | ||
| 35 | CONFIG_MOMENCO_OCELOT=y | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | ||
| 38 | # CONFIG_PNX8550_JBS is not set | ||
| 39 | # CONFIG_PNX8550_STB810 is not set | ||
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | ||
| 42 | # CONFIG_PMC_YOSEMITE is not set | ||
| 43 | # CONFIG_QEMU is not set | ||
| 44 | # CONFIG_MARKEINS is not set | ||
| 45 | # CONFIG_SGI_IP22 is not set | ||
| 46 | # CONFIG_SGI_IP27 is not set | ||
| 47 | # CONFIG_SGI_IP32 is not set | ||
| 48 | # CONFIG_SIBYTE_BIGSUR is not set | ||
| 49 | # CONFIG_SIBYTE_SWARM is not set | ||
| 50 | # CONFIG_SIBYTE_SENTOSA is not set | ||
| 51 | # CONFIG_SIBYTE_RHONE is not set | ||
| 52 | # CONFIG_SIBYTE_CARMEL is not set | ||
| 53 | # CONFIG_SIBYTE_PTSWARM is not set | ||
| 54 | # CONFIG_SIBYTE_LITTLESUR is not set | ||
| 55 | # CONFIG_SIBYTE_CRHINE is not set | ||
| 56 | # CONFIG_SIBYTE_CRHONE is not set | ||
| 57 | # CONFIG_SNI_RM is not set | ||
| 58 | # CONFIG_TOSHIBA_JMR3927 is not set | ||
| 59 | # CONFIG_TOSHIBA_RBTX4927 is not set | ||
| 60 | # CONFIG_TOSHIBA_RBTX4938 is not set | ||
| 61 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 62 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 63 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 64 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
| 65 | CONFIG_GENERIC_HWEIGHT=y | ||
| 66 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 67 | CONFIG_GENERIC_TIME=y | ||
| 68 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | ||
| 69 | # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set | ||
| 70 | CONFIG_DMA_NONCOHERENT=y | ||
| 71 | CONFIG_DMA_NEED_PCI_MAP_STATE=y | ||
| 72 | CONFIG_CPU_BIG_ENDIAN=y | ||
| 73 | # CONFIG_CPU_LITTLE_ENDIAN is not set | ||
| 74 | CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y | ||
| 75 | CONFIG_IRQ_CPU=y | ||
| 76 | CONFIG_IRQ_CPU_RM7K=y | ||
| 77 | CONFIG_MIPS_GT64120=y | ||
| 78 | CONFIG_SWAP_IO_SPACE=y | ||
| 79 | # CONFIG_SYSCLK_75 is not set | ||
| 80 | # CONFIG_SYSCLK_83 is not set | ||
| 81 | CONFIG_SYSCLK_100=y | ||
| 82 | CONFIG_MIPS_L1_CACHE_SHIFT=5 | ||
| 83 | |||
| 84 | # | ||
| 85 | # CPU selection | ||
| 86 | # | ||
| 87 | # CONFIG_CPU_MIPS32_R1 is not set | ||
| 88 | # CONFIG_CPU_MIPS32_R2 is not set | ||
| 89 | # CONFIG_CPU_MIPS64_R1 is not set | ||
| 90 | # CONFIG_CPU_MIPS64_R2 is not set | ||
| 91 | # CONFIG_CPU_R3000 is not set | ||
| 92 | # CONFIG_CPU_TX39XX is not set | ||
| 93 | # CONFIG_CPU_VR41XX is not set | ||
| 94 | # CONFIG_CPU_R4300 is not set | ||
| 95 | # CONFIG_CPU_R4X00 is not set | ||
| 96 | # CONFIG_CPU_TX49XX is not set | ||
| 97 | # CONFIG_CPU_R5000 is not set | ||
| 98 | # CONFIG_CPU_R5432 is not set | ||
| 99 | # CONFIG_CPU_R6000 is not set | ||
| 100 | # CONFIG_CPU_NEVADA is not set | ||
| 101 | # CONFIG_CPU_R8000 is not set | ||
| 102 | # CONFIG_CPU_R10000 is not set | ||
| 103 | CONFIG_CPU_RM7000=y | ||
| 104 | # CONFIG_CPU_RM9000 is not set | ||
| 105 | # CONFIG_CPU_SB1 is not set | ||
| 106 | CONFIG_SYS_HAS_CPU_RM7000=y | ||
| 107 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y | ||
| 108 | CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y | ||
| 109 | CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y | ||
| 110 | CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y | ||
| 111 | |||
| 112 | # | ||
| 113 | # Kernel type | ||
| 114 | # | ||
| 115 | CONFIG_32BIT=y | ||
| 116 | # CONFIG_64BIT is not set | ||
| 117 | CONFIG_PAGE_SIZE_4KB=y | ||
| 118 | # CONFIG_PAGE_SIZE_8KB is not set | ||
| 119 | # CONFIG_PAGE_SIZE_16KB is not set | ||
| 120 | # CONFIG_PAGE_SIZE_64KB is not set | ||
| 121 | CONFIG_BOARD_SCACHE=y | ||
| 122 | CONFIG_RM7000_CPU_SCACHE=y | ||
| 123 | CONFIG_CPU_HAS_PREFETCH=y | ||
| 124 | CONFIG_MIPS_MT_DISABLED=y | ||
| 125 | # CONFIG_MIPS_MT_SMP is not set | ||
| 126 | # CONFIG_MIPS_MT_SMTC is not set | ||
| 127 | # CONFIG_MIPS_VPE_LOADER is not set | ||
| 128 | # CONFIG_64BIT_PHYS_ADDR is not set | ||
| 129 | CONFIG_CPU_HAS_LLSC=y | ||
| 130 | CONFIG_CPU_HAS_SYNC=y | ||
| 131 | CONFIG_GENERIC_HARDIRQS=y | ||
| 132 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 133 | CONFIG_CPU_SUPPORTS_HIGHMEM=y | ||
| 134 | CONFIG_ARCH_FLATMEM_ENABLE=y | ||
| 135 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 136 | CONFIG_FLATMEM_MANUAL=y | ||
| 137 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 138 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 139 | CONFIG_FLATMEM=y | ||
| 140 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 141 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 142 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 143 | # CONFIG_RESOURCES_64BIT is not set | ||
| 144 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 145 | # CONFIG_HZ_48 is not set | ||
| 146 | # CONFIG_HZ_100 is not set | ||
| 147 | # CONFIG_HZ_128 is not set | ||
| 148 | # CONFIG_HZ_250 is not set | ||
| 149 | # CONFIG_HZ_256 is not set | ||
| 150 | CONFIG_HZ_1000=y | ||
| 151 | # CONFIG_HZ_1024 is not set | ||
| 152 | CONFIG_SYS_SUPPORTS_ARBIT_HZ=y | ||
| 153 | CONFIG_HZ=1000 | ||
| 154 | CONFIG_PREEMPT_NONE=y | ||
| 155 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 156 | # CONFIG_PREEMPT is not set | ||
| 157 | # CONFIG_KEXEC is not set | ||
| 158 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 159 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 160 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 161 | |||
| 162 | # | ||
| 163 | # Code maturity level options | ||
| 164 | # | ||
| 165 | CONFIG_EXPERIMENTAL=y | ||
| 166 | CONFIG_BROKEN_ON_SMP=y | ||
| 167 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 168 | |||
| 169 | # | ||
| 170 | # General setup | ||
| 171 | # | ||
| 172 | CONFIG_LOCALVERSION="" | ||
| 173 | CONFIG_LOCALVERSION_AUTO=y | ||
| 174 | CONFIG_SWAP=y | ||
| 175 | CONFIG_SYSVIPC=y | ||
| 176 | # CONFIG_IPC_NS is not set | ||
| 177 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 178 | # CONFIG_POSIX_MQUEUE is not set | ||
| 179 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 180 | # CONFIG_TASKSTATS is not set | ||
| 181 | # CONFIG_UTS_NS is not set | ||
| 182 | # CONFIG_AUDIT is not set | ||
| 183 | # CONFIG_IKCONFIG is not set | ||
| 184 | CONFIG_SYSFS_DEPRECATED=y | ||
| 185 | CONFIG_RELAY=y | ||
| 186 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 187 | CONFIG_SYSCTL=y | ||
| 188 | CONFIG_EMBEDDED=y | ||
| 189 | CONFIG_SYSCTL_SYSCALL=y | ||
| 190 | CONFIG_KALLSYMS=y | ||
| 191 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 192 | # CONFIG_HOTPLUG is not set | ||
| 193 | CONFIG_PRINTK=y | ||
| 194 | CONFIG_BUG=y | ||
| 195 | CONFIG_ELF_CORE=y | ||
| 196 | CONFIG_BASE_FULL=y | ||
| 197 | CONFIG_FUTEX=y | ||
| 198 | CONFIG_EPOLL=y | ||
| 199 | CONFIG_SHMEM=y | ||
| 200 | CONFIG_SLAB=y | ||
| 201 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 202 | CONFIG_RT_MUTEXES=y | ||
| 203 | # CONFIG_TINY_SHMEM is not set | ||
| 204 | CONFIG_BASE_SMALL=0 | ||
| 205 | # CONFIG_SLOB is not set | ||
| 206 | |||
| 207 | # | ||
| 208 | # Loadable module support | ||
| 209 | # | ||
| 210 | # CONFIG_MODULES is not set | ||
| 211 | |||
| 212 | # | ||
| 213 | # Block layer | ||
| 214 | # | ||
| 215 | CONFIG_BLOCK=y | ||
| 216 | # CONFIG_LBD is not set | ||
| 217 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 218 | # CONFIG_LSF is not set | ||
| 219 | |||
| 220 | # | ||
| 221 | # IO Schedulers | ||
| 222 | # | ||
| 223 | CONFIG_IOSCHED_NOOP=y | ||
| 224 | CONFIG_IOSCHED_AS=y | ||
| 225 | CONFIG_IOSCHED_DEADLINE=y | ||
| 226 | CONFIG_IOSCHED_CFQ=y | ||
| 227 | CONFIG_DEFAULT_AS=y | ||
| 228 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 229 | # CONFIG_DEFAULT_CFQ is not set | ||
| 230 | # CONFIG_DEFAULT_NOOP is not set | ||
| 231 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 232 | |||
| 233 | # | ||
| 234 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) | ||
| 235 | # | ||
| 236 | CONFIG_HW_HAS_PCI=y | ||
| 237 | # CONFIG_PCI is not set | ||
| 238 | CONFIG_MMU=y | ||
| 239 | |||
| 240 | # | ||
| 241 | # PCCARD (PCMCIA/CardBus) support | ||
| 242 | # | ||
| 243 | |||
| 244 | # | ||
| 245 | # PCI Hotplug Support | ||
| 246 | # | ||
| 247 | |||
| 248 | # | ||
| 249 | # Executable file formats | ||
| 250 | # | ||
| 251 | CONFIG_BINFMT_ELF=y | ||
| 252 | # CONFIG_BINFMT_MISC is not set | ||
| 253 | CONFIG_TRAD_SIGNALS=y | ||
| 254 | |||
| 255 | # | ||
| 256 | # Power management options | ||
| 257 | # | ||
| 258 | CONFIG_PM=y | ||
| 259 | # CONFIG_PM_LEGACY is not set | ||
| 260 | # CONFIG_PM_DEBUG is not set | ||
| 261 | # CONFIG_PM_SYSFS_DEPRECATED is not set | ||
| 262 | |||
| 263 | # | ||
| 264 | # Networking | ||
| 265 | # | ||
| 266 | CONFIG_NET=y | ||
| 267 | |||
| 268 | # | ||
| 269 | # Networking options | ||
| 270 | # | ||
| 271 | # CONFIG_NETDEBUG is not set | ||
| 272 | # CONFIG_PACKET is not set | ||
| 273 | CONFIG_UNIX=y | ||
| 274 | CONFIG_XFRM=y | ||
| 275 | CONFIG_XFRM_USER=y | ||
| 276 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 277 | CONFIG_XFRM_MIGRATE=y | ||
| 278 | CONFIG_NET_KEY=y | ||
| 279 | CONFIG_NET_KEY_MIGRATE=y | ||
| 280 | CONFIG_INET=y | ||
| 281 | # CONFIG_IP_MULTICAST is not set | ||
| 282 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 283 | CONFIG_IP_FIB_HASH=y | ||
| 284 | CONFIG_IP_PNP=y | ||
| 285 | # CONFIG_IP_PNP_DHCP is not set | ||
| 286 | CONFIG_IP_PNP_BOOTP=y | ||
| 287 | # CONFIG_IP_PNP_RARP is not set | ||
| 288 | # CONFIG_NET_IPIP is not set | ||
| 289 | # CONFIG_NET_IPGRE is not set | ||
| 290 | # CONFIG_ARPD is not set | ||
| 291 | # CONFIG_SYN_COOKIES is not set | ||
| 292 | # CONFIG_INET_AH is not set | ||
| 293 | # CONFIG_INET_ESP is not set | ||
| 294 | # CONFIG_INET_IPCOMP is not set | ||
| 295 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 296 | # CONFIG_INET_TUNNEL is not set | ||
| 297 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 298 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 299 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 300 | CONFIG_INET_DIAG=y | ||
| 301 | CONFIG_INET_TCP_DIAG=y | ||
| 302 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 303 | CONFIG_TCP_CONG_CUBIC=y | ||
| 304 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 305 | CONFIG_TCP_MD5SIG=y | ||
| 306 | # CONFIG_IPV6 is not set | ||
| 307 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 308 | # CONFIG_INET6_TUNNEL is not set | ||
| 309 | CONFIG_NETWORK_SECMARK=y | ||
| 310 | # CONFIG_NETFILTER is not set | ||
| 311 | |||
| 312 | # | ||
| 313 | # DCCP Configuration (EXPERIMENTAL) | ||
| 314 | # | ||
| 315 | # CONFIG_IP_DCCP is not set | ||
| 316 | |||
| 317 | # | ||
| 318 | # SCTP Configuration (EXPERIMENTAL) | ||
| 319 | # | ||
| 320 | # CONFIG_IP_SCTP is not set | ||
| 321 | |||
| 322 | # | ||
| 323 | # TIPC Configuration (EXPERIMENTAL) | ||
| 324 | # | ||
| 325 | # CONFIG_TIPC is not set | ||
| 326 | # CONFIG_ATM is not set | ||
| 327 | # CONFIG_BRIDGE is not set | ||
| 328 | # CONFIG_VLAN_8021Q is not set | ||
| 329 | # CONFIG_DECNET is not set | ||
| 330 | # CONFIG_LLC2 is not set | ||
| 331 | # CONFIG_IPX is not set | ||
| 332 | # CONFIG_ATALK is not set | ||
| 333 | # CONFIG_X25 is not set | ||
| 334 | # CONFIG_LAPB is not set | ||
| 335 | # CONFIG_ECONET is not set | ||
| 336 | # CONFIG_WAN_ROUTER is not set | ||
| 337 | |||
| 338 | # | ||
| 339 | # QoS and/or fair queueing | ||
| 340 | # | ||
| 341 | # CONFIG_NET_SCHED is not set | ||
| 342 | |||
| 343 | # | ||
| 344 | # Network testing | ||
| 345 | # | ||
| 346 | # CONFIG_NET_PKTGEN is not set | ||
| 347 | # CONFIG_HAMRADIO is not set | ||
| 348 | # CONFIG_IRDA is not set | ||
| 349 | # CONFIG_BT is not set | ||
| 350 | CONFIG_IEEE80211=y | ||
| 351 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 352 | CONFIG_IEEE80211_CRYPT_WEP=y | ||
| 353 | CONFIG_IEEE80211_CRYPT_CCMP=y | ||
| 354 | CONFIG_IEEE80211_SOFTMAC=y | ||
| 355 | # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set | ||
| 356 | CONFIG_WIRELESS_EXT=y | ||
| 357 | |||
| 358 | # | ||
| 359 | # Device Drivers | ||
| 360 | # | ||
| 361 | |||
| 362 | # | ||
| 363 | # Generic Driver Options | ||
| 364 | # | ||
| 365 | CONFIG_STANDALONE=y | ||
| 366 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 367 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 368 | |||
| 369 | # | ||
| 370 | # Connector - unified userspace <-> kernelspace linker | ||
| 371 | # | ||
| 372 | CONFIG_CONNECTOR=y | ||
| 373 | CONFIG_PROC_EVENTS=y | ||
| 374 | |||
| 375 | # | ||
| 376 | # Memory Technology Devices (MTD) | ||
| 377 | # | ||
| 378 | # CONFIG_MTD is not set | ||
| 379 | |||
| 380 | # | ||
| 381 | # Parallel port support | ||
| 382 | # | ||
| 383 | # CONFIG_PARPORT is not set | ||
| 384 | |||
| 385 | # | ||
| 386 | # Plug and Play support | ||
| 387 | # | ||
| 388 | # CONFIG_PNPACPI is not set | ||
| 389 | |||
| 390 | # | ||
| 391 | # Block devices | ||
| 392 | # | ||
| 393 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 394 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 395 | # CONFIG_BLK_DEV_NBD is not set | ||
| 396 | # CONFIG_BLK_DEV_RAM is not set | ||
| 397 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 398 | CONFIG_CDROM_PKTCDVD=y | ||
| 399 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | ||
| 400 | # CONFIG_CDROM_PKTCDVD_WCACHE is not set | ||
| 401 | CONFIG_ATA_OVER_ETH=y | ||
| 402 | |||
| 403 | # | ||
| 404 | # Misc devices | ||
| 405 | # | ||
| 406 | |||
| 407 | # | ||
| 408 | # ATA/ATAPI/MFM/RLL support | ||
| 409 | # | ||
| 410 | # CONFIG_IDE is not set | ||
| 411 | |||
| 412 | # | ||
| 413 | # SCSI device support | ||
| 414 | # | ||
| 415 | CONFIG_RAID_ATTRS=y | ||
| 416 | # CONFIG_SCSI is not set | ||
| 417 | # CONFIG_SCSI_NETLINK is not set | ||
| 418 | |||
| 419 | # | ||
| 420 | # Serial ATA (prod) and Parallel ATA (experimental) drivers | ||
| 421 | # | ||
| 422 | # CONFIG_ATA is not set | ||
| 423 | |||
| 424 | # | ||
| 425 | # Multi-device support (RAID and LVM) | ||
| 426 | # | ||
| 427 | # CONFIG_MD is not set | ||
| 428 | |||
| 429 | # | ||
| 430 | # Fusion MPT device support | ||
| 431 | # | ||
| 432 | # CONFIG_FUSION is not set | ||
| 433 | |||
| 434 | # | ||
| 435 | # IEEE 1394 (FireWire) support | ||
| 436 | # | ||
| 437 | |||
| 438 | # | ||
| 439 | # I2O device support | ||
| 440 | # | ||
| 441 | |||
| 442 | # | ||
| 443 | # Network device support | ||
| 444 | # | ||
| 445 | CONFIG_NETDEVICES=y | ||
| 446 | # CONFIG_DUMMY is not set | ||
| 447 | # CONFIG_BONDING is not set | ||
| 448 | # CONFIG_EQUALIZER is not set | ||
| 449 | # CONFIG_TUN is not set | ||
| 450 | |||
| 451 | # | ||
| 452 | # PHY device support | ||
| 453 | # | ||
| 454 | CONFIG_PHYLIB=y | ||
| 455 | |||
| 456 | # | ||
| 457 | # MII PHY device drivers | ||
| 458 | # | ||
| 459 | CONFIG_MARVELL_PHY=y | ||
| 460 | CONFIG_DAVICOM_PHY=y | ||
| 461 | CONFIG_QSEMI_PHY=y | ||
| 462 | CONFIG_LXT_PHY=y | ||
| 463 | CONFIG_CICADA_PHY=y | ||
| 464 | CONFIG_VITESSE_PHY=y | ||
| 465 | CONFIG_SMSC_PHY=y | ||
| 466 | # CONFIG_BROADCOM_PHY is not set | ||
| 467 | # CONFIG_FIXED_PHY is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # Ethernet (10 or 100Mbit) | ||
| 471 | # | ||
| 472 | CONFIG_NET_ETHERNET=y | ||
| 473 | # CONFIG_MII is not set | ||
| 474 | # CONFIG_DM9000 is not set | ||
| 475 | |||
| 476 | # | ||
| 477 | # Ethernet (1000 Mbit) | ||
| 478 | # | ||
| 479 | |||
| 480 | # | ||
| 481 | # Ethernet (10000 Mbit) | ||
| 482 | # | ||
| 483 | |||
| 484 | # | ||
| 485 | # Token Ring devices | ||
| 486 | # | ||
| 487 | |||
| 488 | # | ||
| 489 | # Wireless LAN (non-hamradio) | ||
| 490 | # | ||
| 491 | # CONFIG_NET_RADIO is not set | ||
| 492 | |||
| 493 | # | ||
| 494 | # Wan interfaces | ||
| 495 | # | ||
| 496 | # CONFIG_WAN is not set | ||
| 497 | # CONFIG_PPP is not set | ||
| 498 | # CONFIG_SLIP is not set | ||
| 499 | # CONFIG_SHAPER is not set | ||
| 500 | # CONFIG_NETCONSOLE is not set | ||
| 501 | # CONFIG_NETPOLL is not set | ||
| 502 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 503 | |||
| 504 | # | ||
| 505 | # ISDN subsystem | ||
| 506 | # | ||
| 507 | # CONFIG_ISDN is not set | ||
| 508 | |||
| 509 | # | ||
| 510 | # Telephony Support | ||
| 511 | # | ||
| 512 | # CONFIG_PHONE is not set | ||
| 513 | |||
| 514 | # | ||
| 515 | # Input device support | ||
| 516 | # | ||
| 517 | CONFIG_INPUT=y | ||
| 518 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 519 | |||
| 520 | # | ||
| 521 | # Userland interfaces | ||
| 522 | # | ||
| 523 | CONFIG_INPUT_MOUSEDEV=y | ||
| 524 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 525 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 526 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 527 | # CONFIG_INPUT_JOYDEV is not set | ||
| 528 | # CONFIG_INPUT_TSDEV is not set | ||
| 529 | # CONFIG_INPUT_EVDEV is not set | ||
| 530 | # CONFIG_INPUT_EVBUG is not set | ||
| 531 | |||
| 532 | # | ||
| 533 | # Input Device Drivers | ||
| 534 | # | ||
| 535 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 536 | # CONFIG_INPUT_MOUSE is not set | ||
| 537 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 538 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 539 | # CONFIG_INPUT_MISC is not set | ||
| 540 | |||
| 541 | # | ||
| 542 | # Hardware I/O ports | ||
| 543 | # | ||
| 544 | CONFIG_SERIO=y | ||
| 545 | # CONFIG_SERIO_I8042 is not set | ||
| 546 | CONFIG_SERIO_SERPORT=y | ||
| 547 | # CONFIG_SERIO_LIBPS2 is not set | ||
| 548 | CONFIG_SERIO_RAW=y | ||
| 549 | # CONFIG_GAMEPORT is not set | ||
| 550 | |||
| 551 | # | ||
| 552 | # Character devices | ||
| 553 | # | ||
| 554 | CONFIG_VT=y | ||
| 555 | CONFIG_VT_CONSOLE=y | ||
| 556 | CONFIG_HW_CONSOLE=y | ||
| 557 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 558 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Serial drivers | ||
| 562 | # | ||
| 563 | CONFIG_SERIAL_8250=y | ||
| 564 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 565 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
| 566 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 567 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 568 | |||
| 569 | # | ||
| 570 | # Non-8250 serial port support | ||
| 571 | # | ||
| 572 | CONFIG_SERIAL_CORE=y | ||
| 573 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 574 | CONFIG_UNIX98_PTYS=y | ||
| 575 | CONFIG_LEGACY_PTYS=y | ||
| 576 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 577 | |||
| 578 | # | ||
| 579 | # IPMI | ||
| 580 | # | ||
| 581 | # CONFIG_IPMI_HANDLER is not set | ||
| 582 | |||
| 583 | # | ||
| 584 | # Watchdog Cards | ||
| 585 | # | ||
| 586 | # CONFIG_WATCHDOG is not set | ||
| 587 | # CONFIG_HW_RANDOM is not set | ||
| 588 | # CONFIG_RTC is not set | ||
| 589 | # CONFIG_GEN_RTC is not set | ||
| 590 | # CONFIG_DTLK is not set | ||
| 591 | # CONFIG_R3964 is not set | ||
| 592 | # CONFIG_RAW_DRIVER is not set | ||
| 593 | |||
| 594 | # | ||
| 595 | # TPM devices | ||
| 596 | # | ||
| 597 | # CONFIG_TCG_TPM is not set | ||
| 598 | |||
| 599 | # | ||
| 600 | # I2C support | ||
| 601 | # | ||
| 602 | # CONFIG_I2C is not set | ||
| 603 | |||
| 604 | # | ||
| 605 | # SPI support | ||
| 606 | # | ||
| 607 | # CONFIG_SPI is not set | ||
| 608 | # CONFIG_SPI_MASTER is not set | ||
| 609 | |||
| 610 | # | ||
| 611 | # Dallas's 1-wire bus | ||
| 612 | # | ||
| 613 | # CONFIG_W1 is not set | ||
| 614 | |||
| 615 | # | ||
| 616 | # Hardware Monitoring support | ||
| 617 | # | ||
| 618 | # CONFIG_HWMON is not set | ||
| 619 | # CONFIG_HWMON_VID is not set | ||
| 620 | |||
| 621 | # | ||
| 622 | # Multimedia devices | ||
| 623 | # | ||
| 624 | # CONFIG_VIDEO_DEV is not set | ||
| 625 | |||
| 626 | # | ||
| 627 | # Digital Video Broadcasting Devices | ||
| 628 | # | ||
| 629 | # CONFIG_DVB is not set | ||
| 630 | |||
| 631 | # | ||
| 632 | # Graphics support | ||
| 633 | # | ||
| 634 | # CONFIG_FIRMWARE_EDID is not set | ||
| 635 | # CONFIG_FB is not set | ||
| 636 | |||
| 637 | # | ||
| 638 | # Console display driver support | ||
| 639 | # | ||
| 640 | # CONFIG_VGA_CONSOLE is not set | ||
| 641 | CONFIG_DUMMY_CONSOLE=y | ||
| 642 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 643 | |||
| 644 | # | ||
| 645 | # Sound | ||
| 646 | # | ||
| 647 | # CONFIG_SOUND is not set | ||
| 648 | |||
| 649 | # | ||
| 650 | # HID Devices | ||
| 651 | # | ||
| 652 | # CONFIG_HID is not set | ||
| 653 | |||
| 654 | # | ||
| 655 | # USB support | ||
| 656 | # | ||
| 657 | # CONFIG_USB_ARCH_HAS_HCD is not set | ||
| 658 | # CONFIG_USB_ARCH_HAS_OHCI is not set | ||
| 659 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 660 | |||
| 661 | # | ||
| 662 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 663 | # | ||
| 664 | |||
| 665 | # | ||
| 666 | # USB Gadget Support | ||
| 667 | # | ||
| 668 | # CONFIG_USB_GADGET is not set | ||
| 669 | |||
| 670 | # | ||
| 671 | # MMC/SD Card support | ||
| 672 | # | ||
| 673 | # CONFIG_MMC is not set | ||
| 674 | |||
| 675 | # | ||
| 676 | # LED devices | ||
| 677 | # | ||
| 678 | # CONFIG_NEW_LEDS is not set | ||
| 679 | |||
| 680 | # | ||
| 681 | # LED drivers | ||
| 682 | # | ||
| 683 | |||
| 684 | # | ||
| 685 | # LED Triggers | ||
| 686 | # | ||
| 687 | |||
| 688 | # | ||
| 689 | # InfiniBand support | ||
| 690 | # | ||
| 691 | |||
| 692 | # | ||
| 693 | # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) | ||
| 694 | # | ||
| 695 | |||
| 696 | # | ||
| 697 | # Real Time Clock | ||
| 698 | # | ||
| 699 | # CONFIG_RTC_CLASS is not set | ||
| 700 | |||
| 701 | # | ||
| 702 | # DMA Engine support | ||
| 703 | # | ||
| 704 | # CONFIG_DMA_ENGINE is not set | ||
| 705 | |||
| 706 | # | ||
| 707 | # DMA Clients | ||
| 708 | # | ||
| 709 | |||
| 710 | # | ||
| 711 | # DMA Devices | ||
| 712 | # | ||
| 713 | |||
| 714 | # | ||
| 715 | # Auxiliary Display support | ||
| 716 | # | ||
| 717 | |||
| 718 | # | ||
| 719 | # Virtualization | ||
| 720 | # | ||
| 721 | |||
| 722 | # | ||
| 723 | # File systems | ||
| 724 | # | ||
| 725 | CONFIG_EXT2_FS=y | ||
| 726 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 727 | # CONFIG_EXT2_FS_XIP is not set | ||
| 728 | # CONFIG_EXT3_FS is not set | ||
| 729 | # CONFIG_EXT4DEV_FS is not set | ||
| 730 | # CONFIG_REISERFS_FS is not set | ||
| 731 | # CONFIG_JFS_FS is not set | ||
| 732 | CONFIG_FS_POSIX_ACL=y | ||
| 733 | # CONFIG_XFS_FS is not set | ||
| 734 | # CONFIG_GFS2_FS is not set | ||
| 735 | # CONFIG_OCFS2_FS is not set | ||
| 736 | # CONFIG_MINIX_FS is not set | ||
| 737 | # CONFIG_ROMFS_FS is not set | ||
| 738 | CONFIG_INOTIFY=y | ||
| 739 | CONFIG_INOTIFY_USER=y | ||
| 740 | # CONFIG_QUOTA is not set | ||
| 741 | CONFIG_DNOTIFY=y | ||
| 742 | # CONFIG_AUTOFS_FS is not set | ||
| 743 | # CONFIG_AUTOFS4_FS is not set | ||
| 744 | CONFIG_FUSE_FS=y | ||
| 745 | CONFIG_GENERIC_ACL=y | ||
| 746 | |||
| 747 | # | ||
| 748 | # CD-ROM/DVD Filesystems | ||
| 749 | # | ||
| 750 | # CONFIG_ISO9660_FS is not set | ||
| 751 | # CONFIG_UDF_FS is not set | ||
| 752 | |||
| 753 | # | ||
| 754 | # DOS/FAT/NT Filesystems | ||
| 755 | # | ||
| 756 | # CONFIG_MSDOS_FS is not set | ||
| 757 | # CONFIG_VFAT_FS is not set | ||
| 758 | # CONFIG_NTFS_FS is not set | ||
| 759 | |||
| 760 | # | ||
| 761 | # Pseudo filesystems | ||
| 762 | # | ||
| 763 | CONFIG_PROC_FS=y | ||
| 764 | CONFIG_PROC_KCORE=y | ||
| 765 | CONFIG_PROC_SYSCTL=y | ||
| 766 | CONFIG_SYSFS=y | ||
| 767 | CONFIG_TMPFS=y | ||
| 768 | CONFIG_TMPFS_POSIX_ACL=y | ||
| 769 | # CONFIG_HUGETLB_PAGE is not set | ||
| 770 | CONFIG_RAMFS=y | ||
| 771 | CONFIG_CONFIGFS_FS=y | ||
| 772 | |||
| 773 | # | ||
| 774 | # Miscellaneous filesystems | ||
| 775 | # | ||
| 776 | # CONFIG_ADFS_FS is not set | ||
| 777 | # CONFIG_AFFS_FS is not set | ||
| 778 | # CONFIG_ECRYPT_FS is not set | ||
| 779 | # CONFIG_HFS_FS is not set | ||
| 780 | # CONFIG_HFSPLUS_FS is not set | ||
| 781 | # CONFIG_BEFS_FS is not set | ||
| 782 | # CONFIG_BFS_FS is not set | ||
| 783 | # CONFIG_EFS_FS is not set | ||
| 784 | # CONFIG_CRAMFS is not set | ||
| 785 | # CONFIG_VXFS_FS is not set | ||
| 786 | # CONFIG_HPFS_FS is not set | ||
| 787 | # CONFIG_QNX4FS_FS is not set | ||
| 788 | # CONFIG_SYSV_FS is not set | ||
| 789 | # CONFIG_UFS_FS is not set | ||
| 790 | |||
| 791 | # | ||
| 792 | # Network File Systems | ||
| 793 | # | ||
| 794 | CONFIG_NFS_FS=y | ||
| 795 | # CONFIG_NFS_V3 is not set | ||
| 796 | # CONFIG_NFS_V4 is not set | ||
| 797 | # CONFIG_NFS_DIRECTIO is not set | ||
| 798 | CONFIG_NFSD=y | ||
| 799 | # CONFIG_NFSD_V3 is not set | ||
| 800 | # CONFIG_NFSD_TCP is not set | ||
| 801 | CONFIG_ROOT_NFS=y | ||
| 802 | CONFIG_LOCKD=y | ||
| 803 | CONFIG_EXPORTFS=y | ||
| 804 | CONFIG_NFS_COMMON=y | ||
| 805 | CONFIG_SUNRPC=y | ||
| 806 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 807 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 808 | # CONFIG_SMB_FS is not set | ||
| 809 | # CONFIG_CIFS is not set | ||
| 810 | # CONFIG_NCP_FS is not set | ||
| 811 | # CONFIG_CODA_FS is not set | ||
| 812 | # CONFIG_AFS_FS is not set | ||
| 813 | # CONFIG_9P_FS is not set | ||
| 814 | |||
| 815 | # | ||
| 816 | # Partition Types | ||
| 817 | # | ||
| 818 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 819 | CONFIG_MSDOS_PARTITION=y | ||
| 820 | |||
| 821 | # | ||
| 822 | # Native Language Support | ||
| 823 | # | ||
| 824 | # CONFIG_NLS is not set | ||
| 825 | |||
| 826 | # | ||
| 827 | # Distributed Lock Manager | ||
| 828 | # | ||
| 829 | CONFIG_DLM=y | ||
| 830 | CONFIG_DLM_TCP=y | ||
| 831 | # CONFIG_DLM_SCTP is not set | ||
| 832 | # CONFIG_DLM_DEBUG is not set | ||
| 833 | |||
| 834 | # | ||
| 835 | # Profiling support | ||
| 836 | # | ||
| 837 | # CONFIG_PROFILING is not set | ||
| 838 | |||
| 839 | # | ||
| 840 | # Kernel hacking | ||
| 841 | # | ||
| 842 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 843 | # CONFIG_PRINTK_TIME is not set | ||
| 844 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 845 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 846 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 847 | # CONFIG_DEBUG_FS is not set | ||
| 848 | # CONFIG_HEADERS_CHECK is not set | ||
| 849 | # CONFIG_DEBUG_KERNEL is not set | ||
| 850 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 851 | CONFIG_CROSSCOMPILE=y | ||
| 852 | CONFIG_CMDLINE="" | ||
| 853 | CONFIG_SYS_SUPPORTS_KGDB=y | ||
| 854 | |||
| 855 | # | ||
| 856 | # Security options | ||
| 857 | # | ||
| 858 | CONFIG_KEYS=y | ||
| 859 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | ||
| 860 | # CONFIG_SECURITY is not set | ||
| 861 | |||
| 862 | # | ||
| 863 | # Cryptographic options | ||
| 864 | # | ||
| 865 | CONFIG_CRYPTO=y | ||
| 866 | CONFIG_CRYPTO_ALGAPI=y | ||
| 867 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 868 | CONFIG_CRYPTO_HASH=y | ||
| 869 | CONFIG_CRYPTO_MANAGER=y | ||
| 870 | CONFIG_CRYPTO_HMAC=y | ||
| 871 | CONFIG_CRYPTO_XCBC=y | ||
| 872 | CONFIG_CRYPTO_NULL=y | ||
| 873 | CONFIG_CRYPTO_MD4=y | ||
| 874 | CONFIG_CRYPTO_MD5=y | ||
| 875 | CONFIG_CRYPTO_SHA1=y | ||
| 876 | CONFIG_CRYPTO_SHA256=y | ||
| 877 | CONFIG_CRYPTO_SHA512=y | ||
| 878 | CONFIG_CRYPTO_WP512=y | ||
| 879 | CONFIG_CRYPTO_TGR192=y | ||
| 880 | CONFIG_CRYPTO_GF128MUL=y | ||
| 881 | CONFIG_CRYPTO_ECB=y | ||
| 882 | CONFIG_CRYPTO_CBC=y | ||
| 883 | CONFIG_CRYPTO_PCBC=y | ||
| 884 | CONFIG_CRYPTO_LRW=y | ||
| 885 | CONFIG_CRYPTO_DES=y | ||
| 886 | CONFIG_CRYPTO_FCRYPT=y | ||
| 887 | CONFIG_CRYPTO_BLOWFISH=y | ||
| 888 | CONFIG_CRYPTO_TWOFISH=y | ||
| 889 | CONFIG_CRYPTO_TWOFISH_COMMON=y | ||
| 890 | CONFIG_CRYPTO_SERPENT=y | ||
| 891 | CONFIG_CRYPTO_AES=y | ||
| 892 | CONFIG_CRYPTO_CAST5=y | ||
| 893 | CONFIG_CRYPTO_CAST6=y | ||
| 894 | CONFIG_CRYPTO_TEA=y | ||
| 895 | CONFIG_CRYPTO_ARC4=y | ||
| 896 | CONFIG_CRYPTO_KHAZAD=y | ||
| 897 | CONFIG_CRYPTO_ANUBIS=y | ||
| 898 | CONFIG_CRYPTO_DEFLATE=y | ||
| 899 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 900 | CONFIG_CRYPTO_CRC32C=y | ||
| 901 | CONFIG_CRYPTO_CAMELLIA=y | ||
| 902 | |||
| 903 | # | ||
| 904 | # Hardware crypto devices | ||
| 905 | # | ||
| 906 | |||
| 907 | # | ||
| 908 | # Library routines | ||
| 909 | # | ||
| 910 | CONFIG_BITREVERSE=y | ||
| 911 | # CONFIG_CRC_CCITT is not set | ||
| 912 | CONFIG_CRC16=y | ||
| 913 | CONFIG_CRC32=y | ||
| 914 | CONFIG_LIBCRC32C=y | ||
| 915 | CONFIG_ZLIB_INFLATE=y | ||
| 916 | CONFIG_ZLIB_DEFLATE=y | ||
| 917 | CONFIG_PLIST=y | ||
| 918 | CONFIG_HAS_IOMEM=y | ||
| 919 | CONFIG_HAS_IOPORT=y | ||
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 0028aef0af9d..d53fa8f8e099 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_PB1100=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index 8a1d5888739c..dc4aa0c66847 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_PB1500=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 5581ad2ca411..24428e13002b 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig | |||
| @@ -33,12 +33,9 @@ CONFIG_MIPS_PB1550=y | |||
| 33 | # CONFIG_WR_PPMC is not set | 33 | # CONFIG_WR_PPMC is not set |
| 34 | # CONFIG_MIPS_SIM is not set | 34 | # CONFIG_MIPS_SIM is not set |
| 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 35 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 36 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 37 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 38 | # CONFIG_MIPS_XXS1500 is not set | 36 | # CONFIG_MIPS_XXS1500 is not set |
| 39 | # CONFIG_PNX8550_JBS is not set | 37 | # CONFIG_PNX8550_JBS is not set |
| 40 | # CONFIG_PNX8550_STB810 is not set | 38 | # CONFIG_PNX8550_STB810 is not set |
| 41 | # CONFIG_DDB5477 is not set | ||
| 42 | # CONFIG_MACH_VR41XX is not set | 39 | # CONFIG_MACH_VR41XX is not set |
| 43 | # CONFIG_PMC_YOSEMITE is not set | 40 | # CONFIG_PMC_YOSEMITE is not set |
| 44 | # CONFIG_QEMU is not set | 41 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 821c1cee5639..f6906b069e04 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | CONFIG_PNX8550_JBS=y | 36 | CONFIG_PNX8550_JBS=y |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index 0e8bd92b38cf..b741f81696fb 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | CONFIG_PNX8550_STB810=y | 37 | CONFIG_PNX8550_STB810=y |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig index 703de002e372..b3caf5125c15 100644 --- a/arch/mips/configs/qemu_defconfig +++ b/arch/mips/configs/qemu_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | CONFIG_QEMU=y | 40 | CONFIG_QEMU=y |
diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig index 20a38526d483..9913980add21 100644 --- a/arch/mips/configs/rbhma4200_defconfig +++ b/arch/mips/configs/rbhma4200_defconfig | |||
| @@ -30,11 +30,9 @@ CONFIG_MIPS=y | |||
| 30 | # CONFIG_MIPS_SEAD is not set | 30 | # CONFIG_MIPS_SEAD is not set |
| 31 | # CONFIG_WR_PPMC is not set | 31 | # CONFIG_WR_PPMC is not set |
| 32 | # CONFIG_MIPS_SIM is not set | 32 | # CONFIG_MIPS_SIM is not set |
| 33 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 34 | # CONFIG_MIPS_XXS1500 is not set | 33 | # CONFIG_MIPS_XXS1500 is not set |
| 35 | # CONFIG_PNX8550_JBS is not set | 34 | # CONFIG_PNX8550_JBS is not set |
| 36 | # CONFIG_PNX8550_STB810 is not set | 35 | # CONFIG_PNX8550_STB810 is not set |
| 37 | # CONFIG_DDB5477 is not set | ||
| 38 | # CONFIG_MACH_VR41XX is not set | 36 | # CONFIG_MACH_VR41XX is not set |
| 39 | # CONFIG_PMC_YOSEMITE is not set | 37 | # CONFIG_PMC_YOSEMITE is not set |
| 40 | # CONFIG_QEMU is not set | 38 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig index 5dbb250f71c7..40453cd7c70e 100644 --- a/arch/mips/configs/rbhma4500_defconfig +++ b/arch/mips/configs/rbhma4500_defconfig | |||
| @@ -20,10 +20,8 @@ CONFIG_ZONE_DMA=y | |||
| 20 | # CONFIG_MIPS_SEAD is not set | 20 | # CONFIG_MIPS_SEAD is not set |
| 21 | # CONFIG_WR_PPMC is not set | 21 | # CONFIG_WR_PPMC is not set |
| 22 | # CONFIG_MIPS_SIM is not set | 22 | # CONFIG_MIPS_SIM is not set |
| 23 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 24 | # CONFIG_PNX8550_JBS is not set | 23 | # CONFIG_PNX8550_JBS is not set |
| 25 | # CONFIG_PNX8550_STB810 is not set | 24 | # CONFIG_PNX8550_STB810 is not set |
| 26 | # CONFIG_DDB5477 is not set | ||
| 27 | # CONFIG_MACH_VR41XX is not set | 25 | # CONFIG_MACH_VR41XX is not set |
| 28 | # CONFIG_PMC_MSP is not set | 26 | # CONFIG_PMC_MSP is not set |
| 29 | # CONFIG_PMC_YOSEMITE is not set | 27 | # CONFIG_PMC_YOSEMITE is not set |
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index a5dc5cb97aae..fc388118b114 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 98a914092258..e72fdf36b3fe 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig index 69c08b24c82a..2b6282d132a8 100644 --- a/arch/mips/configs/sead_defconfig +++ b/arch/mips/configs/sead_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_MIPS_SEAD=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index 5d4fc0e4f729..e9f2cef4c716 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | CONFIG_MACH_VR41XX=y | 38 | CONFIG_MACH_VR41XX=y |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index 1b92b48de051..aea67568842a 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | CONFIG_MACH_VR41XX=y | 38 | CONFIG_MACH_VR41XX=y |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 5b77c7a5d83a..66383ecff200 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | CONFIG_MACH_VR41XX=y | 38 | CONFIG_MACH_VR41XX=y |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index 94a4f94a8b24..db6fd4f15719 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | CONFIG_MACH_VR41XX=y | 38 | CONFIG_MACH_VR41XX=y |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index e38bd9b0eadc..7e410e10fed7 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | CONFIG_WR_PPMC=y | 32 | CONFIG_WR_PPMC=y |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index f342d8c887b8..acaf0e21bb00 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | CONFIG_PMC_YOSEMITE=y | 39 | CONFIG_PMC_YOSEMITE=y |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/ddb5xxx/Kconfig b/arch/mips/ddb5xxx/Kconfig deleted file mode 100644 index e9b5de49f4c2..000000000000 --- a/arch/mips/ddb5xxx/Kconfig +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | config DDB5477_BUS_FREQUENCY | ||
| 2 | int "bus frequency (in kHZ, 0 for auto-detect)" | ||
| 3 | depends on DDB5477 | ||
| 4 | default 0 | ||
diff --git a/arch/mips/ddb5xxx/common/Makefile b/arch/mips/ddb5xxx/common/Makefile deleted file mode 100644 index bc44e3032711..000000000000 --- a/arch/mips/ddb5xxx/common/Makefile +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile for the common code of NEC DDB-Vrc5xxx board | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += nile4.o prom.o rtc_ds1386.o | ||
diff --git a/arch/mips/ddb5xxx/common/nile4.c b/arch/mips/ddb5xxx/common/nile4.c deleted file mode 100644 index 7ec7d903ba97..000000000000 --- a/arch/mips/ddb5xxx/common/nile4.c +++ /dev/null | |||
| @@ -1,130 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Copyright 2001 MontaVista Software Inc. | ||
| 4 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 5 | * | ||
| 6 | * arch/mips/ddb5xxx/common/nile4.c | ||
| 7 | * misc low-level routines for vrc-5xxx controllers. | ||
| 8 | * | ||
| 9 | * derived from original code by Geert Uytterhoeven <geert@sonycom.com> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify it | ||
| 12 | * under the terms of the GNU General Public License as published by the | ||
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 14 | * option) any later version. | ||
| 15 | */ | ||
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | |||
| 19 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 20 | |||
| 21 | u32 | ||
| 22 | ddb_calc_pdar(u32 phys, u32 size, int width, | ||
| 23 | int on_memory_bus, int pci_visible) | ||
| 24 | { | ||
| 25 | u32 maskbits; | ||
| 26 | u32 widthbits; | ||
| 27 | |||
| 28 | switch (size) { | ||
| 29 | #if 0 /* We don't support 4 GB yet */ | ||
| 30 | case 0x100000000: /* 4 GB */ | ||
| 31 | maskbits = 4; | ||
| 32 | break; | ||
| 33 | #endif | ||
| 34 | case 0x80000000: /* 2 GB */ | ||
| 35 | maskbits = 5; | ||
| 36 | break; | ||
| 37 | case 0x40000000: /* 1 GB */ | ||
| 38 | maskbits = 6; | ||
| 39 | break; | ||
| 40 | case 0x20000000: /* 512 MB */ | ||
| 41 | maskbits = 7; | ||
| 42 | break; | ||
| 43 | case 0x10000000: /* 256 MB */ | ||
| 44 | maskbits = 8; | ||
| 45 | break; | ||
| 46 | case 0x08000000: /* 128 MB */ | ||
| 47 | maskbits = 9; | ||
| 48 | break; | ||
| 49 | case 0x04000000: /* 64 MB */ | ||
| 50 | maskbits = 10; | ||
| 51 | break; | ||
| 52 | case 0x02000000: /* 32 MB */ | ||
| 53 | maskbits = 11; | ||
| 54 | break; | ||
| 55 | case 0x01000000: /* 16 MB */ | ||
| 56 | maskbits = 12; | ||
| 57 | break; | ||
| 58 | case 0x00800000: /* 8 MB */ | ||
| 59 | maskbits = 13; | ||
| 60 | break; | ||
| 61 | case 0x00400000: /* 4 MB */ | ||
| 62 | maskbits = 14; | ||
| 63 | break; | ||
| 64 | case 0x00200000: /* 2 MB */ | ||
| 65 | maskbits = 15; | ||
| 66 | break; | ||
| 67 | case 0: /* OFF */ | ||
| 68 | maskbits = 0; | ||
| 69 | break; | ||
| 70 | default: | ||
| 71 | panic("nile4_set_pdar: unsupported size %p", (void *) size); | ||
| 72 | } | ||
| 73 | switch (width) { | ||
| 74 | case 8: | ||
| 75 | widthbits = 0; | ||
| 76 | break; | ||
| 77 | case 16: | ||
| 78 | widthbits = 1; | ||
| 79 | break; | ||
| 80 | case 32: | ||
| 81 | widthbits = 2; | ||
| 82 | break; | ||
| 83 | case 64: | ||
| 84 | widthbits = 3; | ||
| 85 | break; | ||
| 86 | default: | ||
| 87 | panic("nile4_set_pdar: unsupported width %d", width); | ||
| 88 | } | ||
| 89 | |||
| 90 | return maskbits | (on_memory_bus ? 0x10 : 0) | | ||
| 91 | (pci_visible ? 0x20 : 0) | (widthbits << 6) | | ||
| 92 | (phys & 0xffe00000); | ||
| 93 | } | ||
| 94 | |||
| 95 | void | ||
| 96 | ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width, | ||
| 97 | int on_memory_bus, int pci_visible) | ||
| 98 | { | ||
| 99 | u32 temp= ddb_calc_pdar(phys, size, width, on_memory_bus, pci_visible); | ||
| 100 | ddb_out32(pdar, temp); | ||
| 101 | ddb_out32(pdar + 4, 0); | ||
| 102 | |||
| 103 | /* | ||
| 104 | * When programming a PDAR, the register should be read immediately | ||
| 105 | * after writing it. This ensures that address decoders are properly | ||
| 106 | * configured. | ||
| 107 | * [jsun] is this really necessary? | ||
| 108 | */ | ||
| 109 | ddb_in32(pdar); | ||
| 110 | ddb_in32(pdar + 4); | ||
| 111 | } | ||
| 112 | |||
| 113 | /* | ||
| 114 | * routines that mess with PCIINITx registers | ||
| 115 | */ | ||
| 116 | |||
| 117 | void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options) | ||
| 118 | { | ||
| 119 | switch (type) { | ||
| 120 | case DDB_PCICMD_IACK: /* PCI Interrupt Acknowledge */ | ||
| 121 | case DDB_PCICMD_IO: /* PCI I/O Space */ | ||
| 122 | case DDB_PCICMD_MEM: /* PCI Memory Space */ | ||
| 123 | case DDB_PCICMD_CFG: /* PCI Configuration Space */ | ||
| 124 | break; | ||
| 125 | default: | ||
| 126 | panic("nile4_set_pmr: invalid type %d", type); | ||
| 127 | } | ||
| 128 | ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options ); | ||
| 129 | ddb_out32(pmr + 4, 0); | ||
| 130 | } | ||
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c deleted file mode 100644 index 54a857b5e3ba..000000000000 --- a/arch/mips/ddb5xxx/common/prom.c +++ /dev/null | |||
| @@ -1,132 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of the GNU General Public License as published by the | ||
| 7 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 8 | * option) any later version. | ||
| 9 | */ | ||
| 10 | #include <linux/init.h> | ||
| 11 | #include <linux/mm.h> | ||
| 12 | #include <linux/sched.h> | ||
| 13 | #include <linux/bootmem.h> | ||
| 14 | |||
| 15 | #include <asm/addrspace.h> | ||
| 16 | #include <asm/bootinfo.h> | ||
| 17 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 18 | #include <asm/debug.h> | ||
| 19 | |||
| 20 | const char *get_system_type(void) | ||
| 21 | { | ||
| 22 | switch (mips_machtype) { | ||
| 23 | case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477"; | ||
| 24 | case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper"; | ||
| 25 | case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII"; | ||
| 26 | default: return "Unknown NEC board"; | ||
| 27 | } | ||
| 28 | } | ||
| 29 | |||
| 30 | #if defined(CONFIG_DDB5477) | ||
| 31 | void ddb5477_runtime_detection(void); | ||
| 32 | #endif | ||
| 33 | |||
| 34 | /* [jsun@junsun.net] PMON passes arguments in C main() style */ | ||
| 35 | void __init prom_init(void) | ||
| 36 | { | ||
| 37 | int argc = fw_arg0; | ||
| 38 | char **arg = (char**) fw_arg1; | ||
| 39 | int i; | ||
| 40 | |||
| 41 | /* if user passes kernel args, ignore the default one */ | ||
| 42 | if (argc > 1) | ||
| 43 | arcs_cmdline[0] = '\0'; | ||
| 44 | |||
| 45 | /* arg[0] is "g", the rest is boot parameters */ | ||
| 46 | for (i = 1; i < argc; i++) { | ||
| 47 | if (strlen(arcs_cmdline) + strlen(arg[i] + 1) | ||
| 48 | >= sizeof(arcs_cmdline)) | ||
| 49 | break; | ||
| 50 | strcat(arcs_cmdline, arg[i]); | ||
| 51 | strcat(arcs_cmdline, " "); | ||
| 52 | } | ||
| 53 | |||
| 54 | mips_machgroup = MACH_GROUP_NEC_DDB; | ||
| 55 | |||
| 56 | #if defined(CONFIG_DDB5477) | ||
| 57 | ddb5477_runtime_detection(); | ||
| 58 | add_memory_region(0, board_ram_size, BOOT_MEM_RAM); | ||
| 59 | #endif | ||
| 60 | } | ||
| 61 | |||
| 62 | void __init prom_free_prom_memory(void) | ||
| 63 | { | ||
| 64 | } | ||
| 65 | |||
| 66 | #if defined(CONFIG_DDB5477) | ||
| 67 | |||
| 68 | #define DEFAULT_LCS1_BASE 0x19000000 | ||
| 69 | #define TESTVAL1 'K' | ||
| 70 | #define TESTVAL2 'S' | ||
| 71 | |||
| 72 | int board_ram_size; | ||
| 73 | void ddb5477_runtime_detection(void) | ||
| 74 | { | ||
| 75 | volatile char *test_offset; | ||
| 76 | char saved_test_byte; | ||
| 77 | |||
| 78 | /* Determine if this is a DDB5477 board, or a BSB-VR0300 | ||
| 79 | base board. We can tell by checking for the location of | ||
| 80 | the NVRAM. It lives at the beginning of LCS1 on the DDB5477, | ||
| 81 | and the beginning of LCS1 on the BSB-VR0300 is flash memory. | ||
| 82 | The first 2K of the NVRAM are reserved, so don't we'll poke | ||
| 83 | around just after that. | ||
| 84 | */ | ||
| 85 | |||
| 86 | /* We can only use the PCI bus to distinquish between | ||
| 87 | the Rockhopper and RockhopperII backplanes and this must | ||
| 88 | wait until ddb5477_board_init() in setup.c after the 5477 | ||
| 89 | is initialized. So, until then handle | ||
| 90 | both Rockhopper and RockhopperII backplanes as Rockhopper 1 | ||
| 91 | */ | ||
| 92 | |||
| 93 | test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800); | ||
| 94 | saved_test_byte = *test_offset; | ||
| 95 | |||
| 96 | *test_offset = TESTVAL1; | ||
| 97 | if (*test_offset != TESTVAL1) { | ||
| 98 | /* We couldn't set our test value, so it must not be NVRAM, | ||
| 99 | so it's a BSB_VR0300 */ | ||
| 100 | mips_machtype = MACH_NEC_ROCKHOPPER; | ||
| 101 | } else { | ||
| 102 | /* We may have gotten lucky, and the TESTVAL1 was already | ||
| 103 | stored at the test location, so we must check a second | ||
| 104 | test value */ | ||
| 105 | *test_offset = TESTVAL2; | ||
| 106 | if (*test_offset != TESTVAL2) { | ||
| 107 | /* OK, we couldn't set this value either, so it must | ||
| 108 | definately be a BSB_VR0300 */ | ||
| 109 | mips_machtype = MACH_NEC_ROCKHOPPER; | ||
| 110 | } else { | ||
| 111 | /* We could change the value twice, so it must be | ||
| 112 | NVRAM, so it's a DDB_VRC5477 */ | ||
| 113 | mips_machtype = MACH_NEC_DDB5477; | ||
| 114 | } | ||
| 115 | } | ||
| 116 | /* Restore the original byte */ | ||
| 117 | *test_offset = saved_test_byte; | ||
| 118 | |||
| 119 | /* before we know a better way, we will trust PMON for getting | ||
| 120 | * RAM size | ||
| 121 | */ | ||
| 122 | board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf)); | ||
| 123 | |||
| 124 | db_run(printk("DDB run-time detection : %s, %d MB RAM\n", | ||
| 125 | mips_machtype == MACH_NEC_DDB5477 ? | ||
| 126 | "DDB5477" : "Rockhopper", | ||
| 127 | board_ram_size >> 20)); | ||
| 128 | |||
| 129 | /* we can't handle ram size > 128 MB */ | ||
| 130 | db_assert(board_ram_size <= (128 << 20)); | ||
| 131 | } | ||
| 132 | #endif | ||
diff --git a/arch/mips/ddb5xxx/common/rtc_ds1386.c b/arch/mips/ddb5xxx/common/rtc_ds1386.c deleted file mode 100644 index 5dc34daa7150..000000000000 --- a/arch/mips/ddb5xxx/common/rtc_ds1386.c +++ /dev/null | |||
| @@ -1,170 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * arch/mips/ddb5xxx/common/rtc_ds1386.c | ||
| 6 | * low-level RTC hookups for s for Dallas 1396 chip. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | */ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * This file exports a function, rtc_ds1386_init(), which expects an | ||
| 17 | * uncached base address as the argument. It will set the two function | ||
| 18 | * pointers expected by the MIPS generic timer code. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/types.h> | ||
| 22 | #include <linux/time.h> | ||
| 23 | #include <linux/bcd.h> | ||
| 24 | |||
| 25 | #include <asm/time.h> | ||
| 26 | #include <asm/addrspace.h> | ||
| 27 | |||
| 28 | #include <asm/mc146818rtc.h> | ||
| 29 | #include <asm/debug.h> | ||
| 30 | |||
| 31 | #define EPOCH 2000 | ||
| 32 | |||
| 33 | #define READ_RTC(x) *(volatile unsigned char*)(rtc_base+x) | ||
| 34 | #define WRITE_RTC(x, y) *(volatile unsigned char*)(rtc_base+x) = y | ||
| 35 | |||
| 36 | static unsigned long rtc_base; | ||
| 37 | |||
| 38 | static unsigned long | ||
| 39 | rtc_ds1386_get_time(void) | ||
| 40 | { | ||
| 41 | u8 byte; | ||
| 42 | u8 temp; | ||
| 43 | unsigned int year, month, day, hour, minute, second; | ||
| 44 | unsigned long flags; | ||
| 45 | |||
| 46 | spin_lock_irqsave(&rtc_lock, flags); | ||
| 47 | /* let us freeze external registers */ | ||
| 48 | byte = READ_RTC(0xB); | ||
| 49 | byte &= 0x3f; | ||
| 50 | WRITE_RTC(0xB, byte); | ||
| 51 | |||
| 52 | /* read time data */ | ||
| 53 | year = BCD2BIN(READ_RTC(0xA)) + EPOCH; | ||
| 54 | month = BCD2BIN(READ_RTC(0x9) & 0x1f); | ||
| 55 | day = BCD2BIN(READ_RTC(0x8)); | ||
| 56 | minute = BCD2BIN(READ_RTC(0x2)); | ||
| 57 | second = BCD2BIN(READ_RTC(0x1)); | ||
| 58 | |||
| 59 | /* hour is special - deal with it later */ | ||
| 60 | temp = READ_RTC(0x4); | ||
| 61 | |||
| 62 | /* enable time transfer */ | ||
| 63 | byte |= 0x80; | ||
| 64 | WRITE_RTC(0xB, byte); | ||
| 65 | spin_unlock_irqrestore(&rtc_lock, flags); | ||
| 66 | |||
| 67 | /* calc hour */ | ||
| 68 | if (temp & 0x40) { | ||
| 69 | /* 12 hour format */ | ||
| 70 | hour = BCD2BIN(temp & 0x1f); | ||
| 71 | if (temp & 0x20) hour += 12; /* PM */ | ||
| 72 | } else { | ||
| 73 | /* 24 hour format */ | ||
| 74 | hour = BCD2BIN(temp & 0x3f); | ||
| 75 | } | ||
| 76 | |||
| 77 | return mktime(year, month, day, hour, minute, second); | ||
| 78 | } | ||
| 79 | |||
| 80 | static int | ||
| 81 | rtc_ds1386_set_time(unsigned long t) | ||
| 82 | { | ||
| 83 | struct rtc_time tm; | ||
| 84 | u8 byte; | ||
| 85 | u8 temp; | ||
| 86 | u8 year, month, day, hour, minute, second; | ||
| 87 | unsigned long flags; | ||
| 88 | |||
| 89 | spin_lock_irqsave(&rtc_lock, flags); | ||
| 90 | /* let us freeze external registers */ | ||
| 91 | byte = READ_RTC(0xB); | ||
| 92 | byte &= 0x3f; | ||
| 93 | WRITE_RTC(0xB, byte); | ||
| 94 | |||
| 95 | /* convert */ | ||
| 96 | to_tm(t, &tm); | ||
| 97 | |||
| 98 | |||
| 99 | /* check each field one by one */ | ||
| 100 | year = BIN2BCD(tm.tm_year - EPOCH); | ||
| 101 | if (year != READ_RTC(0xA)) { | ||
| 102 | WRITE_RTC(0xA, year); | ||
| 103 | } | ||
| 104 | |||
| 105 | temp = READ_RTC(0x9); | ||
| 106 | month = BIN2BCD(tm.tm_mon+1); /* tm_mon starts from 0 to 11 */ | ||
| 107 | if (month != (temp & 0x1f)) { | ||
| 108 | WRITE_RTC( 0x9, | ||
| 109 | (month & 0x1f) | (temp & ~0x1f) ); | ||
| 110 | } | ||
| 111 | |||
| 112 | day = BIN2BCD(tm.tm_mday); | ||
| 113 | if (day != READ_RTC(0x8)) { | ||
| 114 | WRITE_RTC(0x8, day); | ||
| 115 | } | ||
| 116 | |||
| 117 | temp = READ_RTC(0x4); | ||
| 118 | if (temp & 0x40) { | ||
| 119 | /* 12 hour format */ | ||
| 120 | hour = 0x40; | ||
| 121 | if (tm.tm_hour > 12) { | ||
| 122 | hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f); | ||
| 123 | } else { | ||
| 124 | hour |= BIN2BCD(tm.tm_hour); | ||
| 125 | } | ||
| 126 | } else { | ||
| 127 | /* 24 hour format */ | ||
| 128 | hour = BIN2BCD(tm.tm_hour) & 0x3f; | ||
| 129 | } | ||
| 130 | if (hour != temp) WRITE_RTC(0x4, hour); | ||
| 131 | |||
| 132 | minute = BIN2BCD(tm.tm_min); | ||
| 133 | if (minute != READ_RTC(0x2)) { | ||
| 134 | WRITE_RTC(0x2, minute); | ||
| 135 | } | ||
| 136 | |||
| 137 | second = BIN2BCD(tm.tm_sec); | ||
| 138 | if (second != READ_RTC(0x1)) { | ||
| 139 | WRITE_RTC(0x1, second); | ||
| 140 | } | ||
| 141 | spin_unlock_irqrestore(&rtc_lock, flags); | ||
| 142 | |||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | void | ||
| 147 | rtc_ds1386_init(unsigned long base) | ||
| 148 | { | ||
| 149 | unsigned char byte; | ||
| 150 | |||
| 151 | /* remember the base */ | ||
| 152 | rtc_base = base; | ||
| 153 | db_assert((rtc_base & 0xe0000000) == KSEG1); | ||
| 154 | |||
| 155 | /* turn on RTC if it is not on */ | ||
| 156 | byte = READ_RTC(0x9); | ||
| 157 | if (byte & 0x80) { | ||
| 158 | byte &= 0x7f; | ||
| 159 | WRITE_RTC(0x9, byte); | ||
| 160 | } | ||
| 161 | |||
| 162 | /* enable time transfer */ | ||
| 163 | byte = READ_RTC(0xB); | ||
| 164 | byte |= 0x80; | ||
| 165 | WRITE_RTC(0xB, byte); | ||
| 166 | |||
| 167 | /* set the function pointers */ | ||
| 168 | rtc_mips_get_time = rtc_ds1386_get_time; | ||
| 169 | rtc_mips_set_time = rtc_ds1386_set_time; | ||
| 170 | } | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/Makefile b/arch/mips/ddb5xxx/ddb5477/Makefile deleted file mode 100644 index 4864b8a659c7..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/Makefile +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile for NEC DDB-Vrc5477 board | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += ddb5477-platform.o irq.o irq_5477.o setup.o \ | ||
| 6 | lcd44780.o | ||
| 7 | |||
| 8 | obj-$(CONFIG_RUNTIME_DEBUG) += debug.o | ||
| 9 | obj-$(CONFIG_KGDB) += kgdb_io.o | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c b/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c deleted file mode 100644 index c16020ad54c2..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) | ||
| 7 | */ | ||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/serial_8250.h> | ||
| 11 | |||
| 12 | #include <asm/ddb5xxx/ddb5477.h> | ||
| 13 | |||
| 14 | #define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) | ||
| 15 | |||
| 16 | #define DDB5477_PORT(base, int) \ | ||
| 17 | { \ | ||
| 18 | .mapbase = base, \ | ||
| 19 | .irq = int, \ | ||
| 20 | .uartclk = 1843200, \ | ||
| 21 | .iotype = UPIO_MEM, \ | ||
| 22 | .flags = DDB_UART_FLAGS, \ | ||
| 23 | .regshift = 3, \ | ||
| 24 | } | ||
| 25 | |||
| 26 | static struct plat_serial8250_port uart8250_data[] = { | ||
| 27 | DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0), | ||
| 28 | DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1), | ||
| 29 | { }, | ||
| 30 | }; | ||
| 31 | |||
| 32 | static struct platform_device uart8250_device = { | ||
| 33 | .name = "serial8250", | ||
| 34 | .id = PLAT8250_DEV_PLATFORM, | ||
| 35 | .dev = { | ||
| 36 | .platform_data = uart8250_data, | ||
| 37 | }, | ||
| 38 | }; | ||
| 39 | |||
| 40 | static int __init uart8250_init(void) | ||
| 41 | { | ||
| 42 | return platform_device_register(&uart8250_device); | ||
| 43 | } | ||
| 44 | |||
| 45 | module_init(uart8250_init); | ||
| 46 | |||
| 47 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); | ||
| 48 | MODULE_LICENSE("GPL"); | ||
| 49 | MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477"); | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/debug.c b/arch/mips/ddb5xxx/ddb5477/debug.c deleted file mode 100644 index 68919d5f8ffd..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/debug.c +++ /dev/null | |||
| @@ -1,160 +0,0 @@ | |||
| 1 | /*********************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright 2001 MontaVista Software Inc. | ||
| 4 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 5 | * | ||
| 6 | * arch/mips/ddb5xxx/ddb5477/debug.c | ||
| 7 | * vrc5477 specific debug routines. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | *********************************************************************** | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | |||
| 19 | #include <asm/mipsregs.h> | ||
| 20 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 21 | |||
| 22 | typedef struct { | ||
| 23 | const char *regname; | ||
| 24 | unsigned regaddr; | ||
| 25 | } Register; | ||
| 26 | |||
| 27 | void jsun_show_regs(char *name, Register *regs) | ||
| 28 | { | ||
| 29 | int i; | ||
| 30 | |||
| 31 | printk("\nshow regs: %s\n", name); | ||
| 32 | for(i=0;regs[i].regname!= NULL; i++) { | ||
| 33 | printk("%-16s= %08x\t\t(@%08x)\n", | ||
| 34 | regs[i].regname, | ||
| 35 | *(unsigned *)(regs[i].regaddr), | ||
| 36 | regs[i].regaddr); | ||
| 37 | } | ||
| 38 | } | ||
| 39 | |||
| 40 | static Register int_regs[] = { | ||
| 41 | {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0}, | ||
| 42 | {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1}, | ||
| 43 | {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2}, | ||
| 44 | {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3}, | ||
| 45 | {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT}, | ||
| 46 | {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT}, | ||
| 47 | {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT}, | ||
| 48 | {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT}, | ||
| 49 | {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT}, | ||
| 50 | {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT}, | ||
| 51 | {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0}, | ||
| 52 | {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1}, | ||
| 53 | {NULL, 0x0} | ||
| 54 | }; | ||
| 55 | |||
| 56 | void vrc5477_show_int_regs() | ||
| 57 | { | ||
| 58 | jsun_show_regs("interrupt registers", int_regs); | ||
| 59 | printk("CPU CAUSE = %08x\n", read_c0_cause()); | ||
| 60 | printk("CPU STATUS = %08x\n", read_c0_status()); | ||
| 61 | } | ||
| 62 | static Register pdar_regs[] = { | ||
| 63 | {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0}, | ||
| 64 | {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1}, | ||
| 65 | {"DDB_LCS0", DDB_BASE + DDB_LCS0}, | ||
| 66 | {"DDB_LCS1", DDB_BASE + DDB_LCS1}, | ||
| 67 | {"DDB_LCS2", DDB_BASE + DDB_LCS2}, | ||
| 68 | {"DDB_INTCS", DDB_BASE + DDB_INTCS}, | ||
| 69 | {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS}, | ||
| 70 | {"DDB_PCIW0", DDB_BASE + DDB_PCIW0}, | ||
| 71 | {"DDB_PCIW1", DDB_BASE + DDB_PCIW1}, | ||
| 72 | {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0}, | ||
| 73 | {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1}, | ||
| 74 | {NULL, 0x0} | ||
| 75 | }; | ||
| 76 | void vrc5477_show_pdar_regs(void) | ||
| 77 | { | ||
| 78 | jsun_show_regs("PDAR regs", pdar_regs); | ||
| 79 | } | ||
| 80 | |||
| 81 | static Register bar_regs[] = { | ||
| 82 | {"DDB_BARC0", DDB_BASE + DDB_BARC0}, | ||
| 83 | {"DDB_BARM010", DDB_BASE + DDB_BARM010}, | ||
| 84 | {"DDB_BARM230", DDB_BASE + DDB_BARM230}, | ||
| 85 | {"DDB_BAR00", DDB_BASE + DDB_BAR00}, | ||
| 86 | {"DDB_BAR10", DDB_BASE + DDB_BAR10}, | ||
| 87 | {"DDB_BAR20", DDB_BASE + DDB_BAR20}, | ||
| 88 | {"DDB_BAR30", DDB_BASE + DDB_BAR30}, | ||
| 89 | {"DDB_BAR40", DDB_BASE + DDB_BAR40}, | ||
| 90 | {"DDB_BAR50", DDB_BASE + DDB_BAR50}, | ||
| 91 | {"DDB_BARB0", DDB_BASE + DDB_BARB0}, | ||
| 92 | {"DDB_BARC1", DDB_BASE + DDB_BARC1}, | ||
| 93 | {"DDB_BARM011", DDB_BASE + DDB_BARM011}, | ||
| 94 | {"DDB_BARM231", DDB_BASE + DDB_BARM231}, | ||
| 95 | {"DDB_BAR01", DDB_BASE + DDB_BAR01}, | ||
| 96 | {"DDB_BAR11", DDB_BASE + DDB_BAR11}, | ||
| 97 | {"DDB_BAR21", DDB_BASE + DDB_BAR21}, | ||
| 98 | {"DDB_BAR31", DDB_BASE + DDB_BAR31}, | ||
| 99 | {"DDB_BAR41", DDB_BASE + DDB_BAR41}, | ||
| 100 | {"DDB_BAR51", DDB_BASE + DDB_BAR51}, | ||
| 101 | {"DDB_BARB1", DDB_BASE + DDB_BARB1}, | ||
| 102 | {NULL, 0x0} | ||
| 103 | }; | ||
| 104 | void vrc5477_show_bar_regs(void) | ||
| 105 | { | ||
| 106 | jsun_show_regs("BAR regs", bar_regs); | ||
| 107 | } | ||
| 108 | |||
| 109 | static Register pci_regs[] = { | ||
| 110 | {"DDB_PCIW0", DDB_BASE + DDB_PCIW0}, | ||
| 111 | {"DDB_PCIW1", DDB_BASE + DDB_PCIW1}, | ||
| 112 | {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00}, | ||
| 113 | {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10}, | ||
| 114 | {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L}, | ||
| 115 | {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H}, | ||
| 116 | {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L}, | ||
| 117 | {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H}, | ||
| 118 | {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0}, | ||
| 119 | {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0}, | ||
| 120 | {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0}, | ||
| 121 | {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1}, | ||
| 122 | {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01}, | ||
| 123 | {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11}, | ||
| 124 | {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L}, | ||
| 125 | {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H}, | ||
| 126 | {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L}, | ||
| 127 | {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H}, | ||
| 128 | {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1}, | ||
| 129 | {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1}, | ||
| 130 | {NULL, 0x0} | ||
| 131 | }; | ||
| 132 | void vrc5477_show_pci_regs(void) | ||
| 133 | { | ||
| 134 | jsun_show_regs("PCI regs", pci_regs); | ||
| 135 | } | ||
| 136 | |||
| 137 | static Register lb_regs[] = { | ||
| 138 | {"DDB_LCNFG", DDB_BASE + DDB_LCNFG}, | ||
| 139 | {"DDB_LCST0", DDB_BASE + DDB_LCST0}, | ||
| 140 | {"DDB_LCST1", DDB_BASE + DDB_LCST1}, | ||
| 141 | {"DDB_LCST2", DDB_BASE + DDB_LCST2}, | ||
| 142 | {"DDB_ERRADR", DDB_BASE + DDB_ERRADR}, | ||
| 143 | {"DDB_ERRCS", DDB_BASE + DDB_ERRCS}, | ||
| 144 | {"DDB_BTM", DDB_BASE + DDB_BTM}, | ||
| 145 | {"DDB_BCST", DDB_BASE + DDB_BCST}, | ||
| 146 | {NULL, 0x0} | ||
| 147 | }; | ||
| 148 | void vrc5477_show_lb_regs(void) | ||
| 149 | { | ||
| 150 | jsun_show_regs("Local Bus regs", lb_regs); | ||
| 151 | } | ||
| 152 | |||
| 153 | void vrc5477_show_all_regs(void) | ||
| 154 | { | ||
| 155 | vrc5477_show_pdar_regs(); | ||
| 156 | vrc5477_show_pci_regs(); | ||
| 157 | vrc5477_show_bar_regs(); | ||
| 158 | vrc5477_show_int_regs(); | ||
| 159 | vrc5477_show_lb_regs(); | ||
| 160 | } | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c deleted file mode 100644 index faa4a506bf82..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ /dev/null | |||
| @@ -1,209 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * arch/mips/ddb5xxx/ddb5477/irq.c | ||
| 6 | * The irq setup and misc routines for DDB5476. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | */ | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/interrupt.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/ptrace.h> | ||
| 18 | |||
| 19 | #include <asm/i8259.h> | ||
| 20 | #include <asm/irq_cpu.h> | ||
| 21 | #include <asm/system.h> | ||
| 22 | #include <asm/mipsregs.h> | ||
| 23 | #include <asm/debug.h> | ||
| 24 | #include <asm/addrspace.h> | ||
| 25 | #include <asm/bootinfo.h> | ||
| 26 | |||
| 27 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * IRQ mapping | ||
| 32 | * | ||
| 33 | * 0-7: 8 CPU interrupts | ||
| 34 | * 0 - software interrupt 0 | ||
| 35 | * 1 - software interrupt 1 | ||
| 36 | * 2 - most Vrc5477 interrupts are routed to this pin | ||
| 37 | * 3 - (optional) some other interrupts routed to this pin for debugg | ||
| 38 | * 4 - not used | ||
| 39 | * 5 - not used | ||
| 40 | * 6 - not used | ||
| 41 | * 7 - cpu timer (used by default) | ||
| 42 | * | ||
| 43 | * 8-39: 32 Vrc5477 interrupt sources | ||
| 44 | * (refer to the Vrc5477 manual) | ||
| 45 | */ | ||
| 46 | |||
| 47 | #define PCI0 DDB_INTPPES0 | ||
| 48 | #define PCI1 DDB_INTPPES1 | ||
| 49 | |||
| 50 | #define ACTIVE_LOW 1 | ||
| 51 | #define ACTIVE_HIGH 0 | ||
| 52 | |||
| 53 | #define LEVEL_SENSE 2 | ||
| 54 | #define EDGE_TRIGGER 0 | ||
| 55 | |||
| 56 | #define INTA 0 | ||
| 57 | #define INTB 1 | ||
| 58 | #define INTC 2 | ||
| 59 | #define INTD 3 | ||
| 60 | #define INTE 4 | ||
| 61 | |||
| 62 | static inline void | ||
| 63 | set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) | ||
| 64 | { | ||
| 65 | u32 reg_value; | ||
| 66 | u32 reg_bitmask; | ||
| 67 | |||
| 68 | reg_value = ddb_in32(pci); | ||
| 69 | reg_bitmask = 0x3 << (intn * 2); | ||
| 70 | |||
| 71 | reg_value &= ~reg_bitmask; | ||
| 72 | reg_value |= (active | trigger) << (intn * 2); | ||
| 73 | ddb_out32(pci, reg_value); | ||
| 74 | } | ||
| 75 | |||
| 76 | extern void vrc5477_irq_init(u32 base); | ||
| 77 | static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; | ||
| 78 | |||
| 79 | void __init arch_init_irq(void) | ||
| 80 | { | ||
| 81 | /* by default, we disable all interrupts and route all vrc5477 | ||
| 82 | * interrupts to pin 0 (irq 2) */ | ||
| 83 | ddb_out32(DDB_INTCTRL0, 0); | ||
| 84 | ddb_out32(DDB_INTCTRL1, 0); | ||
| 85 | ddb_out32(DDB_INTCTRL2, 0); | ||
| 86 | ddb_out32(DDB_INTCTRL3, 0); | ||
| 87 | |||
| 88 | clear_c0_status(0xff00); | ||
| 89 | set_c0_status(0x0400); | ||
| 90 | |||
| 91 | /* setup PCI interrupt attributes */ | ||
| 92 | set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); | ||
| 93 | set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); | ||
| 94 | if (mips_machtype == MACH_NEC_ROCKHOPPERII) | ||
| 95 | set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); | ||
| 96 | else | ||
| 97 | set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); | ||
| 98 | set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE); | ||
| 99 | set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE); | ||
| 100 | |||
| 101 | set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE); | ||
| 102 | set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE); | ||
| 103 | set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE); | ||
| 104 | set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE); | ||
| 105 | set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE); | ||
| 106 | |||
| 107 | /* | ||
| 108 | * for debugging purpose, we enable several error interrupts | ||
| 109 | * and route them to pin 1. (IP3) | ||
| 110 | */ | ||
| 111 | /* cpu parity check - 0 */ | ||
| 112 | ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0); | ||
| 113 | /* cpu no-target decode - 1 */ | ||
| 114 | ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1); | ||
| 115 | /* local bus read time-out - 7 */ | ||
| 116 | ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7); | ||
| 117 | /* PCI SERR# - 14 */ | ||
| 118 | ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14); | ||
| 119 | /* PCI internal error - 15 */ | ||
| 120 | ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15); | ||
| 121 | /* IOPCI SERR# - 30 */ | ||
| 122 | ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30); | ||
| 123 | /* IOPCI internal error - 31 */ | ||
| 124 | ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31); | ||
| 125 | |||
| 126 | /* init all controllers */ | ||
| 127 | init_i8259_irqs(); | ||
| 128 | mips_cpu_irq_init(); | ||
| 129 | vrc5477_irq_init(VRC5477_IRQ_BASE); | ||
| 130 | |||
| 131 | |||
| 132 | /* setup cascade interrupts */ | ||
| 133 | setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); | ||
| 134 | setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); | ||
| 135 | } | ||
| 136 | |||
| 137 | u8 i8259_interrupt_ack(void) | ||
| 138 | { | ||
| 139 | u8 irq; | ||
| 140 | u32 reg; | ||
| 141 | |||
| 142 | /* Set window 0 for interrupt acknowledge */ | ||
| 143 | reg = ddb_in32(DDB_PCIINIT10); | ||
| 144 | |||
| 145 | ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); | ||
| 146 | irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); | ||
| 147 | ddb_out32(DDB_PCIINIT10, reg); | ||
| 148 | |||
| 149 | return irq; | ||
| 150 | } | ||
| 151 | /* | ||
| 152 | * the first level int-handler will jump here if it is a vrc5477 irq | ||
| 153 | */ | ||
| 154 | #define NUM_5477_IRQS 32 | ||
| 155 | static void vrc5477_irq_dispatch(void) | ||
| 156 | { | ||
| 157 | u32 intStatus; | ||
| 158 | u32 bitmask; | ||
| 159 | u32 i; | ||
| 160 | |||
| 161 | db_assert(ddb_in32(DDB_INT2STAT) == 0); | ||
| 162 | db_assert(ddb_in32(DDB_INT3STAT) == 0); | ||
| 163 | db_assert(ddb_in32(DDB_INT4STAT) == 0); | ||
| 164 | db_assert(ddb_in32(DDB_NMISTAT) == 0); | ||
| 165 | |||
| 166 | if (ddb_in32(DDB_INT1STAT) != 0) { | ||
| 167 | #if defined(CONFIG_RUNTIME_DEBUG) | ||
| 168 | vrc5477_show_int_regs(); | ||
| 169 | #endif | ||
| 170 | panic("error interrupt has happened."); | ||
| 171 | } | ||
| 172 | |||
| 173 | intStatus = ddb_in32(DDB_INT0STAT); | ||
| 174 | |||
| 175 | if (mips_machtype == MACH_NEC_ROCKHOPPERII) { | ||
| 176 | /* check for i8259 interrupts */ | ||
| 177 | if (intStatus & (1 << VRC5477_I8259_CASCADE)) { | ||
| 178 | int i8259_irq = i8259_interrupt_ack(); | ||
| 179 | do_IRQ(i8259_irq); | ||
| 180 | return; | ||
| 181 | } | ||
| 182 | } | ||
| 183 | |||
| 184 | for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { | ||
| 185 | /* do we need to "and" with the int mask? */ | ||
| 186 | if (intStatus & bitmask) { | ||
| 187 | do_IRQ(VRC5477_IRQ_BASE + i); | ||
| 188 | return; | ||
| 189 | } | ||
| 190 | } | ||
| 191 | } | ||
| 192 | |||
| 193 | #define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6) | ||
| 194 | |||
| 195 | asmlinkage void plat_irq_dispatch(void) | ||
| 196 | { | ||
| 197 | unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; | ||
| 198 | |||
| 199 | if (pending & STATUSF_IP7) | ||
| 200 | do_IRQ(CPU_IRQ_BASE + 7); | ||
| 201 | else if (pending & VR5477INTS) | ||
| 202 | vrc5477_irq_dispatch(); | ||
| 203 | else if (pending & STATUSF_IP0) | ||
| 204 | do_IRQ(CPU_IRQ_BASE); | ||
| 205 | else if (pending & STATUSF_IP1) | ||
| 206 | do_IRQ(CPU_IRQ_BASE + 1); | ||
| 207 | else | ||
| 208 | spurious_interrupt(); | ||
| 209 | } | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c deleted file mode 100644 index 98c3b15eb369..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c +++ /dev/null | |||
| @@ -1,154 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * arch/mips/ddb5xxx/ddb5477/irq_5477.c | ||
| 6 | * This file defines the irq handler for Vrc5477. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Vrc5477 defines 32 IRQs. | ||
| 17 | * | ||
| 18 | * This file exports one function: | ||
| 19 | * vrc5477_irq_init(u32 irq_base); | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/interrupt.h> | ||
| 23 | #include <linux/types.h> | ||
| 24 | #include <linux/ptrace.h> | ||
| 25 | |||
| 26 | #include <asm/debug.h> | ||
| 27 | |||
| 28 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 29 | |||
| 30 | /* number of total irqs supported by Vrc5477 */ | ||
| 31 | #define NUM_5477_IRQ 32 | ||
| 32 | |||
| 33 | static int vrc5477_irq_base = -1; | ||
| 34 | |||
| 35 | |||
| 36 | static void | ||
| 37 | vrc5477_irq_enable(unsigned int irq) | ||
| 38 | { | ||
| 39 | db_assert(vrc5477_irq_base != -1); | ||
| 40 | db_assert(irq >= vrc5477_irq_base); | ||
| 41 | db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); | ||
| 42 | |||
| 43 | ll_vrc5477_irq_enable(irq - vrc5477_irq_base); | ||
| 44 | } | ||
| 45 | |||
| 46 | static void | ||
| 47 | vrc5477_irq_disable(unsigned int irq) | ||
| 48 | { | ||
| 49 | db_assert(vrc5477_irq_base != -1); | ||
| 50 | db_assert(irq >= vrc5477_irq_base); | ||
| 51 | db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); | ||
| 52 | |||
| 53 | ll_vrc5477_irq_disable(irq - vrc5477_irq_base); | ||
| 54 | } | ||
| 55 | |||
| 56 | static void | ||
| 57 | vrc5477_irq_ack(unsigned int irq) | ||
| 58 | { | ||
| 59 | db_assert(vrc5477_irq_base != -1); | ||
| 60 | db_assert(irq >= vrc5477_irq_base); | ||
| 61 | db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); | ||
| 62 | |||
| 63 | /* clear the interrupt bit */ | ||
| 64 | /* some irqs require the driver to clear the sources */ | ||
| 65 | ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base)); | ||
| 66 | |||
| 67 | /* disable interrupt - some handler will re-enable the irq | ||
| 68 | * and if the interrupt is leveled, we will have infinite loop | ||
| 69 | */ | ||
| 70 | ll_vrc5477_irq_disable(irq - vrc5477_irq_base); | ||
| 71 | } | ||
| 72 | |||
| 73 | static void | ||
| 74 | vrc5477_irq_end(unsigned int irq) | ||
| 75 | { | ||
| 76 | db_assert(vrc5477_irq_base != -1); | ||
| 77 | db_assert(irq >= vrc5477_irq_base); | ||
| 78 | db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); | ||
| 79 | |||
| 80 | if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | ||
| 81 | ll_vrc5477_irq_enable( irq - vrc5477_irq_base); | ||
| 82 | } | ||
| 83 | |||
| 84 | struct irq_chip vrc5477_irq_controller = { | ||
| 85 | .name = "vrc5477_irq", | ||
| 86 | .ack = vrc5477_irq_ack, | ||
| 87 | .mask = vrc5477_irq_disable, | ||
| 88 | .mask_ack = vrc5477_irq_ack, | ||
| 89 | .unmask = vrc5477_irq_enable, | ||
| 90 | .end = vrc5477_irq_end | ||
| 91 | }; | ||
| 92 | |||
| 93 | void __init vrc5477_irq_init(u32 irq_base) | ||
| 94 | { | ||
| 95 | u32 i; | ||
| 96 | |||
| 97 | for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) | ||
| 98 | set_irq_chip(i, &vrc5477_irq_controller); | ||
| 99 | |||
| 100 | vrc5477_irq_base = irq_base; | ||
| 101 | } | ||
| 102 | |||
| 103 | void ll_vrc5477_irq_route(int vrc5477_irq, int ip) | ||
| 104 | { | ||
| 105 | u32 reg_value; | ||
| 106 | u32 reg_bitmask; | ||
| 107 | u32 reg_index; | ||
| 108 | |||
| 109 | db_assert(vrc5477_irq >= 0); | ||
| 110 | db_assert(vrc5477_irq < NUM_5477_IRQ); | ||
| 111 | db_assert(ip >= 0); | ||
| 112 | db_assert((ip < 5) || (ip == 6)); | ||
| 113 | |||
| 114 | reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; | ||
| 115 | reg_value = ddb_in32(reg_index); | ||
| 116 | reg_bitmask = 7 << (vrc5477_irq % 8 * 4); | ||
| 117 | reg_value &= ~reg_bitmask; | ||
| 118 | reg_value |= ip << (vrc5477_irq % 8 * 4); | ||
| 119 | ddb_out32(reg_index, reg_value); | ||
| 120 | } | ||
| 121 | |||
| 122 | void ll_vrc5477_irq_enable(int vrc5477_irq) | ||
| 123 | { | ||
| 124 | u32 reg_value; | ||
| 125 | u32 reg_bitmask; | ||
| 126 | u32 reg_index; | ||
| 127 | |||
| 128 | db_assert(vrc5477_irq >= 0); | ||
| 129 | db_assert(vrc5477_irq < NUM_5477_IRQ); | ||
| 130 | |||
| 131 | reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; | ||
| 132 | reg_value = ddb_in32(reg_index); | ||
| 133 | reg_bitmask = 8 << (vrc5477_irq % 8 * 4); | ||
| 134 | db_assert((reg_value & reg_bitmask) == 0); | ||
| 135 | ddb_out32(reg_index, reg_value | reg_bitmask); | ||
| 136 | } | ||
| 137 | |||
| 138 | void ll_vrc5477_irq_disable(int vrc5477_irq) | ||
| 139 | { | ||
| 140 | u32 reg_value; | ||
| 141 | u32 reg_bitmask; | ||
| 142 | u32 reg_index; | ||
| 143 | |||
| 144 | db_assert(vrc5477_irq >= 0); | ||
| 145 | db_assert(vrc5477_irq < NUM_5477_IRQ); | ||
| 146 | |||
| 147 | reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; | ||
| 148 | reg_value = ddb_in32(reg_index); | ||
| 149 | reg_bitmask = 8 << (vrc5477_irq % 8 * 4); | ||
| 150 | |||
| 151 | /* we assert that the interrupt is enabled (perhaps over-zealous) */ | ||
| 152 | db_assert( (reg_value & reg_bitmask) != 0); | ||
| 153 | ddb_out32(reg_index, reg_value & ~reg_bitmask); | ||
| 154 | } | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c deleted file mode 100644 index 385bbdb10170..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c +++ /dev/null | |||
| @@ -1,136 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * kgdb io functions for DDB5477. We use the second serial port (upper one). | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 MontaVista Software Inc. | ||
| 5 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | /* ======================= CONFIG ======================== */ | ||
| 15 | |||
| 16 | /* [jsun] we use the second serial port for kdb */ | ||
| 17 | #define BASE 0xbfa04240 | ||
| 18 | #define MAX_BAUD 115200 | ||
| 19 | |||
| 20 | /* distance in bytes between two serial registers */ | ||
| 21 | #define REG_OFFSET 8 | ||
| 22 | |||
| 23 | /* | ||
| 24 | * 0 - kgdb does serial init | ||
| 25 | * 1 - kgdb skip serial init | ||
| 26 | */ | ||
| 27 | static int remoteDebugInitialized = 0; | ||
| 28 | |||
| 29 | /* | ||
| 30 | * the default baud rate *if* kgdb does serial init | ||
| 31 | */ | ||
| 32 | #define BAUD_DEFAULT UART16550_BAUD_38400 | ||
| 33 | |||
| 34 | /* ======================= END OF CONFIG ======================== */ | ||
| 35 | |||
| 36 | typedef unsigned char uint8; | ||
| 37 | typedef unsigned int uint32; | ||
| 38 | |||
| 39 | #define UART16550_BAUD_2400 2400 | ||
| 40 | #define UART16550_BAUD_4800 4800 | ||
| 41 | #define UART16550_BAUD_9600 9600 | ||
| 42 | #define UART16550_BAUD_19200 19200 | ||
| 43 | #define UART16550_BAUD_38400 38400 | ||
| 44 | #define UART16550_BAUD_57600 57600 | ||
| 45 | #define UART16550_BAUD_115200 115200 | ||
| 46 | |||
| 47 | #define UART16550_PARITY_NONE 0 | ||
| 48 | #define UART16550_PARITY_ODD 0x08 | ||
| 49 | #define UART16550_PARITY_EVEN 0x18 | ||
| 50 | #define UART16550_PARITY_MARK 0x28 | ||
| 51 | #define UART16550_PARITY_SPACE 0x38 | ||
| 52 | |||
| 53 | #define UART16550_DATA_5BIT 0x0 | ||
| 54 | #define UART16550_DATA_6BIT 0x1 | ||
| 55 | #define UART16550_DATA_7BIT 0x2 | ||
| 56 | #define UART16550_DATA_8BIT 0x3 | ||
| 57 | |||
| 58 | #define UART16550_STOP_1BIT 0x0 | ||
| 59 | #define UART16550_STOP_2BIT 0x4 | ||
| 60 | |||
| 61 | /* register offset */ | ||
| 62 | #define OFS_RCV_BUFFER 0 | ||
| 63 | #define OFS_TRANS_HOLD 0 | ||
| 64 | #define OFS_SEND_BUFFER 0 | ||
| 65 | #define OFS_INTR_ENABLE (1*REG_OFFSET) | ||
| 66 | #define OFS_INTR_ID (2*REG_OFFSET) | ||
| 67 | #define OFS_DATA_FORMAT (3*REG_OFFSET) | ||
| 68 | #define OFS_LINE_CONTROL (3*REG_OFFSET) | ||
| 69 | #define OFS_MODEM_CONTROL (4*REG_OFFSET) | ||
| 70 | #define OFS_RS232_OUTPUT (4*REG_OFFSET) | ||
| 71 | #define OFS_LINE_STATUS (5*REG_OFFSET) | ||
| 72 | #define OFS_MODEM_STATUS (6*REG_OFFSET) | ||
| 73 | #define OFS_RS232_INPUT (6*REG_OFFSET) | ||
| 74 | #define OFS_SCRATCH_PAD (7*REG_OFFSET) | ||
| 75 | |||
| 76 | #define OFS_DIVISOR_LSB (0*REG_OFFSET) | ||
| 77 | #define OFS_DIVISOR_MSB (1*REG_OFFSET) | ||
| 78 | |||
| 79 | |||
| 80 | /* memory-mapped read/write of the port */ | ||
| 81 | #define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) | ||
| 82 | #define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) | ||
| 83 | |||
| 84 | void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) | ||
| 85 | { | ||
| 86 | /* disable interrupts */ | ||
| 87 | UART16550_WRITE(OFS_INTR_ENABLE, 0); | ||
| 88 | |||
| 89 | /* set up baud rate */ | ||
| 90 | { | ||
| 91 | uint32 divisor; | ||
| 92 | |||
| 93 | /* set DIAB bit */ | ||
| 94 | UART16550_WRITE(OFS_LINE_CONTROL, 0x80); | ||
| 95 | |||
| 96 | /* set divisor */ | ||
| 97 | divisor = MAX_BAUD / baud; | ||
| 98 | UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); | ||
| 99 | UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); | ||
| 100 | |||
| 101 | /* clear DIAB bit */ | ||
| 102 | UART16550_WRITE(OFS_LINE_CONTROL, 0x0); | ||
| 103 | } | ||
| 104 | |||
| 105 | /* set data format */ | ||
| 106 | UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); | ||
| 107 | } | ||
| 108 | |||
| 109 | |||
| 110 | uint8 getDebugChar(void) | ||
| 111 | { | ||
| 112 | if (!remoteDebugInitialized) { | ||
| 113 | remoteDebugInitialized = 1; | ||
| 114 | debugInit(BAUD_DEFAULT, | ||
| 115 | UART16550_DATA_8BIT, | ||
| 116 | UART16550_PARITY_NONE, UART16550_STOP_1BIT); | ||
| 117 | } | ||
| 118 | |||
| 119 | while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); | ||
| 120 | return UART16550_READ(OFS_RCV_BUFFER); | ||
| 121 | } | ||
| 122 | |||
| 123 | |||
| 124 | int putDebugChar(uint8 byte) | ||
| 125 | { | ||
| 126 | if (!remoteDebugInitialized) { | ||
| 127 | remoteDebugInitialized = 1; | ||
| 128 | debugInit(BAUD_DEFAULT, | ||
| 129 | UART16550_DATA_8BIT, | ||
| 130 | UART16550_PARITY_NONE, UART16550_STOP_1BIT); | ||
| 131 | } | ||
| 132 | |||
| 133 | while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); | ||
| 134 | UART16550_WRITE(OFS_SEND_BUFFER, byte); | ||
| 135 | return 1; | ||
| 136 | } | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.c b/arch/mips/ddb5xxx/ddb5477/lcd44780.c deleted file mode 100644 index 9510b9ae6453..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/lcd44780.c +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * lcd44780.c | ||
| 3 | * Simple "driver" for a memory-mapped 44780-style LCD display. | ||
| 4 | * | ||
| 5 | * Copyright 2001 Bradley D. LaRonde <brad@ltc.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000) | ||
| 15 | #define LCD44780_DATA ((volatile unsigned char *)0xbe020001) | ||
| 16 | |||
| 17 | #define LCD44780_4BIT_1LINE 0x20 | ||
| 18 | #define LCD44780_4BIT_2LINE 0x28 | ||
| 19 | #define LCD44780_8BIT_1LINE 0x30 | ||
| 20 | #define LCD44780_8BIT_2LINE 0x38 | ||
| 21 | #define LCD44780_MODE_DEC 0x04 | ||
| 22 | #define LCD44780_MODE_DEC_SHIFT 0x05 | ||
| 23 | #define LCD44780_MODE_INC 0x06 | ||
| 24 | #define LCD44780_MODE_INC_SHIFT 0x07 | ||
| 25 | #define LCD44780_SCROLL_LEFT 0x18 | ||
| 26 | #define LCD44780_SCROLL_RIGHT 0x1e | ||
| 27 | #define LCD44780_CURSOR_UNDERLINE 0x0e | ||
| 28 | #define LCD44780_CURSOR_BLOCK 0x0f | ||
| 29 | #define LCD44780_CURSOR_OFF 0x0c | ||
| 30 | #define LCD44780_CLEAR 0x01 | ||
| 31 | #define LCD44780_BLANK 0x08 | ||
| 32 | #define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF | ||
| 33 | #define LCD44780_HOME 0x02 | ||
| 34 | #define LCD44780_LEFT 0x10 | ||
| 35 | #define LCD44780_RIGHT 0x14 | ||
| 36 | |||
| 37 | void lcd44780_wait(void) | ||
| 38 | { | ||
| 39 | int i, j; | ||
| 40 | for(i=0; i < 400; i++) | ||
| 41 | for(j=0; j < 10000; j++); | ||
| 42 | } | ||
| 43 | |||
| 44 | void lcd44780_command(unsigned char c) | ||
| 45 | { | ||
| 46 | *LCD44780_COMMAND = c; | ||
| 47 | lcd44780_wait(); | ||
| 48 | } | ||
| 49 | |||
| 50 | void lcd44780_data(unsigned char c) | ||
| 51 | { | ||
| 52 | *LCD44780_DATA = c; | ||
| 53 | lcd44780_wait(); | ||
| 54 | } | ||
| 55 | |||
| 56 | void lcd44780_puts(const char* s) | ||
| 57 | { | ||
| 58 | int j; | ||
| 59 | int pos = 0; | ||
| 60 | |||
| 61 | lcd44780_command(LCD44780_CLEAR); | ||
| 62 | while(*s) { | ||
| 63 | lcd44780_data(*s); | ||
| 64 | s++; | ||
| 65 | pos++; | ||
| 66 | if (pos == 8) { | ||
| 67 | /* We must write 32 of spaces to get cursor to 2nd line */ | ||
| 68 | for (j=0; j<32; j++) { | ||
| 69 | lcd44780_data(' '); | ||
| 70 | } | ||
| 71 | } | ||
| 72 | if (pos == 16) { | ||
| 73 | /* We have filled all 16 character positions, so stop | ||
| 74 | outputing data */ | ||
| 75 | break; | ||
| 76 | } | ||
| 77 | } | ||
| 78 | #ifdef LCD44780_PUTS_PAUSE | ||
| 79 | { | ||
| 80 | int i; | ||
| 81 | |||
| 82 | for(i = 1; i < 2000; i++) | ||
| 83 | lcd44780_wait(); | ||
| 84 | } | ||
| 85 | #endif | ||
| 86 | } | ||
| 87 | |||
| 88 | void lcd44780_init(void) | ||
| 89 | { | ||
| 90 | // The display on the RockHopper is physically a single | ||
| 91 | // 16 char line (two 8 char lines concatenated). bdl | ||
| 92 | lcd44780_command(LCD44780_8BIT_2LINE); | ||
| 93 | lcd44780_command(LCD44780_MODE_INC); | ||
| 94 | lcd44780_command(LCD44780_CURSOR_BLOCK); | ||
| 95 | lcd44780_command(LCD44780_CLEAR); | ||
| 96 | } | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/lcd44780.h b/arch/mips/ddb5xxx/ddb5477/lcd44780.h deleted file mode 100644 index cf2f0f71eee5..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/lcd44780.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * lcd44780.h | ||
| 3 | * Simple "driver" for a memory-mapped 44780-style LCD display. | ||
| 4 | * | ||
| 5 | * Copyright 2001 Bradley D. LaRonde <brad@ltc.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | void lcd44780_puts(const char* s); | ||
| 15 | void lcd44780_init(void); | ||
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c deleted file mode 100644 index f0cc0e8a8afa..000000000000 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ /dev/null | |||
| @@ -1,399 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Copyright 2001 MontaVista Software Inc. | ||
| 4 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | ||
| 7 | * | ||
| 8 | * arch/mips/ddb5xxx/ddb5477/setup.c | ||
| 9 | * Setup file for DDB5477. | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify it | ||
| 12 | * under the terms of the GNU General Public License as published by the | ||
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 14 | * option) any later version. | ||
| 15 | */ | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/types.h> | ||
| 19 | #include <linux/sched.h> | ||
| 20 | #include <linux/pci.h> | ||
| 21 | #include <linux/ide.h> | ||
| 22 | #include <linux/irq.h> | ||
| 23 | #include <linux/fs.h> | ||
| 24 | #include <linux/ioport.h> | ||
| 25 | #include <linux/param.h> /* for HZ */ | ||
| 26 | #include <linux/major.h> | ||
| 27 | #include <linux/kdev_t.h> | ||
| 28 | #include <linux/root_dev.h> | ||
| 29 | #include <linux/pm.h> | ||
| 30 | |||
| 31 | #include <asm/cpu.h> | ||
| 32 | #include <asm/bootinfo.h> | ||
| 33 | #include <asm/addrspace.h> | ||
| 34 | #include <asm/time.h> | ||
| 35 | #include <asm/bcache.h> | ||
| 36 | #include <asm/irq.h> | ||
| 37 | #include <asm/reboot.h> | ||
| 38 | #include <asm/gdb-stub.h> | ||
| 39 | #include <asm/traps.h> | ||
| 40 | #include <asm/debug.h> | ||
| 41 | |||
| 42 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 43 | |||
| 44 | #include "lcd44780.h" | ||
| 45 | |||
| 46 | |||
| 47 | #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ | ||
| 48 | |||
| 49 | #define SP_TIMER_BASE DDB_SPT1CTRL_L | ||
| 50 | #define SP_TIMER_IRQ VRC5477_IRQ_SPT1 | ||
| 51 | |||
| 52 | static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000; | ||
| 53 | |||
| 54 | static void ddb_machine_restart(char *command) | ||
| 55 | { | ||
| 56 | static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; | ||
| 57 | |||
| 58 | u32 t; | ||
| 59 | |||
| 60 | /* PCI cold reset */ | ||
| 61 | ddb_pci_reset_bus(); | ||
| 62 | |||
| 63 | /* CPU cold reset */ | ||
| 64 | t = ddb_in32(DDB_CPUSTAT); | ||
| 65 | db_assert((t&1)); | ||
| 66 | ddb_out32(DDB_CPUSTAT, t); | ||
| 67 | |||
| 68 | /* Call the PROM */ | ||
| 69 | back_to_prom(); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void ddb_machine_halt(void) | ||
| 73 | { | ||
| 74 | printk("DDB Vrc-5477 halted.\n"); | ||
| 75 | while (1); | ||
| 76 | } | ||
| 77 | |||
| 78 | static void ddb_machine_power_off(void) | ||
| 79 | { | ||
| 80 | printk("DDB Vrc-5477 halted. Please turn off the power.\n"); | ||
| 81 | while (1); | ||
| 82 | } | ||
| 83 | |||
| 84 | extern void rtc_ds1386_init(unsigned long base); | ||
| 85 | |||
| 86 | static unsigned int __init detect_bus_frequency(unsigned long rtc_base) | ||
| 87 | { | ||
| 88 | unsigned int freq; | ||
| 89 | unsigned char c; | ||
| 90 | unsigned int t1, t2; | ||
| 91 | unsigned i; | ||
| 92 | |||
| 93 | ddb_out32(SP_TIMER_BASE, 0xffffffff); | ||
| 94 | ddb_out32(SP_TIMER_BASE+4, 0x1); | ||
| 95 | ddb_out32(SP_TIMER_BASE+8, 0xffffffff); | ||
| 96 | |||
| 97 | /* check if rtc is running */ | ||
| 98 | c= *(volatile unsigned char*)rtc_base; | ||
| 99 | for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++); | ||
| 100 | if (c == *(volatile unsigned char*)rtc_base) { | ||
| 101 | printk("Failed to detect bus frequency. Use default 83.3MHz.\n"); | ||
| 102 | return 83333000; | ||
| 103 | } | ||
| 104 | |||
| 105 | c= *(volatile unsigned char*)rtc_base; | ||
| 106 | while (c == *(volatile unsigned char*)rtc_base); | ||
| 107 | /* we are now at the turn of 1/100th second, if no error. */ | ||
| 108 | t1 = ddb_in32(SP_TIMER_BASE+8); | ||
| 109 | |||
| 110 | for (i=0; i< 10; i++) { | ||
| 111 | c= *(volatile unsigned char*)rtc_base; | ||
| 112 | while (c == *(volatile unsigned char*)rtc_base); | ||
| 113 | /* we are now at the turn of another 1/100th second */ | ||
| 114 | t2 = ddb_in32(SP_TIMER_BASE+8); | ||
| 115 | } | ||
| 116 | |||
| 117 | ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */ | ||
| 118 | |||
| 119 | freq = (t1 - t2)*10; | ||
| 120 | printk("DDB bus frequency detection : %u \n", freq); | ||
| 121 | return freq; | ||
| 122 | } | ||
| 123 | |||
| 124 | static void __init ddb_time_init(void) | ||
| 125 | { | ||
| 126 | unsigned long rtc_base; | ||
| 127 | unsigned int i; | ||
| 128 | |||
| 129 | /* we have ds1396 RTC chip */ | ||
| 130 | if (mips_machtype == MACH_NEC_ROCKHOPPER | ||
| 131 | || mips_machtype == MACH_NEC_ROCKHOPPERII) { | ||
| 132 | rtc_base = KSEG1ADDR(DDB_LCS2_BASE); | ||
| 133 | } else { | ||
| 134 | rtc_base = KSEG1ADDR(DDB_LCS1_BASE); | ||
| 135 | } | ||
| 136 | rtc_ds1386_init(rtc_base); | ||
| 137 | |||
| 138 | /* do we need to do run-time detection of bus speed? */ | ||
| 139 | if (bus_frequency == 0) { | ||
| 140 | bus_frequency = detect_bus_frequency(rtc_base); | ||
| 141 | } | ||
| 142 | |||
| 143 | /* mips_hpt_frequency is 1/2 of the cpu core freq */ | ||
| 144 | i = (read_c0_config() >> 28 ) & 7; | ||
| 145 | if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) | ||
| 146 | i = 4; | ||
| 147 | mips_hpt_frequency = bus_frequency*(i+4)/4; | ||
| 148 | } | ||
| 149 | |||
| 150 | void __init plat_timer_setup(struct irqaction *irq) | ||
| 151 | { | ||
| 152 | #if defined(USE_CPU_COUNTER_TIMER) | ||
| 153 | |||
| 154 | /* we are using the cpu counter for timer interrupts */ | ||
| 155 | setup_irq(CPU_IRQ_BASE + 7, irq); | ||
| 156 | |||
| 157 | #else | ||
| 158 | |||
| 159 | /* if we use Special purpose timer 1 */ | ||
| 160 | ddb_out32(SP_TIMER_BASE, bus_frequency/HZ); | ||
| 161 | ddb_out32(SP_TIMER_BASE+4, 0x1); | ||
| 162 | setup_irq(SP_TIMER_IRQ, irq); | ||
| 163 | |||
| 164 | #endif | ||
| 165 | } | ||
| 166 | |||
| 167 | static void ddb5477_board_init(void); | ||
| 168 | |||
| 169 | extern struct pci_controller ddb5477_ext_controller; | ||
| 170 | extern struct pci_controller ddb5477_io_controller; | ||
| 171 | |||
| 172 | void __init plat_mem_setup(void) | ||
| 173 | { | ||
| 174 | /* initialize board - we don't trust the loader */ | ||
| 175 | ddb5477_board_init(); | ||
| 176 | |||
| 177 | set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); | ||
| 178 | |||
| 179 | board_time_init = ddb_time_init; | ||
| 180 | |||
| 181 | _machine_restart = ddb_machine_restart; | ||
| 182 | _machine_halt = ddb_machine_halt; | ||
| 183 | pm_power_off = ddb_machine_power_off; | ||
| 184 | |||
| 185 | /* setup resource limits */ | ||
| 186 | ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1; | ||
| 187 | iomem_resource.end = 0xffffffff; | ||
| 188 | |||
| 189 | /* Reboot on panic */ | ||
| 190 | panic_timeout = 180; | ||
| 191 | |||
| 192 | register_pci_controller (&ddb5477_ext_controller); | ||
| 193 | register_pci_controller (&ddb5477_io_controller); | ||
| 194 | } | ||
| 195 | |||
| 196 | static void __init ddb5477_board_init(void) | ||
| 197 | { | ||
| 198 | /* ----------- setup PDARs ------------ */ | ||
| 199 | |||
| 200 | /* SDRAM should have been set */ | ||
| 201 | db_assert(ddb_in32(DDB_SDRAM0) == | ||
| 202 | ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1)); | ||
| 203 | |||
| 204 | /* SDRAM1 should be turned off. What is this for anyway ? */ | ||
| 205 | db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); | ||
| 206 | |||
| 207 | /* Setup local bus. */ | ||
| 208 | |||
| 209 | /* Flash U12 PDAR and timing. */ | ||
| 210 | ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0); | ||
| 211 | ddb_out32(DDB_LCST0, 0x00090842); | ||
| 212 | |||
| 213 | /* We need to setup LCS1 and LCS2 differently based on the | ||
| 214 | board_version */ | ||
| 215 | if (mips_machtype == MACH_NEC_ROCKHOPPER) { | ||
| 216 | /* Flash U13 PDAR and timing. */ | ||
| 217 | ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0); | ||
| 218 | ddb_out32(DDB_LCST1, 0x00090842); | ||
| 219 | |||
| 220 | /* EPLD (NVRAM, switch, LCD, and mezzanie). */ | ||
| 221 | ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0); | ||
| 222 | } else { | ||
| 223 | /* misc */ | ||
| 224 | ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0); | ||
| 225 | /* mezzanie (?) */ | ||
| 226 | ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0); | ||
| 227 | } | ||
| 228 | |||
| 229 | /* verify VRC5477 base addr */ | ||
| 230 | db_assert(ddb_in32(DDB_VRC5477) == | ||
| 231 | ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1)); | ||
| 232 | |||
| 233 | /* verify BOOT ROM addr */ | ||
| 234 | db_assert(ddb_in32(DDB_BOOTCS) == | ||
| 235 | ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); | ||
| 236 | |||
| 237 | /* setup PCI windows - window0 for MEM/config, window1 for IO */ | ||
| 238 | ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); | ||
| 239 | ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1); | ||
| 240 | ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1); | ||
| 241 | ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1); | ||
| 242 | |||
| 243 | /* ------------ reset PCI bus and BARs ----------------- */ | ||
| 244 | ddb_pci_reset_bus(); | ||
| 245 | |||
| 246 | ddb_out32(DDB_BARM010, 0x00000008); | ||
| 247 | ddb_out32(DDB_BARM011, 0x00000008); | ||
| 248 | |||
| 249 | ddb_out32(DDB_BARC0, 0xffffffff); | ||
| 250 | ddb_out32(DDB_BARM230, 0xffffffff); | ||
| 251 | ddb_out32(DDB_BAR00, 0xffffffff); | ||
| 252 | ddb_out32(DDB_BAR10, 0xffffffff); | ||
| 253 | ddb_out32(DDB_BAR20, 0xffffffff); | ||
| 254 | ddb_out32(DDB_BAR30, 0xffffffff); | ||
| 255 | ddb_out32(DDB_BAR40, 0xffffffff); | ||
| 256 | ddb_out32(DDB_BAR50, 0xffffffff); | ||
| 257 | ddb_out32(DDB_BARB0, 0xffffffff); | ||
| 258 | |||
| 259 | ddb_out32(DDB_BARC1, 0xffffffff); | ||
| 260 | ddb_out32(DDB_BARM231, 0xffffffff); | ||
| 261 | ddb_out32(DDB_BAR01, 0xffffffff); | ||
| 262 | ddb_out32(DDB_BAR11, 0xffffffff); | ||
| 263 | ddb_out32(DDB_BAR21, 0xffffffff); | ||
| 264 | ddb_out32(DDB_BAR31, 0xffffffff); | ||
| 265 | ddb_out32(DDB_BAR41, 0xffffffff); | ||
| 266 | ddb_out32(DDB_BAR51, 0xffffffff); | ||
| 267 | ddb_out32(DDB_BARB1, 0xffffffff); | ||
| 268 | |||
| 269 | /* | ||
| 270 | * We use pci master register 0 for memory space / config space | ||
| 271 | * And we use register 1 for IO space. | ||
| 272 | * Note that for memory space, we bump up the pci base address | ||
| 273 | * so that we have 1:1 mapping between PCI memory and cpu physical. | ||
| 274 | * For PCI IO space, it starts from 0 in PCI IO space but with | ||
| 275 | * DDB_xx_IO_BASE in CPU physical address space. | ||
| 276 | */ | ||
| 277 | ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE, | ||
| 278 | DDB_PCI_ACCESS_32); | ||
| 279 | ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); | ||
| 280 | |||
| 281 | ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE, | ||
| 282 | DDB_PCI_ACCESS_32); | ||
| 283 | ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE, | ||
| 284 | DDB_PCI_ACCESS_32); | ||
| 285 | |||
| 286 | |||
| 287 | /* PCI cross window should be set properly */ | ||
| 288 | ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1); | ||
| 289 | ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1); | ||
| 290 | ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); | ||
| 291 | ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1); | ||
| 292 | |||
| 293 | if (mips_machtype == MACH_NEC_ROCKHOPPER | ||
| 294 | || mips_machtype == MACH_NEC_ROCKHOPPERII) { | ||
| 295 | /* Disable bus diagnostics. */ | ||
| 296 | ddb_out32(DDB_PCICTL0_L, 0); | ||
| 297 | ddb_out32(DDB_PCICTL0_H, 0); | ||
| 298 | ddb_out32(DDB_PCICTL1_L, 0); | ||
| 299 | ddb_out32(DDB_PCICTL1_H, 0); | ||
| 300 | } | ||
| 301 | |||
| 302 | if (mips_machtype == MACH_NEC_ROCKHOPPER) { | ||
| 303 | u16 vid; | ||
| 304 | struct pci_bus bus; | ||
| 305 | struct pci_dev dev_m1533; | ||
| 306 | extern struct pci_ops ddb5477_ext_pci_ops; | ||
| 307 | |||
| 308 | bus.parent = NULL; /* we scan the top level only */ | ||
| 309 | bus.ops = &ddb5477_ext_pci_ops; | ||
| 310 | dev_m1533.bus = &bus; | ||
| 311 | dev_m1533.sysdata = NULL; | ||
| 312 | dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. | ||
| 313 | pci_read_config_word(&dev_m1533, 0, &vid); | ||
| 314 | if (vid == PCI_VENDOR_ID_AL) { | ||
| 315 | printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n"); | ||
| 316 | mips_machtype = MACH_NEC_ROCKHOPPERII; | ||
| 317 | } | ||
| 318 | } | ||
| 319 | |||
| 320 | /* enable USB input buffers */ | ||
| 321 | ddb_out32(DDB_PIBMISC, 0x00000007); | ||
| 322 | |||
| 323 | /* For dual-function pins, make them all non-GPIO */ | ||
| 324 | ddb_out32(DDB_GIUFUNSEL, 0x0); | ||
| 325 | // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */ | ||
| 326 | |||
| 327 | if (mips_machtype == MACH_NEC_ROCKHOPPERII) { | ||
| 328 | |||
| 329 | /* enable IDE controller on Ali chip (south bridge) */ | ||
| 330 | u8 temp8; | ||
| 331 | struct pci_bus bus; | ||
| 332 | struct pci_dev dev_m1533; | ||
| 333 | struct pci_dev dev_m5229; | ||
| 334 | extern struct pci_ops ddb5477_ext_pci_ops; | ||
| 335 | |||
| 336 | /* Setup M1535 registers */ | ||
| 337 | bus.parent = NULL; /* we scan the top level only */ | ||
| 338 | bus.ops = &ddb5477_ext_pci_ops; | ||
| 339 | dev_m1533.bus = &bus; | ||
| 340 | dev_m1533.sysdata = NULL; | ||
| 341 | dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. | ||
| 342 | |||
| 343 | /* setup IDE controller | ||
| 344 | * enable IDE controller (bit 6 - 1) | ||
| 345 | * IDE IDSEL to be addr:A15 (bit 4:5 - 11) | ||
| 346 | * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) | ||
| 347 | * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1) | ||
| 348 | */ | ||
| 349 | pci_write_config_byte(&dev_m1533, 0x58, 0x74); | ||
| 350 | |||
| 351 | /* | ||
| 352 | * positive decode (bit6 -0) | ||
| 353 | * enable IDE controler interrupt (bit 4 -1) | ||
| 354 | * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) | ||
| 355 | */ | ||
| 356 | pci_write_config_byte(&dev_m1533, 0x44, 0x1d); | ||
| 357 | |||
| 358 | /* Setup M5229 registers */ | ||
| 359 | dev_m5229.bus = &bus; | ||
| 360 | dev_m5229.sysdata = NULL; | ||
| 361 | dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE | ||
| 362 | |||
| 363 | /* | ||
| 364 | * enable IDE in the M5229 config register 0x50 (bit 0 - 1) | ||
| 365 | * M5229 IDSEL is addr:15; see above setting | ||
| 366 | */ | ||
| 367 | pci_read_config_byte(&dev_m5229, 0x50, &temp8); | ||
| 368 | pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); | ||
| 369 | |||
| 370 | /* | ||
| 371 | * enable bus master (bit 2) and IO decoding (bit 0) | ||
| 372 | */ | ||
| 373 | pci_read_config_byte(&dev_m5229, 0x04, &temp8); | ||
| 374 | pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); | ||
| 375 | |||
| 376 | /* | ||
| 377 | * enable native, copied from arch/ppc/k2boot/head.S | ||
| 378 | * TODO - need volatile, need to be portable | ||
| 379 | */ | ||
| 380 | pci_write_config_byte(&dev_m5229, 0x09, 0xef); | ||
| 381 | |||
| 382 | /* Set Primary Channel Command Block Timing */ | ||
| 383 | pci_write_config_byte(&dev_m5229, 0x59, 0x31); | ||
| 384 | |||
| 385 | /* | ||
| 386 | * Enable primary channel 40-pin cable | ||
| 387 | * M5229 register 0x4a (bit 0) | ||
| 388 | */ | ||
| 389 | pci_read_config_byte(&dev_m5229, 0x4a, &temp8); | ||
| 390 | pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1); | ||
| 391 | } | ||
| 392 | |||
| 393 | if (mips_machtype == MACH_NEC_ROCKHOPPER | ||
| 394 | || mips_machtype == MACH_NEC_ROCKHOPPERII) { | ||
| 395 | printk("lcd44780: initializing\n"); | ||
| 396 | lcd44780_init(); | ||
| 397 | lcd44780_puts("MontaVista Linux"); | ||
| 398 | } | ||
| 399 | } | ||
diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile index 9eb2f9c036aa..c530208ee154 100644 --- a/arch/mips/dec/Makefile +++ b/arch/mips/dec/Makefile | |||
| @@ -8,3 +8,5 @@ obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \ | |||
| 8 | obj-$(CONFIG_PROM_CONSOLE) += promcon.o | 8 | obj-$(CONFIG_PROM_CONSOLE) += promcon.o |
| 9 | obj-$(CONFIG_TC) += tc.o | 9 | obj-$(CONFIG_TC) += tc.o |
| 10 | obj-$(CONFIG_CPU_HAS_WB) += wbflush.o | 10 | obj-$(CONFIG_CPU_HAS_WB) += wbflush.o |
| 11 | |||
| 12 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/defconfig b/arch/mips/defconfig index b3b6e58058f6..d3d81fb2765a 100644 --- a/arch/mips/defconfig +++ b/arch/mips/defconfig | |||
| @@ -32,12 +32,9 @@ CONFIG_ZONE_DMA=y | |||
| 32 | # CONFIG_WR_PPMC is not set | 32 | # CONFIG_WR_PPMC is not set |
| 33 | # CONFIG_MIPS_SIM is not set | 33 | # CONFIG_MIPS_SIM is not set |
| 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | 34 | # CONFIG_MOMENCO_JAGUAR_ATX is not set |
| 35 | # CONFIG_MOMENCO_OCELOT is not set | ||
| 36 | # CONFIG_MOMENCO_OCELOT_G is not set | ||
| 37 | # CONFIG_MIPS_XXS1500 is not set | 35 | # CONFIG_MIPS_XXS1500 is not set |
| 38 | # CONFIG_PNX8550_JBS is not set | 36 | # CONFIG_PNX8550_JBS is not set |
| 39 | # CONFIG_PNX8550_STB810 is not set | 37 | # CONFIG_PNX8550_STB810 is not set |
| 40 | # CONFIG_DDB5477 is not set | ||
| 41 | # CONFIG_MACH_VR41XX is not set | 38 | # CONFIG_MACH_VR41XX is not set |
| 42 | # CONFIG_PMC_YOSEMITE is not set | 39 | # CONFIG_PMC_YOSEMITE is not set |
| 43 | # CONFIG_QEMU is not set | 40 | # CONFIG_QEMU is not set |
diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile deleted file mode 100644 index 1ef676e22ab4..000000000000 --- a/arch/mips/gt64120/common/Makefile +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile for common code of gt64120-based boards. | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += time.o | ||
diff --git a/arch/mips/gt64120/common/time.c b/arch/mips/gt64120/common/time.c deleted file mode 100644 index c47eeb768192..000000000000 --- a/arch/mips/gt64120/common/time.c +++ /dev/null | |||
| @@ -1,101 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This program is free software; you can redistribute it and/or modify it | ||
| 3 | * under the terms of the GNU General Public License as published by the | ||
| 4 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 5 | * option) any later version. | ||
| 6 | * | ||
| 7 | * Galileo Technology chip interrupt handler | ||
| 8 | */ | ||
| 9 | #include <linux/interrupt.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/sched.h> | ||
| 12 | #include <linux/kernel_stat.h> | ||
| 13 | #include <asm/irq_regs.h> | ||
| 14 | #include <asm/gt64120.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * These are interrupt handlers for the GT on-chip interrupts. They all come | ||
| 18 | * in to the MIPS on a single interrupt line, and have to be handled and ack'ed | ||
| 19 | * differently than other MIPS interrupts. | ||
| 20 | */ | ||
| 21 | |||
| 22 | static irqreturn_t gt64120_irq(int irq, void *dev_id) | ||
| 23 | { | ||
| 24 | unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; | ||
| 25 | int handled = 0; | ||
| 26 | |||
| 27 | irq_src = GT_READ(GT_INTRCAUSE_OFS); | ||
| 28 | irq_src_mask = GT_READ(GT_INTRMASK_OFS); | ||
| 29 | int_high_src = GT_READ(GT_HINTRCAUSE_OFS); | ||
| 30 | int_high_src_mask = GT_READ(GT_HINTRMASK_OFS); | ||
| 31 | irq_src = irq_src & irq_src_mask; | ||
| 32 | int_high_src = int_high_src & int_high_src_mask; | ||
| 33 | |||
| 34 | if (irq_src & 0x00000800) { /* Check for timer interrupt */ | ||
| 35 | handled = 1; | ||
| 36 | irq_src &= ~0x00000800; | ||
| 37 | do_timer(1); | ||
| 38 | #ifndef CONFIG_SMP | ||
| 39 | update_process_times(user_mode(get_irq_regs())); | ||
| 40 | #endif | ||
| 41 | } | ||
| 42 | |||
| 43 | GT_WRITE(GT_INTRCAUSE_OFS, 0); | ||
| 44 | GT_WRITE(GT_HINTRCAUSE_OFS, 0); | ||
| 45 | |||
| 46 | return IRQ_HANDLED; | ||
| 47 | } | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Initializes timer using galileo's built in timer. | ||
| 51 | */ | ||
| 52 | #ifdef CONFIG_SYSCLK_100 | ||
| 53 | #define Sys_clock (100 * 1000000) // 100 MHz | ||
| 54 | #endif | ||
| 55 | #ifdef CONFIG_SYSCLK_83 | ||
| 56 | #define Sys_clock (83.333 * 1000000) // 83.333 MHz | ||
| 57 | #endif | ||
| 58 | #ifdef CONFIG_SYSCLK_75 | ||
| 59 | #define Sys_clock (75 * 1000000) // 75 MHz | ||
| 60 | #endif | ||
| 61 | |||
| 62 | /* | ||
| 63 | * This will ignore the standard MIPS timer interrupt handler that is passed in | ||
| 64 | * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt | ||
| 65 | * handling. | ||
| 66 | */ | ||
| 67 | void __init plat_timer_setup(struct irqaction *irq) | ||
| 68 | { | ||
| 69 | static struct irqaction timer; | ||
| 70 | |||
| 71 | /* Disable timer first */ | ||
| 72 | GT_WRITE(GT_TC_CONTROL_OFS, 0); | ||
| 73 | /* Load timer value for 100 Hz */ | ||
| 74 | GT_WRITE(GT_TC3_OFS, Sys_clock / HZ); | ||
| 75 | |||
| 76 | /* | ||
| 77 | * Create the IRQ structure entry for the timer. Since we're too early | ||
| 78 | * in the boot process to use the "request_irq()" call, we'll hard-code | ||
| 79 | * the values to the correct interrupt line. | ||
| 80 | */ | ||
| 81 | timer.handler = gt64120_irq; | ||
| 82 | timer.flags = IRQF_SHARED | IRQF_DISABLED; | ||
| 83 | timer.name = "timer"; | ||
| 84 | timer.dev_id = NULL; | ||
| 85 | timer.next = NULL; | ||
| 86 | timer.mask = CPU_MASK_NONE; | ||
| 87 | irq_desc[GT_TIMER].action = &timer; | ||
| 88 | |||
| 89 | enable_irq(GT_TIMER); | ||
| 90 | |||
| 91 | /* Enable timer ints */ | ||
| 92 | GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); | ||
| 93 | /* clear Cause register first */ | ||
| 94 | GT_WRITE(GT_INTRCAUSE_OFS, 0x0); | ||
| 95 | /* Unmask timer int */ | ||
| 96 | GT_WRITE(GT_INTRMASK_OFS, 0x800); | ||
| 97 | /* Clear High int register */ | ||
| 98 | GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); | ||
| 99 | /* Mask All interrupts at High cause interrupt */ | ||
| 100 | GT_WRITE(GT_HINTRMASK_OFS, 0x0); | ||
| 101 | } | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/Makefile b/arch/mips/gt64120/momenco_ocelot/Makefile deleted file mode 100644 index 1df5fe23c642..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/Makefile +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile for Momentum's Ocelot board. | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += irq.o ocelot-platform.o prom.o reset.o setup.o | ||
| 6 | |||
| 7 | obj-$(CONFIG_KGDB) += dbg_io.o | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c deleted file mode 100644 index 32d6fb4ee679..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/dbg_io.c +++ /dev/null | |||
| @@ -1,121 +0,0 @@ | |||
| 1 | |||
| 2 | #include <asm/serial.h> /* For the serial port location and base baud */ | ||
| 3 | |||
| 4 | /* --- CONFIG --- */ | ||
| 5 | |||
| 6 | typedef unsigned char uint8; | ||
| 7 | typedef unsigned int uint32; | ||
| 8 | |||
| 9 | /* --- END OF CONFIG --- */ | ||
| 10 | |||
| 11 | #define UART16550_BAUD_2400 2400 | ||
| 12 | #define UART16550_BAUD_4800 4800 | ||
| 13 | #define UART16550_BAUD_9600 9600 | ||
| 14 | #define UART16550_BAUD_19200 19200 | ||
| 15 | #define UART16550_BAUD_38400 38400 | ||
| 16 | #define UART16550_BAUD_57600 57600 | ||
| 17 | #define UART16550_BAUD_115200 115200 | ||
| 18 | |||
| 19 | #define UART16550_PARITY_NONE 0 | ||
| 20 | #define UART16550_PARITY_ODD 0x08 | ||
| 21 | #define UART16550_PARITY_EVEN 0x18 | ||
| 22 | #define UART16550_PARITY_MARK 0x28 | ||
| 23 | #define UART16550_PARITY_SPACE 0x38 | ||
| 24 | |||
| 25 | #define UART16550_DATA_5BIT 0x0 | ||
| 26 | #define UART16550_DATA_6BIT 0x1 | ||
| 27 | #define UART16550_DATA_7BIT 0x2 | ||
| 28 | #define UART16550_DATA_8BIT 0x3 | ||
| 29 | |||
| 30 | #define UART16550_STOP_1BIT 0x0 | ||
| 31 | #define UART16550_STOP_2BIT 0x4 | ||
| 32 | |||
| 33 | /* ----------------------------------------------------- */ | ||
| 34 | |||
| 35 | /* === CONFIG === */ | ||
| 36 | |||
| 37 | /* [jsun] we use the second serial port for kdb */ | ||
| 38 | #define BASE OCELOT_SERIAL1_BASE | ||
| 39 | #define MAX_BAUD OCELOT_BASE_BAUD | ||
| 40 | |||
| 41 | /* === END OF CONFIG === */ | ||
| 42 | |||
| 43 | #define REG_OFFSET 4 | ||
| 44 | |||
| 45 | /* register offset */ | ||
| 46 | #define OFS_RCV_BUFFER 0 | ||
| 47 | #define OFS_TRANS_HOLD 0 | ||
| 48 | #define OFS_SEND_BUFFER 0 | ||
| 49 | #define OFS_INTR_ENABLE (1*REG_OFFSET) | ||
| 50 | #define OFS_INTR_ID (2*REG_OFFSET) | ||
| 51 | #define OFS_DATA_FORMAT (3*REG_OFFSET) | ||
| 52 | #define OFS_LINE_CONTROL (3*REG_OFFSET) | ||
| 53 | #define OFS_MODEM_CONTROL (4*REG_OFFSET) | ||
| 54 | #define OFS_RS232_OUTPUT (4*REG_OFFSET) | ||
| 55 | #define OFS_LINE_STATUS (5*REG_OFFSET) | ||
| 56 | #define OFS_MODEM_STATUS (6*REG_OFFSET) | ||
| 57 | #define OFS_RS232_INPUT (6*REG_OFFSET) | ||
| 58 | #define OFS_SCRATCH_PAD (7*REG_OFFSET) | ||
| 59 | |||
| 60 | #define OFS_DIVISOR_LSB (0*REG_OFFSET) | ||
| 61 | #define OFS_DIVISOR_MSB (1*REG_OFFSET) | ||
| 62 | |||
| 63 | |||
| 64 | /* memory-mapped read/write of the port */ | ||
| 65 | #define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) | ||
| 66 | #define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) | ||
| 67 | |||
| 68 | void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) | ||
| 69 | { | ||
| 70 | /* disable interrupts */ | ||
| 71 | UART16550_WRITE(OFS_INTR_ENABLE, 0); | ||
| 72 | |||
| 73 | /* set up baud rate */ | ||
| 74 | { | ||
| 75 | uint32 divisor; | ||
| 76 | |||
| 77 | /* set DIAB bit */ | ||
| 78 | UART16550_WRITE(OFS_LINE_CONTROL, 0x80); | ||
| 79 | |||
| 80 | /* set divisor */ | ||
| 81 | divisor = MAX_BAUD / baud; | ||
| 82 | UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); | ||
| 83 | UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); | ||
| 84 | |||
| 85 | /* clear DIAB bit */ | ||
| 86 | UART16550_WRITE(OFS_LINE_CONTROL, 0x0); | ||
| 87 | } | ||
| 88 | |||
| 89 | /* set data format */ | ||
| 90 | UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); | ||
| 91 | } | ||
| 92 | |||
| 93 | static int remoteDebugInitialized = 0; | ||
| 94 | |||
| 95 | uint8 getDebugChar(void) | ||
| 96 | { | ||
| 97 | if (!remoteDebugInitialized) { | ||
| 98 | remoteDebugInitialized = 1; | ||
| 99 | debugInit(UART16550_BAUD_38400, | ||
| 100 | UART16550_DATA_8BIT, | ||
| 101 | UART16550_PARITY_NONE, UART16550_STOP_1BIT); | ||
| 102 | } | ||
| 103 | |||
| 104 | while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); | ||
| 105 | return UART16550_READ(OFS_RCV_BUFFER); | ||
| 106 | } | ||
| 107 | |||
| 108 | |||
| 109 | int putDebugChar(uint8 byte) | ||
| 110 | { | ||
| 111 | if (!remoteDebugInitialized) { | ||
| 112 | remoteDebugInitialized = 1; | ||
| 113 | debugInit(UART16550_BAUD_38400, | ||
| 114 | UART16550_DATA_8BIT, | ||
| 115 | UART16550_PARITY_NONE, UART16550_STOP_1BIT); | ||
| 116 | } | ||
| 117 | |||
| 118 | while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); | ||
| 119 | UART16550_WRITE(OFS_SEND_BUFFER, byte); | ||
| 120 | return 1; | ||
| 121 | } | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c deleted file mode 100644 index 2585d9dbda33..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/irq.c +++ /dev/null | |||
| @@ -1,95 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000 RidgeRun, Inc. | ||
| 3 | * Author: RidgeRun, Inc. | ||
| 4 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
| 5 | * | ||
| 6 | * Copyright 2001 MontaVista Software Inc. | ||
| 7 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 8 | * Copyright (C) 2000, 2001, 2003 Ralf Baechle (ralf@gnu.org) | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License along | ||
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 29 | * | ||
| 30 | */ | ||
| 31 | #include <linux/errno.h> | ||
| 32 | #include <linux/init.h> | ||
| 33 | #include <linux/kernel_stat.h> | ||
| 34 | #include <linux/module.h> | ||
| 35 | #include <linux/signal.h> | ||
| 36 | #include <linux/sched.h> | ||
| 37 | #include <linux/types.h> | ||
| 38 | #include <linux/interrupt.h> | ||
| 39 | #include <linux/ioport.h> | ||
| 40 | #include <linux/timex.h> | ||
| 41 | #include <linux/slab.h> | ||
| 42 | #include <linux/random.h> | ||
| 43 | #include <linux/bitops.h> | ||
| 44 | #include <asm/bootinfo.h> | ||
| 45 | #include <asm/io.h> | ||
| 46 | #include <asm/irq.h> | ||
| 47 | #include <asm/irq_cpu.h> | ||
| 48 | #include <asm/mipsregs.h> | ||
| 49 | #include <asm/system.h> | ||
| 50 | |||
| 51 | asmlinkage void plat_irq_dispatch(void) | ||
| 52 | { | ||
| 53 | unsigned int pending = read_c0_status() & read_c0_cause(); | ||
| 54 | |||
| 55 | if (pending & STATUSF_IP2) /* int0 hardware line */ | ||
| 56 | do_IRQ(2); | ||
| 57 | else if (pending & STATUSF_IP3) /* int1 hardware line */ | ||
| 58 | do_IRQ(3); | ||
| 59 | else if (pending & STATUSF_IP4) /* int2 hardware line */ | ||
| 60 | do_IRQ(4); | ||
| 61 | else if (pending & STATUSF_IP5) /* int3 hardware line */ | ||
| 62 | do_IRQ(5); | ||
| 63 | else if (pending & STATUSF_IP6) /* int4 hardware line */ | ||
| 64 | do_IRQ(6); | ||
| 65 | else if (pending & STATUSF_IP7) /* cpu timer */ | ||
| 66 | do_IRQ(7); | ||
| 67 | else { | ||
| 68 | /* | ||
| 69 | * Now look at the extended interrupts | ||
| 70 | */ | ||
| 71 | pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; | ||
| 72 | |||
| 73 | if (pending & STATUSF_IP8) /* int6 hardware line */ | ||
| 74 | do_IRQ(8); | ||
| 75 | else if (pending & STATUSF_IP9) /* int7 hardware line */ | ||
| 76 | do_IRQ(9); | ||
| 77 | else if (pending & STATUSF_IP10) /* int8 hardware line */ | ||
| 78 | do_IRQ(10); | ||
| 79 | else if (pending & STATUSF_IP11) /* int9 hardware line */ | ||
| 80 | do_IRQ(11); | ||
| 81 | } | ||
| 82 | } | ||
| 83 | |||
| 84 | void __init arch_init_irq(void) | ||
| 85 | { | ||
| 86 | /* | ||
| 87 | * Clear all of the interrupts while we change the able around a bit. | ||
| 88 | * int-handler is not on bootstrap | ||
| 89 | */ | ||
| 90 | clear_c0_status(ST0_IM); | ||
| 91 | local_irq_disable(); | ||
| 92 | |||
| 93 | mips_cpu_irq_init(); | ||
| 94 | rm7k_cpu_irq_init(); | ||
| 95 | } | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c b/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c deleted file mode 100644 index 81d9031a5a2a..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/ocelot-platform.c +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) | ||
| 7 | * | ||
| 8 | * A NS16552 DUART with a 20MHz crystal. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/serial_8250.h> | ||
| 14 | |||
| 15 | #define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) | ||
| 16 | |||
| 17 | static struct plat_serial8250_port uart8250_data[] = { | ||
| 18 | { | ||
| 19 | .mapbase = 0xe0001020, | ||
| 20 | .irq = 4, | ||
| 21 | .uartclk = 20000000, | ||
| 22 | .iotype = UPIO_MEM, | ||
| 23 | .flags = OCELOT_UART_FLAGS, | ||
| 24 | .regshift = 2, | ||
| 25 | }, | ||
| 26 | { }, | ||
| 27 | }; | ||
| 28 | |||
| 29 | static struct platform_device uart8250_device = { | ||
| 30 | .name = "serial8250", | ||
| 31 | .id = PLAT8250_DEV_PLATFORM, | ||
| 32 | .dev = { | ||
| 33 | .platform_data = uart8250_data, | ||
| 34 | }, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static int __init uart8250_init(void) | ||
| 38 | { | ||
| 39 | return platform_device_register(&uart8250_device); | ||
| 40 | } | ||
| 41 | |||
| 42 | module_init(uart8250_init); | ||
| 43 | |||
| 44 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); | ||
| 45 | MODULE_LICENSE("GPL"); | ||
| 46 | MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot"); | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h deleted file mode 100644 index 11f02c402b2a..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Ocelot Board Register Definitions | ||
| 3 | * | ||
| 4 | * (C) 2001 Red Hat, Inc. | ||
| 5 | * | ||
| 6 | * GPL'd | ||
| 7 | */ | ||
| 8 | #ifndef __MOMENCO_OCELOT_PLD_H__ | ||
| 9 | #define __MOMENCO_OCELOT_PLD_H__ | ||
| 10 | |||
| 11 | #define OCELOT_CS0_ADDR (0xe0020000) | ||
| 12 | |||
| 13 | #define OCELOT_REG_BOARDREV (0) | ||
| 14 | #define OCELOT_REG_PLD1_ID (1) | ||
| 15 | #define OCELOT_REG_PLD2_ID (2) | ||
| 16 | #define OCELOT_REG_RESET_STATUS (3) | ||
| 17 | #define OCELOT_REG_BOARD_STATUS (4) | ||
| 18 | #define OCELOT_REG_CPCI_ID (5) | ||
| 19 | #define OCELOT_REG_I2C_CTRL (8) | ||
| 20 | #define OCELOT_REG_EEPROM_MODE (9) | ||
| 21 | #define OCELOT_REG_INTMASK (10) | ||
| 22 | #define OCELOT_REG_INTSTATUS (11) | ||
| 23 | #define OCELOT_REG_INTSET (12) | ||
| 24 | #define OCELOT_REG_INTCLR (13) | ||
| 25 | |||
| 26 | #define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) | ||
| 27 | #define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) | ||
| 28 | |||
| 29 | |||
| 30 | #endif /* __MOMENCO_OCELOT_PLD_H__ */ | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c deleted file mode 100644 index c71c85276c74..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/prom.c +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of the GNU General Public License as published by the | ||
| 7 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 8 | * option) any later version. | ||
| 9 | */ | ||
| 10 | #include <linux/init.h> | ||
| 11 | #include <linux/mm.h> | ||
| 12 | #include <linux/sched.h> | ||
| 13 | #include <linux/bootmem.h> | ||
| 14 | |||
| 15 | #include <asm/addrspace.h> | ||
| 16 | #include <asm/bootinfo.h> | ||
| 17 | #include <asm/pmon.h> | ||
| 18 | |||
| 19 | struct callvectors* debug_vectors; | ||
| 20 | |||
| 21 | extern unsigned long gt64120_base; | ||
| 22 | |||
| 23 | const char *get_system_type(void) | ||
| 24 | { | ||
| 25 | return "Momentum Ocelot"; | ||
| 26 | } | ||
| 27 | |||
| 28 | /* [jsun@junsun.net] PMON passes arguments in C main() style */ | ||
| 29 | void __init prom_init(void) | ||
| 30 | { | ||
| 31 | int argc = fw_arg0; | ||
| 32 | char **arg = (char **) fw_arg1; | ||
| 33 | char **env = (char **) fw_arg2; | ||
| 34 | struct callvectors *cv = (struct callvectors *) fw_arg3; | ||
| 35 | int i; | ||
| 36 | |||
| 37 | /* save the PROM vectors for debugging use */ | ||
| 38 | debug_vectors = cv; | ||
| 39 | |||
| 40 | /* arg[0] is "g", the rest is boot parameters */ | ||
| 41 | arcs_cmdline[0] = '\0'; | ||
| 42 | for (i = 1; i < argc; i++) { | ||
| 43 | if (strlen(arcs_cmdline) + strlen(arg[i] + 1) | ||
| 44 | >= sizeof(arcs_cmdline)) | ||
| 45 | break; | ||
| 46 | strcat(arcs_cmdline, arg[i]); | ||
| 47 | strcat(arcs_cmdline, " "); | ||
| 48 | } | ||
| 49 | |||
| 50 | mips_machgroup = MACH_GROUP_MOMENCO; | ||
| 51 | mips_machtype = MACH_MOMENCO_OCELOT; | ||
| 52 | |||
| 53 | while (*env) { | ||
| 54 | if (strncmp("gtbase", *env, 6) == 0) { | ||
| 55 | gt64120_base = simple_strtol(*env + strlen("gtbase="), | ||
| 56 | NULL, 16); | ||
| 57 | break; | ||
| 58 | } | ||
| 59 | *env++; | ||
| 60 | } | ||
| 61 | |||
| 62 | debug_vectors->printf("Booting Linux kernel...\n"); | ||
| 63 | |||
| 64 | /* All the boards have at least 64MiB. If there's more, we | ||
| 65 | detect and register it later */ | ||
| 66 | add_memory_region(0, 64 << 20, BOOT_MEM_RAM); | ||
| 67 | } | ||
| 68 | |||
| 69 | void __init prom_free_prom_memory(void) | ||
| 70 | { | ||
| 71 | } | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/reset.c b/arch/mips/gt64120/momenco_ocelot/reset.c deleted file mode 100644 index 3fd499adf4cf..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/reset.c +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This program is free software; you can redistribute it and/or modify it | ||
| 3 | * under the terms of the GNU General Public License as published by the | ||
| 4 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 5 | * option) any later version. | ||
| 6 | * | ||
| 7 | * Copyright (C) 1997, 2001 Ralf Baechle | ||
| 8 | * Copyright 2001 MontaVista Software Inc. | ||
| 9 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 10 | */ | ||
| 11 | #include <linux/sched.h> | ||
| 12 | #include <linux/mm.h> | ||
| 13 | #include <asm/io.h> | ||
| 14 | #include <asm/pgtable.h> | ||
| 15 | #include <asm/processor.h> | ||
| 16 | #include <asm/reboot.h> | ||
| 17 | #include <asm/system.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | |||
| 20 | void momenco_ocelot_restart(char *command) | ||
| 21 | { | ||
| 22 | void *nvram = ioremap_nocache(0x2c807000, 0x1000); | ||
| 23 | |||
| 24 | if (!nvram) { | ||
| 25 | printk(KERN_NOTICE "ioremap of reset register failed\n"); | ||
| 26 | return; | ||
| 27 | } | ||
| 28 | writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to | ||
| 29 | assert reset in 1/16 second */ | ||
| 30 | mdelay(10+(1000/16)); | ||
| 31 | iounmap(nvram); | ||
| 32 | printk(KERN_NOTICE "Watchdog reset failed\n"); | ||
| 33 | } | ||
| 34 | |||
| 35 | void momenco_ocelot_halt(void) | ||
| 36 | { | ||
| 37 | printk(KERN_NOTICE "\n** You can safely turn off the power\n"); | ||
| 38 | while (1) | ||
| 39 | __asm__(".set\tmips3\n\t" | ||
| 40 | "wait\n\t" | ||
| 41 | ".set\tmips0"); | ||
| 42 | } | ||
| 43 | |||
| 44 | void momenco_ocelot_power_off(void) | ||
| 45 | { | ||
| 46 | momenco_ocelot_halt(); | ||
| 47 | } | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c deleted file mode 100644 index 98b6fb38096d..000000000000 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ /dev/null | |||
| @@ -1,365 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * setup.c | ||
| 3 | * | ||
| 4 | * BRIEF MODULE DESCRIPTION | ||
| 5 | * Momentum Computer Ocelot (CP7000) - board dependent boot routines | ||
| 6 | * | ||
| 7 | * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org) | ||
| 8 | * Copyright (C) 2000 RidgeRun, Inc. | ||
| 9 | * Copyright (C) 2001 Red Hat, Inc. | ||
| 10 | * Copyright (C) 2002 Momentum Computer | ||
| 11 | * | ||
| 12 | * Author: RidgeRun, Inc. | ||
| 13 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
| 14 | * | ||
| 15 | * Copyright 2001 MontaVista Software Inc. | ||
| 16 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 17 | * | ||
| 18 | * This program is free software; you can redistribute it and/or modify it | ||
| 19 | * under the terms of the GNU General Public License as published by the | ||
| 20 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 21 | * option) any later version. | ||
| 22 | * | ||
| 23 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 26 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 33 | * | ||
| 34 | * You should have received a copy of the GNU General Public License along | ||
| 35 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 36 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 37 | * | ||
| 38 | */ | ||
| 39 | #include <linux/init.h> | ||
| 40 | #include <linux/kernel.h> | ||
| 41 | #include <linux/types.h> | ||
| 42 | #include <linux/mm.h> | ||
| 43 | #include <linux/swap.h> | ||
| 44 | #include <linux/ioport.h> | ||
| 45 | #include <linux/sched.h> | ||
| 46 | #include <linux/interrupt.h> | ||
| 47 | #include <linux/pci.h> | ||
| 48 | #include <linux/timex.h> | ||
| 49 | #include <linux/vmalloc.h> | ||
| 50 | #include <linux/pm.h> | ||
| 51 | |||
| 52 | #include <asm/time.h> | ||
| 53 | #include <asm/bootinfo.h> | ||
| 54 | #include <asm/page.h> | ||
| 55 | #include <asm/io.h> | ||
| 56 | #include <asm/irq.h> | ||
| 57 | #include <asm/pci.h> | ||
| 58 | #include <asm/processor.h> | ||
| 59 | #include <asm/reboot.h> | ||
| 60 | #include <asm/traps.h> | ||
| 61 | #include <linux/bootmem.h> | ||
| 62 | #include <linux/initrd.h> | ||
| 63 | #include <asm/gt64120.h> | ||
| 64 | #include "ocelot_pld.h" | ||
| 65 | |||
| 66 | unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE); | ||
| 67 | |||
| 68 | /* These functions are used for rebooting or halting the machine*/ | ||
| 69 | extern void momenco_ocelot_restart(char *command); | ||
| 70 | extern void momenco_ocelot_halt(void); | ||
| 71 | extern void momenco_ocelot_power_off(void); | ||
| 72 | |||
| 73 | extern void momenco_ocelot_irq_setup(void); | ||
| 74 | |||
| 75 | static char reset_reason; | ||
| 76 | |||
| 77 | #define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1) | ||
| 78 | |||
| 79 | static void __init setup_l3cache(unsigned long size); | ||
| 80 | |||
| 81 | /* setup code for a handoff from a version 1 PMON 2000 PROM */ | ||
| 82 | static void PMON_v1_setup(void) | ||
| 83 | { | ||
| 84 | /* A wired TLB entry for the GT64120A and the serial port. The | ||
| 85 | GT64120A is going to be hit on every IRQ anyway - there's | ||
| 86 | absolutely no point in letting it be a random TLB entry, as | ||
| 87 | it'll just cause needless churning of the TLB. And we use | ||
| 88 | the other half for the serial port, which is just a PITA | ||
| 89 | otherwise :) | ||
| 90 | |||
| 91 | Device Physical Virtual | ||
| 92 | GT64120 Internal Regs 0x24000000 0xe0000000 | ||
| 93 | UARTs (CS2) 0x2d000000 0xe0001000 | ||
| 94 | */ | ||
| 95 | add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K); | ||
| 96 | |||
| 97 | /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM | ||
| 98 | in the CS[012] region. We can't use ioremap() yet. The NVRAM | ||
| 99 | is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. | ||
| 100 | |||
| 101 | Ocelot PLD (CS0) 0x2c000000 0xe0020000 | ||
| 102 | NVRAM 0x2c800000 0xe0030000 | ||
| 103 | */ | ||
| 104 | |||
| 105 | add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K); | ||
| 106 | |||
| 107 | /* Relocate the CS3/BootCS region */ | ||
| 108 | GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21); | ||
| 109 | |||
| 110 | /* Relocate CS[012] */ | ||
| 111 | GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21); | ||
| 112 | |||
| 113 | /* Relocate the GT64120A itself... */ | ||
| 114 | GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21); | ||
| 115 | mb(); | ||
| 116 | gt64120_base = 0xe0000000; | ||
| 117 | |||
| 118 | /* ...and the PCI0 view of it. */ | ||
| 119 | GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020); | ||
| 120 | GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000); | ||
| 121 | GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024); | ||
| 122 | GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001); | ||
| 123 | } | ||
| 124 | |||
| 125 | /* setup code for a handoff from a version 2 PMON 2000 PROM */ | ||
| 126 | void PMON_v2_setup() | ||
| 127 | { | ||
| 128 | /* A wired TLB entry for the GT64120A and the serial port. The | ||
| 129 | GT64120A is going to be hit on every IRQ anyway - there's | ||
| 130 | absolutely no point in letting it be a random TLB entry, as | ||
| 131 | it'll just cause needless churning of the TLB. And we use | ||
| 132 | the other half for the serial port, which is just a PITA | ||
| 133 | otherwise :) | ||
| 134 | |||
| 135 | Device Physical Virtual | ||
| 136 | GT64120 Internal Regs 0xf4000000 0xe0000000 | ||
| 137 | UARTs (CS2) 0xfd000000 0xe0001000 | ||
| 138 | */ | ||
| 139 | add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K); | ||
| 140 | |||
| 141 | /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM | ||
| 142 | in the CS[012] region. We can't use ioremap() yet. The NVRAM | ||
| 143 | is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. | ||
| 144 | |||
| 145 | Ocelot PLD (CS0) 0xfc000000 0xe0020000 | ||
| 146 | NVRAM 0xfc800000 0xe0030000 | ||
| 147 | */ | ||
| 148 | add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K); | ||
| 149 | |||
| 150 | gt64120_base = 0xe0000000; | ||
| 151 | } | ||
| 152 | |||
| 153 | void __init plat_mem_setup(void) | ||
| 154 | { | ||
| 155 | void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); | ||
| 156 | unsigned int tmpword; | ||
| 157 | |||
| 158 | _machine_restart = momenco_ocelot_restart; | ||
| 159 | _machine_halt = momenco_ocelot_halt; | ||
| 160 | pm_power_off = momenco_ocelot_power_off; | ||
| 161 | |||
| 162 | /* | ||
| 163 | * initrd_start = (unsigned long)ocelot_initrd_start; | ||
| 164 | * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; | ||
| 165 | * initrd_below_start_ok = 1; | ||
| 166 | */ | ||
| 167 | |||
| 168 | /* do handoff reconfiguration */ | ||
| 169 | if (gt64120_base == KSEG1ADDR(GT_DEF_BASE)) | ||
| 170 | PMON_v1_setup(); | ||
| 171 | else | ||
| 172 | PMON_v2_setup(); | ||
| 173 | |||
| 174 | /* Turn off the Bit-Error LED */ | ||
| 175 | OCELOT_PLD_WRITE(0x80, INTCLR); | ||
| 176 | |||
| 177 | /* Relocate all the PCI1 stuff, not that we use it */ | ||
| 178 | GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21); | ||
| 179 | GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21); | ||
| 180 | GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21); | ||
| 181 | |||
| 182 | /* Relocate PCI0 I/O and Mem0 */ | ||
| 183 | GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21); | ||
| 184 | GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21); | ||
| 185 | |||
| 186 | /* Relocate PCI0 Mem1 */ | ||
| 187 | GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21); | ||
| 188 | |||
| 189 | /* For the initial programming, we assume 512MB configuration */ | ||
| 190 | /* Relocate the CPU's view of the RAM... */ | ||
| 191 | GT_WRITE(GT_SCS10LD_OFS, 0); | ||
| 192 | GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21); | ||
| 193 | GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21); | ||
| 194 | GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); | ||
| 195 | |||
| 196 | GT_WRITE(GT_SCS1LD_OFS, 0xff); | ||
| 197 | GT_WRITE(GT_SCS1HD_OFS, 0x00); | ||
| 198 | GT_WRITE(GT_SCS0LD_OFS, 0); | ||
| 199 | GT_WRITE(GT_SCS0HD_OFS, 0xff); | ||
| 200 | GT_WRITE(GT_SCS3LD_OFS, 0xff); | ||
| 201 | GT_WRITE(GT_SCS3HD_OFS, 0x00); | ||
| 202 | GT_WRITE(GT_SCS2LD_OFS, 0); | ||
| 203 | GT_WRITE(GT_SCS2HD_OFS, 0xff); | ||
| 204 | |||
| 205 | /* ...and the PCI0 view of it. */ | ||
| 206 | GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010); | ||
| 207 | GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000); | ||
| 208 | GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); | ||
| 209 | GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000); | ||
| 210 | GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); | ||
| 211 | GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); | ||
| 212 | |||
| 213 | tmpword = OCELOT_PLD_READ(BOARDREV); | ||
| 214 | if (tmpword < 26) | ||
| 215 | printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword); | ||
| 216 | else | ||
| 217 | printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword); | ||
| 218 | |||
| 219 | tmpword = OCELOT_PLD_READ(PLD1_ID); | ||
| 220 | printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); | ||
| 221 | tmpword = OCELOT_PLD_READ(PLD2_ID); | ||
| 222 | printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); | ||
| 223 | tmpword = OCELOT_PLD_READ(RESET_STATUS); | ||
| 224 | printk("Reset reason: 0x%x\n", tmpword); | ||
| 225 | reset_reason = tmpword; | ||
| 226 | OCELOT_PLD_WRITE(0xff, RESET_STATUS); | ||
| 227 | |||
| 228 | tmpword = OCELOT_PLD_READ(BOARD_STATUS); | ||
| 229 | printk("Board Status register: 0x%02x\n", tmpword); | ||
| 230 | printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); | ||
| 231 | printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); | ||
| 232 | printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); | ||
| 233 | printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); | ||
| 234 | printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); | ||
| 235 | |||
| 236 | if (tmpword&12) | ||
| 237 | l3func((1<<(((tmpword&12) >> 2)+20))); | ||
| 238 | |||
| 239 | switch(tmpword &3) { | ||
| 240 | case 3: | ||
| 241 | /* 512MiB */ | ||
| 242 | /* Decoders are allready set -- just add the | ||
| 243 | * appropriate region */ | ||
| 244 | add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM); | ||
| 245 | add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); | ||
| 246 | break; | ||
| 247 | case 2: | ||
| 248 | /* 256MiB -- two banks of 128MiB */ | ||
| 249 | GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21); | ||
| 250 | GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21); | ||
| 251 | GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); | ||
| 252 | |||
| 253 | GT_WRITE(GT_SCS0HD_OFS, 0x7f); | ||
| 254 | GT_WRITE(GT_SCS2LD_OFS, 0x80); | ||
| 255 | GT_WRITE(GT_SCS2HD_OFS, 0xff); | ||
| 256 | |||
| 257 | /* reconfigure the PCI0 interface view of memory */ | ||
| 258 | GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); | ||
| 259 | GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000); | ||
| 260 | GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); | ||
| 261 | GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); | ||
| 262 | |||
| 263 | add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); | ||
| 264 | add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); | ||
| 265 | break; | ||
| 266 | case 1: | ||
| 267 | /* 128MiB -- 64MiB per bank */ | ||
| 268 | GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21); | ||
| 269 | GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21); | ||
| 270 | GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21); | ||
| 271 | |||
| 272 | GT_WRITE(GT_SCS0HD_OFS, 0x3f); | ||
| 273 | GT_WRITE(GT_SCS2LD_OFS, 0x40); | ||
| 274 | GT_WRITE(GT_SCS2HD_OFS, 0x7f); | ||
| 275 | |||
| 276 | /* reconfigure the PCI0 interface view of memory */ | ||
| 277 | GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); | ||
| 278 | GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); | ||
| 279 | GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000); | ||
| 280 | GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000); | ||
| 281 | |||
| 282 | /* add the appropriate region */ | ||
| 283 | add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); | ||
| 284 | break; | ||
| 285 | case 0: | ||
| 286 | /* 64MiB */ | ||
| 287 | GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21); | ||
| 288 | GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21); | ||
| 289 | GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21); | ||
| 290 | |||
| 291 | GT_WRITE(GT_SCS0HD_OFS, 0x1f); | ||
| 292 | GT_WRITE(GT_SCS2LD_OFS, 0x20); | ||
| 293 | GT_WRITE(GT_SCS2HD_OFS, 0x3f); | ||
| 294 | |||
| 295 | /* reconfigure the PCI0 interface view of memory */ | ||
| 296 | GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); | ||
| 297 | GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); | ||
| 298 | GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000); | ||
| 299 | GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000); | ||
| 300 | |||
| 301 | break; | ||
| 302 | } | ||
| 303 | |||
| 304 | /* Fix up the DiskOnChip mapping */ | ||
| 305 | GT_WRITE(GT_DEV_B3_OFS, 0xfef73); | ||
| 306 | } | ||
| 307 | |||
| 308 | extern int rm7k_tcache_enabled; | ||
| 309 | /* | ||
| 310 | * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() | ||
| 311 | */ | ||
| 312 | #define Page_Invalidate_T 0x16 | ||
| 313 | static void __init setup_l3cache(unsigned long size) | ||
| 314 | { | ||
| 315 | int register i; | ||
| 316 | unsigned long tmp; | ||
| 317 | |||
| 318 | printk("Enabling L3 cache..."); | ||
| 319 | |||
| 320 | /* Enable the L3 cache in the GT64120A's CPU Configuration register */ | ||
| 321 | tmp = GT_READ(GT_CPU_OFS); | ||
| 322 | GT_WRITE(GT_CPU_OFS, tmp | (1<<14)); | ||
| 323 | |||
| 324 | /* Enable the L3 cache in the CPU */ | ||
| 325 | set_c0_config(1<<12 /* CONF_TE */); | ||
| 326 | |||
| 327 | /* Clear the cache */ | ||
| 328 | write_c0_taglo(0); | ||
| 329 | write_c0_taghi(0); | ||
| 330 | |||
| 331 | for (i=0; i < size; i+= 4096) { | ||
| 332 | __asm__ __volatile__ ( | ||
| 333 | ".set noreorder\n\t" | ||
| 334 | ".set mips3\n\t" | ||
| 335 | "cache %1, (%0)\n\t" | ||
| 336 | ".set mips0\n\t" | ||
| 337 | ".set reorder" | ||
| 338 | : | ||
| 339 | : "r" (KSEG0ADDR(i)), | ||
| 340 | "i" (Page_Invalidate_T)); | ||
| 341 | } | ||
| 342 | |||
| 343 | /* Let the RM7000 MM code know that the tertiary cache is enabled */ | ||
| 344 | rm7k_tcache_enabled = 1; | ||
| 345 | |||
| 346 | printk("Done\n"); | ||
| 347 | } | ||
| 348 | |||
| 349 | |||
| 350 | /* This needs to be one of the first initcalls, because no I/O port access | ||
| 351 | can work before this */ | ||
| 352 | |||
| 353 | static int io_base_ioremap(void) | ||
| 354 | { | ||
| 355 | void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE); | ||
| 356 | |||
| 357 | if (!io_remap_range) { | ||
| 358 | panic("Could not ioremap I/O port range"); | ||
| 359 | } | ||
| 360 | set_io_port_base(io_remap_range - GT_PCI_IO_BASE); | ||
| 361 | |||
| 362 | return 0; | ||
| 363 | } | ||
| 364 | |||
| 365 | module_init(io_base_ioremap); | ||
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile index e4250435ad89..bef15c90ae15 100644 --- a/arch/mips/gt64120/wrppmc/Makefile +++ b/arch/mips/gt64120/wrppmc/Makefile | |||
| @@ -10,3 +10,5 @@ | |||
| 10 | # | 10 | # |
| 11 | 11 | ||
| 12 | obj-y += irq.o reset.o setup.o time.o pci.o | 12 | obj-y += irq.o reset.o setup.o time.o pci.o |
| 13 | |||
| 14 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile index ae4c402b5004..575a9442bc82 100644 --- a/arch/mips/jazz/Makefile +++ b/arch/mips/jazz/Makefile | |||
| @@ -3,3 +3,5 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o | 5 | obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o |
| 6 | |||
| 7 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/jmr3927/common/Makefile b/arch/mips/jmr3927/common/Makefile index 01e7db19bcbe..8fd4fcccf10e 100644 --- a/arch/mips/jmr3927/common/Makefile +++ b/arch/mips/jmr3927/common/Makefile | |||
| @@ -3,3 +3,5 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y += prom.o puts.o | 5 | obj-y += prom.o puts.o |
| 6 | |||
| 7 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/jmr3927/rbhma3100/Makefile b/arch/mips/jmr3927/rbhma3100/Makefile index 8d00ba460cef..d86e30dca8f3 100644 --- a/arch/mips/jmr3927/rbhma3100/Makefile +++ b/arch/mips/jmr3927/rbhma3100/Makefile | |||
| @@ -4,3 +4,5 @@ | |||
| 4 | 4 | ||
| 5 | obj-y += init.o irq.o setup.o | 5 | obj-y += init.o irq.o setup.o |
| 6 | obj-$(CONFIG_KGDB) += kgdb_io.o | 6 | obj-$(CONFIG_KGDB) += kgdb_io.o |
| 7 | |||
| 8 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 5c8085b6d7ab..07344cb37596 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile | |||
| @@ -71,3 +71,5 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o | |||
| 71 | CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) | 71 | CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) |
| 72 | 72 | ||
| 73 | obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o | 73 | obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o |
| 74 | |||
| 75 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 3b27309d54b1..013327286c26 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c | |||
| @@ -132,7 +132,6 @@ void output_thread_defines(void) | |||
| 132 | offset("#define THREAD_ECODE ", struct task_struct, \ | 132 | offset("#define THREAD_ECODE ", struct task_struct, \ |
| 133 | thread.error_code); | 133 | thread.error_code); |
| 134 | offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no); | 134 | offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no); |
| 135 | offset("#define THREAD_MFLAGS ", struct task_struct, thread.mflags); | ||
| 136 | offset("#define THREAD_TRAMP ", struct task_struct, \ | 135 | offset("#define THREAD_TRAMP ", struct task_struct, \ |
| 137 | thread.irix_trampoline); | 136 | thread.irix_trampoline); |
| 138 | offset("#define THREAD_OLDCTX ", struct task_struct, \ | 137 | offset("#define THREAD_OLDCTX ", struct task_struct, \ |
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index c15bbc436bbd..e46782b0ebc8 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S | |||
| @@ -138,7 +138,6 @@ | |||
| 138 | .fill 0x400 | 138 | .fill 0x400 |
| 139 | #endif | 139 | #endif |
| 140 | 140 | ||
| 141 | EXPORT(stext) # used for profiling | ||
| 142 | EXPORT(_stext) | 141 | EXPORT(_stext) |
| 143 | 142 | ||
| 144 | #ifndef CONFIG_BOOT_RAW | 143 | #ifndef CONFIG_BOOT_RAW |
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c index c6580018c94b..cb9a14a1ca5b 100644 --- a/arch/mips/kernel/kspd.c +++ b/arch/mips/kernel/kspd.c | |||
| @@ -89,7 +89,7 @@ static int sp_stopping = 0; | |||
| 89 | #define MTSP_O_EXCL 0x0800 | 89 | #define MTSP_O_EXCL 0x0800 |
| 90 | #define MTSP_O_BINARY 0x8000 | 90 | #define MTSP_O_BINARY 0x8000 |
| 91 | 91 | ||
| 92 | #define SP_VPE 1 | 92 | extern int tclimit; |
| 93 | 93 | ||
| 94 | struct apsp_table { | 94 | struct apsp_table { |
| 95 | int sp; | 95 | int sp; |
| @@ -225,8 +225,8 @@ void sp_work_handle_request(void) | |||
| 225 | /* Run the syscall at the priviledge of the user who loaded the | 225 | /* Run the syscall at the priviledge of the user who loaded the |
| 226 | SP program */ | 226 | SP program */ |
| 227 | 227 | ||
| 228 | if (vpe_getuid(SP_VPE)) | 228 | if (vpe_getuid(tclimit)) |
| 229 | sp_setfsuidgid( vpe_getuid(SP_VPE), vpe_getgid(SP_VPE)); | 229 | sp_setfsuidgid(vpe_getuid(tclimit), vpe_getgid(tclimit)); |
| 230 | 230 | ||
| 231 | switch (sc.cmd) { | 231 | switch (sc.cmd) { |
| 232 | /* needs the flags argument translating from SDE kit to | 232 | /* needs the flags argument translating from SDE kit to |
| @@ -245,7 +245,7 @@ void sp_work_handle_request(void) | |||
| 245 | 245 | ||
| 246 | case MTSP_SYSCALL_EXIT: | 246 | case MTSP_SYSCALL_EXIT: |
| 247 | list_for_each_entry(n, &kspd_notifylist, list) | 247 | list_for_each_entry(n, &kspd_notifylist, list) |
| 248 | n->kspd_sp_exit(SP_VPE); | 248 | n->kspd_sp_exit(tclimit); |
| 249 | sp_stopping = 1; | 249 | sp_stopping = 1; |
| 250 | 250 | ||
| 251 | printk(KERN_DEBUG "KSPD got exit syscall from SP exitcode %d\n", | 251 | printk(KERN_DEBUG "KSPD got exit syscall from SP exitcode %d\n", |
| @@ -255,7 +255,7 @@ void sp_work_handle_request(void) | |||
| 255 | case MTSP_SYSCALL_OPEN: | 255 | case MTSP_SYSCALL_OPEN: |
| 256 | generic.arg1 = translate_open_flags(generic.arg1); | 256 | generic.arg1 = translate_open_flags(generic.arg1); |
| 257 | 257 | ||
| 258 | vcwd = vpe_getcwd(SP_VPE); | 258 | vcwd = vpe_getcwd(tclimit); |
| 259 | 259 | ||
| 260 | /* change to the cwd of the process that loaded the SP program */ | 260 | /* change to the cwd of the process that loaded the SP program */ |
| 261 | old_fs = get_fs(); | 261 | old_fs = get_fs(); |
| @@ -283,7 +283,7 @@ void sp_work_handle_request(void) | |||
| 283 | break; | 283 | break; |
| 284 | } /* switch */ | 284 | } /* switch */ |
| 285 | 285 | ||
| 286 | if (vpe_getuid(SP_VPE)) | 286 | if (vpe_getuid(tclimit)) |
| 287 | sp_setfsuidgid( 0, 0); | 287 | sp_setfsuidgid( 0, 0); |
| 288 | 288 | ||
| 289 | old_fs = get_fs(); | 289 | old_fs = get_fs(); |
| @@ -364,10 +364,9 @@ static void startwork(int vpe) | |||
| 364 | } | 364 | } |
| 365 | 365 | ||
| 366 | INIT_WORK(&work, sp_work); | 366 | INIT_WORK(&work, sp_work); |
| 367 | queue_work(workqueue, &work); | 367 | } |
| 368 | } else | ||
| 369 | queue_work(workqueue, &work); | ||
| 370 | 368 | ||
| 369 | queue_work(workqueue, &work); | ||
| 371 | } | 370 | } |
| 372 | 371 | ||
| 373 | static void stopwork(int vpe) | 372 | static void stopwork(int vpe) |
| @@ -389,7 +388,7 @@ static int kspd_module_init(void) | |||
| 389 | 388 | ||
| 390 | notify.start = startwork; | 389 | notify.start = startwork; |
| 391 | notify.stop = stopwork; | 390 | notify.stop = stopwork; |
| 392 | vpe_notify(SP_VPE, ¬ify); | 391 | vpe_notify(tclimit, ¬ify); |
| 393 | 392 | ||
| 394 | return 0; | 393 | return 0; |
| 395 | } | 394 | } |
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index c37568d6fb55..135d9a5fe337 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c | |||
| @@ -566,6 +566,13 @@ asmlinkage long sys32_fadvise64_64(int fd, int __pad, | |||
| 566 | flags); | 566 | flags); |
| 567 | } | 567 | } |
| 568 | 568 | ||
| 569 | asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2, | ||
| 570 | unsigned offset_a3, unsigned len_a4, unsigned len_a5) | ||
| 571 | { | ||
| 572 | return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3), | ||
| 573 | merge_64(len_a4, len_a5)); | ||
| 574 | } | ||
| 575 | |||
| 569 | save_static_function(sys32_clone); | 576 | save_static_function(sys32_clone); |
| 570 | static int noinline __used | 577 | static int noinline __used |
| 571 | _sys32_clone(nabi_no_regargs struct pt_regs regs) | 578 | _sys32_clone(nabi_no_regargs struct pt_regs regs) |
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c index 8f42fa85ac9e..22960d67cf07 100644 --- a/arch/mips/kernel/machine_kexec.c +++ b/arch/mips/kernel/machine_kexec.c | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | #include <asm/page.h> | 14 | #include <asm/page.h> |
| 15 | 15 | ||
| 16 | extern const unsigned char relocate_new_kernel[]; | 16 | extern const unsigned char relocate_new_kernel[]; |
| 17 | extern const unsigned int relocate_new_kernel_size; | 17 | extern const size_t relocate_new_kernel_size; |
| 18 | 18 | ||
| 19 | extern unsigned long kexec_start_address; | 19 | extern unsigned long kexec_start_address; |
| 20 | extern unsigned long kexec_indirection_page; | 20 | extern unsigned long kexec_indirection_page; |
| @@ -40,6 +40,8 @@ machine_crash_shutdown(struct pt_regs *regs) | |||
| 40 | { | 40 | { |
| 41 | } | 41 | } |
| 42 | 42 | ||
| 43 | typedef void (*noretfun_t)(void) __attribute__((noreturn)); | ||
| 44 | |||
| 43 | void | 45 | void |
| 44 | machine_kexec(struct kimage *image) | 46 | machine_kexec(struct kimage *image) |
| 45 | { | 47 | { |
| @@ -51,7 +53,8 @@ machine_kexec(struct kimage *image) | |||
| 51 | (unsigned long)page_address(image->control_code_page); | 53 | (unsigned long)page_address(image->control_code_page); |
| 52 | 54 | ||
| 53 | kexec_start_address = image->start; | 55 | kexec_start_address = image->start; |
| 54 | kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK); | 56 | kexec_indirection_page = |
| 57 | (unsigned long) phys_to_virt(image->head & PAGE_MASK); | ||
| 55 | 58 | ||
| 56 | memcpy((void*)reboot_code_buffer, relocate_new_kernel, | 59 | memcpy((void*)reboot_code_buffer, relocate_new_kernel, |
| 57 | relocate_new_kernel_size); | 60 | relocate_new_kernel_size); |
| @@ -67,7 +70,7 @@ machine_kexec(struct kimage *image) | |||
| 67 | phys_to_virt(entry & PAGE_MASK) : ptr + 1) { | 70 | phys_to_virt(entry & PAGE_MASK) : ptr + 1) { |
| 68 | if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION || | 71 | if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION || |
| 69 | *ptr & IND_DESTINATION) | 72 | *ptr & IND_DESTINATION) |
| 70 | *ptr = phys_to_virt(*ptr); | 73 | *ptr = (unsigned long) phys_to_virt(*ptr); |
| 71 | } | 74 | } |
| 72 | 75 | ||
| 73 | /* | 76 | /* |
| @@ -78,8 +81,8 @@ machine_kexec(struct kimage *image) | |||
| 78 | flush_icache_range(reboot_code_buffer, | 81 | flush_icache_range(reboot_code_buffer, |
| 79 | reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE); | 82 | reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE); |
| 80 | 83 | ||
| 81 | printk("Will call new kernel at %08x\n", image->start); | 84 | printk("Will call new kernel at %08lx\n", image->start); |
| 82 | printk("Bye ...\n"); | 85 | printk("Bye ...\n"); |
| 83 | flush_cache_all(); | 86 | flush_cache_all(); |
| 84 | ((void (*)(void))reboot_code_buffer)(); | 87 | ((noretfun_t) reboot_code_buffer)(); |
| 85 | } | 88 | } |
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c index ede5d73d652e..892665bb12b1 100644 --- a/arch/mips/kernel/mips-mt-fpaff.c +++ b/arch/mips/kernel/mips-mt-fpaff.c | |||
| @@ -50,6 +50,7 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len, | |||
| 50 | cpumask_t effective_mask; | 50 | cpumask_t effective_mask; |
| 51 | int retval; | 51 | int retval; |
| 52 | struct task_struct *p; | 52 | struct task_struct *p; |
| 53 | struct thread_info *ti; | ||
| 53 | 54 | ||
| 54 | if (len < sizeof(new_mask)) | 55 | if (len < sizeof(new_mask)) |
| 55 | return -EINVAL; | 56 | return -EINVAL; |
| @@ -93,16 +94,16 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len, | |||
| 93 | read_unlock(&tasklist_lock); | 94 | read_unlock(&tasklist_lock); |
| 94 | 95 | ||
| 95 | /* Compute new global allowed CPU set if necessary */ | 96 | /* Compute new global allowed CPU set if necessary */ |
| 96 | if ((p->thread.mflags & MF_FPUBOUND) | 97 | ti = task_thread_info(p); |
| 97 | && cpus_intersects(new_mask, mt_fpu_cpumask)) { | 98 | if (test_ti_thread_flag(ti, TIF_FPUBOUND) && |
| 99 | cpus_intersects(new_mask, mt_fpu_cpumask)) { | ||
| 98 | cpus_and(effective_mask, new_mask, mt_fpu_cpumask); | 100 | cpus_and(effective_mask, new_mask, mt_fpu_cpumask); |
| 99 | retval = set_cpus_allowed(p, effective_mask); | 101 | retval = set_cpus_allowed(p, effective_mask); |
| 100 | } else { | 102 | } else { |
| 101 | p->thread.mflags &= ~MF_FPUBOUND; | 103 | clear_ti_thread_flag(ti, TIF_FPUBOUND); |
| 102 | retval = set_cpus_allowed(p, new_mask); | 104 | retval = set_cpus_allowed(p, new_mask); |
| 103 | } | 105 | } |
| 104 | 106 | ||
| 105 | |||
| 106 | out_unlock: | 107 | out_unlock: |
| 107 | put_task_struct(p); | 108 | put_task_struct(p); |
| 108 | unlock_cpu_hotplug(); | 109 | unlock_cpu_hotplug(); |
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c index 1a7d89231299..7169a4db37b8 100644 --- a/arch/mips/kernel/mips-mt.c +++ b/arch/mips/kernel/mips-mt.c | |||
| @@ -21,6 +21,28 @@ | |||
| 21 | #include <asm/r4kcache.h> | 21 | #include <asm/r4kcache.h> |
| 22 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
| 23 | 23 | ||
| 24 | int vpelimit; | ||
| 25 | |||
| 26 | static int __init maxvpes(char *str) | ||
| 27 | { | ||
| 28 | get_option(&str, &vpelimit); | ||
| 29 | |||
| 30 | return 1; | ||
| 31 | } | ||
| 32 | |||
| 33 | __setup("maxvpes=", maxvpes); | ||
| 34 | |||
| 35 | int tclimit; | ||
| 36 | |||
| 37 | static int __init maxtcs(char *str) | ||
| 38 | { | ||
| 39 | get_option(&str, &tclimit); | ||
| 40 | |||
| 41 | return 1; | ||
| 42 | } | ||
| 43 | |||
| 44 | __setup("maxtcs=", maxtcs); | ||
| 45 | |||
| 24 | /* | 46 | /* |
| 25 | * Dump new MIPS MT state for the core. Does not leave TCs halted. | 47 | * Dump new MIPS MT state for the core. Does not leave TCs halted. |
| 26 | * Takes an argument which taken to be a pre-call MVPControl value. | 48 | * Takes an argument which taken to be a pre-call MVPControl value. |
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index bd05f5a927ea..e6ce943099a0 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c | |||
| @@ -77,7 +77,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) | |||
| 77 | status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); | 77 | status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); |
| 78 | #ifdef CONFIG_64BIT | 78 | #ifdef CONFIG_64BIT |
| 79 | status &= ~ST0_FR; | 79 | status &= ~ST0_FR; |
| 80 | status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR; | 80 | status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR; |
| 81 | #endif | 81 | #endif |
| 82 | status |= KU_USER; | 82 | status |= KU_USER; |
| 83 | regs->cp0_status = status; | 83 | regs->cp0_status = status; |
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 893e7bccf226..bbd57b20b43e 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c | |||
| @@ -20,11 +20,11 @@ | |||
| 20 | #include <linux/mm.h> | 20 | #include <linux/mm.h> |
| 21 | #include <linux/errno.h> | 21 | #include <linux/errno.h> |
| 22 | #include <linux/ptrace.h> | 22 | #include <linux/ptrace.h> |
| 23 | #include <linux/audit.h> | ||
| 24 | #include <linux/smp.h> | 23 | #include <linux/smp.h> |
| 25 | #include <linux/user.h> | 24 | #include <linux/user.h> |
| 26 | #include <linux/security.h> | 25 | #include <linux/security.h> |
| 27 | #include <linux/signal.h> | 26 | #include <linux/audit.h> |
| 27 | #include <linux/seccomp.h> | ||
| 28 | 28 | ||
| 29 | #include <asm/byteorder.h> | 29 | #include <asm/byteorder.h> |
| 30 | #include <asm/cpu.h> | 30 | #include <asm/cpu.h> |
| @@ -470,12 +470,17 @@ static inline int audit_arch(void) | |||
| 470 | */ | 470 | */ |
| 471 | asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) | 471 | asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) |
| 472 | { | 472 | { |
| 473 | /* do the secure computing check first */ | ||
| 474 | if (!entryexit) | ||
| 475 | secure_computing(regs->regs[0]); | ||
| 476 | |||
| 473 | if (unlikely(current->audit_context) && entryexit) | 477 | if (unlikely(current->audit_context) && entryexit) |
| 474 | audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]), | 478 | audit_syscall_exit(AUDITSC_RESULT(regs->regs[2]), |
| 475 | regs->regs[2]); | 479 | regs->regs[2]); |
| 476 | 480 | ||
| 477 | if (!(current->ptrace & PT_PTRACED)) | 481 | if (!(current->ptrace & PT_PTRACED)) |
| 478 | goto out; | 482 | goto out; |
| 483 | |||
| 479 | if (!test_thread_flag(TIF_SYSCALL_TRACE)) | 484 | if (!test_thread_flag(TIF_SYSCALL_TRACE)) |
| 480 | goto out; | 485 | goto out; |
| 481 | 486 | ||
| @@ -493,9 +498,10 @@ asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit) | |||
| 493 | send_sig(current->exit_code, current, 1); | 498 | send_sig(current->exit_code, current, 1); |
| 494 | current->exit_code = 0; | 499 | current->exit_code = 0; |
| 495 | } | 500 | } |
| 496 | out: | 501 | |
| 502 | out: | ||
| 497 | if (unlikely(current->audit_context) && !entryexit) | 503 | if (unlikely(current->audit_context) && !entryexit) |
| 498 | audit_syscall_entry(audit_arch(), regs->regs[2], | 504 | audit_syscall_entry(audit_arch(), regs->regs[0], |
| 499 | regs->regs[4], regs->regs[5], | 505 | regs->regs[4], regs->regs[5], |
| 500 | regs->regs[6], regs->regs[7]); | 506 | regs->regs[6], regs->regs[7]); |
| 501 | } | 507 | } |
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S index a3f0d00c1334..87481f916a61 100644 --- a/arch/mips/kernel/relocate_kernel.S +++ b/arch/mips/kernel/relocate_kernel.S | |||
| @@ -14,67 +14,69 @@ | |||
| 14 | #include <asm/stackframe.h> | 14 | #include <asm/stackframe.h> |
| 15 | #include <asm/addrspace.h> | 15 | #include <asm/addrspace.h> |
| 16 | 16 | ||
| 17 | .globl relocate_new_kernel | 17 | LEAF(relocate_new_kernel) |
| 18 | relocate_new_kernel: | 18 | PTR_L s0, kexec_indirection_page |
| 19 | 19 | PTR_L s1, kexec_start_address | |
| 20 | PTR_L s0, kexec_indirection_page | ||
| 21 | PTR_L s1, kexec_start_address | ||
| 22 | 20 | ||
| 23 | process_entry: | 21 | process_entry: |
| 24 | PTR_L s2, (s0) | 22 | PTR_L s2, (s0) |
| 25 | PTR_ADD s0, s0, SZREG | 23 | PTR_ADD s0, s0, SZREG |
| 26 | 24 | ||
| 27 | /* destination page */ | 25 | /* destination page */ |
| 28 | and s3, s2, 0x1 | 26 | and s3, s2, 0x1 |
| 29 | beq s3, zero, 1f | 27 | beq s3, zero, 1f |
| 30 | and s4, s2, ~0x1 /* store destination addr in s4 */ | 28 | and s4, s2, ~0x1 /* store destination addr in s4 */ |
| 31 | move a0, s4 | 29 | move a0, s4 |
| 32 | b process_entry | 30 | b process_entry |
| 33 | 31 | ||
| 34 | 1: | 32 | 1: |
| 35 | /* indirection page, update s0 */ | 33 | /* indirection page, update s0 */ |
| 36 | and s3, s2, 0x2 | 34 | and s3, s2, 0x2 |
| 37 | beq s3, zero, 1f | 35 | beq s3, zero, 1f |
| 38 | and s0, s2, ~0x2 | 36 | and s0, s2, ~0x2 |
| 39 | b process_entry | 37 | b process_entry |
| 40 | 38 | ||
| 41 | 1: | 39 | 1: |
| 42 | /* done page */ | 40 | /* done page */ |
| 43 | and s3, s2, 0x4 | 41 | and s3, s2, 0x4 |
| 44 | beq s3, zero, 1f | 42 | beq s3, zero, 1f |
| 45 | b done | 43 | b done |
| 46 | 1: | 44 | 1: |
| 47 | /* source page */ | 45 | /* source page */ |
| 48 | and s3, s2, 0x8 | 46 | and s3, s2, 0x8 |
| 49 | beq s3, zero, process_entry | 47 | beq s3, zero, process_entry |
| 50 | and s2, s2, ~0x8 | 48 | and s2, s2, ~0x8 |
| 51 | li s6, (1 << PAGE_SHIFT) / SZREG | 49 | li s6, (1 << PAGE_SHIFT) / SZREG |
| 52 | 50 | ||
| 53 | copy_word: | 51 | copy_word: |
| 54 | /* copy page word by word */ | 52 | /* copy page word by word */ |
| 55 | REG_L s5, (s2) | 53 | REG_L s5, (s2) |
| 56 | REG_S s5, (s4) | 54 | REG_S s5, (s4) |
| 57 | INT_ADD s4, s4, SZREG | 55 | PTR_ADD s4, s4, SZREG |
| 58 | INT_ADD s2, s2, SZREG | 56 | PTR_ADD s2, s2, SZREG |
| 59 | INT_SUB s6, s6, 1 | 57 | LONG_SUB s6, s6, 1 |
| 60 | beq s6, zero, process_entry | 58 | beq s6, zero, process_entry |
| 61 | b copy_word | 59 | b copy_word |
| 62 | b process_entry | 60 | b process_entry |
| 63 | 61 | ||
| 64 | done: | 62 | done: |
| 65 | /* jump to kexec_start_address */ | 63 | /* jump to kexec_start_address */ |
| 66 | j s1 | 64 | j s1 |
| 65 | END(relocate_new_kernel) | ||
| 67 | 66 | ||
| 68 | .globl kexec_start_address | ||
| 69 | kexec_start_address: | 67 | kexec_start_address: |
| 70 | .long 0x0 | 68 | EXPORT(kexec_start_address) |
| 69 | PTR 0x0 | ||
| 70 | .size kexec_start_address, PTRSIZE | ||
| 71 | 71 | ||
| 72 | .globl kexec_indirection_page | ||
| 73 | kexec_indirection_page: | 72 | kexec_indirection_page: |
| 74 | .long 0x0 | 73 | EXPORT(kexec_indirection_page) |
| 74 | PTR 0 | ||
| 75 | .size kexec_indirection_page, PTRSIZE | ||
| 75 | 76 | ||
| 76 | relocate_new_kernel_end: | 77 | relocate_new_kernel_end: |
| 77 | 78 | ||
| 78 | .globl relocate_new_kernel_size | ||
| 79 | relocate_new_kernel_size: | 79 | relocate_new_kernel_size: |
| 80 | .long relocate_new_kernel_end - relocate_new_kernel | 80 | EXPORT(relocate_new_kernel_size) |
| 81 | PTR relocate_new_kernel_end - relocate_new_kernel | ||
| 82 | .size relocate_new_kernel_size, PTRSIZE | ||
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 8cf24d716d41..aab89e97abb5 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c | |||
| @@ -40,12 +40,11 @@ | |||
| 40 | #include <asm/atomic.h> | 40 | #include <asm/atomic.h> |
| 41 | #include <asm/cpu.h> | 41 | #include <asm/cpu.h> |
| 42 | #include <asm/processor.h> | 42 | #include <asm/processor.h> |
| 43 | #include <asm/mips_mt.h> | ||
| 43 | #include <asm/system.h> | 44 | #include <asm/system.h> |
| 44 | #include <asm/vpe.h> | 45 | #include <asm/vpe.h> |
| 45 | #include <asm/rtlx.h> | 46 | #include <asm/rtlx.h> |
| 46 | 47 | ||
| 47 | #define RTLX_TARG_VPE 1 | ||
| 48 | |||
| 49 | static struct rtlx_info *rtlx; | 48 | static struct rtlx_info *rtlx; |
| 50 | static int major; | 49 | static int major; |
| 51 | static char module_name[] = "rtlx"; | 50 | static char module_name[] = "rtlx"; |
| @@ -165,10 +164,10 @@ int rtlx_open(int index, int can_sleep) | |||
| 165 | } | 164 | } |
| 166 | 165 | ||
| 167 | if (rtlx == NULL) { | 166 | if (rtlx == NULL) { |
| 168 | if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) { | 167 | if( (p = vpe_get_shared(tclimit)) == NULL) { |
| 169 | if (can_sleep) { | 168 | if (can_sleep) { |
| 170 | __wait_event_interruptible(channel_wqs[index].lx_queue, | 169 | __wait_event_interruptible(channel_wqs[index].lx_queue, |
| 171 | (p = vpe_get_shared(RTLX_TARG_VPE)), | 170 | (p = vpe_get_shared(tclimit)), |
| 172 | ret); | 171 | ret); |
| 173 | if (ret) | 172 | if (ret) |
| 174 | goto out_fail; | 173 | goto out_fail; |
| @@ -472,11 +471,24 @@ static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; | |||
| 472 | static char register_chrdev_failed[] __initdata = | 471 | static char register_chrdev_failed[] __initdata = |
| 473 | KERN_ERR "rtlx_module_init: unable to register device\n"; | 472 | KERN_ERR "rtlx_module_init: unable to register device\n"; |
| 474 | 473 | ||
| 475 | static int rtlx_module_init(void) | 474 | static int __init rtlx_module_init(void) |
| 476 | { | 475 | { |
| 477 | struct device *dev; | 476 | struct device *dev; |
| 478 | int i, err; | 477 | int i, err; |
| 479 | 478 | ||
| 479 | if (!cpu_has_mipsmt) { | ||
| 480 | printk("VPE loader: not a MIPS MT capable processor\n"); | ||
| 481 | return -ENODEV; | ||
| 482 | } | ||
| 483 | |||
| 484 | if (tclimit == 0) { | ||
| 485 | printk(KERN_WARNING "No TCs reserved for AP/SP, not " | ||
| 486 | "initializing RTLX.\nPass maxtcs=<n> argument as kernel " | ||
| 487 | "argument\n"); | ||
| 488 | |||
| 489 | return -ENODEV; | ||
| 490 | } | ||
| 491 | |||
| 480 | major = register_chrdev(0, module_name, &rtlx_fops); | 492 | major = register_chrdev(0, module_name, &rtlx_fops); |
| 481 | if (major < 0) { | 493 | if (major < 0) { |
| 482 | printk(register_chrdev_failed); | 494 | printk(register_chrdev_failed); |
| @@ -501,7 +513,7 @@ static int rtlx_module_init(void) | |||
| 501 | /* set up notifiers */ | 513 | /* set up notifiers */ |
| 502 | notify.start = starting; | 514 | notify.start = starting; |
| 503 | notify.stop = stopping; | 515 | notify.stop = stopping; |
| 504 | vpe_notify(RTLX_TARG_VPE, ¬ify); | 516 | vpe_notify(tclimit, ¬ify); |
| 505 | 517 | ||
| 506 | if (cpu_has_vint) | 518 | if (cpu_has_vint) |
| 507 | set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); | 519 | set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); |
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index ae985d1fcca1..82480a1717d8 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S | |||
| @@ -662,6 +662,7 @@ einval: li v0, -EINVAL | |||
| 662 | sys sys_signalfd 3 | 662 | sys sys_signalfd 3 |
| 663 | sys sys_timerfd 4 | 663 | sys sys_timerfd 4 |
| 664 | sys sys_eventfd 1 | 664 | sys sys_eventfd 1 |
| 665 | sys sys_fallocate 6 /* 4320 */ | ||
| 665 | .endm | 666 | .endm |
| 666 | 667 | ||
| 667 | /* We pre-compute the number of _instruction_ bytes needed to | 668 | /* We pre-compute the number of _instruction_ bytes needed to |
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 7bcd5a1a85f5..c2c10876da2e 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S | |||
| @@ -477,4 +477,5 @@ sys_call_table: | |||
| 477 | PTR sys_signalfd | 477 | PTR sys_signalfd |
| 478 | PTR sys_timerfd | 478 | PTR sys_timerfd |
| 479 | PTR sys_eventfd | 479 | PTR sys_eventfd |
| 480 | PTR sys_fallocate | ||
| 480 | .size sys_call_table,.-sys_call_table | 481 | .size sys_call_table,.-sys_call_table |
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 532a2f3b42fc..53d7a977193c 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S | |||
| @@ -403,4 +403,5 @@ EXPORT(sysn32_call_table) | |||
| 403 | PTR compat_sys_signalfd /* 5280 */ | 403 | PTR compat_sys_signalfd /* 5280 */ |
| 404 | PTR compat_sys_timerfd | 404 | PTR compat_sys_timerfd |
| 405 | PTR sys_eventfd | 405 | PTR sys_eventfd |
| 406 | PTR sys_fallocate | ||
| 406 | .size sysn32_call_table,.-sysn32_call_table | 407 | .size sysn32_call_table,.-sysn32_call_table |
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 6bbe0f4ed8ba..b3ed731a24c6 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S | |||
| @@ -525,4 +525,5 @@ sys_call_table: | |||
| 525 | PTR compat_sys_signalfd | 525 | PTR compat_sys_signalfd |
| 526 | PTR compat_sys_timerfd | 526 | PTR compat_sys_timerfd |
| 527 | PTR sys_eventfd | 527 | PTR sys_eventfd |
| 528 | PTR sys_fallocate /* 4320 */ | ||
| 528 | .size sys_call_table,.-sys_call_table | 529 | .size sys_call_table,.-sys_call_table |
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 486b8e5f52d0..64b612a0a622 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c | |||
| @@ -18,7 +18,6 @@ | |||
| 18 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
| 19 | #include <linux/wait.h> | 19 | #include <linux/wait.h> |
| 20 | #include <linux/ptrace.h> | 20 | #include <linux/ptrace.h> |
| 21 | #include <linux/compat.h> | ||
| 22 | #include <linux/suspend.h> | 21 | #include <linux/suspend.h> |
| 23 | #include <linux/compiler.h> | 22 | #include <linux/compiler.h> |
| 24 | #include <linux/uaccess.h> | 23 | #include <linux/uaccess.h> |
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 04bbbd8d91ab..73b0dab02668 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c | |||
| @@ -194,6 +194,61 @@ void smp_call_function_interrupt(void) | |||
| 194 | } | 194 | } |
| 195 | } | 195 | } |
| 196 | 196 | ||
| 197 | int smp_call_function_single(int cpu, void (*func) (void *info), void *info, | ||
| 198 | int retry, int wait) | ||
| 199 | { | ||
| 200 | struct call_data_struct data; | ||
| 201 | int me; | ||
| 202 | |||
| 203 | /* | ||
| 204 | * Can die spectacularly if this CPU isn't yet marked online | ||
| 205 | */ | ||
| 206 | if (!cpu_online(cpu)) | ||
| 207 | return 0; | ||
| 208 | |||
| 209 | me = get_cpu(); | ||
| 210 | BUG_ON(!cpu_online(me)); | ||
| 211 | |||
| 212 | if (cpu == me) { | ||
| 213 | local_irq_disable(); | ||
| 214 | func(info); | ||
| 215 | local_irq_enable(); | ||
| 216 | put_cpu(); | ||
| 217 | return 0; | ||
| 218 | } | ||
| 219 | |||
| 220 | /* Can deadlock when called with interrupts disabled */ | ||
| 221 | WARN_ON(irqs_disabled()); | ||
| 222 | |||
| 223 | data.func = func; | ||
| 224 | data.info = info; | ||
| 225 | atomic_set(&data.started, 0); | ||
| 226 | data.wait = wait; | ||
| 227 | if (wait) | ||
| 228 | atomic_set(&data.finished, 0); | ||
| 229 | |||
| 230 | spin_lock(&smp_call_lock); | ||
| 231 | call_data = &data; | ||
| 232 | smp_mb(); | ||
| 233 | |||
| 234 | /* Send a message to the other CPU */ | ||
| 235 | core_send_ipi(cpu, SMP_CALL_FUNCTION); | ||
| 236 | |||
| 237 | /* Wait for response */ | ||
| 238 | /* FIXME: lock-up detection, backtrace on lock-up */ | ||
| 239 | while (atomic_read(&data.started) != 1) | ||
| 240 | barrier(); | ||
| 241 | |||
| 242 | if (wait) | ||
| 243 | while (atomic_read(&data.finished) != 1) | ||
| 244 | barrier(); | ||
| 245 | call_data = NULL; | ||
| 246 | spin_unlock(&smp_call_lock); | ||
| 247 | |||
| 248 | put_cpu(); | ||
| 249 | return 0; | ||
| 250 | } | ||
| 251 | |||
| 197 | static void stop_this_cpu(void *dummy) | 252 | static void stop_this_cpu(void *dummy) |
| 198 | { | 253 | { |
| 199 | /* | 254 | /* |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 342d873b2ecc..16aa5d37117c 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
| @@ -86,25 +86,11 @@ unsigned int smtc_status = 0; | |||
| 86 | 86 | ||
| 87 | /* Boot command line configuration overrides */ | 87 | /* Boot command line configuration overrides */ |
| 88 | 88 | ||
| 89 | static int vpelimit = 0; | ||
| 90 | static int tclimit = 0; | ||
| 91 | static int ipibuffers = 0; | 89 | static int ipibuffers = 0; |
| 92 | static int nostlb = 0; | 90 | static int nostlb = 0; |
| 93 | static int asidmask = 0; | 91 | static int asidmask = 0; |
| 94 | unsigned long smtc_asid_mask = 0xff; | 92 | unsigned long smtc_asid_mask = 0xff; |
| 95 | 93 | ||
| 96 | static int __init maxvpes(char *str) | ||
| 97 | { | ||
| 98 | get_option(&str, &vpelimit); | ||
| 99 | return 1; | ||
| 100 | } | ||
| 101 | |||
| 102 | static int __init maxtcs(char *str) | ||
| 103 | { | ||
| 104 | get_option(&str, &tclimit); | ||
| 105 | return 1; | ||
| 106 | } | ||
| 107 | |||
| 108 | static int __init ipibufs(char *str) | 94 | static int __init ipibufs(char *str) |
| 109 | { | 95 | { |
| 110 | get_option(&str, &ipibuffers); | 96 | get_option(&str, &ipibuffers); |
| @@ -137,8 +123,6 @@ static int __init asidmask_set(char *str) | |||
| 137 | return 1; | 123 | return 1; |
| 138 | } | 124 | } |
| 139 | 125 | ||
| 140 | __setup("maxvpes=", maxvpes); | ||
| 141 | __setup("maxtcs=", maxtcs); | ||
| 142 | __setup("ipibufs=", ipibufs); | 126 | __setup("ipibufs=", ipibufs); |
| 143 | __setup("nostlb", stlb_disable); | 127 | __setup("nostlb", stlb_disable); |
| 144 | __setup("asidmask=", asidmask_set); | 128 | __setup("asidmask=", asidmask_set); |
| @@ -168,9 +152,9 @@ static int __init tintq(char *str) | |||
| 168 | 152 | ||
| 169 | __setup("tintq=", tintq); | 153 | __setup("tintq=", tintq); |
| 170 | 154 | ||
| 171 | int imstuckcount[2][8]; | 155 | static int imstuckcount[2][8]; |
| 172 | /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ | 156 | /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ |
| 173 | int vpemask[2][8] = { | 157 | static int vpemask[2][8] = { |
| 174 | {0, 0, 1, 0, 0, 0, 0, 1}, | 158 | {0, 0, 1, 0, 0, 0, 0, 1}, |
| 175 | {0, 0, 0, 0, 0, 0, 0, 1} | 159 | {0, 0, 0, 0, 0, 0, 0, 1} |
| 176 | }; | 160 | }; |
| @@ -540,7 +524,7 @@ void mipsmt_prepare_cpus(void) | |||
| 540 | * (unsigned long)idle->thread_info the gp | 524 | * (unsigned long)idle->thread_info the gp |
| 541 | * | 525 | * |
| 542 | */ | 526 | */ |
| 543 | void smtc_boot_secondary(int cpu, struct task_struct *idle) | 527 | void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) |
| 544 | { | 528 | { |
| 545 | extern u32 kernelsp[NR_CPUS]; | 529 | extern u32 kernelsp[NR_CPUS]; |
| 546 | long flags; | 530 | long flags; |
| @@ -876,7 +860,7 @@ void deferred_smtc_ipi(void) | |||
| 876 | * Send clock tick to all TCs except the one executing the funtion | 860 | * Send clock tick to all TCs except the one executing the funtion |
| 877 | */ | 861 | */ |
| 878 | 862 | ||
| 879 | void smtc_timer_broadcast(int vpe) | 863 | void smtc_timer_broadcast(void) |
| 880 | { | 864 | { |
| 881 | int cpu; | 865 | int cpu; |
| 882 | int myTC = cpu_data[smp_processor_id()].tc_id; | 866 | int myTC = cpu_data[smp_processor_id()].tc_id; |
| @@ -975,7 +959,12 @@ static void ipi_irq_dispatch(void) | |||
| 975 | do_IRQ(cpu_ipi_irq); | 959 | do_IRQ(cpu_ipi_irq); |
| 976 | } | 960 | } |
| 977 | 961 | ||
| 978 | static struct irqaction irq_ipi; | 962 | static struct irqaction irq_ipi = { |
| 963 | .handler = ipi_interrupt, | ||
| 964 | .flags = IRQF_DISABLED, | ||
| 965 | .name = "SMTC_IPI", | ||
| 966 | .flags = IRQF_PERCPU | ||
| 967 | }; | ||
| 979 | 968 | ||
| 980 | static void setup_cross_vpe_interrupts(unsigned int nvpe) | 969 | static void setup_cross_vpe_interrupts(unsigned int nvpe) |
| 981 | { | 970 | { |
| @@ -987,13 +976,8 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe) | |||
| 987 | 976 | ||
| 988 | set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); | 977 | set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); |
| 989 | 978 | ||
| 990 | irq_ipi.handler = ipi_interrupt; | ||
| 991 | irq_ipi.flags = IRQF_DISABLED; | ||
| 992 | irq_ipi.name = "SMTC_IPI"; | ||
| 993 | |||
| 994 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); | 979 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); |
| 995 | 980 | ||
| 996 | irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; | ||
| 997 | set_irq_handler(cpu_ipi_irq, handle_percpu_irq); | 981 | set_irq_handler(cpu_ipi_irq, handle_percpu_irq); |
| 998 | } | 982 | } |
| 999 | 983 | ||
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 541b5005957e..7c800ec3ff55 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c | |||
| @@ -281,16 +281,24 @@ asmlinkage int sys_set_thread_area(unsigned long addr) | |||
| 281 | 281 | ||
| 282 | asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) | 282 | asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) |
| 283 | { | 283 | { |
| 284 | int tmp; | 284 | switch (cmd) { |
| 285 | |||
| 286 | switch(cmd) { | ||
| 287 | case MIPS_ATOMIC_SET: | 285 | case MIPS_ATOMIC_SET: |
| 288 | printk(KERN_CRIT "How did I get here?\n"); | 286 | printk(KERN_CRIT "How did I get here?\n"); |
| 289 | return -EINVAL; | 287 | return -EINVAL; |
| 290 | 288 | ||
| 291 | case MIPS_FIXADE: | 289 | case MIPS_FIXADE: |
| 292 | tmp = current->thread.mflags & ~3; | 290 | if (arg1 & ~3) |
| 293 | current->thread.mflags = tmp | (arg1 & 3); | 291 | return -EINVAL; |
| 292 | |||
| 293 | if (arg1 & 1) | ||
| 294 | set_thread_flag(TIF_FIXADE); | ||
| 295 | else | ||
| 296 | clear_thread_flag(TIF_FIXADE); | ||
| 297 | if (arg1 & 2) | ||
| 298 | set_thread_flag(TIF_LOGADE); | ||
| 299 | else | ||
| 300 | clear_thread_flag(TIF_FIXADE); | ||
| 301 | |||
| 294 | return 0; | 302 | return 0; |
| 295 | 303 | ||
| 296 | case FLUSH_CACHE: | 304 | case FLUSH_CACHE: |
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ce277cb34dd0..c8e291c83057 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
| @@ -775,7 +775,7 @@ static void mt_ase_fp_affinity(void) | |||
| 775 | cpus_and(tmask, current->thread.user_cpus_allowed, | 775 | cpus_and(tmask, current->thread.user_cpus_allowed, |
| 776 | mt_fpu_cpumask); | 776 | mt_fpu_cpumask); |
| 777 | set_cpus_allowed(current, tmask); | 777 | set_cpus_allowed(current, tmask); |
| 778 | current->thread.mflags |= MF_FPUBOUND; | 778 | set_thread_flag(TIF_FPUBOUND); |
| 779 | } | 779 | } |
| 780 | } | 780 | } |
| 781 | #endif /* CONFIG_MIPS_MT_FPAFF */ | 781 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 8b9c34ffae18..d34b1fb3665d 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c | |||
| @@ -101,16 +101,14 @@ static u32 unaligned_action; | |||
| 101 | #endif | 101 | #endif |
| 102 | extern void show_registers(struct pt_regs *regs); | 102 | extern void show_registers(struct pt_regs *regs); |
| 103 | 103 | ||
| 104 | static inline int emulate_load_store_insn(struct pt_regs *regs, | 104 | static void emulate_load_store_insn(struct pt_regs *regs, |
| 105 | void __user *addr, unsigned int __user *pc, | 105 | void __user *addr, unsigned int __user *pc) |
| 106 | unsigned long **regptr, unsigned long *newvalue) | ||
| 107 | { | 106 | { |
| 108 | union mips_instruction insn; | 107 | union mips_instruction insn; |
| 109 | unsigned long value; | 108 | unsigned long value; |
| 110 | unsigned int res; | 109 | unsigned int res; |
| 111 | 110 | ||
| 112 | regs->regs[0] = 0; | 111 | regs->regs[0] = 0; |
| 113 | *regptr=NULL; | ||
| 114 | 112 | ||
| 115 | /* | 113 | /* |
| 116 | * This load never faults. | 114 | * This load never faults. |
| @@ -179,8 +177,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 179 | : "r" (addr), "i" (-EFAULT)); | 177 | : "r" (addr), "i" (-EFAULT)); |
| 180 | if (res) | 178 | if (res) |
| 181 | goto fault; | 179 | goto fault; |
| 182 | *newvalue = value; | 180 | compute_return_epc(regs); |
| 183 | *regptr = ®s->regs[insn.i_format.rt]; | 181 | regs->regs[insn.i_format.rt] = value; |
| 184 | break; | 182 | break; |
| 185 | 183 | ||
| 186 | case lw_op: | 184 | case lw_op: |
| @@ -209,8 +207,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 209 | : "r" (addr), "i" (-EFAULT)); | 207 | : "r" (addr), "i" (-EFAULT)); |
| 210 | if (res) | 208 | if (res) |
| 211 | goto fault; | 209 | goto fault; |
| 212 | *newvalue = value; | 210 | compute_return_epc(regs); |
| 213 | *regptr = ®s->regs[insn.i_format.rt]; | 211 | regs->regs[insn.i_format.rt] = value; |
| 214 | break; | 212 | break; |
| 215 | 213 | ||
| 216 | case lhu_op: | 214 | case lhu_op: |
| @@ -243,8 +241,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 243 | : "r" (addr), "i" (-EFAULT)); | 241 | : "r" (addr), "i" (-EFAULT)); |
| 244 | if (res) | 242 | if (res) |
| 245 | goto fault; | 243 | goto fault; |
| 246 | *newvalue = value; | 244 | compute_return_epc(regs); |
| 247 | *regptr = ®s->regs[insn.i_format.rt]; | 245 | regs->regs[insn.i_format.rt] = value; |
| 248 | break; | 246 | break; |
| 249 | 247 | ||
| 250 | case lwu_op: | 248 | case lwu_op: |
| @@ -283,8 +281,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 283 | : "r" (addr), "i" (-EFAULT)); | 281 | : "r" (addr), "i" (-EFAULT)); |
| 284 | if (res) | 282 | if (res) |
| 285 | goto fault; | 283 | goto fault; |
| 286 | *newvalue = value; | 284 | compute_return_epc(regs); |
| 287 | *regptr = ®s->regs[insn.i_format.rt]; | 285 | regs->regs[insn.i_format.rt] = value; |
| 288 | break; | 286 | break; |
| 289 | #endif /* CONFIG_64BIT */ | 287 | #endif /* CONFIG_64BIT */ |
| 290 | 288 | ||
| @@ -325,8 +323,8 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 325 | : "r" (addr), "i" (-EFAULT)); | 323 | : "r" (addr), "i" (-EFAULT)); |
| 326 | if (res) | 324 | if (res) |
| 327 | goto fault; | 325 | goto fault; |
| 328 | *newvalue = value; | 326 | compute_return_epc(regs); |
| 329 | *regptr = ®s->regs[insn.i_format.rt]; | 327 | regs->regs[insn.i_format.rt] = value; |
| 330 | break; | 328 | break; |
| 331 | #endif /* CONFIG_64BIT */ | 329 | #endif /* CONFIG_64BIT */ |
| 332 | 330 | ||
| @@ -367,6 +365,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 367 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 365 | : "r" (value), "r" (addr), "i" (-EFAULT)); |
| 368 | if (res) | 366 | if (res) |
| 369 | goto fault; | 367 | goto fault; |
| 368 | compute_return_epc(regs); | ||
| 370 | break; | 369 | break; |
| 371 | 370 | ||
| 372 | case sw_op: | 371 | case sw_op: |
| @@ -397,6 +396,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 397 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 396 | : "r" (value), "r" (addr), "i" (-EFAULT)); |
| 398 | if (res) | 397 | if (res) |
| 399 | goto fault; | 398 | goto fault; |
| 399 | compute_return_epc(regs); | ||
| 400 | break; | 400 | break; |
| 401 | 401 | ||
| 402 | case sd_op: | 402 | case sd_op: |
| @@ -435,6 +435,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 435 | : "r" (value), "r" (addr), "i" (-EFAULT)); | 435 | : "r" (value), "r" (addr), "i" (-EFAULT)); |
| 436 | if (res) | 436 | if (res) |
| 437 | goto fault; | 437 | goto fault; |
| 438 | compute_return_epc(regs); | ||
| 438 | break; | 439 | break; |
| 439 | #endif /* CONFIG_64BIT */ | 440 | #endif /* CONFIG_64BIT */ |
| 440 | 441 | ||
| @@ -473,34 +474,31 @@ static inline int emulate_load_store_insn(struct pt_regs *regs, | |||
| 473 | unaligned_instructions++; | 474 | unaligned_instructions++; |
| 474 | #endif | 475 | #endif |
| 475 | 476 | ||
| 476 | return 0; | 477 | return; |
| 477 | 478 | ||
| 478 | fault: | 479 | fault: |
| 479 | /* Did we have an exception handler installed? */ | 480 | /* Did we have an exception handler installed? */ |
| 480 | if (fixup_exception(regs)) | 481 | if (fixup_exception(regs)) |
| 481 | return 1; | 482 | return; |
| 482 | 483 | ||
| 483 | die_if_kernel ("Unhandled kernel unaligned access", regs); | 484 | die_if_kernel ("Unhandled kernel unaligned access", regs); |
| 484 | send_sig(SIGSEGV, current, 1); | 485 | send_sig(SIGSEGV, current, 1); |
| 485 | 486 | ||
| 486 | return 0; | 487 | return; |
| 487 | 488 | ||
| 488 | sigbus: | 489 | sigbus: |
| 489 | die_if_kernel("Unhandled kernel unaligned access", regs); | 490 | die_if_kernel("Unhandled kernel unaligned access", regs); |
| 490 | send_sig(SIGBUS, current, 1); | 491 | send_sig(SIGBUS, current, 1); |
| 491 | 492 | ||
| 492 | return 0; | 493 | return; |
| 493 | 494 | ||
| 494 | sigill: | 495 | sigill: |
| 495 | die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); | 496 | die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); |
| 496 | send_sig(SIGILL, current, 1); | 497 | send_sig(SIGILL, current, 1); |
| 497 | |||
| 498 | return 0; | ||
| 499 | } | 498 | } |
| 500 | 499 | ||
| 501 | asmlinkage void do_ade(struct pt_regs *regs) | 500 | asmlinkage void do_ade(struct pt_regs *regs) |
| 502 | { | 501 | { |
| 503 | unsigned long *regptr, newval; | ||
| 504 | extern int do_dsemulret(struct pt_regs *); | 502 | extern int do_dsemulret(struct pt_regs *); |
| 505 | unsigned int __user *pc; | 503 | unsigned int __user *pc; |
| 506 | mm_segment_t seg; | 504 | mm_segment_t seg; |
| @@ -524,7 +522,7 @@ asmlinkage void do_ade(struct pt_regs *regs) | |||
| 524 | goto sigbus; | 522 | goto sigbus; |
| 525 | 523 | ||
| 526 | pc = (unsigned int __user *) exception_epc(regs); | 524 | pc = (unsigned int __user *) exception_epc(regs); |
| 527 | if (user_mode(regs) && (current->thread.mflags & MF_FIXADE) == 0) | 525 | if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) |
| 528 | goto sigbus; | 526 | goto sigbus; |
| 529 | if (unaligned_action == UNALIGNED_ACTION_SIGNAL) | 527 | if (unaligned_action == UNALIGNED_ACTION_SIGNAL) |
| 530 | goto sigbus; | 528 | goto sigbus; |
| @@ -538,16 +536,7 @@ asmlinkage void do_ade(struct pt_regs *regs) | |||
| 538 | seg = get_fs(); | 536 | seg = get_fs(); |
| 539 | if (!user_mode(regs)) | 537 | if (!user_mode(regs)) |
| 540 | set_fs(KERNEL_DS); | 538 | set_fs(KERNEL_DS); |
| 541 | if (!emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc, | 539 | emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); |
| 542 | ®ptr, &newval)) { | ||
| 543 | compute_return_epc(regs); | ||
| 544 | /* | ||
| 545 | * Now that branch is evaluated, update the dest | ||
| 546 | * register if necessary | ||
| 547 | */ | ||
| 548 | if (regptr) | ||
| 549 | *regptr = newval; | ||
| 550 | } | ||
| 551 | set_fs(seg); | 540 | set_fs(seg); |
| 552 | 541 | ||
| 553 | return; | 542 | return; |
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index a2bee10f04cf..3c09b9785f4c 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | * To load and run, simply cat a SP 'program file' to /dev/vpe1. | 27 | * To load and run, simply cat a SP 'program file' to /dev/vpe1. |
| 28 | * i.e cat spapp >/dev/vpe1. | 28 | * i.e cat spapp >/dev/vpe1. |
| 29 | */ | 29 | */ |
| 30 | |||
| 31 | #include <linux/kernel.h> | 30 | #include <linux/kernel.h> |
| 32 | #include <linux/device.h> | 31 | #include <linux/device.h> |
| 33 | #include <linux/module.h> | 32 | #include <linux/module.h> |
| @@ -54,6 +53,7 @@ | |||
| 54 | #include <asm/system.h> | 53 | #include <asm/system.h> |
| 55 | #include <asm/vpe.h> | 54 | #include <asm/vpe.h> |
| 56 | #include <asm/kspd.h> | 55 | #include <asm/kspd.h> |
| 56 | #include <asm/mips_mt.h> | ||
| 57 | 57 | ||
| 58 | typedef void *vpe_handle; | 58 | typedef void *vpe_handle; |
| 59 | 59 | ||
| @@ -64,6 +64,10 @@ typedef void *vpe_handle; | |||
| 64 | /* If this is set, the section belongs in the init part of the module */ | 64 | /* If this is set, the section belongs in the init part of the module */ |
| 65 | #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) | 65 | #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) |
| 66 | 66 | ||
| 67 | /* | ||
| 68 | * The number of TCs and VPEs physically available on the core | ||
| 69 | */ | ||
| 70 | static int hw_tcs, hw_vpes; | ||
| 67 | static char module_name[] = "vpe"; | 71 | static char module_name[] = "vpe"; |
| 68 | static int major; | 72 | static int major; |
| 69 | static const int minor = 1; /* fixed for now */ | 73 | static const int minor = 1; /* fixed for now */ |
| @@ -126,20 +130,17 @@ struct vpe { | |||
| 126 | 130 | ||
| 127 | /* the list of who wants to know when something major happens */ | 131 | /* the list of who wants to know when something major happens */ |
| 128 | struct list_head notify; | 132 | struct list_head notify; |
| 133 | |||
| 134 | unsigned int ntcs; | ||
| 129 | }; | 135 | }; |
| 130 | 136 | ||
| 131 | struct tc { | 137 | struct tc { |
| 132 | enum tc_state state; | 138 | enum tc_state state; |
| 133 | int index; | 139 | int index; |
| 134 | 140 | ||
| 135 | /* parent VPE */ | 141 | struct vpe *pvpe; /* parent VPE */ |
| 136 | struct vpe *pvpe; | 142 | struct list_head tc; /* The list of TC's with this VPE */ |
| 137 | 143 | struct list_head list; /* The global list of tc's */ | |
| 138 | /* The list of TC's with this VPE */ | ||
| 139 | struct list_head tc; | ||
| 140 | |||
| 141 | /* The global list of tc's */ | ||
| 142 | struct list_head list; | ||
| 143 | }; | 144 | }; |
| 144 | 145 | ||
| 145 | struct { | 146 | struct { |
| @@ -217,18 +218,17 @@ struct vpe *alloc_vpe(int minor) | |||
| 217 | /* allocate a tc. At startup only tc0 is running, all other can be halted. */ | 218 | /* allocate a tc. At startup only tc0 is running, all other can be halted. */ |
| 218 | struct tc *alloc_tc(int index) | 219 | struct tc *alloc_tc(int index) |
| 219 | { | 220 | { |
| 220 | struct tc *t; | 221 | struct tc *tc; |
| 221 | 222 | ||
| 222 | if ((t = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) { | 223 | if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) |
| 223 | return NULL; | 224 | goto out; |
| 224 | } | ||
| 225 | |||
| 226 | INIT_LIST_HEAD(&t->tc); | ||
| 227 | list_add_tail(&t->list, &vpecontrol.tc_list); | ||
| 228 | 225 | ||
| 229 | t->index = index; | 226 | INIT_LIST_HEAD(&tc->tc); |
| 227 | tc->index = index; | ||
| 228 | list_add_tail(&tc->list, &vpecontrol.tc_list); | ||
| 230 | 229 | ||
| 231 | return t; | 230 | out: |
| 231 | return tc; | ||
| 232 | } | 232 | } |
| 233 | 233 | ||
| 234 | /* clean up and free everything */ | 234 | /* clean up and free everything */ |
| @@ -663,66 +663,48 @@ static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, | |||
| 663 | } | 663 | } |
| 664 | #endif | 664 | #endif |
| 665 | 665 | ||
| 666 | static void dump_tc(struct tc *t) | ||
| 667 | { | ||
| 668 | unsigned long val; | ||
| 669 | |||
| 670 | settc(t->index); | ||
| 671 | printk(KERN_DEBUG "VPE loader: TC index %d targtc %ld " | ||
| 672 | "TCStatus 0x%lx halt 0x%lx\n", | ||
| 673 | t->index, read_c0_vpecontrol() & VPECONTROL_TARGTC, | ||
| 674 | read_tc_c0_tcstatus(), read_tc_c0_tchalt()); | ||
| 675 | |||
| 676 | printk(KERN_DEBUG " tcrestart 0x%lx\n", read_tc_c0_tcrestart()); | ||
| 677 | printk(KERN_DEBUG " tcbind 0x%lx\n", read_tc_c0_tcbind()); | ||
| 678 | |||
| 679 | val = read_c0_vpeconf0(); | ||
| 680 | printk(KERN_DEBUG " VPEConf0 0x%lx MVP %ld\n", val, | ||
| 681 | (val & VPECONF0_MVP) >> VPECONF0_MVP_SHIFT); | ||
| 682 | |||
| 683 | printk(KERN_DEBUG " c0 status 0x%lx\n", read_vpe_c0_status()); | ||
| 684 | printk(KERN_DEBUG " c0 cause 0x%lx\n", read_vpe_c0_cause()); | ||
| 685 | |||
| 686 | printk(KERN_DEBUG " c0 badvaddr 0x%lx\n", read_vpe_c0_badvaddr()); | ||
| 687 | printk(KERN_DEBUG " c0 epc 0x%lx\n", read_vpe_c0_epc()); | ||
| 688 | } | ||
| 689 | |||
| 690 | static void dump_tclist(void) | ||
| 691 | { | ||
| 692 | struct tc *t; | ||
| 693 | |||
| 694 | list_for_each_entry(t, &vpecontrol.tc_list, list) { | ||
| 695 | dump_tc(t); | ||
| 696 | } | ||
| 697 | } | ||
| 698 | |||
| 699 | /* We are prepared so configure and start the VPE... */ | 666 | /* We are prepared so configure and start the VPE... */ |
| 700 | static int vpe_run(struct vpe * v) | 667 | static int vpe_run(struct vpe * v) |
| 701 | { | 668 | { |
| 669 | unsigned long flags, val, dmt_flag; | ||
| 702 | struct vpe_notifications *n; | 670 | struct vpe_notifications *n; |
| 703 | unsigned long val, dmt_flag; | 671 | unsigned int vpeflags; |
| 704 | struct tc *t; | 672 | struct tc *t; |
| 705 | 673 | ||
| 706 | /* check we are the Master VPE */ | 674 | /* check we are the Master VPE */ |
| 675 | local_irq_save(flags); | ||
| 707 | val = read_c0_vpeconf0(); | 676 | val = read_c0_vpeconf0(); |
| 708 | if (!(val & VPECONF0_MVP)) { | 677 | if (!(val & VPECONF0_MVP)) { |
| 709 | printk(KERN_WARNING | 678 | printk(KERN_WARNING |
| 710 | "VPE loader: only Master VPE's are allowed to configure MT\n"); | 679 | "VPE loader: only Master VPE's are allowed to configure MT\n"); |
| 680 | local_irq_restore(flags); | ||
| 681 | |||
| 711 | return -1; | 682 | return -1; |
| 712 | } | 683 | } |
| 713 | 684 | ||
| 714 | /* disable MT (using dvpe) */ | 685 | dmt_flag = dmt(); |
| 715 | dvpe(); | 686 | vpeflags = dvpe(); |
| 716 | 687 | ||
| 717 | if (!list_empty(&v->tc)) { | 688 | if (!list_empty(&v->tc)) { |
| 718 | if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { | 689 | if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { |
| 719 | printk(KERN_WARNING "VPE loader: TC %d is already in use.\n", | 690 | evpe(vpeflags); |
| 720 | t->index); | 691 | emt(dmt_flag); |
| 692 | local_irq_restore(flags); | ||
| 693 | |||
| 694 | printk(KERN_WARNING | ||
| 695 | "VPE loader: TC %d is already in use.\n", | ||
| 696 | t->index); | ||
| 721 | return -ENOEXEC; | 697 | return -ENOEXEC; |
| 722 | } | 698 | } |
| 723 | } else { | 699 | } else { |
| 724 | printk(KERN_WARNING "VPE loader: No TC's associated with VPE %d\n", | 700 | evpe(vpeflags); |
| 701 | emt(dmt_flag); | ||
| 702 | local_irq_restore(flags); | ||
| 703 | |||
| 704 | printk(KERN_WARNING | ||
| 705 | "VPE loader: No TC's associated with VPE %d\n", | ||
| 725 | v->minor); | 706 | v->minor); |
| 707 | |||
| 726 | return -ENOEXEC; | 708 | return -ENOEXEC; |
| 727 | } | 709 | } |
| 728 | 710 | ||
| @@ -733,21 +715,20 @@ static int vpe_run(struct vpe * v) | |||
| 733 | 715 | ||
| 734 | /* should check it is halted, and not activated */ | 716 | /* should check it is halted, and not activated */ |
| 735 | if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) { | 717 | if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) { |
| 736 | printk(KERN_WARNING "VPE loader: TC %d is already doing something!\n", | 718 | evpe(vpeflags); |
| 719 | emt(dmt_flag); | ||
| 720 | local_irq_restore(flags); | ||
| 721 | |||
| 722 | printk(KERN_WARNING "VPE loader: TC %d is already active!\n", | ||
| 737 | t->index); | 723 | t->index); |
| 738 | dump_tclist(); | 724 | |
| 739 | return -ENOEXEC; | 725 | return -ENOEXEC; |
| 740 | } | 726 | } |
| 741 | 727 | ||
| 742 | /* | ||
| 743 | * Disable multi-threaded execution whilst we activate, clear the | ||
| 744 | * halt bit and bound the tc to the other VPE... | ||
| 745 | */ | ||
| 746 | dmt_flag = dmt(); | ||
| 747 | |||
| 748 | /* Write the address we want it to start running from in the TCPC register. */ | 728 | /* Write the address we want it to start running from in the TCPC register. */ |
| 749 | write_tc_c0_tcrestart((unsigned long)v->__start); | 729 | write_tc_c0_tcrestart((unsigned long)v->__start); |
| 750 | write_tc_c0_tccontext((unsigned long)0); | 730 | write_tc_c0_tccontext((unsigned long)0); |
| 731 | |||
| 751 | /* | 732 | /* |
| 752 | * Mark the TC as activated, not interrupt exempt and not dynamically | 733 | * Mark the TC as activated, not interrupt exempt and not dynamically |
| 753 | * allocatable | 734 | * allocatable |
| @@ -763,15 +744,15 @@ static int vpe_run(struct vpe * v) | |||
| 763 | * here... Or set $a3 to zero and define DFLT_STACK_SIZE and | 744 | * here... Or set $a3 to zero and define DFLT_STACK_SIZE and |
| 764 | * DFLT_HEAP_SIZE when you compile your program | 745 | * DFLT_HEAP_SIZE when you compile your program |
| 765 | */ | 746 | */ |
| 766 | mttgpr(7, physical_memsize); | 747 | mttgpr(6, v->ntcs); |
| 767 | 748 | mttgpr(7, physical_memsize); | |
| 768 | 749 | ||
| 769 | /* set up VPE1 */ | 750 | /* set up VPE1 */ |
| 770 | /* | 751 | /* |
| 771 | * bind the TC to VPE 1 as late as possible so we only have the final | 752 | * bind the TC to VPE 1 as late as possible so we only have the final |
| 772 | * VPE registers to set up, and so an EJTAG probe can trigger on it | 753 | * VPE registers to set up, and so an EJTAG probe can trigger on it |
| 773 | */ | 754 | */ |
| 774 | write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor); | 755 | write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); |
| 775 | 756 | ||
| 776 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); | 757 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); |
| 777 | 758 | ||
| @@ -793,15 +774,16 @@ static int vpe_run(struct vpe * v) | |||
| 793 | /* take system out of configuration state */ | 774 | /* take system out of configuration state */ |
| 794 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | 775 | clear_c0_mvpcontrol(MVPCONTROL_VPC); |
| 795 | 776 | ||
| 796 | /* now safe to re-enable multi-threading */ | 777 | #ifdef CONFIG_SMP |
| 797 | emt(dmt_flag); | ||
| 798 | |||
| 799 | /* set it running */ | ||
| 800 | evpe(EVPE_ENABLE); | 778 | evpe(EVPE_ENABLE); |
| 779 | #else | ||
| 780 | evpe(vpeflags); | ||
| 781 | #endif | ||
| 782 | emt(dmt_flag); | ||
| 783 | local_irq_restore(flags); | ||
| 801 | 784 | ||
| 802 | list_for_each_entry(n, &v->notify, list) { | 785 | list_for_each_entry(n, &v->notify, list) |
| 803 | n->start(v->minor); | 786 | n->start(minor); |
| 804 | } | ||
| 805 | 787 | ||
| 806 | return 0; | 788 | return 0; |
| 807 | } | 789 | } |
| @@ -1023,23 +1005,15 @@ static int vpe_elfload(struct vpe * v) | |||
| 1023 | return 0; | 1005 | return 0; |
| 1024 | } | 1006 | } |
| 1025 | 1007 | ||
| 1026 | void __used dump_vpe(struct vpe * v) | ||
| 1027 | { | ||
| 1028 | struct tc *t; | ||
| 1029 | |||
| 1030 | settc(v->minor); | ||
| 1031 | |||
| 1032 | printk(KERN_DEBUG "VPEControl 0x%lx\n", read_vpe_c0_vpecontrol()); | ||
| 1033 | printk(KERN_DEBUG "VPEConf0 0x%lx\n", read_vpe_c0_vpeconf0()); | ||
| 1034 | |||
| 1035 | list_for_each_entry(t, &vpecontrol.tc_list, list) | ||
| 1036 | dump_tc(t); | ||
| 1037 | } | ||
| 1038 | |||
| 1039 | static void cleanup_tc(struct tc *tc) | 1008 | static void cleanup_tc(struct tc *tc) |
| 1040 | { | 1009 | { |
| 1010 | unsigned long flags; | ||
| 1011 | unsigned int mtflags, vpflags; | ||
| 1041 | int tmp; | 1012 | int tmp; |
| 1042 | 1013 | ||
| 1014 | local_irq_save(flags); | ||
| 1015 | mtflags = dmt(); | ||
| 1016 | vpflags = dvpe(); | ||
| 1043 | /* Put MVPE's into 'configuration state' */ | 1017 | /* Put MVPE's into 'configuration state' */ |
| 1044 | set_c0_mvpcontrol(MVPCONTROL_VPC); | 1018 | set_c0_mvpcontrol(MVPCONTROL_VPC); |
| 1045 | 1019 | ||
| @@ -1054,9 +1028,12 @@ static void cleanup_tc(struct tc *tc) | |||
| 1054 | write_tc_c0_tchalt(TCHALT_H); | 1028 | write_tc_c0_tchalt(TCHALT_H); |
| 1055 | 1029 | ||
| 1056 | /* bind it to anything other than VPE1 */ | 1030 | /* bind it to anything other than VPE1 */ |
| 1057 | write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE | 1031 | // write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE |
| 1058 | 1032 | ||
| 1059 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | 1033 | clear_c0_mvpcontrol(MVPCONTROL_VPC); |
| 1034 | evpe(vpflags); | ||
| 1035 | emt(mtflags); | ||
| 1036 | local_irq_restore(flags); | ||
| 1060 | } | 1037 | } |
| 1061 | 1038 | ||
| 1062 | static int getcwd(char *buff, int size) | 1039 | static int getcwd(char *buff, int size) |
| @@ -1077,36 +1054,32 @@ static int getcwd(char *buff, int size) | |||
| 1077 | /* checks VPE is unused and gets ready to load program */ | 1054 | /* checks VPE is unused and gets ready to load program */ |
| 1078 | static int vpe_open(struct inode *inode, struct file *filp) | 1055 | static int vpe_open(struct inode *inode, struct file *filp) |
| 1079 | { | 1056 | { |
| 1080 | int minor, ret; | ||
| 1081 | enum vpe_state state; | 1057 | enum vpe_state state; |
| 1082 | struct vpe *v; | ||
| 1083 | struct vpe_notifications *not; | 1058 | struct vpe_notifications *not; |
| 1059 | struct vpe *v; | ||
| 1060 | int ret; | ||
| 1084 | 1061 | ||
| 1085 | /* assume only 1 device at the mo. */ | 1062 | if (minor != iminor(inode)) { |
| 1086 | if ((minor = iminor(inode)) != 1) { | 1063 | /* assume only 1 device at the moment. */ |
| 1087 | printk(KERN_WARNING "VPE loader: only vpe1 is supported\n"); | 1064 | printk(KERN_WARNING "VPE loader: only vpe1 is supported\n"); |
| 1088 | return -ENODEV; | 1065 | return -ENODEV; |
| 1089 | } | 1066 | } |
| 1090 | 1067 | ||
| 1091 | if ((v = get_vpe(minor)) == NULL) { | 1068 | if ((v = get_vpe(tclimit)) == NULL) { |
| 1092 | printk(KERN_WARNING "VPE loader: unable to get vpe\n"); | 1069 | printk(KERN_WARNING "VPE loader: unable to get vpe\n"); |
| 1093 | return -ENODEV; | 1070 | return -ENODEV; |
| 1094 | } | 1071 | } |
| 1095 | 1072 | ||
| 1096 | state = xchg(&v->state, VPE_STATE_INUSE); | 1073 | state = xchg(&v->state, VPE_STATE_INUSE); |
| 1097 | if (state != VPE_STATE_UNUSED) { | 1074 | if (state != VPE_STATE_UNUSED) { |
| 1098 | dvpe(); | ||
| 1099 | |||
| 1100 | printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n"); | 1075 | printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n"); |
| 1101 | 1076 | ||
| 1102 | dump_tc(get_tc(minor)); | ||
| 1103 | |||
| 1104 | list_for_each_entry(not, &v->notify, list) { | 1077 | list_for_each_entry(not, &v->notify, list) { |
| 1105 | not->stop(minor); | 1078 | not->stop(tclimit); |
| 1106 | } | 1079 | } |
| 1107 | 1080 | ||
| 1108 | release_progmem(v->load_addr); | 1081 | release_progmem(v->load_addr); |
| 1109 | cleanup_tc(get_tc(minor)); | 1082 | cleanup_tc(get_tc(tclimit)); |
| 1110 | } | 1083 | } |
| 1111 | 1084 | ||
| 1112 | /* this of-course trashes what was there before... */ | 1085 | /* this of-course trashes what was there before... */ |
| @@ -1133,26 +1106,25 @@ static int vpe_open(struct inode *inode, struct file *filp) | |||
| 1133 | 1106 | ||
| 1134 | v->shared_ptr = NULL; | 1107 | v->shared_ptr = NULL; |
| 1135 | v->__start = 0; | 1108 | v->__start = 0; |
| 1109 | |||
| 1136 | return 0; | 1110 | return 0; |
| 1137 | } | 1111 | } |
| 1138 | 1112 | ||
| 1139 | static int vpe_release(struct inode *inode, struct file *filp) | 1113 | static int vpe_release(struct inode *inode, struct file *filp) |
| 1140 | { | 1114 | { |
| 1141 | int minor, ret = 0; | ||
| 1142 | struct vpe *v; | 1115 | struct vpe *v; |
| 1143 | Elf_Ehdr *hdr; | 1116 | Elf_Ehdr *hdr; |
| 1117 | int ret = 0; | ||
| 1144 | 1118 | ||
| 1145 | minor = iminor(inode); | 1119 | v = get_vpe(tclimit); |
| 1146 | if ((v = get_vpe(minor)) == NULL) | 1120 | if (v == NULL) |
| 1147 | return -ENODEV; | 1121 | return -ENODEV; |
| 1148 | 1122 | ||
| 1149 | // simple case of fire and forget, so tell the VPE to run... | ||
| 1150 | |||
| 1151 | hdr = (Elf_Ehdr *) v->pbuffer; | 1123 | hdr = (Elf_Ehdr *) v->pbuffer; |
| 1152 | if (memcmp(hdr->e_ident, ELFMAG, 4) == 0) { | 1124 | if (memcmp(hdr->e_ident, ELFMAG, 4) == 0) { |
| 1153 | if (vpe_elfload(v) >= 0) | 1125 | if (vpe_elfload(v) >= 0) { |
| 1154 | vpe_run(v); | 1126 | vpe_run(v); |
| 1155 | else { | 1127 | } else { |
| 1156 | printk(KERN_WARNING "VPE loader: ELF load failed.\n"); | 1128 | printk(KERN_WARNING "VPE loader: ELF load failed.\n"); |
| 1157 | ret = -ENOEXEC; | 1129 | ret = -ENOEXEC; |
| 1158 | } | 1130 | } |
| @@ -1179,12 +1151,14 @@ static int vpe_release(struct inode *inode, struct file *filp) | |||
| 1179 | static ssize_t vpe_write(struct file *file, const char __user * buffer, | 1151 | static ssize_t vpe_write(struct file *file, const char __user * buffer, |
| 1180 | size_t count, loff_t * ppos) | 1152 | size_t count, loff_t * ppos) |
| 1181 | { | 1153 | { |
| 1182 | int minor; | ||
| 1183 | size_t ret = count; | 1154 | size_t ret = count; |
| 1184 | struct vpe *v; | 1155 | struct vpe *v; |
| 1185 | 1156 | ||
| 1186 | minor = iminor(file->f_path.dentry->d_inode); | 1157 | if (iminor(file->f_path.dentry->d_inode) != minor) |
| 1187 | if ((v = get_vpe(minor)) == NULL) | 1158 | return -ENODEV; |
| 1159 | |||
| 1160 | v = get_vpe(tclimit); | ||
| 1161 | if (v == NULL) | ||
| 1188 | return -ENODEV; | 1162 | return -ENODEV; |
| 1189 | 1163 | ||
| 1190 | if (v->pbuffer == NULL) { | 1164 | if (v->pbuffer == NULL) { |
| @@ -1366,62 +1340,173 @@ static void kspd_sp_exit( int sp_id) | |||
| 1366 | } | 1340 | } |
| 1367 | #endif | 1341 | #endif |
| 1368 | 1342 | ||
| 1369 | static struct device *vpe_dev; | 1343 | static ssize_t store_kill(struct class_device *dev, const char *buf, size_t len) |
| 1344 | { | ||
| 1345 | struct vpe *vpe = get_vpe(tclimit); | ||
| 1346 | struct vpe_notifications *not; | ||
| 1347 | |||
| 1348 | list_for_each_entry(not, &vpe->notify, list) { | ||
| 1349 | not->stop(tclimit); | ||
| 1350 | } | ||
| 1351 | |||
| 1352 | release_progmem(vpe->load_addr); | ||
| 1353 | cleanup_tc(get_tc(tclimit)); | ||
| 1354 | vpe_stop(vpe); | ||
| 1355 | vpe_free(vpe); | ||
| 1356 | |||
| 1357 | return len; | ||
| 1358 | } | ||
| 1359 | |||
| 1360 | static ssize_t show_ntcs(struct class_device *cd, char *buf) | ||
| 1361 | { | ||
| 1362 | struct vpe *vpe = get_vpe(tclimit); | ||
| 1363 | |||
| 1364 | return sprintf(buf, "%d\n", vpe->ntcs); | ||
| 1365 | } | ||
| 1366 | |||
| 1367 | static ssize_t store_ntcs(struct class_device *dev, const char *buf, size_t len) | ||
| 1368 | { | ||
| 1369 | struct vpe *vpe = get_vpe(tclimit); | ||
| 1370 | unsigned long new; | ||
| 1371 | char *endp; | ||
| 1372 | |||
| 1373 | new = simple_strtoul(buf, &endp, 0); | ||
| 1374 | if (endp == buf) | ||
| 1375 | goto out_einval; | ||
| 1376 | |||
| 1377 | if (new == 0 || new > (hw_tcs - tclimit)) | ||
| 1378 | goto out_einval; | ||
| 1379 | |||
| 1380 | vpe->ntcs = new; | ||
| 1381 | |||
| 1382 | return len; | ||
| 1383 | |||
| 1384 | out_einval: | ||
| 1385 | return -EINVAL;; | ||
| 1386 | } | ||
| 1387 | |||
| 1388 | static struct class_device_attribute vpe_class_attributes[] = { | ||
| 1389 | __ATTR(kill, S_IWUSR, NULL, store_kill), | ||
| 1390 | __ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs), | ||
| 1391 | {} | ||
| 1392 | }; | ||
| 1393 | |||
| 1394 | static void vpe_class_device_release(struct class_device *cd) | ||
| 1395 | { | ||
| 1396 | kfree(cd); | ||
| 1397 | } | ||
| 1398 | |||
| 1399 | struct class vpe_class = { | ||
| 1400 | .name = "vpe", | ||
| 1401 | .owner = THIS_MODULE, | ||
| 1402 | .release = vpe_class_device_release, | ||
| 1403 | .class_dev_attrs = vpe_class_attributes, | ||
| 1404 | }; | ||
| 1405 | |||
| 1406 | struct class_device vpe_device; | ||
| 1370 | 1407 | ||
| 1371 | static int __init vpe_module_init(void) | 1408 | static int __init vpe_module_init(void) |
| 1372 | { | 1409 | { |
| 1410 | unsigned int mtflags, vpflags; | ||
| 1411 | unsigned long flags, val; | ||
| 1373 | struct vpe *v = NULL; | 1412 | struct vpe *v = NULL; |
| 1374 | struct device *dev; | ||
| 1375 | struct tc *t; | 1413 | struct tc *t; |
| 1376 | unsigned long val; | 1414 | int tc, err; |
| 1377 | int i, err; | ||
| 1378 | 1415 | ||
| 1379 | if (!cpu_has_mipsmt) { | 1416 | if (!cpu_has_mipsmt) { |
| 1380 | printk("VPE loader: not a MIPS MT capable processor\n"); | 1417 | printk("VPE loader: not a MIPS MT capable processor\n"); |
| 1381 | return -ENODEV; | 1418 | return -ENODEV; |
| 1382 | } | 1419 | } |
| 1383 | 1420 | ||
| 1421 | if (vpelimit == 0) { | ||
| 1422 | printk(KERN_WARNING "No VPEs reserved for AP/SP, not " | ||
| 1423 | "initializing VPE loader.\nPass maxvpes=<n> argument as " | ||
| 1424 | "kernel argument\n"); | ||
| 1425 | |||
| 1426 | return -ENODEV; | ||
| 1427 | } | ||
| 1428 | |||
| 1429 | if (tclimit == 0) { | ||
| 1430 | printk(KERN_WARNING "No TCs reserved for AP/SP, not " | ||
| 1431 | "initializing VPE loader.\nPass maxtcs=<n> argument as " | ||
| 1432 | "kernel argument\n"); | ||
| 1433 | |||
| 1434 | return -ENODEV; | ||
| 1435 | } | ||
| 1436 | |||
| 1384 | major = register_chrdev(0, module_name, &vpe_fops); | 1437 | major = register_chrdev(0, module_name, &vpe_fops); |
| 1385 | if (major < 0) { | 1438 | if (major < 0) { |
| 1386 | printk("VPE loader: unable to register character device\n"); | 1439 | printk("VPE loader: unable to register character device\n"); |
| 1387 | return major; | 1440 | return major; |
| 1388 | } | 1441 | } |
| 1389 | 1442 | ||
| 1390 | dev = device_create(mt_class, NULL, MKDEV(major, minor), | 1443 | err = class_register(&vpe_class); |
| 1391 | "tc%d", minor); | 1444 | if (err) { |
| 1392 | if (IS_ERR(dev)) { | 1445 | printk(KERN_ERR "vpe_class registration failed\n"); |
| 1393 | err = PTR_ERR(dev); | ||
| 1394 | goto out_chrdev; | 1446 | goto out_chrdev; |
| 1395 | } | 1447 | } |
| 1396 | vpe_dev = dev; | ||
| 1397 | 1448 | ||
| 1398 | dmt(); | 1449 | class_device_initialize(&vpe_device); |
| 1399 | dvpe(); | 1450 | vpe_device.class = &vpe_class, |
| 1451 | vpe_device.parent = NULL, | ||
| 1452 | strlcpy(vpe_device.class_id, "vpe1", BUS_ID_SIZE); | ||
| 1453 | vpe_device.devt = MKDEV(major, minor); | ||
| 1454 | err = class_device_add(&vpe_device); | ||
| 1455 | if (err) { | ||
| 1456 | printk(KERN_ERR "Adding vpe_device failed\n"); | ||
| 1457 | goto out_class; | ||
| 1458 | } | ||
| 1459 | |||
| 1460 | local_irq_save(flags); | ||
| 1461 | mtflags = dmt(); | ||
| 1462 | vpflags = dvpe(); | ||
| 1400 | 1463 | ||
| 1401 | /* Put MVPE's into 'configuration state' */ | 1464 | /* Put MVPE's into 'configuration state' */ |
| 1402 | set_c0_mvpcontrol(MVPCONTROL_VPC); | 1465 | set_c0_mvpcontrol(MVPCONTROL_VPC); |
| 1403 | 1466 | ||
| 1404 | /* dump_mtregs(); */ | 1467 | /* dump_mtregs(); */ |
| 1405 | 1468 | ||
| 1406 | |||
| 1407 | val = read_c0_mvpconf0(); | 1469 | val = read_c0_mvpconf0(); |
| 1408 | for (i = 0; i < ((val & MVPCONF0_PTC) + 1); i++) { | 1470 | hw_tcs = (val & MVPCONF0_PTC) + 1; |
| 1409 | t = alloc_tc(i); | 1471 | hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; |
| 1472 | |||
| 1473 | for (tc = tclimit; tc < hw_tcs; tc++) { | ||
| 1474 | /* | ||
| 1475 | * Must re-enable multithreading temporarily or in case we | ||
| 1476 | * reschedule send IPIs or similar we might hang. | ||
| 1477 | */ | ||
| 1478 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | ||
| 1479 | evpe(vpflags); | ||
| 1480 | emt(mtflags); | ||
| 1481 | local_irq_restore(flags); | ||
| 1482 | t = alloc_tc(tc); | ||
| 1483 | if (!t) { | ||
| 1484 | err = -ENOMEM; | ||
| 1485 | goto out; | ||
| 1486 | } | ||
| 1487 | |||
| 1488 | local_irq_save(flags); | ||
| 1489 | mtflags = dmt(); | ||
| 1490 | vpflags = dvpe(); | ||
| 1491 | set_c0_mvpcontrol(MVPCONTROL_VPC); | ||
| 1410 | 1492 | ||
| 1411 | /* VPE's */ | 1493 | /* VPE's */ |
| 1412 | if (i < ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1) { | 1494 | if (tc < hw_tcs) { |
| 1413 | settc(i); | 1495 | settc(tc); |
| 1414 | 1496 | ||
| 1415 | if ((v = alloc_vpe(i)) == NULL) { | 1497 | if ((v = alloc_vpe(tc)) == NULL) { |
| 1416 | printk(KERN_WARNING "VPE: unable to allocate VPE\n"); | 1498 | printk(KERN_WARNING "VPE: unable to allocate VPE\n"); |
| 1417 | return -ENODEV; | 1499 | |
| 1500 | goto out_reenable; | ||
| 1418 | } | 1501 | } |
| 1419 | 1502 | ||
| 1503 | v->ntcs = hw_tcs - tclimit; | ||
| 1504 | |||
| 1420 | /* add the tc to the list of this vpe's tc's. */ | 1505 | /* add the tc to the list of this vpe's tc's. */ |
| 1421 | list_add(&t->tc, &v->tc); | 1506 | list_add(&t->tc, &v->tc); |
| 1422 | 1507 | ||
| 1423 | /* deactivate all but vpe0 */ | 1508 | /* deactivate all but vpe0 */ |
| 1424 | if (i != 0) { | 1509 | if (tc >= tclimit) { |
| 1425 | unsigned long tmp = read_vpe_c0_vpeconf0(); | 1510 | unsigned long tmp = read_vpe_c0_vpeconf0(); |
| 1426 | 1511 | ||
| 1427 | tmp &= ~VPECONF0_VPA; | 1512 | tmp &= ~VPECONF0_VPA; |
| @@ -1434,7 +1519,7 @@ static int __init vpe_module_init(void) | |||
| 1434 | /* disable multi-threading with TC's */ | 1519 | /* disable multi-threading with TC's */ |
| 1435 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); | 1520 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); |
| 1436 | 1521 | ||
| 1437 | if (i != 0) { | 1522 | if (tc >= vpelimit) { |
| 1438 | /* | 1523 | /* |
| 1439 | * Set config to be the same as vpe0, | 1524 | * Set config to be the same as vpe0, |
| 1440 | * particularly kseg0 coherency alg | 1525 | * particularly kseg0 coherency alg |
| @@ -1446,10 +1531,10 @@ static int __init vpe_module_init(void) | |||
| 1446 | /* TC's */ | 1531 | /* TC's */ |
| 1447 | t->pvpe = v; /* set the parent vpe */ | 1532 | t->pvpe = v; /* set the parent vpe */ |
| 1448 | 1533 | ||
| 1449 | if (i != 0) { | 1534 | if (tc >= tclimit) { |
| 1450 | unsigned long tmp; | 1535 | unsigned long tmp; |
| 1451 | 1536 | ||
| 1452 | settc(i); | 1537 | settc(tc); |
| 1453 | 1538 | ||
| 1454 | /* Any TC that is bound to VPE0 gets left as is - in case | 1539 | /* Any TC that is bound to VPE0 gets left as is - in case |
| 1455 | we are running SMTC on VPE0. A TC that is bound to any | 1540 | we are running SMTC on VPE0. A TC that is bound to any |
| @@ -1479,17 +1564,25 @@ static int __init vpe_module_init(void) | |||
| 1479 | } | 1564 | } |
| 1480 | } | 1565 | } |
| 1481 | 1566 | ||
| 1567 | out_reenable: | ||
| 1482 | /* release config state */ | 1568 | /* release config state */ |
| 1483 | clear_c0_mvpcontrol(MVPCONTROL_VPC); | 1569 | clear_c0_mvpcontrol(MVPCONTROL_VPC); |
| 1484 | 1570 | ||
| 1571 | evpe(vpflags); | ||
| 1572 | emt(mtflags); | ||
| 1573 | local_irq_restore(flags); | ||
| 1574 | |||
| 1485 | #ifdef CONFIG_MIPS_APSP_KSPD | 1575 | #ifdef CONFIG_MIPS_APSP_KSPD |
| 1486 | kspd_events.kspd_sp_exit = kspd_sp_exit; | 1576 | kspd_events.kspd_sp_exit = kspd_sp_exit; |
| 1487 | #endif | 1577 | #endif |
| 1488 | return 0; | 1578 | return 0; |
| 1489 | 1579 | ||
| 1580 | out_class: | ||
| 1581 | class_unregister(&vpe_class); | ||
| 1490 | out_chrdev: | 1582 | out_chrdev: |
| 1491 | unregister_chrdev(major, module_name); | 1583 | unregister_chrdev(major, module_name); |
| 1492 | 1584 | ||
| 1585 | out: | ||
| 1493 | return err; | 1586 | return err; |
| 1494 | } | 1587 | } |
| 1495 | 1588 | ||
| @@ -1503,7 +1596,7 @@ static void __exit vpe_module_exit(void) | |||
| 1503 | } | 1596 | } |
| 1504 | } | 1597 | } |
| 1505 | 1598 | ||
| 1506 | device_destroy(mt_class, MKDEV(major, minor)); | 1599 | class_device_del(&vpe_device); |
| 1507 | unregister_chrdev(major, module_name); | 1600 | unregister_chrdev(major, module_name); |
| 1508 | } | 1601 | } |
| 1509 | 1602 | ||
diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile index fb1b48c48cb3..dcaf6f4c3a37 100644 --- a/arch/mips/lemote/lm2e/Makefile +++ b/arch/mips/lemote/lm2e/Makefile | |||
| @@ -3,5 +3,6 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o | 5 | obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o |
| 6 | EXTRA_AFLAGS := $(CFLAGS) | ||
| 7 | 6 | ||
| 7 | EXTRA_AFLAGS := $(CFLAGS) | ||
| 8 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c index 05693bceaeaf..3e0b7beb1009 100644 --- a/arch/mips/lemote/lm2e/irq.c +++ b/arch/mips/lemote/lm2e/irq.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | */ | 25 | */ |
| 26 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
| 27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 28 | #include <linux/irq.h> | ||
| 29 | #include <linux/init.h> | 28 | #include <linux/init.h> |
| 30 | #include <linux/interrupt.h> | 29 | #include <linux/interrupt.h> |
| 31 | #include <linux/irq.h> | 30 | #include <linux/irq.h> |
diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c index 67312d7acf2a..3efb1cf111f2 100644 --- a/arch/mips/lemote/lm2e/prom.c +++ b/arch/mips/lemote/lm2e/prom.c | |||
| @@ -15,15 +15,11 @@ | |||
| 15 | * option) any later version. | 15 | * option) any later version. |
| 16 | */ | 16 | */ |
| 17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
| 18 | #include <linux/mm.h> | ||
| 19 | #include <linux/sched.h> | ||
| 20 | #include <linux/bootmem.h> | 18 | #include <linux/bootmem.h> |
| 21 | |||
| 22 | #include <asm/addrspace.h> | ||
| 23 | #include <asm/bootinfo.h> | 19 | #include <asm/bootinfo.h> |
| 24 | 20 | ||
| 25 | extern unsigned long bus_clock; | 21 | extern unsigned long bus_clock; |
| 26 | extern unsigned long cpu_clock; | 22 | extern unsigned long cpu_clock_freq; |
| 27 | extern unsigned int memsize, highmemsize; | 23 | extern unsigned int memsize, highmemsize; |
| 28 | extern int putDebugChar(unsigned char byte); | 24 | extern int putDebugChar(unsigned char byte); |
| 29 | 25 | ||
| @@ -81,7 +77,7 @@ do { \ | |||
| 81 | l = (long)*env; | 77 | l = (long)*env; |
| 82 | while (l != 0) { | 78 | while (l != 0) { |
| 83 | parse_even_earlier(bus_clock, "busclock", l); | 79 | parse_even_earlier(bus_clock, "busclock", l); |
| 84 | parse_even_earlier(cpu_clock, "cpuclock", l); | 80 | parse_even_earlier(cpu_clock_freq, "cpuclock", l); |
| 85 | parse_even_earlier(memsize, "memsize", l); | 81 | parse_even_earlier(memsize, "memsize", l); |
| 86 | parse_even_earlier(highmemsize, "highmemsize", l); | 82 | parse_even_earlier(highmemsize, "highmemsize", l); |
| 87 | env++; | 83 | env++; |
| @@ -91,7 +87,7 @@ do { \ | |||
| 91 | memsize = 256; | 87 | memsize = 256; |
| 92 | 88 | ||
| 93 | pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", | 89 | pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", |
| 94 | bus_clock, cpu_clock, memsize, highmemsize); | 90 | bus_clock, cpu_clock_freq, memsize, highmemsize); |
| 95 | } | 91 | } |
| 96 | 92 | ||
| 97 | void __init prom_free_prom_memory(void) | 93 | void __init prom_free_prom_memory(void) |
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c index 0e4d1fa572b5..f34350a4f271 100644 --- a/arch/mips/lemote/lm2e/setup.c +++ b/arch/mips/lemote/lm2e/setup.c | |||
| @@ -28,17 +28,7 @@ | |||
| 28 | */ | 28 | */ |
| 29 | #include <linux/bootmem.h> | 29 | #include <linux/bootmem.h> |
| 30 | #include <linux/init.h> | 30 | #include <linux/init.h> |
| 31 | #include <linux/io.h> | ||
| 32 | #include <linux/ioport.h> | ||
| 33 | #include <linux/interrupt.h> | ||
| 34 | #include <linux/irq.h> | 31 | #include <linux/irq.h> |
| 35 | #include <linux/kernel.h> | ||
| 36 | #include <linux/mc146818rtc.h> | ||
| 37 | #include <linux/mm.h> | ||
| 38 | #include <linux/module.h> | ||
| 39 | #include <linux/pci.h> | ||
| 40 | #include <linux/tty.h> | ||
| 41 | #include <linux/types.h> | ||
| 42 | 32 | ||
| 43 | #include <asm/bootinfo.h> | 33 | #include <asm/bootinfo.h> |
| 44 | #include <asm/mc146818-time.h> | 34 | #include <asm/mc146818-time.h> |
| @@ -58,7 +48,7 @@ extern void mips_reboot_setup(void); | |||
| 58 | #define PTR_PAD(p) (p) | 48 | #define PTR_PAD(p) (p) |
| 59 | #endif | 49 | #endif |
| 60 | 50 | ||
| 61 | unsigned long cpu_clock; | 51 | unsigned long cpu_clock_freq; |
| 62 | unsigned long bus_clock; | 52 | unsigned long bus_clock; |
| 63 | unsigned int memsize; | 53 | unsigned int memsize; |
| 64 | unsigned int highmemsize = 0; | 54 | unsigned int highmemsize = 0; |
| @@ -71,7 +61,7 @@ void __init plat_timer_setup(struct irqaction *irq) | |||
| 71 | static void __init loongson2e_time_init(void) | 61 | static void __init loongson2e_time_init(void) |
| 72 | { | 62 | { |
| 73 | /* setup mips r4k timer */ | 63 | /* setup mips r4k timer */ |
| 74 | mips_hpt_frequency = cpu_clock / 2; | 64 | mips_hpt_frequency = cpu_clock_freq / 2; |
| 75 | } | 65 | } |
| 76 | 66 | ||
| 77 | static unsigned long __init mips_rtc_get_time(void) | 67 | static unsigned long __init mips_rtc_get_time(void) |
diff --git a/arch/mips/math-emu/Makefile b/arch/mips/math-emu/Makefile index 121a848a3594..d547efdeedc2 100644 --- a/arch/mips/math-emu/Makefile +++ b/arch/mips/math-emu/Makefile | |||
| @@ -9,3 +9,5 @@ obj-y := cp1emu.o ieee754m.o ieee754d.o ieee754dp.o ieee754sp.o ieee754.o \ | |||
| 9 | sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_logb.o \ | 9 | sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_logb.o \ |
| 10 | sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \ | 10 | sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \ |
| 11 | dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o | 11 | dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o |
| 12 | |||
| 13 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/mips-boards/atlas/Makefile b/arch/mips/mips-boards/atlas/Makefile index d8dab75906bf..f71c2dd1041a 100644 --- a/arch/mips/mips-boards/atlas/Makefile +++ b/arch/mips/mips-boards/atlas/Makefile | |||
| @@ -18,3 +18,5 @@ | |||
| 18 | 18 | ||
| 19 | obj-y := atlas_int.o atlas_setup.o | 19 | obj-y := atlas_int.o atlas_setup.o |
| 20 | obj-$(CONFIG_KGDB) += atlas_gdb.o | 20 | obj-$(CONFIG_KGDB) += atlas_gdb.o |
| 21 | |||
| 22 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 6c8f0255e85d..3c692abc2553 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c | |||
| @@ -245,6 +245,7 @@ void __init arch_init_irq(void) | |||
| 245 | case MIPS_REVISION_CORID_CORE_MSC: | 245 | case MIPS_REVISION_CORID_CORE_MSC: |
| 246 | case MIPS_REVISION_CORID_CORE_FPGA2: | 246 | case MIPS_REVISION_CORID_CORE_FPGA2: |
| 247 | case MIPS_REVISION_CORID_CORE_FPGA3: | 247 | case MIPS_REVISION_CORID_CORE_FPGA3: |
| 248 | case MIPS_REVISION_CORID_CORE_FPGA4: | ||
| 248 | case MIPS_REVISION_CORID_CORE_24K: | 249 | case MIPS_REVISION_CORID_CORE_24K: |
| 249 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 250 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 250 | if (cpu_has_veic) | 251 | if (cpu_has_veic) |
diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile index aade36d78787..b31d8dfed1be 100644 --- a/arch/mips/mips-boards/generic/Makefile +++ b/arch/mips/mips-boards/generic/Makefile | |||
| @@ -24,3 +24,5 @@ obj-y := reset.o display.o init.o memory.o \ | |||
| 24 | obj-$(CONFIG_EARLY_PRINTK) += console.o | 24 | obj-$(CONFIG_EARLY_PRINTK) += console.o |
| 25 | obj-$(CONFIG_PCI) += pci.o | 25 | obj-$(CONFIG_PCI) += pci.o |
| 26 | obj-$(CONFIG_KGDB) += gdb_hook.o | 26 | obj-$(CONFIG_KGDB) += gdb_hook.o |
| 27 | |||
| 28 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 4eabc1eadd23..e2c7147fedf7 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c | |||
| @@ -294,6 +294,7 @@ void __init prom_init(void) | |||
| 294 | case MIPS_REVISION_CORID_CORE_MSC: | 294 | case MIPS_REVISION_CORID_CORE_MSC: |
| 295 | case MIPS_REVISION_CORID_CORE_FPGA2: | 295 | case MIPS_REVISION_CORID_CORE_FPGA2: |
| 296 | case MIPS_REVISION_CORID_CORE_FPGA3: | 296 | case MIPS_REVISION_CORID_CORE_FPGA3: |
| 297 | case MIPS_REVISION_CORID_CORE_FPGA4: | ||
| 297 | case MIPS_REVISION_CORID_CORE_24K: | 298 | case MIPS_REVISION_CORID_CORE_24K: |
| 298 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 299 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 299 | mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; | 300 | mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; |
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index c45d556aa96b..d7bff9ca5356 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c | |||
| @@ -55,7 +55,7 @@ unsigned long cpu_khz; | |||
| 55 | 55 | ||
| 56 | static int mips_cpu_timer_irq; | 56 | static int mips_cpu_timer_irq; |
| 57 | extern int cp0_perfcount_irq; | 57 | extern int cp0_perfcount_irq; |
| 58 | extern void smtc_timer_broadcast(int); | 58 | extern void smtc_timer_broadcast(void); |
| 59 | 59 | ||
| 60 | static void mips_timer_dispatch(void) | 60 | static void mips_timer_dispatch(void) |
| 61 | { | 61 | { |
| @@ -131,7 +131,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id) | |||
| 131 | (mips_hpt_frequency/HZ)); | 131 | (mips_hpt_frequency/HZ)); |
| 132 | local_timer_interrupt(irq, dev_id); | 132 | local_timer_interrupt(irq, dev_id); |
| 133 | } | 133 | } |
| 134 | smtc_timer_broadcast(cpu_data[cpu].vpe_id); | 134 | smtc_timer_broadcast(); |
| 135 | } | 135 | } |
| 136 | #else /* CONFIG_MIPS_MT_SMTC */ | 136 | #else /* CONFIG_MIPS_MT_SMTC */ |
| 137 | int r2 = cpu_has_mips_r2; | 137 | int r2 = cpu_has_mips_r2; |
diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile index a242b0fc377d..931ca4600a63 100644 --- a/arch/mips/mips-boards/malta/Makefile +++ b/arch/mips/mips-boards/malta/Makefile | |||
| @@ -23,3 +23,5 @@ obj-y := malta_int.o malta_platform.o malta_setup.o | |||
| 23 | 23 | ||
| 24 | obj-$(CONFIG_MTD) += malta_mtd.o | 24 | obj-$(CONFIG_MTD) += malta_mtd.o |
| 25 | obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o | 25 | obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o |
| 26 | |||
| 27 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index c78d48349600..97aeb8c4e601 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c | |||
| @@ -330,6 +330,18 @@ void __init arch_init_irq(void) | |||
| 330 | (0x100 << MIPSCPU_INT_I8259A)); | 330 | (0x100 << MIPSCPU_INT_I8259A)); |
| 331 | setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, | 331 | setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, |
| 332 | &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); | 332 | &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); |
| 333 | /* | ||
| 334 | * Temporary hack to ensure that the subsidiary device | ||
| 335 | * interrupts coing in via the i8259A, but associated | ||
| 336 | * with low IRQ numbers, will restore the Status.IM | ||
| 337 | * value associated with the i8259A. | ||
| 338 | */ | ||
| 339 | { | ||
| 340 | int i; | ||
| 341 | |||
| 342 | for (i = 0; i < 16; i++) | ||
| 343 | irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); | ||
| 344 | } | ||
| 333 | #else /* Not SMTC */ | 345 | #else /* Not SMTC */ |
| 334 | setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); | 346 | setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); |
| 335 | setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); | 347 | setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); |
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c index d1c80f631100..0fb4c269901c 100644 --- a/arch/mips/mips-boards/malta/malta_smtc.c +++ b/arch/mips/mips-boards/malta/malta_smtc.c | |||
| @@ -58,7 +58,7 @@ void prom_init_secondary(void) | |||
| 58 | * but it may be multithreaded. | 58 | * but it may be multithreaded. |
| 59 | */ | 59 | */ |
| 60 | 60 | ||
| 61 | void plat_smp_setup(void) | 61 | void __cpuinit plat_smp_setup(void) |
| 62 | { | 62 | { |
| 63 | if (read_c0_config3() & (1<<2)) | 63 | if (read_c0_config3() & (1<<2)) |
| 64 | mipsmt_build_cpu_map(0); | 64 | mipsmt_build_cpu_map(0); |
diff --git a/arch/mips/mips-boards/sead/Makefile b/arch/mips/mips-boards/sead/Makefile index 224bb848f16b..3682fe217bd5 100644 --- a/arch/mips/mips-boards/sead/Makefile +++ b/arch/mips/mips-boards/sead/Makefile | |||
| @@ -24,3 +24,5 @@ | |||
| 24 | # | 24 | # |
| 25 | 25 | ||
| 26 | obj-y := sead_int.o sead_setup.o | 26 | obj-y := sead_int.o sead_setup.o |
| 27 | |||
| 28 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile index dc0bfda11427..75568b584df4 100644 --- a/arch/mips/mipssim/Makefile +++ b/arch/mips/mipssim/Makefile | |||
| @@ -22,3 +22,5 @@ obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \ | |||
| 22 | 22 | ||
| 23 | obj-$(CONFIG_EARLY_PRINTK) += sim_console.o | 23 | obj-$(CONFIG_EARLY_PRINTK) += sim_console.o |
| 24 | obj-$(CONFIG_SMP) += sim_smp.o | 24 | obj-$(CONFIG_SMP) += sim_smp.o |
| 25 | |||
| 26 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c index 17819b594105..d012719c4d24 100644 --- a/arch/mips/mipssim/sim_setup.c +++ b/arch/mips/mipssim/sim_setup.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
| 24 | #include <linux/ioport.h> | 24 | #include <linux/ioport.h> |
| 25 | #include <linux/serial.h> | ||
| 26 | #include <linux/tty.h> | 25 | #include <linux/tty.h> |
| 27 | #include <linux/serial.h> | 26 | #include <linux/serial.h> |
| 28 | #include <linux/serial_core.h> | 27 | #include <linux/serial_core.h> |
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 19a0e544c4e9..43e4810dcaa8 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile | |||
| @@ -32,3 +32,5 @@ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o | |||
| 32 | obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o | 32 | obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o |
| 33 | obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o | 33 | obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o |
| 34 | obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o | 34 | obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o |
| 35 | |||
| 36 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index be96231dccb6..bad571971bf6 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <asm/page.h> | 23 | #include <asm/page.h> |
| 24 | #include <asm/pgtable.h> | 24 | #include <asm/pgtable.h> |
| 25 | #include <asm/r4kcache.h> | 25 | #include <asm/r4kcache.h> |
| 26 | #include <asm/sections.h> | ||
| 26 | #include <asm/system.h> | 27 | #include <asm/system.h> |
| 27 | #include <asm/mmu_context.h> | 28 | #include <asm/mmu_context.h> |
| 28 | #include <asm/war.h> | 29 | #include <asm/war.h> |
| @@ -1010,7 +1011,6 @@ static void __init probe_pcache(void) | |||
| 1010 | */ | 1011 | */ |
| 1011 | static int __init probe_scache(void) | 1012 | static int __init probe_scache(void) |
| 1012 | { | 1013 | { |
| 1013 | extern unsigned long stext; | ||
| 1014 | unsigned long flags, addr, begin, end, pow2; | 1014 | unsigned long flags, addr, begin, end, pow2; |
| 1015 | unsigned int config = read_c0_config(); | 1015 | unsigned int config = read_c0_config(); |
| 1016 | struct cpuinfo_mips *c = ¤t_cpu_data; | 1016 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| @@ -1019,7 +1019,7 @@ static int __init probe_scache(void) | |||
| 1019 | if (config & CONF_SC) | 1019 | if (config & CONF_SC) |
| 1020 | return 0; | 1020 | return 0; |
| 1021 | 1021 | ||
| 1022 | begin = (unsigned long) &stext; | 1022 | begin = (unsigned long) &_stext; |
| 1023 | begin &= ~((4 * 1024 * 1024) - 1); | 1023 | begin &= ~((4 * 1024 * 1024) - 1); |
| 1024 | end = begin + (4 * 1024 * 1024); | 1024 | end = begin + (4 * 1024 * 1024); |
| 1025 | 1025 | ||
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c index 7dc9bf6f1321..d29040a56aea 100644 --- a/arch/mips/oprofile/op_model_rm9000.c +++ b/arch/mips/oprofile/op_model_rm9000.c | |||
| @@ -83,6 +83,7 @@ static void rm9000_cpu_stop(void *args) | |||
| 83 | static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id) | 83 | static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id) |
| 84 | { | 84 | { |
| 85 | unsigned int control = read_c0_perfcontrol(); | 85 | unsigned int control = read_c0_perfcontrol(); |
| 86 | struct pt_regs *regs = get_irq_regs(); | ||
| 86 | uint32_t counter1, counter2; | 87 | uint32_t counter1, counter2; |
| 87 | uint64_t counters; | 88 | uint64_t counters; |
| 88 | 89 | ||
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index c58bd3d036f4..4ee6800e67e6 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile | |||
| @@ -19,7 +19,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o | |||
| 19 | # These are still pretty much in the old state, watch, go blind. | 19 | # These are still pretty much in the old state, watch, go blind. |
| 20 | # | 20 | # |
| 21 | obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o | 21 | obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o |
| 22 | obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o | ||
| 23 | obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o | 22 | obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o |
| 24 | obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o | 23 | obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o |
| 25 | obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o | 24 | obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o |
| @@ -27,7 +26,6 @@ obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o | |||
| 27 | obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o | 26 | obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o |
| 28 | obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o | 27 | obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o |
| 29 | obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o | 28 | obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o |
| 30 | obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o | ||
| 31 | obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o | 29 | obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o |
| 32 | obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o | 30 | obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o |
| 33 | obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o | 31 | obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o |
diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c deleted file mode 100644 index 2f1444e60654..000000000000 --- a/arch/mips/pci/fixup-ddb5477.c +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * BRIEF MODULE DESCRIPTION | ||
| 4 | * Board specific pci fixups. | ||
| 5 | * | ||
| 6 | * Copyright 2001, 2002, 2003 MontaVista Software Inc. | ||
| 7 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License along | ||
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 28 | */ | ||
| 29 | |||
| 30 | #include <linux/types.h> | ||
| 31 | #include <linux/pci.h> | ||
| 32 | #include <linux/kernel.h> | ||
| 33 | #include <linux/init.h> | ||
| 34 | |||
| 35 | static void ddb5477_fixup(struct pci_dev *dev) | ||
| 36 | { | ||
| 37 | u8 old; | ||
| 38 | |||
| 39 | printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n"); | ||
| 40 | pci_read_config_byte(dev, 0x41, &old); | ||
| 41 | pci_write_config_byte(dev, 0x41, old | 0xd0); | ||
| 42 | } | ||
| 43 | |||
| 44 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, | ||
| 45 | ddb5477_fixup); | ||
| 46 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535, | ||
| 47 | ddb5477_fixup); | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Fixup baseboard AMD chip so that tx does not underflow. | ||
| 51 | * bcr_18 |= 0x0800 | ||
| 52 | * This sets NOUFLO bit which makes tx not start until whole pkt | ||
| 53 | * is fetched to the chip. | ||
| 54 | */ | ||
| 55 | #define PCNET32_WIO_RDP 0x10 | ||
| 56 | #define PCNET32_WIO_RAP 0x12 | ||
| 57 | #define PCNET32_WIO_RESET 0x14 | ||
| 58 | #define PCNET32_WIO_BDP 0x16 | ||
| 59 | |||
| 60 | static void ddb5477_amd_lance_fixup(struct pci_dev *dev) | ||
| 61 | { | ||
| 62 | unsigned long ioaddr; | ||
| 63 | u16 temp; | ||
| 64 | |||
| 65 | ioaddr = pci_resource_start(dev, 0); | ||
| 66 | |||
| 67 | inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ | ||
| 68 | |||
| 69 | /* bcr_18 |= 0x0800 */ | ||
| 70 | outw(18, ioaddr + PCNET32_WIO_RAP); | ||
| 71 | temp = inw(ioaddr + PCNET32_WIO_BDP); | ||
| 72 | temp |= 0x0800; | ||
| 73 | outw(18, ioaddr + PCNET32_WIO_RAP); | ||
| 74 | outw(temp, ioaddr + PCNET32_WIO_BDP); | ||
| 75 | } | ||
| 76 | |||
| 77 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, | ||
| 78 | ddb5477_amd_lance_fixup); | ||
diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c deleted file mode 100644 index 99629bd047ce..000000000000 --- a/arch/mips/pci/fixup-ocelot.c +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * arch/mips/gt64120/momenco_ocelot/pci.c | ||
| 6 | * Board-specific PCI routines for gt64120 controller. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | */ | ||
| 13 | #include <linux/types.h> | ||
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <asm/pci.h> | ||
| 18 | |||
| 19 | |||
| 20 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) | ||
| 21 | { | ||
| 22 | struct pci_bus *current_bus = bus; | ||
| 23 | struct pci_dev *devices; | ||
| 24 | struct list_head *devices_link; | ||
| 25 | u16 cmd; | ||
| 26 | |||
| 27 | list_for_each(devices_link, &(current_bus->devices)) { | ||
| 28 | |||
| 29 | devices = pci_dev_b(devices_link); | ||
| 30 | if (devices == NULL) | ||
| 31 | continue; | ||
| 32 | |||
| 33 | if (PCI_SLOT(devices->devfn) == 1) { | ||
| 34 | /* | ||
| 35 | * Slot 1 is primary ether port, i82559 | ||
| 36 | * we double-check against that assumption | ||
| 37 | */ | ||
| 38 | if ((devices->vendor != 0x8086) || | ||
| 39 | (devices->device != 0x1209)) { | ||
| 40 | panic("pcibios_fixup_bus: found " | ||
| 41 | "unexpected PCI device in slot 1."); | ||
| 42 | } | ||
| 43 | devices->irq = 2; /* irq_nr is 2 for INT0 */ | ||
| 44 | } else if (PCI_SLOT(devices->devfn) == 2) { | ||
| 45 | /* | ||
| 46 | * Slot 2 is secondary ether port, i21143 | ||
| 47 | * we double-check against that assumption | ||
| 48 | */ | ||
| 49 | if ((devices->vendor != 0x1011) || | ||
| 50 | (devices->device != 0x19)) { | ||
| 51 | panic("galileo_pcibios_fixup_bus: " | ||
| 52 | "found unexpected PCI device in slot 2."); | ||
| 53 | } | ||
| 54 | devices->irq = 3; /* irq_nr is 3 for INT1 */ | ||
| 55 | } else if (PCI_SLOT(devices->devfn) == 4) { | ||
| 56 | /* PMC Slot 1 */ | ||
| 57 | devices->irq = 8; /* irq_nr is 8 for INT6 */ | ||
| 58 | } else if (PCI_SLOT(devices->devfn) == 5) { | ||
| 59 | /* PMC Slot 1 */ | ||
| 60 | devices->irq = 9; /* irq_nr is 9 for INT7 */ | ||
| 61 | } else { | ||
| 62 | /* We don't have assign interrupts for other devices. */ | ||
| 63 | devices->irq = 0xff; | ||
| 64 | } | ||
| 65 | |||
| 66 | /* Assign an interrupt number for the device */ | ||
| 67 | bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, | ||
| 68 | devices->irq); | ||
| 69 | |||
| 70 | /* enable master */ | ||
| 71 | bus->ops->read_word(devices, PCI_COMMAND, &cmd); | ||
| 72 | cmd |= PCI_COMMAND_MASTER; | ||
| 73 | bus->ops->write_word(devices, PCI_COMMAND, cmd); | ||
| 74 | } | ||
| 75 | } | ||
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 3cdbecb8e714..7450c335b387 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c | |||
| @@ -79,7 +79,7 @@ static unsigned char backplane_pci_irq[4][4] = { | |||
| 79 | TX4927_IRQ_IOC_PCIC} | 79 | TX4927_IRQ_IOC_PCIC} |
| 80 | }; | 80 | }; |
| 81 | 81 | ||
| 82 | int pci_get_irq(struct pci_dev *dev, int pin) | 82 | static int pci_get_irq(const struct pci_dev *dev, int pin) |
| 83 | { | 83 | { |
| 84 | unsigned char irq = pin; | 84 | unsigned char irq = pin; |
| 85 | 85 | ||
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c index 2485f47dfe6f..f2ba06ee0c10 100644 --- a/arch/mips/pci/fixup-tx4938.c +++ b/arch/mips/pci/fixup-tx4938.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | extern struct pci_controller tx4938_pci_controller[]; | 19 | extern struct pci_controller tx4938_pci_controller[]; |
| 20 | 20 | ||
| 21 | int pci_get_irq(struct pci_dev *dev, int pin) | 21 | static int pci_get_irq(const struct pci_dev *dev, int pin) |
| 22 | { | 22 | { |
| 23 | int irq = pin; | 23 | int irq = pin; |
| 24 | u8 slot = PCI_SLOT(dev->devfn); | 24 | u8 slot = PCI_SLOT(dev->devfn); |
diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c deleted file mode 100644 index 8e57d4c5d90f..000000000000 --- a/arch/mips/pci/ops-ddb5477.c +++ /dev/null | |||
| @@ -1,278 +0,0 @@ | |||
| 1 | /*********************************************************************** | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * arch/mips/ddb5xxx/ddb5477/pci_ops.c | ||
| 6 | * Define the pci_ops for DB5477. | ||
| 7 | * | ||
| 8 | * Much of the code is derived from the original DDB5074 port by | ||
| 9 | * Geert Uytterhoeven <geert@sonycom.com> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify it | ||
| 12 | * under the terms of the GNU General Public License as published by the | ||
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 14 | * option) any later version. | ||
| 15 | *********************************************************************** | ||
| 16 | */ | ||
| 17 | |||
| 18 | /* | ||
| 19 | * DDB5477 has two PCI channels, external PCI and IOPIC (internal) | ||
| 20 | * Therefore we provide two sets of pci_ops. | ||
| 21 | */ | ||
| 22 | #include <linux/pci.h> | ||
| 23 | #include <linux/kernel.h> | ||
| 24 | #include <linux/types.h> | ||
| 25 | |||
| 26 | #include <asm/addrspace.h> | ||
| 27 | #include <asm/debug.h> | ||
| 28 | |||
| 29 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 30 | |||
| 31 | /* | ||
| 32 | * config_swap structure records what set of pdar/pmr are used | ||
| 33 | * to access pci config space. It also provides a place hold the | ||
| 34 | * original values for future restoring. | ||
| 35 | */ | ||
| 36 | struct pci_config_swap { | ||
| 37 | u32 pdar; | ||
| 38 | u32 pmr; | ||
| 39 | u32 config_base; | ||
| 40 | u32 config_size; | ||
| 41 | u32 pdar_backup; | ||
| 42 | u32 pmr_backup; | ||
| 43 | }; | ||
| 44 | |||
| 45 | /* | ||
| 46 | * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI. | ||
| 47 | */ | ||
| 48 | struct pci_config_swap ext_pci_swap = { | ||
| 49 | DDB_PCIW0, | ||
| 50 | DDB_PCIINIT00, | ||
| 51 | DDB_PCI0_CONFIG_BASE, | ||
| 52 | DDB_PCI0_CONFIG_SIZE | ||
| 53 | }; | ||
| 54 | struct pci_config_swap io_pci_swap = { | ||
| 55 | DDB_IOPCIW0, | ||
| 56 | DDB_PCIINIT01, | ||
| 57 | DDB_PCI1_CONFIG_BASE, | ||
| 58 | DDB_PCI1_CONFIG_SIZE | ||
| 59 | }; | ||
| 60 | |||
| 61 | |||
| 62 | /* | ||
| 63 | * access config space | ||
| 64 | */ | ||
| 65 | static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ | ||
| 66 | u32 slot_num) | ||
| 67 | { | ||
| 68 | u32 pci_addr = 0; | ||
| 69 | u32 pciinit_offset = 0; | ||
| 70 | u32 virt_addr; | ||
| 71 | u32 option; | ||
| 72 | |||
| 73 | /* minimum pdar (window) size is 2MB */ | ||
| 74 | db_assert(swap->config_size >= (2 << 20)); | ||
| 75 | |||
| 76 | db_assert(slot_num < (1 << 5)); | ||
| 77 | db_assert(bus < (1 << 8)); | ||
| 78 | |||
| 79 | /* backup registers */ | ||
| 80 | swap->pdar_backup = ddb_in32(swap->pdar); | ||
| 81 | swap->pmr_backup = ddb_in32(swap->pmr); | ||
| 82 | |||
| 83 | /* set the pdar (pci window) register */ | ||
| 84 | ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ | ||
| 85 | 0, /* not on local memory bus */ | ||
| 86 | 0); /* not visible from PCI bus (N/A) */ | ||
| 87 | |||
| 88 | /* | ||
| 89 | * calcuate the absolute pci config addr; | ||
| 90 | * according to the spec, we start scanning from adr:11 (0x800) | ||
| 91 | */ | ||
| 92 | if (bus == 0) { | ||
| 93 | /* type 0 config */ | ||
| 94 | pci_addr = 0x800 << slot_num; | ||
| 95 | } else { | ||
| 96 | /* type 1 config */ | ||
| 97 | pci_addr = (bus << 16) | (slot_num << 11); | ||
| 98 | } | ||
| 99 | |||
| 100 | /* | ||
| 101 | * if pci_addr is less than pci config window size, we set | ||
| 102 | * pciinit_offset to 0 and adjust the virt_address. | ||
| 103 | * Otherwise we will try to adjust pciinit_offset. | ||
| 104 | */ | ||
| 105 | if (pci_addr < swap->config_size) { | ||
| 106 | virt_addr = KSEG1ADDR(swap->config_base + pci_addr); | ||
| 107 | pciinit_offset = 0; | ||
| 108 | } else { | ||
| 109 | db_assert((pci_addr & (swap->config_size - 1)) == 0); | ||
| 110 | virt_addr = KSEG1ADDR(swap->config_base); | ||
| 111 | pciinit_offset = pci_addr; | ||
| 112 | } | ||
| 113 | |||
| 114 | /* set the pmr register */ | ||
| 115 | option = DDB_PCI_ACCESS_32; | ||
| 116 | if (bus != 0) | ||
| 117 | option |= DDB_PCI_CFGTYPE1; | ||
| 118 | ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); | ||
| 119 | |||
| 120 | return virt_addr; | ||
| 121 | } | ||
| 122 | |||
| 123 | static inline void ddb_close_config_base(struct pci_config_swap *swap) | ||
| 124 | { | ||
| 125 | ddb_out32(swap->pdar, swap->pdar_backup); | ||
| 126 | ddb_out32(swap->pmr, swap->pmr_backup); | ||
| 127 | } | ||
| 128 | |||
| 129 | static int read_config_dword(struct pci_config_swap *swap, | ||
| 130 | struct pci_bus *bus, u32 devfn, u32 where, | ||
| 131 | u32 * val) | ||
| 132 | { | ||
| 133 | u32 bus_num, slot_num, func_num; | ||
| 134 | u32 base; | ||
| 135 | |||
| 136 | db_assert((where & 3) == 0); | ||
| 137 | db_assert(where < (1 << 8)); | ||
| 138 | |||
| 139 | /* check if the bus is top-level */ | ||
| 140 | if (bus->parent != NULL) { | ||
| 141 | bus_num = bus->number; | ||
| 142 | db_assert(bus_num != 0); | ||
| 143 | } else { | ||
| 144 | bus_num = 0; | ||
| 145 | } | ||
| 146 | |||
| 147 | slot_num = PCI_SLOT(devfn); | ||
| 148 | func_num = PCI_FUNC(devfn); | ||
| 149 | base = ddb_access_config_base(swap, bus_num, slot_num); | ||
| 150 | *val = *(volatile u32 *) (base + (func_num << 8) + where); | ||
| 151 | ddb_close_config_base(swap); | ||
| 152 | return PCIBIOS_SUCCESSFUL; | ||
| 153 | } | ||
| 154 | |||
| 155 | static int read_config_word(struct pci_config_swap *swap, | ||
| 156 | struct pci_bus *bus, u32 devfn, u32 where, | ||
| 157 | u16 * val) | ||
| 158 | { | ||
| 159 | int status; | ||
| 160 | u32 result; | ||
| 161 | |||
| 162 | db_assert((where & 1) == 0); | ||
| 163 | |||
| 164 | status = read_config_dword(swap, bus, devfn, where & ~3, &result); | ||
| 165 | if (where & 2) | ||
| 166 | result >>= 16; | ||
| 167 | *val = result & 0xffff; | ||
| 168 | return status; | ||
| 169 | } | ||
| 170 | |||
| 171 | static int read_config_byte(struct pci_config_swap *swap, | ||
| 172 | struct pci_bus *bus, u32 devfn, u32 where, | ||
| 173 | u8 * val) | ||
| 174 | { | ||
| 175 | int status; | ||
| 176 | u32 result; | ||
| 177 | |||
| 178 | status = read_config_dword(swap, bus, devfn, where & ~3, &result); | ||
| 179 | if (where & 1) | ||
| 180 | result >>= 8; | ||
| 181 | if (where & 2) | ||
| 182 | result >>= 16; | ||
| 183 | *val = result & 0xff; | ||
| 184 | |||
| 185 | return status; | ||
| 186 | } | ||
| 187 | |||
| 188 | static int write_config_dword(struct pci_config_swap *swap, | ||
| 189 | struct pci_bus *bus, u32 devfn, u32 where, | ||
| 190 | u32 val) | ||
| 191 | { | ||
| 192 | u32 bus_num, slot_num, func_num; | ||
| 193 | u32 base; | ||
| 194 | |||
| 195 | db_assert((where & 3) == 0); | ||
| 196 | db_assert(where < (1 << 8)); | ||
| 197 | |||
| 198 | /* check if the bus is top-level */ | ||
| 199 | if (bus->parent != NULL) { | ||
| 200 | bus_num = bus->number; | ||
| 201 | db_assert(bus_num != 0); | ||
| 202 | } else { | ||
| 203 | bus_num = 0; | ||
| 204 | } | ||
| 205 | |||
| 206 | slot_num = PCI_SLOT(devfn); | ||
| 207 | func_num = PCI_FUNC(devfn); | ||
| 208 | base = ddb_access_config_base(swap, bus_num, slot_num); | ||
| 209 | *(volatile u32 *) (base + (func_num << 8) + where) = val; | ||
| 210 | ddb_close_config_base(swap); | ||
| 211 | return PCIBIOS_SUCCESSFUL; | ||
| 212 | } | ||
| 213 | |||
| 214 | static int write_config_word(struct pci_config_swap *swap, | ||
| 215 | struct pci_bus *bus, u32 devfn, u32 where, u16 val) | ||
| 216 | { | ||
| 217 | int status, shift = 0; | ||
| 218 | u32 result; | ||
| 219 | |||
| 220 | db_assert((where & 1) == 0); | ||
| 221 | |||
| 222 | status = read_config_dword(swap, bus, devfn, where & ~3, &result); | ||
| 223 | if (status != PCIBIOS_SUCCESSFUL) | ||
| 224 | return status; | ||
| 225 | |||
| 226 | if (where & 2) | ||
| 227 | shift += 16; | ||
| 228 | result &= ~(0xffff << shift); | ||
| 229 | result |= val << shift; | ||
| 230 | return write_config_dword(swap, bus, devfn, where & ~3, result); | ||
| 231 | } | ||
| 232 | |||
| 233 | static int write_config_byte(struct pci_config_swap *swap, | ||
| 234 | struct pci_bus *bus, u32 devfn, u32 where, u8 val) | ||
| 235 | { | ||
| 236 | int status, shift = 0; | ||
| 237 | u32 result; | ||
| 238 | |||
| 239 | status = read_config_dword(swap, bus, devfn, where & ~3, &result); | ||
| 240 | if (status != PCIBIOS_SUCCESSFUL) | ||
| 241 | return status; | ||
| 242 | |||
| 243 | if (where & 2) | ||
| 244 | shift += 16; | ||
| 245 | if (where & 1) | ||
| 246 | shift += 8; | ||
| 247 | result &= ~(0xff << shift); | ||
| 248 | result |= val << shift; | ||
| 249 | return write_config_dword(swap, bus, devfn, where & ~3, result); | ||
| 250 | } | ||
| 251 | |||
| 252 | #define MAKE_PCI_OPS(prefix, rw, pciswap, star) \ | ||
| 253 | static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \ | ||
| 254 | { \ | ||
| 255 | if (size == 1) \ | ||
| 256 | return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \ | ||
| 257 | else if (size == 2) \ | ||
| 258 | return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \ | ||
| 259 | /* Size must be 4 */ \ | ||
| 260 | return rw##_config_dword(pciswap, bus, devfn, where, val); \ | ||
| 261 | } | ||
| 262 | |||
| 263 | MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *) | ||
| 264 | MAKE_PCI_OPS(extpci, write, &ext_pci_swap,) | ||
| 265 | |||
| 266 | MAKE_PCI_OPS(iopci, read, &io_pci_swap, *) | ||
| 267 | MAKE_PCI_OPS(iopci, write, &io_pci_swap,) | ||
| 268 | |||
| 269 | struct pci_ops ddb5477_ext_pci_ops = { | ||
| 270 | .read = extpci_read_config, | ||
| 271 | .write = extpci_write_config | ||
| 272 | }; | ||
| 273 | |||
| 274 | |||
| 275 | struct pci_ops ddb5477_io_pci_ops = { | ||
| 276 | .read = iopci_read_config, | ||
| 277 | .write = iopci_write_config | ||
| 278 | }; | ||
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c index 38f181625e10..d31bfc6d4150 100644 --- a/arch/mips/pci/ops-emma2rh.c +++ b/arch/mips/pci/ops-emma2rh.c | |||
| @@ -45,7 +45,7 @@ static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num) | |||
| 45 | /* check if the bus is top-level */ | 45 | /* check if the bus is top-level */ |
| 46 | if (bus->parent != NULL) { | 46 | if (bus->parent != NULL) { |
| 47 | *bus_num = bus->number; | 47 | *bus_num = bus->number; |
| 48 | db_assert(bus_num != 0); | 48 | db_assert(bus_num != NULL); |
| 49 | } else | 49 | } else |
| 50 | *bus_num = 0; | 50 | *bus_num = 0; |
| 51 | 51 | ||
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c index f556b7a8dccd..d61064652498 100644 --- a/arch/mips/pci/ops-pnx8550.c +++ b/arch/mips/pci/ops-pnx8550.c | |||
| @@ -117,7 +117,7 @@ read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val) | |||
| 117 | unsigned int data = 0; | 117 | unsigned int data = 0; |
| 118 | int err; | 118 | int err; |
| 119 | 119 | ||
| 120 | if (bus == 0) | 120 | if (bus == NULL) |
| 121 | return -1; | 121 | return -1; |
| 122 | 122 | ||
| 123 | err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); | 123 | err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); |
| @@ -145,7 +145,7 @@ read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val) | |||
| 145 | unsigned int data = 0; | 145 | unsigned int data = 0; |
| 146 | int err; | 146 | int err; |
| 147 | 147 | ||
| 148 | if (bus == 0) | 148 | if (bus == NULL) |
| 149 | return -1; | 149 | return -1; |
| 150 | 150 | ||
| 151 | if (where & 0x01) | 151 | if (where & 0x01) |
| @@ -168,7 +168,7 @@ static int | |||
| 168 | read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val) | 168 | read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val) |
| 169 | { | 169 | { |
| 170 | int err; | 170 | int err; |
| 171 | if (bus == 0) | 171 | if (bus == NULL) |
| 172 | return -1; | 172 | return -1; |
| 173 | 173 | ||
| 174 | if (where & 0x03) | 174 | if (where & 0x03) |
| @@ -185,7 +185,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) | |||
| 185 | unsigned int data = (unsigned int)val; | 185 | unsigned int data = (unsigned int)val; |
| 186 | int err; | 186 | int err; |
| 187 | 187 | ||
| 188 | if (bus == 0) | 188 | if (bus == NULL) |
| 189 | return -1; | 189 | return -1; |
| 190 | 190 | ||
| 191 | switch (where & 0x03) { | 191 | switch (where & 0x03) { |
| @@ -213,7 +213,7 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val) | |||
| 213 | unsigned int data = (unsigned int)val; | 213 | unsigned int data = (unsigned int)val; |
| 214 | int err; | 214 | int err; |
| 215 | 215 | ||
| 216 | if (bus == 0) | 216 | if (bus == NULL) |
| 217 | return -1; | 217 | return -1; |
| 218 | 218 | ||
| 219 | if (where & 0x01) | 219 | if (where & 0x01) |
| @@ -235,7 +235,7 @@ static int | |||
| 235 | write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) | 235 | write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) |
| 236 | { | 236 | { |
| 237 | int err; | 237 | int err; |
| 238 | if (bus == 0) | 238 | if (bus == NULL) |
| 239 | return -1; | 239 | return -1; |
| 240 | 240 | ||
| 241 | if (where & 0x03) | 241 | if (where & 0x03) |
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c deleted file mode 100644 index 7363e1877842..000000000000 --- a/arch/mips/pci/pci-ddb5477.c +++ /dev/null | |||
| @@ -1,207 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * PCI code for DDB5477. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 MontaVista Software Inc. | ||
| 5 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 6 | * | ||
| 7 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | */ | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/pci.h> | ||
| 18 | |||
| 19 | #include <asm/bootinfo.h> | ||
| 20 | #include <asm/debug.h> | ||
| 21 | |||
| 22 | #include <asm/ddb5xxx/ddb5xxx.h> | ||
| 23 | |||
| 24 | static struct resource extpci_io_resource = { | ||
| 25 | .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, | ||
| 26 | .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, | ||
| 27 | .name = "ext pci IO space", | ||
| 28 | .flags = IORESOURCE_IO | ||
| 29 | }; | ||
| 30 | |||
| 31 | static struct resource extpci_mem_resource = { | ||
| 32 | .start = DDB_PCI0_MEM_BASE + 0x100000, | ||
| 33 | .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, | ||
| 34 | .name = "ext pci memory space", | ||
| 35 | .flags = IORESOURCE_MEM | ||
| 36 | }; | ||
| 37 | |||
| 38 | static struct resource iopci_io_resource = { | ||
| 39 | .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, | ||
| 40 | .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, | ||
| 41 | .name = "io pci IO space", | ||
| 42 | .flags = IORESOURCE_IO | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct resource iopci_mem_resource = { | ||
| 46 | .start = DDB_PCI1_MEM_BASE, | ||
| 47 | .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, | ||
| 48 | .name = "ext pci memory space", | ||
| 49 | .flags = IORESOURCE_MEM | ||
| 50 | }; | ||
| 51 | |||
| 52 | extern struct pci_ops ddb5477_ext_pci_ops; | ||
| 53 | extern struct pci_ops ddb5477_io_pci_ops; | ||
| 54 | |||
| 55 | struct pci_controller ddb5477_ext_controller = { | ||
| 56 | .pci_ops = &ddb5477_ext_pci_ops, | ||
| 57 | .io_resource = &extpci_io_resource, | ||
| 58 | .mem_resource = &extpci_mem_resource | ||
| 59 | }; | ||
| 60 | |||
| 61 | struct pci_controller ddb5477_io_controller = { | ||
| 62 | .pci_ops = &ddb5477_io_pci_ops, | ||
| 63 | .io_resource = &iopci_io_resource, | ||
| 64 | .mem_resource = &iopci_mem_resource | ||
| 65 | }; | ||
| 66 | |||
| 67 | |||
| 68 | |||
| 69 | /* | ||
| 70 | * we fix up irqs based on the slot number. | ||
| 71 | * The first entry is at AD:11. | ||
| 72 | * Fortunately this works because, although we have two pci buses, | ||
| 73 | * they all have different slot numbers (except for rockhopper slot 20 | ||
| 74 | * which is handled below). | ||
| 75 | * | ||
| 76 | */ | ||
| 77 | |||
| 78 | /* | ||
| 79 | * irq mapping : device -> pci int # -> vrc4377 irq# , | ||
| 80 | * ddb5477 board manual page 4 and vrc5477 manual page 46 | ||
| 81 | */ | ||
| 82 | |||
| 83 | /* | ||
| 84 | * based on ddb5477 manual page 11 | ||
| 85 | */ | ||
| 86 | #define MAX_SLOT_NUM 21 | ||
| 87 | static unsigned char irq_map[MAX_SLOT_NUM] = { | ||
| 88 | /* SLOT: 0, AD:11 */ 0xff, | ||
| 89 | /* SLOT: 1, AD:12 */ 0xff, | ||
| 90 | /* SLOT: 2, AD:13 */ 0xff, | ||
| 91 | /* SLOT: 3, AD:14 */ 0xff, | ||
| 92 | /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */ | ||
| 93 | /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */ | ||
| 94 | /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */ | ||
| 95 | /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */ | ||
| 96 | /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */ | ||
| 97 | /* SLOT: 9, AD:20 */ 0xff, | ||
| 98 | /* SLOT: 10, AD:21 */ 0xff, | ||
| 99 | /* SLOT: 11, AD:22 */ 0xff, | ||
| 100 | /* SLOT: 12, AD:23 */ 0xff, | ||
| 101 | /* SLOT: 13, AD:24 */ 0xff, | ||
| 102 | /* SLOT: 14, AD:25 */ 0xff, | ||
| 103 | /* SLOT: 15, AD:26 */ 0xff, | ||
| 104 | /* SLOT: 16, AD:27 */ 0xff, | ||
| 105 | /* SLOT: 17, AD:28 */ 0xff, | ||
| 106 | /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ | ||
| 107 | /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ | ||
| 108 | /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ | ||
| 109 | }; | ||
| 110 | static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = { | ||
| 111 | /* SLOT: 0, AD:11 */ 0xff, | ||
| 112 | /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */ | ||
| 113 | /* SLOT: 2, AD:13 */ 0xff, | ||
| 114 | /* SLOT: 3, AD:14 */ 0xff, | ||
| 115 | /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */ | ||
| 116 | /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */ | ||
| 117 | /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */ | ||
| 118 | /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */ | ||
| 119 | /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */ | ||
| 120 | /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */ | ||
| 121 | /* SLOT: 10, AD:21 */ 0xff, | ||
| 122 | /* SLOT: 11, AD:22 */ 0xff, | ||
| 123 | /* SLOT: 12, AD:23 */ 0xff, | ||
| 124 | /* SLOT: 13, AD:24 */ 0xff, | ||
| 125 | /* SLOT: 14, AD:25 */ 0xff, | ||
| 126 | /* SLOT: 15, AD:26 */ 0xff, | ||
| 127 | /* SLOT: 16, AD:27 */ 0xff, | ||
| 128 | /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */ | ||
| 129 | /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ | ||
| 130 | /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ | ||
| 131 | /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ | ||
| 132 | }; | ||
| 133 | |||
| 134 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | ||
| 135 | { | ||
| 136 | int slot_num; | ||
| 137 | unsigned char *slot_irq_map; | ||
| 138 | unsigned char irq; | ||
| 139 | |||
| 140 | /* | ||
| 141 | * We ignore the swizzled slot and pin values. The original | ||
| 142 | * pci_fixup_irq() codes largely base irq number on the dev slot | ||
| 143 | * numbers because except for one case they are unique even | ||
| 144 | * though there are multiple pci buses. | ||
| 145 | */ | ||
| 146 | |||
| 147 | if (mips_machtype == MACH_NEC_ROCKHOPPERII) | ||
| 148 | slot_irq_map = rockhopperII_irq_map; | ||
| 149 | else | ||
| 150 | slot_irq_map = irq_map; | ||
| 151 | |||
| 152 | slot_num = PCI_SLOT(dev->devfn); | ||
| 153 | irq = slot_irq_map[slot_num]; | ||
| 154 | |||
| 155 | db_assert(slot_num < MAX_SLOT_NUM); | ||
| 156 | |||
| 157 | db_assert(irq != 0xff); | ||
| 158 | |||
| 159 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | ||
| 160 | |||
| 161 | if (mips_machtype == MACH_NEC_ROCKHOPPERII) { | ||
| 162 | /* hack to distinquish overlapping slot 20s, one | ||
| 163 | * on bus 0 (ALI USB on the M1535 on the backplane), | ||
| 164 | * and one on bus 2 (NEC USB controller on the CPU board) | ||
| 165 | * Make the M1535 USB - ISA IRQ number 9. | ||
| 166 | */ | ||
| 167 | if (slot_num == 20 && dev->bus->number == 0) { | ||
| 168 | pci_write_config_byte(dev, | ||
| 169 | PCI_INTERRUPT_LINE, | ||
| 170 | 9); | ||
| 171 | irq = 9; | ||
| 172 | } | ||
| 173 | |||
| 174 | } | ||
| 175 | |||
| 176 | return irq; | ||
| 177 | } | ||
| 178 | |||
| 179 | /* Do platform specific device initialization at pci_enable_device() time */ | ||
| 180 | int pcibios_plat_dev_init(struct pci_dev *dev) | ||
| 181 | { | ||
| 182 | return 0; | ||
| 183 | } | ||
| 184 | |||
| 185 | void ddb_pci_reset_bus(void) | ||
| 186 | { | ||
| 187 | u32 temp; | ||
| 188 | |||
| 189 | /* | ||
| 190 | * I am not sure about the "official" procedure, the following | ||
| 191 | * steps work as far as I know: | ||
| 192 | * We first set PCI cold reset bit (bit 31) in PCICTRL-H. | ||
| 193 | * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. | ||
| 194 | * The same is true for both PCI channels. | ||
| 195 | */ | ||
| 196 | temp = ddb_in32(DDB_PCICTL0_H); | ||
| 197 | temp |= 0x80000000; | ||
| 198 | ddb_out32(DDB_PCICTL0_H, temp); | ||
| 199 | temp &= ~0xc0000000; | ||
| 200 | ddb_out32(DDB_PCICTL0_H, temp); | ||
| 201 | |||
| 202 | temp = ddb_in32(DDB_PCICTL1_H); | ||
| 203 | temp |= 0x80000000; | ||
| 204 | ddb_out32(DDB_PCICTL1_H, temp); | ||
| 205 | temp &= ~0xc0000000; | ||
| 206 | ddb_out32(DDB_PCICTL1_H, temp); | ||
| 207 | } | ||
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c deleted file mode 100644 index 1421d34535ef..000000000000 --- a/arch/mips/pci/pci-ocelot.c +++ /dev/null | |||
| @@ -1,107 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * BRIEF MODULE DESCRIPTION | ||
| 3 | * Galileo Evaluation Boards PCI support. | ||
| 4 | * | ||
| 5 | * The general-purpose functions to read/write and configure the GT64120A's | ||
| 6 | * PCI registers (function names start with pci0 or pci1) are either direct | ||
| 7 | * copies of functions written by Galileo Technology, or are modifications | ||
| 8 | * of their functions to work with Linux 2.4 vs Linux 2.2. These functions | ||
| 9 | * are Copyright - Galileo Technology. | ||
| 10 | * | ||
| 11 | * Other functions are derived from other MIPS PCI implementations, or were | ||
| 12 | * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. | ||
| 13 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
| 14 | * | ||
| 15 | * Copyright 2001 MontaVista Software Inc. | ||
| 16 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
| 17 | * | ||
| 18 | * This program is free software; you can redistribute it and/or modify it | ||
| 19 | * under the terms of the GNU General Public License as published by the | ||
| 20 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 21 | * option) any later version. | ||
| 22 | * | ||
| 23 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 26 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 33 | * | ||
| 34 | * You should have received a copy of the GNU General Public License along | ||
| 35 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 36 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 37 | */ | ||
| 38 | #include <linux/init.h> | ||
| 39 | #include <linux/types.h> | ||
| 40 | #include <linux/pci.h> | ||
| 41 | #include <linux/kernel.h> | ||
| 42 | #include <linux/slab.h> | ||
| 43 | #include <linux/cache.h> | ||
| 44 | #include <asm/pci.h> | ||
| 45 | #include <asm/io.h> | ||
| 46 | #include <asm/gt64120.h> | ||
| 47 | |||
| 48 | static inline unsigned int pci0ReadConfigReg(unsigned int offset) | ||
| 49 | { | ||
| 50 | unsigned int DataForRegCf8; | ||
| 51 | unsigned int data; | ||
| 52 | |||
| 53 | DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | | ||
| 54 | (PCI_FUNC(device->devfn) << 8) | | ||
| 55 | (offset & ~0x3)) | 0x80000000; | ||
| 56 | GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); | ||
| 57 | GT_READ(GT_PCI0_CFGDATA_OFS, &data); | ||
| 58 | |||
| 59 | return data; | ||
| 60 | } | ||
| 61 | |||
| 62 | static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data) | ||
| 63 | { | ||
| 64 | unsigned int DataForRegCf8; | ||
| 65 | |||
| 66 | DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | | ||
| 67 | (PCI_FUNC(device->devfn) << 8) | | ||
| 68 | (offset & ~0x3)) | 0x80000000; | ||
| 69 | GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); | ||
| 70 | GT_WRITE(GT_PCI0_CFGDATA_OFS, data); | ||
| 71 | } | ||
| 72 | |||
| 73 | static struct resource ocelot_mem_resource = { | ||
| 74 | .start = GT_PCI_MEM_BASE, | ||
| 75 | .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1, | ||
| 76 | }; | ||
| 77 | |||
| 78 | static struct resource ocelot_io_resource = { | ||
| 79 | .start = GT_PCI_IO_BASE, | ||
| 80 | .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1, | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct pci_controller ocelot_pci_controller = { | ||
| 84 | .pci_ops = gt64xxx_pci0_ops, | ||
| 85 | .mem_resource = &ocelot_mem_resource, | ||
| 86 | .io_resource = &ocelot_io_resource, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static int __init ocelot_pcibios_init(void) | ||
| 90 | { | ||
| 91 | u32 tmp; | ||
| 92 | |||
| 93 | GT_READ(GT_PCI0_CMD_OFS, &tmp); | ||
| 94 | GT_READ(GT_PCI0_BARE_OFS, &tmp); | ||
| 95 | |||
| 96 | /* | ||
| 97 | * You have to enable bus mastering to configure any other | ||
| 98 | * card on the bus. | ||
| 99 | */ | ||
| 100 | tmp = pci0ReadConfigReg(PCI_COMMAND); | ||
| 101 | tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | ||
| 102 | pci0WriteConfigReg(PCI_COMMAND, tmp); | ||
| 103 | |||
| 104 | register_pci_controller(&ocelot_pci_controller); | ||
| 105 | } | ||
| 106 | |||
| 107 | arch_initcall(ocelot_pcibios_init); | ||
diff --git a/arch/mips/philips/pnx8550/common/Makefile b/arch/mips/philips/pnx8550/common/Makefile index b7c638166e9f..31cc1a5cec3b 100644 --- a/arch/mips/philips/pnx8550/common/Makefile +++ b/arch/mips/philips/pnx8550/common/Makefile | |||
| @@ -25,3 +25,5 @@ | |||
| 25 | obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o | 25 | obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o |
| 26 | obj-$(CONFIG_PCI) += pci.o | 26 | obj-$(CONFIG_PCI) += pci.o |
| 27 | obj-$(CONFIG_KGDB) += gdb_hook.o | 27 | obj-$(CONFIG_KGDB) += gdb_hook.o |
| 28 | |||
| 29 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile index e931e0d44229..8fd9a04e3534 100644 --- a/arch/mips/pmc-sierra/yosemite/Makefile +++ b/arch/mips/pmc-sierra/yosemite/Makefile | |||
| @@ -2,7 +2,9 @@ | |||
| 2 | # Makefile for the PMC-Sierra Titan | 2 | # Makefile for the PMC-Sierra Titan |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y += irq.o i2c-yosemite.o prom.o py-console.o setup.o | 5 | obj-y += irq.o prom.o py-console.o setup.o |
| 6 | 6 | ||
| 7 | obj-$(CONFIG_KGDB) += dbg_io.o | 7 | obj-$(CONFIG_KGDB) += dbg_io.o |
| 8 | obj-$(CONFIG_SMP) += smp.o | 8 | obj-$(CONFIG_SMP) += smp.o |
| 9 | |||
| 10 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c b/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c deleted file mode 100644 index 85b14c73c226..000000000000 --- a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c +++ /dev/null | |||
| @@ -1,188 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2003 PMC-Sierra Inc. | ||
| 3 | * Author: Manish Lachwani (lachwani@pmc-sierra.com) | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it | ||
| 6 | * under the terms of the GNU General Public License as published by the | ||
| 7 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 8 | * option) any later version. | ||
| 9 | * | ||
| 10 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 11 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 12 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 13 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 14 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 15 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 16 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 17 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 18 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 19 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 20 | * | ||
| 21 | * You should have received a copy of the GNU General Public License along | ||
| 22 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 23 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 24 | */ | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Detailed Description: | ||
| 28 | * | ||
| 29 | * This block implements the I2C interface to the slave devices like the | ||
| 30 | * Atmel 24C32 EEPROM and the MAX 1619 Sensors device. The I2C Master interface | ||
| 31 | * can be controlled by the SCMB block. And the SCMB block kicks in only when | ||
| 32 | * using the Ethernet Mode of operation and __not__ the SysAD mode | ||
| 33 | * | ||
| 34 | * The SCMB controls the two modes: MDIO and the I2C. The MDIO mode is used to | ||
| 35 | * communicate with the Quad-PHY from Marvel. The I2C is used to communicate | ||
| 36 | * with the I2C slave devices. It seems that the driver does not explicitly | ||
| 37 | * deal with the control of SDA and SCL serial lines. So, the driver will set | ||
| 38 | * the slave address, drive the command and then the data. The SCMB will then | ||
| 39 | * control the two serial lines as required. | ||
| 40 | * | ||
| 41 | * It seems the documents are very unclear abt this. Hence, I took some time | ||
| 42 | * out to write the desciption to have an idea of how the I2C can actually | ||
| 43 | * work. Currently, this Linux driver wont be integrated into the generic Linux | ||
| 44 | * I2C framework. And finally, the I2C interface is also known as the 2BI | ||
| 45 | * interface. 2BI means 2-bit interface referring to SDA and SCL serial lines | ||
| 46 | * respectively. | ||
| 47 | * | ||
| 48 | * - Manish Lachwani (12/09/2003) | ||
| 49 | */ | ||
| 50 | |||
| 51 | #include "i2c-yosemite.h" | ||
| 52 | |||
| 53 | /* | ||
| 54 | * Poll the I2C interface for the BUSY bit. | ||
| 55 | */ | ||
| 56 | static int titan_i2c_poll(void) | ||
| 57 | { | ||
| 58 | int i = 0; | ||
| 59 | unsigned long val = 0; | ||
| 60 | |||
| 61 | for (i = 0; i < TITAN_I2C_MAX_POLL; i++) { | ||
| 62 | val = TITAN_I2C_READ(TITAN_I2C_COMMAND); | ||
| 63 | |||
| 64 | if (!(val & 0x8000)) | ||
| 65 | return 0; | ||
| 66 | } | ||
| 67 | |||
| 68 | return TITAN_I2C_ERR_TIMEOUT; | ||
| 69 | } | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Execute the I2C command | ||
| 73 | */ | ||
| 74 | int titan_i2c_xfer(unsigned int slave_addr, titan_i2c_command * cmd, | ||
| 75 | int size, unsigned int *addr) | ||
| 76 | { | ||
| 77 | int loop, bytes = 0, i; | ||
| 78 | unsigned int *write_data, data, *read_data; | ||
| 79 | unsigned long reg_val, val; | ||
| 80 | |||
| 81 | write_data = cmd->data; | ||
| 82 | read_data = addr; | ||
| 83 | |||
| 84 | TITAN_I2C_WRITE(TITAN_I2C_SLAVE_ADDRESS, slave_addr); | ||
| 85 | |||
| 86 | if (cmd->type == TITAN_I2C_CMD_WRITE) | ||
| 87 | loop = cmd->write_size; | ||
| 88 | else | ||
| 89 | loop = size; | ||
| 90 | |||
| 91 | while (loop > 0) { | ||
| 92 | if ((cmd->type == TITAN_I2C_CMD_WRITE) || | ||
| 93 | (cmd->type == TITAN_I2C_CMD_READ_WRITE)) { | ||
| 94 | |||
| 95 | reg_val = TITAN_I2C_DATA; | ||
| 96 | for (i = 0; i < TITAN_I2C_MAX_WORDS_PER_RW; | ||
| 97 | ++i, write_data += 2, reg_val += 4) { | ||
| 98 | if (bytes < cmd->write_size) { | ||
| 99 | data = write_data[0]; | ||
| 100 | ++data; | ||
| 101 | } | ||
| 102 | |||
| 103 | if (bytes < cmd->write_size) { | ||
| 104 | data = write_data[1]; | ||
| 105 | ++data; | ||
| 106 | } | ||
| 107 | |||
| 108 | TITAN_I2C_WRITE(reg_val, data); | ||
| 109 | } | ||
| 110 | } | ||
| 111 | |||
| 112 | TITAN_I2C_WRITE(TITAN_I2C_COMMAND, | ||
| 113 | (unsigned int) (cmd->type << 13)); | ||
| 114 | if (titan_i2c_poll() != TITAN_I2C_ERR_OK) | ||
| 115 | return TITAN_I2C_ERR_TIMEOUT; | ||
| 116 | |||
| 117 | if ((cmd->type == TITAN_I2C_CMD_READ) || | ||
| 118 | (cmd->type == TITAN_I2C_CMD_READ_WRITE)) { | ||
| 119 | |||
| 120 | reg_val = TITAN_I2C_DATA; | ||
| 121 | for (i = 0; i < TITAN_I2C_MAX_WORDS_PER_RW; | ||
| 122 | ++i, read_data += 2, reg_val += 4) { | ||
| 123 | data = TITAN_I2C_READ(reg_val); | ||
| 124 | |||
| 125 | if (bytes < size) { | ||
| 126 | read_data[0] = data & 0xff; | ||
| 127 | ++bytes; | ||
| 128 | } | ||
| 129 | |||
| 130 | if (bytes < size) { | ||
| 131 | read_data[1] = | ||
| 132 | ((data >> 8) & 0xff); | ||
| 133 | ++bytes; | ||
| 134 | } | ||
| 135 | } | ||
| 136 | } | ||
| 137 | |||
| 138 | loop -= (TITAN_I2C_MAX_WORDS_PER_RW * 2); | ||
| 139 | } | ||
| 140 | |||
| 141 | /* | ||
| 142 | * Read the Interrupt status and then return the appropriate error code | ||
| 143 | */ | ||
| 144 | |||
| 145 | val = TITAN_I2C_READ(TITAN_I2C_INTERRUPTS); | ||
| 146 | if (val & 0x0020) | ||
| 147 | return TITAN_I2C_ERR_ARB_LOST; | ||
| 148 | |||
| 149 | if (val & 0x0040) | ||
| 150 | return TITAN_I2C_ERR_NO_RESP; | ||
| 151 | |||
| 152 | if (val & 0x0080) | ||
| 153 | return TITAN_I2C_ERR_DATA_COLLISION; | ||
| 154 | |||
| 155 | return TITAN_I2C_ERR_OK; | ||
| 156 | } | ||
| 157 | |||
| 158 | /* | ||
| 159 | * Init the I2C subsystem of the PMC-Sierra Yosemite board | ||
| 160 | */ | ||
| 161 | int titan_i2c_init(titan_i2c_config * config) | ||
| 162 | { | ||
| 163 | unsigned int val; | ||
| 164 | |||
| 165 | /* | ||
| 166 | * Reset the SCMB and program into the I2C mode | ||
| 167 | */ | ||
| 168 | TITAN_I2C_WRITE(TITAN_I2C_SCMB_CONTROL, 0xA000); | ||
| 169 | TITAN_I2C_WRITE(TITAN_I2C_SCMB_CONTROL, 0x2000); | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Configure the filtera and clka values | ||
| 173 | */ | ||
| 174 | val = TITAN_I2C_READ(TITAN_I2C_SCMB_CLOCK_A); | ||
| 175 | val |= ((val & ~(0xF000)) | ((config->filtera << 12) & 0xF000)); | ||
| 176 | val |= ((val & ~(0x03FF)) | (config->clka & 0x03FF)); | ||
| 177 | TITAN_I2C_WRITE(TITAN_I2C_SCMB_CLOCK_A, val); | ||
| 178 | |||
| 179 | /* | ||
| 180 | * Configure the filterb and clkb values | ||
| 181 | */ | ||
| 182 | val = TITAN_I2C_READ(TITAN_I2C_SCMB_CLOCK_B); | ||
| 183 | val |= ((val & ~(0xF000)) | ((config->filterb << 12) & 0xF000)); | ||
| 184 | val |= ((val & ~(0x03FF)) | (config->clkb & 0x03FF)); | ||
| 185 | TITAN_I2C_WRITE(TITAN_I2C_SCMB_CLOCK_B, val); | ||
| 186 | |||
| 187 | return TITAN_I2C_ERR_OK; | ||
| 188 | } | ||
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c index 428d1f45a287..4decc2807867 100644 --- a/arch/mips/pmc-sierra/yosemite/irq.c +++ b/arch/mips/pmc-sierra/yosemite/irq.c | |||
| @@ -56,6 +56,9 @@ | |||
| 56 | #define HYPERTRANSPORT_INTC 0x7a /* INTC# */ | 56 | #define HYPERTRANSPORT_INTC 0x7a /* INTC# */ |
| 57 | #define HYPERTRANSPORT_INTD 0x7b /* INTD# */ | 57 | #define HYPERTRANSPORT_INTD 0x7b /* INTD# */ |
| 58 | 58 | ||
| 59 | extern void titan_mailbox_irq(void); | ||
| 60 | |||
| 61 | #ifdef CONFIG_HYPERTRANSPORT | ||
| 59 | /* | 62 | /* |
| 60 | * Handle hypertransport & SMP interrupts. The interrupt lines are scarce. | 63 | * Handle hypertransport & SMP interrupts. The interrupt lines are scarce. |
| 61 | * For interprocessor interrupts, the best thing to do is to use the INTMSG | 64 | * For interprocessor interrupts, the best thing to do is to use the INTMSG |
| @@ -107,6 +110,7 @@ static void ll_ht_smp_irq_handler(int irq) | |||
| 107 | 110 | ||
| 108 | do_IRQ(irq); | 111 | do_IRQ(irq); |
| 109 | } | 112 | } |
| 113 | #endif | ||
| 110 | 114 | ||
| 111 | asmlinkage void plat_irq_dispatch(void) | 115 | asmlinkage void plat_irq_dispatch(void) |
| 112 | { | 116 | { |
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index 1e1685e415a4..0cd78f0f5f2d 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c | |||
| @@ -34,7 +34,7 @@ extern void prom_grab_secondary(void); | |||
| 34 | struct callvectors *debug_vectors; | 34 | struct callvectors *debug_vectors; |
| 35 | 35 | ||
| 36 | extern unsigned long yosemite_base; | 36 | extern unsigned long yosemite_base; |
| 37 | extern unsigned long cpu_clock; | 37 | extern unsigned long cpu_clock_freq; |
| 38 | 38 | ||
| 39 | const char *get_system_type(void) | 39 | const char *get_system_type(void) |
| 40 | { | 40 | { |
| @@ -119,7 +119,7 @@ void __init prom_init(void) | |||
| 119 | 16); | 119 | 16); |
| 120 | 120 | ||
| 121 | if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) | 121 | if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) |
| 122 | cpu_clock = | 122 | cpu_clock_freq = |
| 123 | simple_strtol(*env + strlen("cpuclock="), NULL, | 123 | simple_strtol(*env + strlen("cpuclock="), NULL, |
| 124 | 10); | 124 | 10); |
| 125 | 125 | ||
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index f7f93ae24c34..58862c8d1d00 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c | |||
| @@ -59,7 +59,7 @@ unsigned char titan_ge_mac_addr_base[6] = { | |||
| 59 | 0x00, 0xe0, 0x04, 0x00, 0x00, 0x21 | 59 | 0x00, 0xe0, 0x04, 0x00, 0x00, 0x21 |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | unsigned long cpu_clock; | 62 | unsigned long cpu_clock_freq; |
| 63 | unsigned long yosemite_base; | 63 | unsigned long yosemite_base; |
| 64 | 64 | ||
| 65 | static struct m48t37_rtc *m48t37_base; | 65 | static struct m48t37_rtc *m48t37_base; |
| @@ -140,7 +140,7 @@ void __init plat_timer_setup(struct irqaction *irq) | |||
| 140 | 140 | ||
| 141 | void yosemite_time_init(void) | 141 | void yosemite_time_init(void) |
| 142 | { | 142 | { |
| 143 | mips_hpt_frequency = cpu_clock / 2; | 143 | mips_hpt_frequency = cpu_clock_freq / 2; |
| 144 | mips_hpt_frequency = 33000000 * 3 * 5; | 144 | mips_hpt_frequency = 33000000 * 3 * 5; |
| 145 | } | 145 | } |
| 146 | 146 | ||
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index d83c4ada14f3..1c852d6a7654 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c | |||
| @@ -106,23 +106,28 @@ void prom_smp_finish(void) | |||
| 106 | { | 106 | { |
| 107 | } | 107 | } |
| 108 | 108 | ||
| 109 | asmlinkage void titan_mailbox_irq(void) | 109 | void titan_mailbox_irq(void) |
| 110 | { | 110 | { |
| 111 | int cpu = smp_processor_id(); | 111 | int cpu = smp_processor_id(); |
| 112 | unsigned long status; | 112 | unsigned long status; |
| 113 | 113 | ||
| 114 | if (cpu == 0) { | 114 | switch (cpu) { |
| 115 | case 0: | ||
| 115 | status = OCD_READ(RM9000x2_OCD_INTP0STATUS3); | 116 | status = OCD_READ(RM9000x2_OCD_INTP0STATUS3); |
| 116 | OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status); | 117 | OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status); |
| 117 | } | ||
| 118 | 118 | ||
| 119 | if (cpu == 1) { | 119 | if (status & 0x2) |
| 120 | smp_call_function_interrupt(); | ||
| 121 | break; | ||
| 122 | |||
| 123 | case 1: | ||
| 120 | status = OCD_READ(RM9000x2_OCD_INTP1STATUS3); | 124 | status = OCD_READ(RM9000x2_OCD_INTP1STATUS3); |
| 121 | OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status); | 125 | OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status); |
| 122 | } | ||
| 123 | 126 | ||
| 124 | if (status & 0x2) | 127 | if (status & 0x2) |
| 125 | smp_call_function_interrupt(); | 128 | smp_call_function_interrupt(); |
| 129 | break; | ||
| 130 | } | ||
| 126 | } | 131 | } |
| 127 | 132 | ||
| 128 | /* | 133 | /* |
diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile index 078cd3029c9f..cec24c117f6e 100644 --- a/arch/mips/qemu/Makefile +++ b/arch/mips/qemu/Makefile | |||
| @@ -5,3 +5,5 @@ | |||
| 5 | obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o | 5 | obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o |
| 6 | 6 | ||
| 7 | obj-$(CONFIG_SMP) += q-smp.o | 7 | obj-$(CONFIG_SMP) += q-smp.o |
| 8 | |||
| 9 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile index 7ce76e20beb9..e0a6871d56e4 100644 --- a/arch/mips/sgi-ip27/Makefile +++ b/arch/mips/sgi-ip27/Makefile | |||
| @@ -9,3 +9,5 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \ | |||
| 9 | obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o | 9 | obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o |
| 10 | obj-$(CONFIG_KGDB) += ip27-dbgio.o | 10 | obj-$(CONFIG_KGDB) += ip27-dbgio.o |
| 11 | obj-$(CONFIG_SMP) += ip27-smp.o | 11 | obj-$(CONFIG_SMP) += ip27-smp.o |
| 12 | |||
| 13 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/sgi-ip27/ip27-klnuma.c b/arch/mips/sgi-ip27/ip27-klnuma.c index f9f404a8ddad..f10d9839006d 100644 --- a/arch/mips/sgi-ip27/ip27-klnuma.c +++ b/arch/mips/sgi-ip27/ip27-klnuma.c | |||
| @@ -28,8 +28,6 @@ static cpumask_t ktext_repmask; | |||
| 28 | */ | 28 | */ |
| 29 | void __init setup_replication_mask(void) | 29 | void __init setup_replication_mask(void) |
| 30 | { | 30 | { |
| 31 | cnodeid_t cnode; | ||
| 32 | |||
| 33 | /* Set only the master cnode's bit. The master cnode is always 0. */ | 31 | /* Set only the master cnode's bit. The master cnode is always 0. */ |
| 34 | cpus_clear(ktext_repmask); | 32 | cpus_clear(ktext_repmask); |
| 35 | cpu_set(0, ktext_repmask); | 33 | cpu_set(0, ktext_repmask); |
| @@ -38,11 +36,15 @@ void __init setup_replication_mask(void) | |||
| 38 | #ifndef CONFIG_MAPPED_KERNEL | 36 | #ifndef CONFIG_MAPPED_KERNEL |
| 39 | #error Kernel replication works with mapped kernel support. No calias support. | 37 | #error Kernel replication works with mapped kernel support. No calias support. |
| 40 | #endif | 38 | #endif |
| 41 | for_each_online_node(cnode) { | 39 | { |
| 42 | if (cnode == 0) | 40 | cnodeid_t cnode; |
| 43 | continue; | 41 | |
| 44 | /* Advertise that we have a copy of the kernel */ | 42 | for_each_online_node(cnode) { |
| 45 | cpu_set(cnode, ktext_repmask); | 43 | if (cnode == 0) |
| 44 | continue; | ||
| 45 | /* Advertise that we have a copy of the kernel */ | ||
| 46 | cpu_set(cnode, ktext_repmask); | ||
| 47 | } | ||
| 46 | } | 48 | } |
| 47 | #endif | 49 | #endif |
| 48 | /* Set up a GDA pointer to the replication mask. */ | 50 | /* Set up a GDA pointer to the replication mask. */ |
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index 09fa7f5216f0..08e79141b47c 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c | |||
| @@ -181,7 +181,7 @@ void __init prom_boot_secondary(int cpu, struct task_struct *idle) | |||
| 181 | 0, (void *) sp, (void *) gp); | 181 | 0, (void *) sp, (void *) gp); |
| 182 | } | 182 | } |
| 183 | 183 | ||
| 184 | void prom_init_secondary(void) | 184 | void __cpuinit prom_init_secondary(void) |
| 185 | { | 185 | { |
| 186 | per_cpu_init(); | 186 | per_cpu_init(); |
| 187 | local_irq_enable(); | 187 | local_irq_enable(); |
diff --git a/arch/mips/sgi-ip32/Makefile b/arch/mips/sgi-ip32/Makefile index 60f0227425e7..31c9aa1bcb40 100644 --- a/arch/mips/sgi-ip32/Makefile +++ b/arch/mips/sgi-ip32/Makefile | |||
| @@ -5,3 +5,5 @@ | |||
| 5 | 5 | ||
| 6 | obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \ | 6 | obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \ |
| 7 | crime.o ip32-memory.o | 7 | crime.o ip32-memory.o |
| 8 | |||
| 9 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index db8084411538..624bbdbff2a8 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c | |||
| @@ -195,7 +195,8 @@ static __init int ip32_reboot_setup(void) | |||
| 195 | blink_timer.function = blink_timeout; | 195 | blink_timer.function = blink_timeout; |
| 196 | atomic_notifier_chain_register(&panic_notifier_list, &panic_block); | 196 | atomic_notifier_chain_register(&panic_notifier_list, &panic_block); |
| 197 | 197 | ||
| 198 | request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL); | 198 | if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL)) |
| 199 | panic("Can't allocate MACEISA RTC IRQ"); | ||
| 199 | 200 | ||
| 200 | return 0; | 201 | return 0; |
| 201 | } | 202 | } |
diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile index cdc4c56c3e29..f292f7df0cfb 100644 --- a/arch/mips/sibyte/bcm1480/Makefile +++ b/arch/mips/sibyte/bcm1480/Makefile | |||
| @@ -1,3 +1,5 @@ | |||
| 1 | obj-y := setup.o irq.o time.o | 1 | obj-y := setup.o irq.o time.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_SMP) += smp.o | 3 | obj-$(CONFIG_SMP) += smp.o |
| 4 | |||
| 5 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c index 89f29233cae1..bb28f28e8042 100644 --- a/arch/mips/sibyte/bcm1480/setup.c +++ b/arch/mips/sibyte/bcm1480/setup.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 17 | */ | 17 | */ |
| 18 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> | ||
| 19 | #include <linux/reboot.h> | 20 | #include <linux/reboot.h> |
| 20 | #include <linux/string.h> | 21 | #include <linux/string.h> |
| 21 | 22 | ||
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile index 8a06a4fb5212..f8ae30066a05 100644 --- a/arch/mips/sibyte/common/Makefile +++ b/arch/mips/sibyte/common/Makefile | |||
| @@ -3,3 +3,4 @@ obj-y := | |||
| 3 | obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o | 3 | obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o |
| 4 | 4 | ||
| 5 | EXTRA_AFLAGS := $(CFLAGS) | 5 | EXTRA_AFLAGS := $(CFLAGS) |
| 6 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile index df662c61473a..697793783a25 100644 --- a/arch/mips/sibyte/sb1250/Makefile +++ b/arch/mips/sibyte/sb1250/Makefile | |||
| @@ -3,3 +3,5 @@ obj-y := setup.o irq.o time.o | |||
| 3 | obj-$(CONFIG_SMP) += smp.o | 3 | obj-$(CONFIG_SMP) += smp.o |
| 4 | obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o | 4 | obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o |
| 5 | obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o | 5 | obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o |
| 6 | |||
| 7 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile index 471418e4f446..3a99cd62c0bd 100644 --- a/arch/mips/sni/Makefile +++ b/arch/mips/sni/Makefile | |||
| @@ -4,3 +4,5 @@ | |||
| 4 | 4 | ||
| 5 | obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o | 5 | obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o |
| 6 | obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o | 6 | obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o |
| 7 | |||
| 8 | EXTRA_CFLAGS += -Werror | ||
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c index 3d25d010f3d5..00b0b975f349 100644 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ b/arch/mips/tx4927/common/tx4927_irq.c | |||
| @@ -43,6 +43,9 @@ | |||
| 43 | #include <asm/mipsregs.h> | 43 | #include <asm/mipsregs.h> |
| 44 | #include <asm/system.h> | 44 | #include <asm/system.h> |
| 45 | #include <asm/tx4927/tx4927.h> | 45 | #include <asm/tx4927/tx4927.h> |
| 46 | #ifdef CONFIG_TOSHIBA_RBTX4927 | ||
| 47 | #include <asm/tx4927/toshiba_rbtx4927.h> | ||
| 48 | #endif | ||
| 46 | 49 | ||
| 47 | /* | 50 | /* |
| 48 | * DEBUG | 51 | * DEBUG |
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 5cc30c10e746..e265fcd31b60 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | |||
| @@ -262,8 +262,6 @@ u32 bit2num(u32 num) | |||
| 262 | int toshiba_rbtx4927_irq_nested(int sw_irq) | 262 | int toshiba_rbtx4927_irq_nested(int sw_irq) |
| 263 | { | 263 | { |
| 264 | u32 level3; | 264 | u32 level3; |
| 265 | u32 level4; | ||
| 266 | u32 level5; | ||
| 267 | 265 | ||
| 268 | level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; | 266 | level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; |
| 269 | if (level3) { | 267 | if (level3) { |
| @@ -275,6 +273,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) | |||
| 275 | #ifdef CONFIG_TOSHIBA_FPCIB0 | 273 | #ifdef CONFIG_TOSHIBA_FPCIB0 |
| 276 | { | 274 | { |
| 277 | if (tx4927_using_backplane) { | 275 | if (tx4927_using_backplane) { |
| 276 | u32 level4; | ||
| 277 | u32 level5; | ||
| 278 | outb(0x0A, 0x20); | 278 | outb(0x0A, 0x20); |
| 279 | level4 = inb(0x20) & 0xff; | 279 | level4 = inb(0x20) & 0xff; |
| 280 | if (level4) { | 280 | if (level4) { |
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index ab72292a172e..ea5a70b252a0 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c | |||
| @@ -159,58 +159,6 @@ int tx4927_pci66 = 0; /* 0:auto */ | |||
| 159 | char *toshiba_name = ""; | 159 | char *toshiba_name = ""; |
| 160 | 160 | ||
| 161 | #ifdef CONFIG_PCI | 161 | #ifdef CONFIG_PCI |
| 162 | static void tx4927_pcierr_interrupt(int irq, void *dev_id) | ||
| 163 | { | ||
| 164 | #ifdef CONFIG_BLK_DEV_IDEPCI | ||
| 165 | /* ignore MasterAbort for ide probing... */ | ||
| 166 | if (irq == TX4927_IRQ_IRC_PCIERR && | ||
| 167 | ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) == | ||
| 168 | PCI_STATUS_REC_MASTER_ABORT) { | ||
| 169 | tx4927_pcicptr->pcistatus = | ||
| 170 | (tx4927_pcicptr-> | ||
| 171 | pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT | ||
| 172 | << 16); | ||
| 173 | |||
| 174 | return; | ||
| 175 | } | ||
| 176 | #endif | ||
| 177 | printk("PCI error interrupt (irq 0x%x).\n", irq); | ||
| 178 | |||
| 179 | printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n", | ||
| 180 | (unsigned short) (tx4927_pcicptr->pcistatus >> 16), | ||
| 181 | tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus); | ||
| 182 | printk("ccfg:%08lx, tear:%02lx_%08lx\n", | ||
| 183 | (unsigned long) tx4927_ccfgptr->ccfg, | ||
| 184 | (unsigned long) (tx4927_ccfgptr->tear >> 32), | ||
| 185 | (unsigned long) tx4927_ccfgptr->tear); | ||
| 186 | show_regs(get_irq_regs()); | ||
| 187 | } | ||
| 188 | |||
| 189 | void __init toshiba_rbtx4927_pci_irq_init(void) | ||
| 190 | { | ||
| 191 | return; | ||
| 192 | } | ||
| 193 | |||
| 194 | void tx4927_reset_pci_pcic(void) | ||
| 195 | { | ||
| 196 | /* Reset PCI Bus */ | ||
| 197 | *tx4927_pcireset_ptr = 1; | ||
| 198 | /* Reset PCIC */ | ||
| 199 | tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST; | ||
| 200 | udelay(10000); | ||
| 201 | /* clear PCIC reset */ | ||
| 202 | tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST; | ||
| 203 | *tx4927_pcireset_ptr = 0; | ||
| 204 | } | ||
| 205 | #endif /* CONFIG_PCI */ | ||
| 206 | |||
| 207 | #ifdef CONFIG_PCI | ||
| 208 | void print_pci_status(void) | ||
| 209 | { | ||
| 210 | printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus); | ||
| 211 | printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus); | ||
| 212 | } | ||
| 213 | |||
| 214 | extern struct pci_controller tx4927_controller; | 162 | extern struct pci_controller tx4927_controller; |
| 215 | 163 | ||
| 216 | static struct pci_dev *fake_pci_dev(struct pci_controller *hose, | 164 | static struct pci_dev *fake_pci_dev(struct pci_controller *hose, |
| @@ -239,10 +187,8 @@ static int early_##rw##_config_##size(struct pci_controller *hose, \ | |||
| 239 | } | 187 | } |
| 240 | 188 | ||
| 241 | EARLY_PCI_OP(read, byte, u8 *) | 189 | EARLY_PCI_OP(read, byte, u8 *) |
| 242 | EARLY_PCI_OP(read, word, u16 *) | ||
| 243 | EARLY_PCI_OP(read, dword, u32 *) | 190 | EARLY_PCI_OP(read, dword, u32 *) |
| 244 | EARLY_PCI_OP(write, byte, u8) | 191 | EARLY_PCI_OP(write, byte, u8) |
| 245 | EARLY_PCI_OP(write, word, u16) | ||
| 246 | EARLY_PCI_OP(write, dword, u32) | 192 | EARLY_PCI_OP(write, dword, u32) |
| 247 | 193 | ||
| 248 | static int __init tx4927_pcibios_init(void) | 194 | static int __init tx4927_pcibios_init(void) |
| @@ -269,7 +215,9 @@ static int __init tx4927_pcibios_init(void) | |||
| 269 | u8 v08_64; | 215 | u8 v08_64; |
| 270 | u32 v32_b0; | 216 | u32 v32_b0; |
| 271 | u8 v08_e1; | 217 | u8 v08_e1; |
| 218 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG | ||
| 272 | char *s = " sb/isa --"; | 219 | char *s = " sb/isa --"; |
| 220 | #endif | ||
| 273 | 221 | ||
| 274 | TOSHIBA_RBTX4927_SETUP_DPRINTK | 222 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 275 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", | 223 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", |
| @@ -354,7 +302,9 @@ static int __init tx4927_pcibios_init(void) | |||
| 354 | u8 v08_41; | 302 | u8 v08_41; |
| 355 | u8 v08_43; | 303 | u8 v08_43; |
| 356 | u8 v08_5c; | 304 | u8 v08_5c; |
| 305 | #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG | ||
| 357 | char *s = " sb/ide --"; | 306 | char *s = " sb/ide --"; |
| 307 | #endif | ||
| 358 | 308 | ||
| 359 | TOSHIBA_RBTX4927_SETUP_DPRINTK | 309 | TOSHIBA_RBTX4927_SETUP_DPRINTK |
| 360 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", | 310 | (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", |
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index 6ed39a5aea72..f9ad482749e4 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c | |||
| @@ -657,7 +657,7 @@ void __init tx4938_board_setup(void) | |||
| 657 | 657 | ||
| 658 | /* clocks */ | 658 | /* clocks */ |
| 659 | if (txx9_master_clock) { | 659 | if (txx9_master_clock) { |
| 660 | /* calculate gbus_clock and cpu_clock from master_clock */ | 660 | /* calculate gbus_clock and cpu_clock_freq from master_clock */ |
| 661 | divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; | 661 | divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; |
| 662 | switch (divmode) { | 662 | switch (divmode) { |
| 663 | case TX4938_CCFG_DIVMODE_8: | 663 | case TX4938_CCFG_DIVMODE_8: |
| @@ -691,7 +691,7 @@ void __init tx4938_board_setup(void) | |||
| 691 | if (txx9_cpu_clock == 0) { | 691 | if (txx9_cpu_clock == 0) { |
| 692 | txx9_cpu_clock = 300000000; /* 300MHz */ | 692 | txx9_cpu_clock = 300000000; /* 300MHz */ |
| 693 | } | 693 | } |
| 694 | /* calculate gbus_clock and master_clock from cpu_clock */ | 694 | /* calculate gbus_clock and master_clock from cpu_clock_freq */ |
| 695 | cpuclk = txx9_cpu_clock; | 695 | cpuclk = txx9_cpu_clock; |
| 696 | divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; | 696 | divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; |
| 697 | switch (divmode) { | 697 | switch (divmode) { |
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile index d0d84ec8d63d..7d5d83b8c582 100644 --- a/arch/mips/vr41xx/common/Makefile +++ b/arch/mips/vr41xx/common/Makefile | |||
| @@ -3,3 +3,5 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o | 5 | obj-y += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o |
| 6 | |||
| 7 | EXTRA_CFLAGS += -Werror | ||
diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c index ab4b2d9b5327..f1c3d6cebd58 100644 --- a/drivers/input/evdev.c +++ b/drivers/input/evdev.c | |||
| @@ -186,7 +186,7 @@ struct input_event_compat { | |||
| 186 | #elif defined(CONFIG_S390) | 186 | #elif defined(CONFIG_S390) |
| 187 | # define COMPAT_TEST test_thread_flag(TIF_31BIT) | 187 | # define COMPAT_TEST test_thread_flag(TIF_31BIT) |
| 188 | #elif defined(CONFIG_MIPS) | 188 | #elif defined(CONFIG_MIPS) |
| 189 | # define COMPAT_TEST (current->thread.mflags & MF_32BIT_ADDR) | 189 | # define COMPAT_TEST test_thread_flag(TIF_32BIT_ADDR) |
| 190 | #else | 190 | #else |
| 191 | # define COMPAT_TEST test_thread_flag(TIF_32BIT) | 191 | # define COMPAT_TEST test_thread_flag(TIF_32BIT) |
| 192 | #endif | 192 | #endif |
diff --git a/drivers/mtd/devices/docprobe.c b/drivers/mtd/devices/docprobe.c index b96ac8e119dc..54aa75907640 100644 --- a/drivers/mtd/devices/docprobe.c +++ b/drivers/mtd/devices/docprobe.c | |||
| @@ -81,9 +81,6 @@ static unsigned long __initdata doc_locations[] = { | |||
| 81 | #endif /* CONFIG_MTD_DOCPROBE_HIGH */ | 81 | #endif /* CONFIG_MTD_DOCPROBE_HIGH */ |
| 82 | #elif defined(__PPC__) | 82 | #elif defined(__PPC__) |
| 83 | 0xe4000000, | 83 | 0xe4000000, |
| 84 | #elif defined(CONFIG_MOMENCO_OCELOT) | ||
| 85 | 0x2f000000, | ||
| 86 | 0xff000000, | ||
| 87 | #elif defined(CONFIG_MOMENCO_OCELOT_G) | 84 | #elif defined(CONFIG_MOMENCO_OCELOT_G) |
| 88 | 0xff000000, | 85 | 0xff000000, |
| 89 | ##else | 86 | ##else |
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c index 17c868034aad..e96259f22cca 100644 --- a/drivers/mtd/nand/diskonchip.c +++ b/drivers/mtd/nand/diskonchip.c | |||
| @@ -56,9 +56,6 @@ static unsigned long __initdata doc_locations[] = { | |||
| 56 | #endif /* CONFIG_MTD_DOCPROBE_HIGH */ | 56 | #endif /* CONFIG_MTD_DOCPROBE_HIGH */ |
| 57 | #elif defined(__PPC__) | 57 | #elif defined(__PPC__) |
| 58 | 0xe4000000, | 58 | 0xe4000000, |
| 59 | #elif defined(CONFIG_MOMENCO_OCELOT) | ||
| 60 | 0x2f000000, | ||
| 61 | 0xff000000, | ||
| 62 | #elif defined(CONFIG_MOMENCO_OCELOT_G) | 59 | #elif defined(CONFIG_MOMENCO_OCELOT_G) |
| 63 | 0xff000000, | 60 | 0xff000000, |
| 64 | #else | 61 | #else |
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h index 1ad60ba186d0..bf55a5b34bef 100644 --- a/include/asm-mips/a.out.h +++ b/include/asm-mips/a.out.h | |||
| @@ -38,7 +38,8 @@ struct exec | |||
| 38 | #define STACK_TOP TASK_SIZE | 38 | #define STACK_TOP TASK_SIZE |
| 39 | #endif | 39 | #endif |
| 40 | #ifdef CONFIG_64BIT | 40 | #ifdef CONFIG_64BIT |
| 41 | #define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE) | 41 | #define STACK_TOP \ |
| 42 | (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) | ||
| 42 | #endif | 43 | #endif |
| 43 | #define STACK_TOP_MAX TASK_SIZE | 44 | #define STACK_TOP_MAX TASK_SIZE |
| 44 | 45 | ||
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 087126a5faf9..c0f052b37b9e 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h | |||
| @@ -86,16 +86,6 @@ | |||
| 86 | #define MACH_COBALT_27 0 /* Proto "27" hardware */ | 86 | #define MACH_COBALT_27 0 /* Proto "27" hardware */ |
| 87 | 87 | ||
| 88 | /* | 88 | /* |
| 89 | * Valid machtype for group NEC DDB | ||
| 90 | */ | ||
| 91 | #define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ | ||
| 92 | #define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ | ||
| 93 | #define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ | ||
| 94 | #define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ | ||
| 95 | #define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */ | ||
| 96 | #define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */ | ||
| 97 | |||
| 98 | /* | ||
| 99 | * Valid machtype for group BAGET | 89 | * Valid machtype for group BAGET |
| 100 | */ | 90 | */ |
| 101 | #define MACH_GROUP_BAGET 9 /* Baget */ | 91 | #define MACH_GROUP_BAGET 9 /* Baget */ |
| @@ -145,9 +135,6 @@ | |||
| 145 | #define MACH_TOSHIBA_RBTX4937 5 | 135 | #define MACH_TOSHIBA_RBTX4937 5 |
| 146 | #define MACH_TOSHIBA_RBTX4938 6 | 136 | #define MACH_TOSHIBA_RBTX4938 6 |
| 147 | 137 | ||
| 148 | #define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ | ||
| 149 | "RBTX4927", "RBTX4937" } | ||
| 150 | |||
| 151 | /* | 138 | /* |
| 152 | * Valid machtype for group Alchemy | 139 | * Valid machtype for group Alchemy |
| 153 | */ | 140 | */ |
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h deleted file mode 100644 index 6cf177caf6d5..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ /dev/null | |||
| @@ -1,342 +0,0 @@ | |||
| 1 | /*********************************************************************** | ||
| 2 | * | ||
| 3 | * Copyright 2001 MontaVista Software Inc. | ||
| 4 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 5 | * | ||
| 6 | * include/asm-mips/ddb5xxx/ddb5477.h | ||
| 7 | * DDB 5477 specific definitions and macros. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify it | ||
| 10 | * under the terms of the GNU General Public License as published by the | ||
| 11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 12 | * option) any later version. | ||
| 13 | * | ||
| 14 | *********************************************************************** | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ASM_DDB5XXX_DDB5477_H | ||
| 18 | #define __ASM_DDB5XXX_DDB5477_H | ||
| 19 | |||
| 20 | #include <irq.h> | ||
| 21 | |||
| 22 | /* | ||
| 23 | * This contains macros that are specific to DDB5477 or renamed from | ||
| 24 | * DDB5476. | ||
| 25 | */ | ||
| 26 | |||
| 27 | /* | ||
| 28 | * renamed PADRs | ||
| 29 | */ | ||
| 30 | #define DDB_LCS0 DDB_DCS2 | ||
| 31 | #define DDB_LCS1 DDB_DCS3 | ||
| 32 | #define DDB_LCS2 DDB_DCS4 | ||
| 33 | #define DDB_VRC5477 DDB_INTCS | ||
| 34 | |||
| 35 | /* | ||
| 36 | * New CPU interface registers | ||
| 37 | */ | ||
| 38 | #define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */ | ||
| 39 | #define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */ | ||
| 40 | #define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */ | ||
| 41 | #define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */ | ||
| 42 | |||
| 43 | #define DDB_INT0STAT 0x0420 /* INT0 Status [R] */ | ||
| 44 | #define DDB_INT1STAT 0x0428 /* INT1 Status [R] */ | ||
| 45 | #define DDB_INT2STAT 0x0430 /* INT2 Status [R] */ | ||
| 46 | #define DDB_INT3STAT 0x0438 /* INT3 Status [R] */ | ||
| 47 | #define DDB_INT4STAT 0x0440 /* INT4 Status [R] */ | ||
| 48 | #define DDB_NMISTAT 0x0450 /* NMI Status [R] */ | ||
| 49 | |||
| 50 | #define DDB_INTCLR32 0x0468 /* Interrupt Clear */ | ||
| 51 | |||
| 52 | #define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */ | ||
| 53 | #define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */ | ||
| 54 | |||
| 55 | #undef DDB_CPUSTAT /* duplicate in Vrc-5477 */ | ||
| 56 | #define DDB_CPUSTAT 0x0480 /* CPU Status [R] */ | ||
| 57 | #define DDB_BUSCTRL 0x0488 /* Internal Bus Control */ | ||
| 58 | |||
| 59 | |||
| 60 | /* | ||
| 61 | * Timer registers | ||
| 62 | */ | ||
| 63 | #define DDB_REFCTRL_L DDB_T0CTRL | ||
| 64 | #define DDB_REFCTRL_H (DDB_T0CTRL+4) | ||
| 65 | #define DDB_REFCNTR DDB_T0CNTR | ||
| 66 | #define DDB_SPT0CTRL_L DDB_T1CTRL | ||
| 67 | #define DDB_SPT0CTRL_H (DDB_T1CTRL+4) | ||
| 68 | #define DDB_SPT1CTRL_L DDB_T2CTRL | ||
| 69 | #define DDB_SPT1CTRL_H (DDB_T2CTRL+4) | ||
| 70 | #define DDB_SPT1CNTR DDB_T1CTRL | ||
| 71 | #define DDB_WDTCTRL_L DDB_T3CTRL | ||
| 72 | #define DDB_WDTCTRL_H (DDB_T3CTRL+4) | ||
| 73 | #define DDB_WDTCNTR DDB_T3CNTR | ||
| 74 | |||
| 75 | /* | ||
| 76 | * DMA registers are moved. We don't care about it for now. TODO. | ||
| 77 | */ | ||
| 78 | |||
| 79 | /* | ||
| 80 | * BARs for ext PCI (PCI0) | ||
| 81 | */ | ||
| 82 | #undef DDB_BARC | ||
| 83 | #undef DDB_BARB | ||
| 84 | |||
| 85 | #define DDB_BARC0 0x0210 /* PCI0 Control */ | ||
| 86 | #define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */ | ||
| 87 | #define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */ | ||
| 88 | #define DDB_BAR00 0x0240 /* PCI0 LDCS0 */ | ||
| 89 | #define DDB_BAR10 0x0248 /* PCI0 LDCS1 */ | ||
| 90 | #define DDB_BAR20 0x0250 /* PCI0 LDCS2 */ | ||
| 91 | #define DDB_BAR30 0x0258 /* PCI0 LDCS3 */ | ||
| 92 | #define DDB_BAR40 0x0260 /* PCI0 LDCS4 */ | ||
| 93 | #define DDB_BAR50 0x0268 /* PCI0 LDCS5 */ | ||
| 94 | #define DDB_BARB0 0x0280 /* PCI0 BOOT */ | ||
| 95 | #define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */ | ||
| 96 | #define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */ | ||
| 97 | |||
| 98 | /* | ||
| 99 | * BARs for IOPIC (PCI1) | ||
| 100 | */ | ||
| 101 | #define DDB_BARC1 0x0610 /* PCI1 Control */ | ||
| 102 | #define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */ | ||
| 103 | #define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */ | ||
| 104 | #define DDB_BAR01 0x0640 /* PCI1 LDCS0 */ | ||
| 105 | #define DDB_BAR11 0x0648 /* PCI1 LDCS1 */ | ||
| 106 | #define DDB_BAR21 0x0650 /* PCI1 LDCS2 */ | ||
| 107 | #define DDB_BAR31 0x0658 /* PCI1 LDCS3 */ | ||
| 108 | #define DDB_BAR41 0x0660 /* PCI1 LDCS4 */ | ||
| 109 | #define DDB_BAR51 0x0668 /* PCI1 LDCS5 */ | ||
| 110 | #define DDB_BARB1 0x0680 /* PCI1 BOOT */ | ||
| 111 | #define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */ | ||
| 112 | #define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */ | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Other registers for ext PCI (PCI0) | ||
| 116 | */ | ||
| 117 | #define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */ | ||
| 118 | #define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */ | ||
| 119 | |||
| 120 | #define DDB_PCISWP0 0x02b0 /* PCI0 Swap */ | ||
| 121 | #define DDB_PCIERR0 0x02b8 /* PCI0 Error */ | ||
| 122 | |||
| 123 | #define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */ | ||
| 124 | #define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */ | ||
| 125 | #define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */ | ||
| 126 | #define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */ | ||
| 127 | |||
| 128 | /* | ||
| 129 | * Other registers for IOPCI (PCI1) | ||
| 130 | */ | ||
| 131 | #define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */ | ||
| 132 | #define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */ | ||
| 133 | |||
| 134 | #define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */ | ||
| 135 | #define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */ | ||
| 136 | |||
| 137 | #define DDB_PCISWP1 0x06b0 /* PCI1 Swap */ | ||
| 138 | #define DDB_PCIERR1 0x06b8 /* PCI1 Error */ | ||
| 139 | |||
| 140 | #define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */ | ||
| 141 | #define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */ | ||
| 142 | #define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */ | ||
| 143 | #define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */ | ||
| 144 | |||
| 145 | /* | ||
| 146 | * Local Bus | ||
| 147 | */ | ||
| 148 | #define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */ | ||
| 149 | #define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */ | ||
| 150 | #undef DDB_LCST2 | ||
| 151 | #define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */ | ||
| 152 | #undef DDB_LCST3 | ||
| 153 | #undef DDB_LCST4 | ||
| 154 | #undef DDB_LCST5 | ||
| 155 | #undef DDB_LCST6 | ||
| 156 | #undef DDB_LCST7 | ||
| 157 | #undef DDB_LCST8 | ||
| 158 | #define DDB_ERRADR 0x0150 /* Error Address Register */ | ||
| 159 | #define DDB_ERRCS 0x0160 | ||
| 160 | #define DDB_BTM 0x0170 /* Boot Time Mode value */ | ||
| 161 | |||
| 162 | /* | ||
| 163 | * MISC registers | ||
| 164 | */ | ||
| 165 | #define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */ | ||
| 166 | #define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */ | ||
| 167 | |||
| 168 | /* | ||
| 169 | * Memory map (physical address) | ||
| 170 | * | ||
| 171 | * Note most of the following address must be properly aligned by the | ||
| 172 | * corresponding size. For example, if PCI_IO_SIZE is 16MB, then | ||
| 173 | * PCI_IO_BASE must be aligned along 16MB boundary. | ||
| 174 | */ | ||
| 175 | |||
| 176 | /* the actual ram size is detected at run-time */ | ||
| 177 | #define DDB_SDRAM_BASE 0x00000000 | ||
| 178 | #define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */ | ||
| 179 | |||
| 180 | #define DDB_PCI0_MEM_BASE 0x08000000 | ||
| 181 | #define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */ | ||
| 182 | |||
| 183 | #define DDB_PCI1_MEM_BASE 0x10000000 | ||
| 184 | #define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */ | ||
| 185 | |||
| 186 | #define DDB_PCI0_CONFIG_BASE 0x18000000 | ||
| 187 | #define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */ | ||
| 188 | |||
| 189 | #define DDB_PCI1_CONFIG_BASE 0x19000000 | ||
| 190 | #define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */ | ||
| 191 | |||
| 192 | #define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */ | ||
| 193 | #define DDB_PCI0_IO_BASE 0x1a000000 | ||
| 194 | #define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */ | ||
| 195 | #define DDB_PCI1_IO_BASE 0x1b000000 | ||
| 196 | #define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */ | ||
| 197 | |||
| 198 | #define DDB_LCS0_BASE 0x1c000000 /* flash memory */ | ||
| 199 | #define DDB_LCS0_SIZE 0x01000000 /* 16 MB */ | ||
| 200 | |||
| 201 | #define DDB_LCS1_BASE 0x1d000000 /* misc */ | ||
| 202 | #define DDB_LCS1_SIZE 0x01000000 /* 16 MB */ | ||
| 203 | |||
| 204 | #define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */ | ||
| 205 | #define DDB_LCS2_SIZE 0x01000000 /* 16 MB */ | ||
| 206 | |||
| 207 | #define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */ | ||
| 208 | #define DDB_VRC5477_SIZE 0x00200000 /* 2MB */ | ||
| 209 | |||
| 210 | #define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */ | ||
| 211 | #define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */ | ||
| 212 | |||
| 213 | #define DDB_LED DDB_LCS1_BASE + 0x10000 | ||
| 214 | |||
| 215 | |||
| 216 | /* | ||
| 217 | * DDB5477 specific functions | ||
| 218 | */ | ||
| 219 | #ifndef __ASSEMBLY__ | ||
| 220 | extern void ddb5477_irq_setup(void); | ||
| 221 | |||
| 222 | /* route irq to cpu int pin */ | ||
| 223 | extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip); | ||
| 224 | |||
| 225 | /* low-level routine for enabling vrc5477 irq, bypassing high-level */ | ||
| 226 | extern void ll_vrc5477_irq_enable(int vrc5477_irq); | ||
| 227 | extern void ll_vrc5477_irq_disable(int vrc5477_irq); | ||
| 228 | #endif /* !__ASSEMBLY__ */ | ||
| 229 | |||
| 230 | /* PCI intr ack share PCIW0 with PCI IO */ | ||
| 231 | #define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE | ||
| 232 | |||
| 233 | /* | ||
| 234 | * Interrupt mapping | ||
| 235 | * | ||
| 236 | * We have three interrupt controllers: | ||
| 237 | * | ||
| 238 | * . CPU itself - 8 sources | ||
| 239 | * . i8259 - 16 sources | ||
| 240 | * . vrc5477 - 32 sources | ||
| 241 | * | ||
| 242 | * They connected as follows: | ||
| 243 | * all vrc5477 interrupts are routed to cpu IP2 (by software setting) | ||
| 244 | * all i8359 are routed to INTC in vrc5477 (by hardware connection) | ||
| 245 | * | ||
| 246 | * All VRC5477 PCI interrupts are level-triggered (no ack needed). | ||
| 247 | * All PCI irq but INTC are active low. | ||
| 248 | */ | ||
| 249 | |||
| 250 | /* | ||
| 251 | * irq number block assignment | ||
| 252 | */ | ||
| 253 | |||
| 254 | #define NUM_CPU_IRQ 8 | ||
| 255 | #define NUM_VRC5477_IRQ 32 | ||
| 256 | |||
| 257 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE | ||
| 258 | #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) | ||
| 259 | |||
| 260 | /* | ||
| 261 | * vrc5477 irq defs | ||
| 262 | */ | ||
| 263 | |||
| 264 | #define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */ | ||
| 265 | #define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */ | ||
| 266 | #define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */ | ||
| 267 | #define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */ | ||
| 268 | #define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE) | ||
| 269 | #define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */ | ||
| 270 | #define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */ | ||
| 271 | #define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */ | ||
| 272 | #define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */ | ||
| 273 | #define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */ | ||
| 274 | #define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */ | ||
| 275 | #define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */ | ||
| 276 | #define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */ | ||
| 277 | #define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */ | ||
| 278 | #define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */ | ||
| 279 | #define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */ | ||
| 280 | #define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */ | ||
| 281 | #define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */ | ||
| 282 | #define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */ | ||
| 283 | #define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */ | ||
| 284 | #define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE) | ||
| 285 | #define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */ | ||
| 286 | #define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */ | ||
| 287 | #define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */ | ||
| 288 | #define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */ | ||
| 289 | #define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */ | ||
| 290 | #define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE) | ||
| 291 | #define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE) | ||
| 292 | #define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE) | ||
| 293 | #define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */ | ||
| 294 | #define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */ | ||
| 295 | #define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE) | ||
| 296 | |||
| 297 | /* | ||
| 298 | * i2859 irq assignment | ||
| 299 | */ | ||
| 300 | #define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE) | ||
| 301 | #define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */ | ||
| 302 | #define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE) | ||
| 303 | #define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ | ||
| 304 | #define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */ | ||
| 305 | #define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */ | ||
| 306 | #define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE) | ||
| 307 | #define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE) | ||
| 308 | #define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */ | ||
| 309 | #define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */ | ||
| 310 | #define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */ | ||
| 311 | #define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE) | ||
| 312 | #define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */ | ||
| 313 | #define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE) | ||
| 314 | #define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */ | ||
| 315 | #define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */ | ||
| 316 | |||
| 317 | |||
| 318 | /* | ||
| 319 | * misc | ||
| 320 | */ | ||
| 321 | #define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE) | ||
| 322 | #define CPU_VRC5477_CASCADE 2 | ||
| 323 | |||
| 324 | /* | ||
| 325 | * debug routines | ||
| 326 | */ | ||
| 327 | #ifndef __ASSEMBLY__ | ||
| 328 | #if defined(CONFIG_RUNTIME_DEBUG) | ||
| 329 | extern void vrc5477_show_pdar_regs(void); | ||
| 330 | extern void vrc5477_show_pci_regs(void); | ||
| 331 | extern void vrc5477_show_bar_regs(void); | ||
| 332 | extern void vrc5477_show_int_regs(void); | ||
| 333 | extern void vrc5477_show_all_regs(void); | ||
| 334 | #endif | ||
| 335 | |||
| 336 | /* | ||
| 337 | * RAM size | ||
| 338 | */ | ||
| 339 | extern int board_ram_size; | ||
| 340 | #endif /* !__ASSEMBLY__ */ | ||
| 341 | |||
| 342 | #endif /* __ASM_DDB5XXX_DDB5477_H */ | ||
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h deleted file mode 100644 index e97fcc8d548b..000000000000 --- a/include/asm-mips/ddb5xxx/ddb5xxx.h +++ /dev/null | |||
| @@ -1,263 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2001 MontaVista Software Inc. | ||
| 3 | * Author: jsun@mvista.com or jsun@junsun.net | ||
| 4 | * | ||
| 5 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
| 6 | * Sony Software Development Center Europe (SDCE), Brussels | ||
| 7 | * | ||
| 8 | * include/asm-mips/ddb5xxx/ddb5xxx.h | ||
| 9 | * Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477. | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify it | ||
| 12 | * under the terms of the GNU General Public License as published by the | ||
| 13 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 14 | * option) any later version. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ASM_DDB5XXX_DDB5XXX_H | ||
| 19 | #define __ASM_DDB5XXX_DDB5XXX_H | ||
| 20 | |||
| 21 | #include <linux/types.h> | ||
| 22 | |||
| 23 | /* | ||
| 24 | * This file is based on the following documentation: | ||
| 25 | * | ||
| 26 | * NEC Vrc 5074 System Controller Data Sheet, June 1998 | ||
| 27 | * | ||
| 28 | * [jsun] It is modified so that this file only contains the macros | ||
| 29 | * that are true for all DDB 5xxx boards. The modification is based on | ||
| 30 | * | ||
| 31 | * uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke) | ||
| 32 | * Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000 | ||
| 33 | * | ||
| 34 | */ | ||
| 35 | |||
| 36 | |||
| 37 | #define DDB_BASE 0xbfa00000 | ||
| 38 | #define DDB_SIZE 0x00200000 /* 2 MB */ | ||
| 39 | |||
| 40 | |||
| 41 | /* | ||
| 42 | * Physical Device Address Registers (PDARs) | ||
| 43 | */ | ||
| 44 | |||
| 45 | #define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ | ||
| 46 | #define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ | ||
| 47 | #define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ | ||
| 48 | #define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ | ||
| 49 | #define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ | ||
| 50 | #define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ | ||
| 51 | #define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ | ||
| 52 | #define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ | ||
| 53 | #define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ | ||
| 54 | #define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ | ||
| 55 | #define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ | ||
| 56 | #define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */ | ||
| 57 | /* [R/W] */ | ||
| 58 | #define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ | ||
| 59 | /* Vrc5477 has two more, IOPCIW0, IOPCIW1 */ | ||
| 60 | |||
| 61 | /* | ||
| 62 | * CPU Interface Registers | ||
| 63 | */ | ||
| 64 | #define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */ | ||
| 65 | #define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */ | ||
| 66 | #define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ | ||
| 67 | #define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ | ||
| 68 | /* Enable [R/W] */ | ||
| 69 | #define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ | ||
| 70 | #define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ | ||
| 71 | |||
| 72 | |||
| 73 | /* | ||
| 74 | * Memory-Interface Registers | ||
| 75 | */ | ||
| 76 | #define DDB_MEMCTRL 0x00C0 /* Memory Control */ | ||
| 77 | #define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ | ||
| 78 | #define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */ | ||
| 79 | |||
| 80 | |||
| 81 | /* | ||
| 82 | * PCI-Bus Registers | ||
| 83 | */ | ||
| 84 | #define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */ | ||
| 85 | #define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ | ||
| 86 | #define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ | ||
| 87 | #define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ | ||
| 88 | #define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */ | ||
| 89 | |||
| 90 | |||
| 91 | /* | ||
| 92 | * Local-Bus Registers | ||
| 93 | */ | ||
| 94 | #define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ | ||
| 95 | #define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ | ||
| 96 | #define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ | ||
| 97 | #define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ | ||
| 98 | #define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ | ||
| 99 | #define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ | ||
| 100 | #define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ | ||
| 101 | #define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ | ||
| 102 | #define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ | ||
| 103 | /* Enables [R/W] */ | ||
| 104 | #define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ | ||
| 105 | #define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ | ||
| 106 | |||
| 107 | |||
| 108 | /* | ||
| 109 | * DMA Registers | ||
| 110 | */ | ||
| 111 | #define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ | ||
| 112 | #define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ | ||
| 113 | #define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ | ||
| 114 | #define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ | ||
| 115 | #define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ | ||
| 116 | #define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ | ||
| 117 | |||
| 118 | |||
| 119 | /* | ||
| 120 | * Timer Registers | ||
| 121 | */ | ||
| 122 | #define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ | ||
| 123 | #define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ | ||
| 124 | #define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ | ||
| 125 | #define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ | ||
| 126 | #define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ | ||
| 127 | #define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ | ||
| 128 | #define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ | ||
| 129 | #define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ | ||
| 130 | |||
| 131 | |||
| 132 | /* | ||
| 133 | * PCI Configuration Space Registers | ||
| 134 | */ | ||
| 135 | #define DDB_PCI_BASE 0x0200 | ||
| 136 | |||
| 137 | #define DDB_VID 0x0200 /* PCI Vendor ID [R] */ | ||
| 138 | #define DDB_DID 0x0202 /* PCI Device ID [R] */ | ||
| 139 | #define DDB_PCICMD 0x0204 /* PCI Command [R/W] */ | ||
| 140 | #define DDB_PCISTS 0x0206 /* PCI Status [R/W] */ | ||
| 141 | #define DDB_REVID 0x0208 /* PCI Revision ID [R] */ | ||
| 142 | #define DDB_CLASS 0x0209 /* PCI Class Code [R] */ | ||
| 143 | #define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ | ||
| 144 | #define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */ | ||
| 145 | #define DDB_HTYPE 0x020E /* PCI Header Type [R] */ | ||
| 146 | #define DDB_BIST 0x020F /* BIST [R] (unimplemented) */ | ||
| 147 | #define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ | ||
| 148 | #define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ | ||
| 149 | #define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ | ||
| 150 | #define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ | ||
| 151 | /* (unimplemented) */ | ||
| 152 | #define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ | ||
| 153 | #define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */ | ||
| 154 | #define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */ | ||
| 155 | /* (unimplemented) */ | ||
| 156 | #define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ | ||
| 157 | #define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */ | ||
| 158 | #define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ | ||
| 159 | #define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ | ||
| 160 | #define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ | ||
| 161 | #define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ | ||
| 162 | #define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ | ||
| 163 | #define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ | ||
| 164 | #define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ | ||
| 165 | #define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ | ||
| 166 | #define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ | ||
| 167 | #define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ | ||
| 168 | |||
| 169 | |||
| 170 | /* | ||
| 171 | * Nile 4 Register Access | ||
| 172 | */ | ||
| 173 | |||
| 174 | static inline void ddb_sync(void) | ||
| 175 | { | ||
| 176 | volatile u32 *p = (volatile u32 *)0xbfc00000; | ||
| 177 | (void)(*p); | ||
| 178 | } | ||
| 179 | |||
| 180 | static inline void ddb_out32(u32 offset, u32 val) | ||
| 181 | { | ||
| 182 | *(volatile u32 *)(DDB_BASE+offset) = val; | ||
| 183 | ddb_sync(); | ||
| 184 | } | ||
| 185 | |||
| 186 | static inline u32 ddb_in32(u32 offset) | ||
| 187 | { | ||
| 188 | u32 val = *(volatile u32 *)(DDB_BASE+offset); | ||
| 189 | ddb_sync(); | ||
| 190 | return val; | ||
| 191 | } | ||
| 192 | |||
| 193 | static inline void ddb_out16(u32 offset, u16 val) | ||
| 194 | { | ||
| 195 | *(volatile u16 *)(DDB_BASE+offset) = val; | ||
| 196 | ddb_sync(); | ||
| 197 | } | ||
| 198 | |||
| 199 | static inline u16 ddb_in16(u32 offset) | ||
| 200 | { | ||
| 201 | u16 val = *(volatile u16 *)(DDB_BASE+offset); | ||
| 202 | ddb_sync(); | ||
| 203 | return val; | ||
| 204 | } | ||
| 205 | |||
| 206 | static inline void ddb_out8(u32 offset, u8 val) | ||
| 207 | { | ||
| 208 | *(volatile u8 *)(DDB_BASE+offset) = val; | ||
| 209 | ddb_sync(); | ||
| 210 | } | ||
| 211 | |||
| 212 | static inline u8 ddb_in8(u32 offset) | ||
| 213 | { | ||
| 214 | u8 val = *(volatile u8 *)(DDB_BASE+offset); | ||
| 215 | ddb_sync(); | ||
| 216 | return val; | ||
| 217 | } | ||
| 218 | |||
| 219 | |||
| 220 | /* | ||
| 221 | * Physical Device Address Registers | ||
| 222 | */ | ||
| 223 | |||
| 224 | extern u32 | ||
| 225 | ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible); | ||
| 226 | extern void | ||
| 227 | ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width, | ||
| 228 | int on_memory_bus, int pci_visible); | ||
| 229 | |||
| 230 | /* | ||
| 231 | * PCI Master Registers | ||
| 232 | */ | ||
| 233 | |||
| 234 | #define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ | ||
| 235 | #define DDB_PCICMD_IO 1 /* PCI I/O Space */ | ||
| 236 | #define DDB_PCICMD_MEM 3 /* PCI Memory Space */ | ||
| 237 | #define DDB_PCICMD_CFG 5 /* PCI Configuration Space */ | ||
| 238 | |||
| 239 | /* | ||
| 240 | * additional options for pci init reg (no shifting needed) | ||
| 241 | */ | ||
| 242 | #define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */ | ||
| 243 | #define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */ | ||
| 244 | |||
| 245 | |||
| 246 | extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options); | ||
| 247 | |||
| 248 | /* | ||
| 249 | * we need to reset pci bus when we start up and shutdown | ||
| 250 | */ | ||
| 251 | extern void ddb_pci_reset_bus(void); | ||
| 252 | |||
| 253 | |||
| 254 | /* | ||
| 255 | * include the board dependent part | ||
| 256 | */ | ||
| 257 | #if defined(CONFIG_DDB5477) | ||
| 258 | #include <asm/ddb5xxx/ddb5477.h> | ||
| 259 | #else | ||
| 260 | #error "Unknown DDB board!" | ||
| 261 | #endif | ||
| 262 | |||
| 263 | #endif /* __ASM_DDB5XXX_DDB5XXX_H */ | ||
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index ebd6bfb19d66..e7d95d48177d 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h | |||
| @@ -265,7 +265,7 @@ do { \ | |||
| 265 | #ifdef CONFIG_MIPS32_N32 | 265 | #ifdef CONFIG_MIPS32_N32 |
| 266 | #define __SET_PERSONALITY32_N32() \ | 266 | #define __SET_PERSONALITY32_N32() \ |
| 267 | do { \ | 267 | do { \ |
| 268 | current->thread.mflags |= MF_N32; \ | 268 | set_thread_flag(TIF_32BIT_ADDR); \ |
| 269 | current->thread.abi = &mips_abi_n32; \ | 269 | current->thread.abi = &mips_abi_n32; \ |
| 270 | } while (0) | 270 | } while (0) |
| 271 | #else | 271 | #else |
| @@ -276,7 +276,8 @@ do { \ | |||
| 276 | #ifdef CONFIG_MIPS32_O32 | 276 | #ifdef CONFIG_MIPS32_O32 |
| 277 | #define __SET_PERSONALITY32_O32() \ | 277 | #define __SET_PERSONALITY32_O32() \ |
| 278 | do { \ | 278 | do { \ |
| 279 | current->thread.mflags |= MF_O32; \ | 279 | set_thread_flag(TIF_32BIT_REGS); \ |
| 280 | set_thread_flag(TIF_32BIT_ADDR); \ | ||
| 280 | current->thread.abi = &mips_abi_32; \ | 281 | current->thread.abi = &mips_abi_32; \ |
| 281 | } while (0) | 282 | } while (0) |
| 282 | #else | 283 | #else |
| @@ -299,13 +300,13 @@ do { \ | |||
| 299 | 300 | ||
| 300 | #define SET_PERSONALITY(ex, ibcs2) \ | 301 | #define SET_PERSONALITY(ex, ibcs2) \ |
| 301 | do { \ | 302 | do { \ |
| 302 | current->thread.mflags &= ~MF_ABI_MASK; \ | 303 | clear_thread_flag(TIF_32BIT_REGS); \ |
| 304 | clear_thread_flag(TIF_32BIT_ADDR); \ | ||
| 305 | \ | ||
| 303 | if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ | 306 | if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ |
| 304 | __SET_PERSONALITY32(ex); \ | 307 | __SET_PERSONALITY32(ex); \ |
| 305 | else { \ | 308 | else \ |
| 306 | current->thread.mflags |= MF_N64; \ | ||
| 307 | current->thread.abi = &mips_abi; \ | 309 | current->thread.abi = &mips_abi; \ |
| 308 | } \ | ||
| 309 | \ | 310 | \ |
| 310 | if (ibcs2) \ | 311 | if (ibcs2) \ |
| 311 | set_personality(PER_SVR4); \ | 312 | set_personality(PER_SVR4); \ |
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index d9119f43f9aa..918a4894b587 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. | 4 | * for more details. |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org> | 6 | * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org> |
| 7 | * Copyright (C) MIPS Technologies, Inc. | 7 | * Copyright (C) MIPS Technologies, Inc. |
| 8 | * written by Ralf Baechle <ralf@linux-mips.org> | 8 | * written by Ralf Baechle <ralf@linux-mips.org> |
| 9 | */ | 9 | */ |
| @@ -23,6 +23,11 @@ static inline void name(void) \ | |||
| 23 | __asm__ __volatile__ (#name); \ | 23 | __asm__ __volatile__ (#name); \ |
| 24 | } | 24 | } |
| 25 | 25 | ||
| 26 | /* | ||
| 27 | * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. | ||
| 28 | */ | ||
| 29 | extern void mips_ihb(void); | ||
| 30 | |||
| 26 | #endif | 31 | #endif |
| 27 | 32 | ||
| 28 | ASMMACRO(_ssnop, | 33 | ASMMACRO(_ssnop, |
diff --git a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h new file mode 100644 index 000000000000..275eaf92c748 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H | ||
| 2 | #define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H | ||
| 3 | |||
| 4 | #define cpu_has_llsc 1 | ||
| 5 | #define cpu_has_64bits 1 | ||
| 6 | #define cpu_has_inclusive_pcaches 0 | ||
| 7 | |||
| 8 | #define cpu_has_mips16 0 | ||
| 9 | #define cpu_has_mdmx 0 | ||
| 10 | #define cpu_has_mips3d 0 | ||
| 11 | #define cpu_has_smartmips 0 | ||
| 12 | #define cpu_has_vtag_icache 0 | ||
| 13 | #define cpu_has_ic_fills_f_dc 0 | ||
| 14 | #define cpu_has_dsp 0 | ||
| 15 | #define cpu_has_mipsmt 0 | ||
| 16 | #define cpu_has_userlocal 0 | ||
| 17 | |||
| 18 | #define cpu_has_mips32r1 0 | ||
| 19 | #define cpu_has_mips32r2 0 | ||
| 20 | #define cpu_has_mips64r1 0 | ||
| 21 | #define cpu_has_mips64r2 0 | ||
| 22 | |||
| 23 | #endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */ | ||
diff --git a/include/asm-mips/mach-tx49xx/kmalloc.h b/include/asm-mips/mach-tx49xx/kmalloc.h new file mode 100644 index 000000000000..913ff196259d --- /dev/null +++ b/include/asm-mips/mach-tx49xx/kmalloc.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef __ASM_MACH_TX49XX_KMALLOC_H | ||
| 2 | #define __ASM_MACH_TX49XX_KMALLOC_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * All happy, no need to define ARCH_KMALLOC_MINALIGN | ||
| 6 | */ | ||
| 7 | |||
| 8 | #endif /* __ASM_MACH_TX49XX_KMALLOC_H */ | ||
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index c8ebcc3e1267..d58977483534 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h | |||
| @@ -67,6 +67,7 @@ | |||
| 67 | #define MIPS_REVISION_CORID_CORE_FPGAR2 8 | 67 | #define MIPS_REVISION_CORID_CORE_FPGAR2 8 |
| 68 | #define MIPS_REVISION_CORID_CORE_FPGA3 9 | 68 | #define MIPS_REVISION_CORID_CORE_FPGA3 9 |
| 69 | #define MIPS_REVISION_CORID_CORE_24K 10 | 69 | #define MIPS_REVISION_CORID_CORE_24K 10 |
| 70 | #define MIPS_REVISION_CORID_CORE_FPGA4 11 | ||
| 70 | 71 | ||
| 71 | /**** Artificial corid defines ****/ | 72 | /**** Artificial corid defines ****/ |
| 72 | /* | 73 | /* |
diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h index 8045abc78d0f..ac7935203f89 100644 --- a/include/asm-mips/mips_mt.h +++ b/include/asm-mips/mips_mt.h | |||
| @@ -8,6 +8,12 @@ | |||
| 8 | 8 | ||
| 9 | #include <linux/cpumask.h> | 9 | #include <linux/cpumask.h> |
| 10 | 10 | ||
| 11 | /* | ||
| 12 | * How many VPEs and TCs is Linux allowed to use? 0 means no limit. | ||
| 13 | */ | ||
| 14 | extern int tclimit; | ||
| 15 | extern int vpelimit; | ||
| 16 | |||
| 11 | extern cpumask_t mt_fpu_cpumask; | 17 | extern cpumask_t mt_fpu_cpumask; |
| 12 | extern unsigned long mt_fpemul_threshold; | 18 | extern unsigned long mt_fpemul_threshold; |
| 13 | 19 | ||
diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h index 260f3448ccf1..6ad519189ce2 100644 --- a/include/asm-mips/pmon.h +++ b/include/asm-mips/pmon.h | |||
| @@ -22,7 +22,7 @@ struct callvectors { | |||
| 22 | char* (*gets) (char*); | 22 | char* (*gets) (char*); |
| 23 | union { | 23 | union { |
| 24 | int (*smpfork) (unsigned long cp, char *sp); | 24 | int (*smpfork) (unsigned long cp, char *sp); |
| 25 | int (*cpustart) (long, long, long, long); | 25 | int (*cpustart) (long, void (*)(void), void *, long); |
| 26 | } _s; | 26 | } _s; |
| 27 | int (*semlock) (int sem); | 27 | int (*semlock) (int sem); |
| 28 | void (*semunlock) (int sem); | 28 | void (*semunlock) (int sem); |
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 1d8b9a8ae324..83bc94534084 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h | |||
| @@ -62,8 +62,9 @@ extern unsigned int vced_count, vcei_count; | |||
| 62 | * This decides where the kernel will search for a free chunk of vm | 62 | * This decides where the kernel will search for a free chunk of vm |
| 63 | * space during mmap's. | 63 | * space during mmap's. |
| 64 | */ | 64 | */ |
| 65 | #define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \ | 65 | #define TASK_UNMAPPED_BASE \ |
| 66 | PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) | 66 | (test_thread_flag(TIF_32BIT_ADDR) ? \ |
| 67 | PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) | ||
| 67 | #endif | 68 | #endif |
| 68 | 69 | ||
| 69 | #define NUM_FPU_REGS 32 | 70 | #define NUM_FPU_REGS 32 |
| @@ -132,22 +133,11 @@ struct thread_struct { | |||
| 132 | unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ | 133 | unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ |
| 133 | unsigned long error_code; | 134 | unsigned long error_code; |
| 134 | unsigned long trap_no; | 135 | unsigned long trap_no; |
| 135 | #define MF_FIXADE 1 /* Fix address errors in software */ | ||
| 136 | #define MF_LOGADE 2 /* Log address errors to syslog */ | ||
| 137 | #define MF_32BIT_REGS 4 /* also implies 16/32 fprs */ | ||
| 138 | #define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */ | ||
| 139 | #define MF_FPUBOUND 0x10 /* thread bound to FPU-full CPU set */ | ||
| 140 | unsigned long mflags; | ||
| 141 | unsigned long irix_trampoline; /* Wheee... */ | 136 | unsigned long irix_trampoline; /* Wheee... */ |
| 142 | unsigned long irix_oldctx; | 137 | unsigned long irix_oldctx; |
| 143 | struct mips_abi *abi; | 138 | struct mips_abi *abi; |
| 144 | }; | 139 | }; |
| 145 | 140 | ||
| 146 | #define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) | ||
| 147 | #define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR) | ||
| 148 | #define MF_N32 MF_32BIT_ADDR | ||
| 149 | #define MF_N64 0 | ||
| 150 | |||
| 151 | #ifdef CONFIG_MIPS_MT_FPAFF | 141 | #ifdef CONFIG_MIPS_MT_FPAFF |
| 152 | #define FPAFF_INIT \ | 142 | #define FPAFF_INIT \ |
| 153 | .emulated_fp = 0, \ | 143 | .emulated_fp = 0, \ |
| @@ -200,10 +190,6 @@ struct thread_struct { | |||
| 200 | .cp0_baduaddr = 0, \ | 190 | .cp0_baduaddr = 0, \ |
| 201 | .error_code = 0, \ | 191 | .error_code = 0, \ |
| 202 | .trap_no = 0, \ | 192 | .trap_no = 0, \ |
| 203 | /* \ | ||
| 204 | * For now the default is to fix address errors \ | ||
| 205 | */ \ | ||
| 206 | .mflags = MF_FIXADE, \ | ||
| 207 | .irix_trampoline = 0, \ | 193 | .irix_trampoline = 0, \ |
| 208 | .irix_oldctx = 0, \ | 194 | .irix_oldctx = 0, \ |
| 209 | } | 195 | } |
diff --git a/include/asm-mips/seccomp.h b/include/asm-mips/seccomp.h new file mode 100644 index 000000000000..36ed44070256 --- /dev/null +++ b/include/asm-mips/seccomp.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | #ifndef __ASM_SECCOMP_H | ||
| 2 | |||
| 3 | #include <linux/thread_info.h> | ||
| 4 | #include <linux/unistd.h> | ||
| 5 | |||
| 6 | #define __NR_seccomp_read __NR_read | ||
| 7 | #define __NR_seccomp_write __NR_write | ||
| 8 | #define __NR_seccomp_exit __NR_exit | ||
| 9 | #define __NR_seccomp_sigreturn __NR_rt_sigreturn | ||
| 10 | |||
| 11 | /* | ||
| 12 | * Kludge alert: | ||
| 13 | * | ||
| 14 | * The generic seccomp code currently allows only a single compat ABI. Until | ||
| 15 | * this is fixed we priorize O32 as the compat ABI over N32. | ||
| 16 | */ | ||
| 17 | #ifdef CONFIG_MIPS32_O32 | ||
| 18 | |||
| 19 | #define TIF_32BIT TIF_32BIT_REGS | ||
| 20 | |||
| 21 | #define __NR_seccomp_read_32 4003 | ||
| 22 | #define __NR_seccomp_write_32 4004 | ||
| 23 | #define __NR_seccomp_exit_32 4001 | ||
| 24 | #define __NR_seccomp_sigreturn_32 4193 /* rt_sigreturn */ | ||
| 25 | |||
| 26 | #elif defined(CONFIG_MIPS32_N32) | ||
| 27 | |||
| 28 | #define TIF_32BIT _TIF_32BIT_ADDR | ||
| 29 | |||
| 30 | #define __NR_seccomp_read_32 6000 | ||
| 31 | #define __NR_seccomp_write_32 6001 | ||
| 32 | #define __NR_seccomp_exit_32 6058 | ||
| 33 | #define __NR_seccomp_sigreturn_32 6211 /* rt_sigreturn */ | ||
| 34 | |||
| 35 | #endif /* CONFIG_MIPS32_O32 */ | ||
| 36 | |||
| 37 | #endif /* __ASM_SECCOMP_H */ | ||
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 8d0b1cd4a45e..357251f42518 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h | |||
| @@ -46,10 +46,12 @@ struct task_struct; | |||
| 46 | 46 | ||
| 47 | #define __mips_mt_fpaff_switch_to(prev) \ | 47 | #define __mips_mt_fpaff_switch_to(prev) \ |
| 48 | do { \ | 48 | do { \ |
| 49 | struct thread_info *__prev_ti = task_thread_info(prev); \ | ||
| 50 | \ | ||
| 49 | if (cpu_has_fpu && \ | 51 | if (cpu_has_fpu && \ |
| 50 | (prev->thread.mflags & MF_FPUBOUND) && \ | 52 | test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \ |
| 51 | (!(KSTK_STATUS(prev) & ST0_CU1))) { \ | 53 | (!(KSTK_STATUS(prev) & ST0_CU1))) { \ |
| 52 | prev->thread.mflags &= ~MF_FPUBOUND; \ | 54 | clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \ |
| 53 | prev->cpus_allowed = prev->thread.user_cpus_allowed; \ | 55 | prev->cpus_allowed = prev->thread.user_cpus_allowed; \ |
| 54 | } \ | 56 | } \ |
| 55 | next->thread.emulated_fp = 0; \ | 57 | next->thread.emulated_fp = 0; \ |
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index 645e7e2a5665..b2772df1a1bd 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h | |||
| @@ -46,7 +46,7 @@ struct thread_info { | |||
| 46 | { \ | 46 | { \ |
| 47 | .task = &tsk, \ | 47 | .task = &tsk, \ |
| 48 | .exec_domain = &default_exec_domain, \ | 48 | .exec_domain = &default_exec_domain, \ |
| 49 | .flags = 0, \ | 49 | .flags = _TIF_FIXADE, \ |
| 50 | .cpu = 0, \ | 50 | .cpu = 0, \ |
| 51 | .preempt_count = 1, \ | 51 | .preempt_count = 1, \ |
| 52 | .addr_limit = KERNEL_DS, \ | 52 | .addr_limit = KERNEL_DS, \ |
| @@ -87,9 +87,8 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
| 87 | ({ \ | 87 | ({ \ |
| 88 | struct thread_info *ret; \ | 88 | struct thread_info *ret; \ |
| 89 | \ | 89 | \ |
| 90 | ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \ | 90 | ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ |
| 91 | if (ret) \ | 91 | \ |
| 92 | memset(ret, 0, THREAD_SIZE); \ | ||
| 93 | ret; \ | 92 | ret; \ |
| 94 | }) | 93 | }) |
| 95 | #else | 94 | #else |
| @@ -118,6 +117,11 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
| 118 | #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ | 117 | #define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ |
| 119 | #define TIF_MEMDIE 18 | 118 | #define TIF_MEMDIE 18 |
| 120 | #define TIF_FREEZE 19 | 119 | #define TIF_FREEZE 19 |
| 120 | #define TIF_FIXADE 20 /* Fix address errors in software */ | ||
| 121 | #define TIF_LOGADE 21 /* Log address errors to syslog */ | ||
| 122 | #define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ | ||
| 123 | #define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ | ||
| 124 | #define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ | ||
| 121 | #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ | 125 | #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ |
| 122 | 126 | ||
| 123 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | 127 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) |
| @@ -129,6 +133,11 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
| 129 | #define _TIF_USEDFPU (1<<TIF_USEDFPU) | 133 | #define _TIF_USEDFPU (1<<TIF_USEDFPU) |
| 130 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | 134 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) |
| 131 | #define _TIF_FREEZE (1<<TIF_FREEZE) | 135 | #define _TIF_FREEZE (1<<TIF_FREEZE) |
| 136 | #define _TIF_FIXADE (1<<TIF_FIXADE) | ||
| 137 | #define _TIF_LOGADE (1<<TIF_LOGADE) | ||
| 138 | #define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) | ||
| 139 | #define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) | ||
| 140 | #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) | ||
| 132 | 141 | ||
| 133 | /* work to do on interrupt/exception return */ | 142 | /* work to do on interrupt/exception return */ |
| 134 | #define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) | 143 | #define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP) |
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index 94bef03d9635..5dc40a867774 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h | |||
| @@ -52,4 +52,6 @@ | |||
| 52 | #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) | 52 | #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) |
| 53 | #define RBTX4927_RTL_8019_IRQ (29) | 53 | #define RBTX4927_RTL_8019_IRQ (29) |
| 54 | 54 | ||
| 55 | int toshiba_rbtx4927_irq_nested(int sw_irq); | ||
| 56 | |||
| 55 | #endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ | 57 | #endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ |
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index ed16de0a6398..fa9a587b3bf1 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h | |||
| @@ -340,16 +340,17 @@ | |||
| 340 | #define __NR_signalfd (__NR_Linux + 317) | 340 | #define __NR_signalfd (__NR_Linux + 317) |
| 341 | #define __NR_timerfd (__NR_Linux + 318) | 341 | #define __NR_timerfd (__NR_Linux + 318) |
| 342 | #define __NR_eventfd (__NR_Linux + 319) | 342 | #define __NR_eventfd (__NR_Linux + 319) |
| 343 | #define __NR_fallocate (__NR_Linux + 320) | ||
| 343 | 344 | ||
| 344 | /* | 345 | /* |
| 345 | * Offset of the last Linux o32 flavoured syscall | 346 | * Offset of the last Linux o32 flavoured syscall |
| 346 | */ | 347 | */ |
| 347 | #define __NR_Linux_syscalls 319 | 348 | #define __NR_Linux_syscalls 320 |
| 348 | 349 | ||
| 349 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ | 350 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ |
| 350 | 351 | ||
| 351 | #define __NR_O32_Linux 4000 | 352 | #define __NR_O32_Linux 4000 |
| 352 | #define __NR_O32_Linux_syscalls 319 | 353 | #define __NR_O32_Linux_syscalls 320 |
| 353 | 354 | ||
| 354 | #if _MIPS_SIM == _MIPS_SIM_ABI64 | 355 | #if _MIPS_SIM == _MIPS_SIM_ABI64 |
| 355 | 356 | ||
| @@ -636,16 +637,17 @@ | |||
| 636 | #define __NR_signalfd (__NR_Linux + 276) | 637 | #define __NR_signalfd (__NR_Linux + 276) |
| 637 | #define __NR_timerfd (__NR_Linux + 277) | 638 | #define __NR_timerfd (__NR_Linux + 277) |
| 638 | #define __NR_eventfd (__NR_Linux + 278) | 639 | #define __NR_eventfd (__NR_Linux + 278) |
| 640 | #define __NR_fallocate (__NR_Linux + 279) | ||
| 639 | 641 | ||
| 640 | /* | 642 | /* |
| 641 | * Offset of the last Linux 64-bit flavoured syscall | 643 | * Offset of the last Linux 64-bit flavoured syscall |
| 642 | */ | 644 | */ |
| 643 | #define __NR_Linux_syscalls 278 | 645 | #define __NR_Linux_syscalls 279 |
| 644 | 646 | ||
| 645 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ | 647 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ |
| 646 | 648 | ||
| 647 | #define __NR_64_Linux 5000 | 649 | #define __NR_64_Linux 5000 |
| 648 | #define __NR_64_Linux_syscalls 278 | 650 | #define __NR_64_Linux_syscalls 279 |
| 649 | 651 | ||
| 650 | #if _MIPS_SIM == _MIPS_SIM_NABI32 | 652 | #if _MIPS_SIM == _MIPS_SIM_NABI32 |
| 651 | 653 | ||
| @@ -936,16 +938,17 @@ | |||
| 936 | #define __NR_signalfd (__NR_Linux + 280) | 938 | #define __NR_signalfd (__NR_Linux + 280) |
| 937 | #define __NR_timerfd (__NR_Linux + 281) | 939 | #define __NR_timerfd (__NR_Linux + 281) |
| 938 | #define __NR_eventfd (__NR_Linux + 282) | 940 | #define __NR_eventfd (__NR_Linux + 282) |
| 941 | #define __NR_fallocate (__NR_Linux + 283) | ||
| 939 | 942 | ||
| 940 | /* | 943 | /* |
| 941 | * Offset of the last N32 flavoured syscall | 944 | * Offset of the last N32 flavoured syscall |
| 942 | */ | 945 | */ |
| 943 | #define __NR_Linux_syscalls 282 | 946 | #define __NR_Linux_syscalls 283 |
| 944 | 947 | ||
| 945 | #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ | 948 | #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ |
| 946 | 949 | ||
| 947 | #define __NR_N32_Linux 6000 | 950 | #define __NR_N32_Linux 6000 |
| 948 | #define __NR_N32_Linux_syscalls 282 | 951 | #define __NR_N32_Linux_syscalls 283 |
| 949 | 952 | ||
| 950 | #ifdef __KERNEL__ | 953 | #ifdef __KERNEL__ |
| 951 | 954 | ||
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 2883ccc69ed0..c0715d0a6b28 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
| @@ -182,9 +182,8 @@ | |||
| 182 | * exceptions. | 182 | * exceptions. |
| 183 | */ | 183 | */ |
| 184 | #if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ | 184 | #if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ |
| 185 | defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \ | 185 | defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \ |
| 186 | defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \ | 186 | defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) |
| 187 | defined(CONFIG_WR_PPMC) | ||
| 188 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | 187 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 |
| 189 | #endif | 188 | #endif |
| 190 | 189 | ||