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authorSujith <Sujith.Manoharan@atheros.com>2008-08-07 01:22:38 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-08-07 09:49:43 -0400
commit60b67f519213cf6d59236d065b0953962b56abca (patch)
tree3af58f097b3899aea9b525c563626930c4cab4b4
parentb08cbcd4546445740c2a04291204b56f8baf7be2 (diff)
ath9k: Cleanup data structures related to HW capabilities
Signed-off-by: Sujith Manoharan <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h183
-rw-r--r--drivers/net/wireless/ath9k/beacon.c10
-rw-r--r--drivers/net/wireless/ath9k/core.c58
-rw-r--r--drivers/net/wireless/ath9k/hw.c369
-rw-r--r--drivers/net/wireless/ath9k/main.c6
-rw-r--r--drivers/net/wireless/ath9k/rc.c2
-rw-r--r--drivers/net/wireless/ath9k/recv.c4
-rw-r--r--drivers/net/wireless/ath9k/regd.c14
-rw-r--r--drivers/net/wireless/ath9k/xmit.c4
9 files changed, 330 insertions, 320 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index dc1da64d2d7c..71027dcdcafc 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -147,94 +147,95 @@ struct ath_desc {
147 147
148#define ATH9K_RXDESC_INTREQ 0x0020 148#define ATH9K_RXDESC_INTREQ 0x0020
149 149
150enum hal_capability_type { 150enum ath9k_hw_caps {
151 HAL_CAP_CIPHER = 0, 151 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
152 HAL_CAP_TKIP_MIC, 152 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
153 HAL_CAP_TKIP_SPLIT, 153 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
154 HAL_CAP_PHYCOUNTERS, 154 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
155 HAL_CAP_DIVERSITY, 155 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
156 HAL_CAP_PSPOLL, 156 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
157 HAL_CAP_TXPOW, 157 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
158 HAL_CAP_PHYDIAG, 158 ATH9K_HW_CAP_VEOL = BIT(7),
159 HAL_CAP_MCAST_KEYSRCH, 159 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
160 HAL_CAP_TSF_ADJUST, 160 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
161 HAL_CAP_WME_TKIPMIC, 161 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
162 HAL_CAP_RFSILENT, 162 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
163 HAL_CAP_ANT_CFG_2GHZ, 163 ATH9K_HW_CAP_HT = BIT(12),
164 HAL_CAP_ANT_CFG_5GHZ 164 ATH9K_HW_CAP_GTT = BIT(13),
165 ATH9K_HW_CAP_FASTCC = BIT(14),
166 ATH9K_HW_CAP_RFSILENT = BIT(15),
167 ATH9K_HW_CAP_WOW = BIT(16),
168 ATH9K_HW_CAP_CST = BIT(17),
169 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
170 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
171 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
172 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
165}; 173};
166 174
167struct hal_capabilities { 175enum ath9k_capability_type {
168 u32 halChanSpreadSupport:1, 176 ATH9K_CAP_CIPHER = 0,
169 halChapTuningSupport:1, 177 ATH9K_CAP_TKIP_MIC,
170 halMicAesCcmSupport:1, 178 ATH9K_CAP_TKIP_SPLIT,
171 halMicCkipSupport:1, 179 ATH9K_CAP_PHYCOUNTERS,
172 halMicTkipSupport:1, 180 ATH9K_CAP_DIVERSITY,
173 halCipherAesCcmSupport:1, 181 ATH9K_CAP_TXPOW,
174 halCipherCkipSupport:1, 182 ATH9K_CAP_PHYDIAG,
175 halCipherTkipSupport:1, 183 ATH9K_CAP_MCAST_KEYSRCH,
176 halVEOLSupport:1, 184 ATH9K_CAP_TSF_ADJUST,
177 halBssIdMaskSupport:1, 185 ATH9K_CAP_WME_TKIPMIC,
178 halMcastKeySrchSupport:1, 186 ATH9K_CAP_RFSILENT,
179 halTsfAddSupport:1, 187 ATH9K_CAP_ANT_CFG_2GHZ,
180 halChanHalfRate:1, 188 ATH9K_CAP_ANT_CFG_5GHZ
181 halChanQuarterRate:1,
182 halHTSupport:1,
183 halGTTSupport:1,
184 halFastCCSupport:1,
185 halRfSilentSupport:1,
186 halWowSupport:1,
187 halCSTSupport:1,
188 halEnhancedPmSupport:1,
189 halAutoSleepSupport:1,
190 hal4kbSplitTransSupport:1,
191 halWowMatchPatternExact:1;
192 u32 halWirelessModes;
193 u16 halTotalQueues;
194 u16 halKeyCacheSize;
195 u16 halLow5GhzChan, halHigh5GhzChan;
196 u16 halLow2GhzChan, halHigh2GhzChan;
197 u16 halNumMRRetries;
198 u16 halRtsAggrLimit;
199 u8 halTxChainMask;
200 u8 halRxChainMask;
201 u16 halTxTrigLevelMax;
202 u16 halRegCap;
203 u8 halNumGpioPins;
204 u8 halNumAntCfg2GHz;
205 u8 halNumAntCfg5GHz;
206}; 189};
207 190
208struct hal_ops_config { 191struct ath9k_hw_capabilities {
209 int ath_hal_dma_beacon_response_time; 192 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
210 int ath_hal_sw_beacon_response_time; 193 u32 wireless_modes;
211 int ath_hal_additional_swba_backoff; 194 u16 total_queues;
212 int ath_hal_6mb_ack; 195 u16 keycache_size;
213 int ath_hal_cwmIgnoreExtCCA; 196 u16 low_5ghz_chan, high_5ghz_chan;
214 u8 ath_hal_pciePowerSaveEnable; 197 u16 low_2ghz_chan, high_2ghz_chan;
215 u8 ath_hal_pcieL1SKPEnable; 198 u16 num_mr_retries;
216 u8 ath_hal_pcieClockReq; 199 u16 rts_aggr_limit;
217 u32 ath_hal_pcieWaen; 200 u8 tx_chainmask;
218 int ath_hal_pciePowerReset; 201 u8 rx_chainmask;
219 u8 ath_hal_pcieRestore; 202 u16 tx_triglevel_max;
220 u8 ath_hal_analogShiftReg; 203 u16 reg_cap;
221 u8 ath_hal_htEnable; 204 u8 num_gpio_pins;
222 u32 ath_hal_ofdmTrigLow; 205 u8 num_antcfg_2ghz;
223 u32 ath_hal_ofdmTrigHigh; 206 u8 num_antcfg_5ghz;
224 u32 ath_hal_cckTrigHigh; 207};
225 u32 ath_hal_cckTrigLow; 208
226 u32 ath_hal_enableANI; 209struct ath9k_ops_config {
227 u8 ath_hal_noiseImmunityLvl; 210 int dma_beacon_response_time;
228 u32 ath_hal_ofdmWeakSigDet; 211 int sw_beacon_response_time;
229 u32 ath_hal_cckWeakSigThr; 212 int additional_swba_backoff;
230 u8 ath_hal_spurImmunityLvl; 213 int ack_6mb;
231 u8 ath_hal_firStepLvl; 214 int cwm_ignore_extcca;
232 int8_t ath_hal_rssiThrHigh; 215 u8 pcie_powersave_enable;
233 int8_t ath_hal_rssiThrLow; 216 u8 pcie_l1skp_enable;
234 u16 ath_hal_diversityControl; 217 u8 pcie_clock_req;
235 u16 ath_hal_antennaSwitchSwap; 218 u32 pcie_waen;
236 int ath_hal_serializeRegMode; 219 int pcie_power_reset;
237 int ath_hal_intrMitigation; 220 u8 pcie_restore;
221 u8 analog_shiftreg;
222 u8 ht_enable;
223 u32 ofdm_trig_low;
224 u32 ofdm_trig_high;
225 u32 cck_trig_high;
226 u32 cck_trig_low;
227 u32 enable_ani;
228 u8 noise_immunity_level;
229 u32 ofdm_weaksignal_det;
230 u32 cck_weaksignal_thr;
231 u8 spur_immunity_level;
232 u8 firstep_level;
233 int8_t rssi_thr_high;
234 int8_t rssi_thr_low;
235 u16 diversity_control;
236 u16 antenna_switch_swap;
237 int serialize_regmode;
238 int intr_mitigation;
238#define SPUR_DISABLE 0 239#define SPUR_DISABLE 0
239#define SPUR_ENABLE_IOCTL 1 240#define SPUR_ENABLE_IOCTL 1
240#define SPUR_ENABLE_EEPROM 2 241#define SPUR_ENABLE_EEPROM 2
@@ -246,8 +247,8 @@ struct hal_ops_config {
246#define AR_BASE_FREQ_5GHZ 4900 247#define AR_BASE_FREQ_5GHZ 4900
247#define AR_SPUR_FEEQ_BOUND_HT40 19 248#define AR_SPUR_FEEQ_BOUND_HT40 19
248#define AR_SPUR_FEEQ_BOUND_HT20 10 249#define AR_SPUR_FEEQ_BOUND_HT20 10
249 int ath_hal_spurMode; 250 int spurmode;
250 u16 ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2]; 251 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
251}; 252};
252 253
253enum ath9k_tx_queue { 254enum ath9k_tx_queue {
@@ -815,8 +816,8 @@ struct ath_hal {
815 u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE]; 816 u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
816 u32 ah_flags; 817 u32 ah_flags;
817 enum ath9k_opmode ah_opmode; 818 enum ath9k_opmode ah_opmode;
818 struct hal_ops_config ah_config; 819 struct ath9k_ops_config ah_config;
819 struct hal_capabilities ah_caps; 820 struct ath9k_hw_capabilities ah_caps;
820 int16_t ah_powerLimit; 821 int16_t ah_powerLimit;
821 u16 ah_maxPowerLevel; 822 u16 ah_maxPowerLevel;
822 u32 ah_tpScale; 823 u32 ah_tpScale;
@@ -878,7 +879,7 @@ struct chan_centers {
878}; 879};
879 880
880int ath_hal_getcapability(struct ath_hal *ah, 881int ath_hal_getcapability(struct ath_hal *ah,
881 enum hal_capability_type type, 882 enum ath9k_capability_type type,
882 u32 capability, 883 u32 capability,
883 u32 *result); 884 u32 *result);
884const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, 885const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
@@ -947,11 +948,11 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
947bool ath9k_hw_phycounters(struct ath_hal *ah); 948bool ath9k_hw_phycounters(struct ath_hal *ah);
948bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); 949bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
949bool ath9k_hw_getcapability(struct ath_hal *ah, 950bool ath9k_hw_getcapability(struct ath_hal *ah,
950 enum hal_capability_type type, 951 enum ath9k_capability_type type,
951 u32 capability, 952 u32 capability,
952 u32 *result); 953 u32 *result);
953bool ath9k_hw_setcapability(struct ath_hal *ah, 954bool ath9k_hw_setcapability(struct ath_hal *ah,
954 enum hal_capability_type type, 955 enum ath9k_capability_type type,
955 u32 capability, 956 u32 capability,
956 u32 setting, 957 u32 setting,
957 int *status); 958 int *status);
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c
index 00993f828c5c..ba3dd253e963 100644
--- a/drivers/net/wireless/ath9k/beacon.c
+++ b/drivers/net/wireless/ath9k/beacon.c
@@ -85,7 +85,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
85 85
86 flags = ATH9K_TXDESC_NOACK; 86 flags = ATH9K_TXDESC_NOACK;
87 87
88 if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport) { 88 if (sc->sc_opmode == ATH9K_M_IBSS &&
89 (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
89 ds->ds_link = bf->bf_daddr; /* self-linked */ 90 ds->ds_link = bf->bf_daddr; /* self-linked */
90 flags |= ATH9K_TXDESC_VEOL; 91 flags |= ATH9K_TXDESC_VEOL;
91 /* Let hardware handle antenna switching. */ 92 /* Let hardware handle antenna switching. */
@@ -375,7 +376,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
375 list_del(&avp->av_bcbuf->list); 376 list_del(&avp->av_bcbuf->list);
376 377
377 if (sc->sc_opmode == ATH9K_M_HOSTAP || 378 if (sc->sc_opmode == ATH9K_M_HOSTAP ||
378 !sc->sc_ah->ah_caps.halVEOLSupport) { 379 !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) {
379 int slot; 380 int slot;
380 /* 381 /*
381 * Assign the vap to a beacon xmit slot. As 382 * Assign the vap to a beacon xmit slot. As
@@ -939,7 +940,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
939 * deal with things. 940 * deal with things.
940 */ 941 */
941 intval |= ATH9K_BEACON_ENA; 942 intval |= ATH9K_BEACON_ENA;
942 if (!ah->ah_caps.halVEOLSupport) 943 if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))
943 sc->sc_imask |= ATH9K_INT_SWBA; 944 sc->sc_imask |= ATH9K_INT_SWBA;
944 ath_beaconq_config(sc); 945 ath_beaconq_config(sc);
945 } else if (sc->sc_opmode == ATH9K_M_HOSTAP) { 946 } else if (sc->sc_opmode == ATH9K_M_HOSTAP) {
@@ -958,7 +959,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
958 * When using a self-linked beacon descriptor in 959 * When using a self-linked beacon descriptor in
959 * ibss mode load it once here. 960 * ibss mode load it once here.
960 */ 961 */
961 if (sc->sc_opmode == ATH9K_M_IBSS && ah->ah_caps.halVEOLSupport) 962 if (sc->sc_opmode == ATH9K_M_IBSS &&
963 (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL))
962 ath_beacon_start_adhoc(sc, 0); 964 ath_beacon_start_adhoc(sc, 0);
963 } 965 }
964#undef TSF_TO_TU 966#undef TSF_TO_TU
diff --git a/drivers/net/wireless/ath9k/core.c b/drivers/net/wireless/ath9k/core.c
index e8b3f1fabb31..f7bf0783f3be 100644
--- a/drivers/net/wireless/ath9k/core.c
+++ b/drivers/net/wireless/ath9k/core.c
@@ -536,7 +536,7 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
536 * sc_chainmask_auto_sel is used for internal global auto-switching 536 * sc_chainmask_auto_sel is used for internal global auto-switching
537 * enabled/disabled setting 537 * enabled/disabled setting
538 */ 538 */
539 if (sc->sc_ah->ah_caps.halTxChainMask != ATH_CHAINMASK_SEL_3X3) { 539 if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) {
540 cm->cur_tx_mask = sc->sc_tx_chainmask; 540 cm->cur_tx_mask = sc->sc_tx_chainmask;
541 return cm->cur_tx_mask; 541 return cm->cur_tx_mask;
542 } 542 }
@@ -580,8 +580,8 @@ void ath_update_chainmask(struct ath_softc *sc, int is_ht)
580{ 580{
581 sc->sc_update_chainmask = 1; 581 sc->sc_update_chainmask = 1;
582 if (is_ht) { 582 if (is_ht) {
583 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.halTxChainMask; 583 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
584 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.halRxChainMask; 584 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
585 } else { 585 } else {
586 sc->sc_tx_chainmask = 1; 586 sc->sc_tx_chainmask = 1;
587 sc->sc_rx_chainmask = 1; 587 sc->sc_rx_chainmask = 1;
@@ -780,8 +780,8 @@ int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
780 ath_stop(sc); 780 ath_stop(sc);
781 781
782 /* Initialize chanmask selection */ 782 /* Initialize chanmask selection */
783 sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask; 783 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
784 sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask; 784 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
785 785
786 /* Reset SERDES registers */ 786 /* Reset SERDES registers */
787 ath9k_hw_configpcipowersave(ah, 0); 787 ath9k_hw_configpcipowersave(ah, 0);
@@ -832,10 +832,10 @@ int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
832 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN 832 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
833 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; 833 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
834 834
835 if (ah->ah_caps.halGTTSupport) 835 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
836 sc->sc_imask |= ATH9K_INT_GTT; 836 sc->sc_imask |= ATH9K_INT_GTT;
837 837
838 if (ah->ah_caps.halHTSupport) 838 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
839 sc->sc_imask |= ATH9K_INT_CST; 839 sc->sc_imask |= ATH9K_INT_CST;
840 840
841 /* 841 /*
@@ -851,8 +851,9 @@ int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
851 * that does, if not overridden by configuration, 851 * that does, if not overridden by configuration,
852 * enable the TIM interrupt when operating as station. 852 * enable the TIM interrupt when operating as station.
853 */ 853 */
854 if (ah->ah_caps.halEnhancedPmSupport && sc->sc_opmode == ATH9K_M_STA && 854 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
855 !sc->sc_config.swBeaconProcess) 855 (sc->sc_opmode == ATH9K_M_STA) &&
856 !sc->sc_config.swBeaconProcess)
856 sc->sc_imask |= ATH9K_INT_TIM; 857 sc->sc_imask |= ATH9K_INT_TIM;
857 /* 858 /*
858 * Don't enable interrupts here as we've not yet built our 859 * Don't enable interrupts here as we've not yet built our
@@ -1061,7 +1062,8 @@ irqreturn_t ath_isr(int irq, void *dev)
1061 ath9k_hw_set_interrupts(ah, sc->sc_imask); 1062 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1062 } 1063 }
1063 if (status & ATH9K_INT_TIM_TIMER) { 1064 if (status & ATH9K_INT_TIM_TIMER) {
1064 if (!ah->ah_caps.halAutoSleepSupport) { 1065 if (!(ah->ah_caps.hw_caps &
1066 ATH9K_HW_CAP_AUTOSLEEP)) {
1065 /* Clear RxAbort bit so that we can 1067 /* Clear RxAbort bit so that we can
1066 * receive frames */ 1068 * receive frames */
1067 ath9k_hw_setrxabort(ah, 0); 1069 ath9k_hw_setrxabort(ah, 0);
@@ -1166,10 +1168,10 @@ int ath_init(u16 devid, struct ath_softc *sc)
1166 sc->sc_ah = ah; 1168 sc->sc_ah = ah;
1167 1169
1168 /* Get the chipset-specific aggr limit. */ 1170 /* Get the chipset-specific aggr limit. */
1169 sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit; 1171 sc->sc_rtsaggrlimit = ah->ah_caps.rts_aggr_limit;
1170 1172
1171 /* Get the hardware key cache size. */ 1173 /* Get the hardware key cache size. */
1172 sc->sc_keymax = ah->ah_caps.halKeyCacheSize; 1174 sc->sc_keymax = ah->ah_caps.keycache_size;
1173 if (sc->sc_keymax > ATH_KEYMAX) { 1175 if (sc->sc_keymax > ATH_KEYMAX) {
1174 DPRINTF(sc, ATH_DBG_KEYCACHE, 1176 DPRINTF(sc, ATH_DBG_KEYCACHE,
1175 "%s: Warning, using only %u entries in %u key cache\n", 1177 "%s: Warning, using only %u entries in %u key cache\n",
@@ -1284,7 +1286,7 @@ int ath_init(u16 devid, struct ath_softc *sc)
1284 goto bad2; 1286 goto bad2;
1285 } 1287 }
1286 1288
1287 if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, 1289 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1288 ATH9K_CIPHER_TKIP, NULL)) { 1290 ATH9K_CIPHER_TKIP, NULL)) {
1289 /* 1291 /*
1290 * Whether we should enable h/w TKIP MIC. 1292 * Whether we should enable h/w TKIP MIC.
@@ -1292,7 +1294,8 @@ int ath_init(u16 devid, struct ath_softc *sc)
1292 * report WMM capable, so it's always safe to turn on 1294 * report WMM capable, so it's always safe to turn on
1293 * TKIP MIC in this case. 1295 * TKIP MIC in this case.
1294 */ 1296 */
1295 ath9k_hw_setcapability(sc->sc_ah, HAL_CAP_TKIP_MIC, 0, 1, NULL); 1297 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1298 0, 1, NULL);
1296 } 1299 }
1297 1300
1298 /* 1301 /*
@@ -1301,30 +1304,30 @@ int ath_init(u16 devid, struct ath_softc *sc)
1301 * With split mic keys the number of stations is limited 1304 * With split mic keys the number of stations is limited
1302 * to 27 otherwise 59. 1305 * to 27 otherwise 59.
1303 */ 1306 */
1304 if (ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, 1307 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1305 ATH9K_CIPHER_TKIP, NULL) 1308 ATH9K_CIPHER_TKIP, NULL)
1306 && ath9k_hw_getcapability(ah, HAL_CAP_CIPHER, 1309 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1307 ATH9K_CIPHER_MIC, NULL) 1310 ATH9K_CIPHER_MIC, NULL)
1308 && ath9k_hw_getcapability(ah, HAL_CAP_TKIP_SPLIT, 1311 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1309 0, NULL)) 1312 0, NULL))
1310 sc->sc_splitmic = 1; 1313 sc->sc_splitmic = 1;
1311 1314
1312 /* turn on mcast key search if possible */ 1315 /* turn on mcast key search if possible */
1313 if (!ath9k_hw_getcapability(ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL)) 1316 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1314 (void)ath9k_hw_setcapability(ah, HAL_CAP_MCAST_KEYSRCH, 1, 1317 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1315 1, NULL); 1318 1, NULL);
1316 1319
1317 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX; 1320 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1318 sc->sc_config.txpowlimit_override = 0; 1321 sc->sc_config.txpowlimit_override = 0;
1319 1322
1320 /* 11n Capabilities */ 1323 /* 11n Capabilities */
1321 if (ah->ah_caps.halHTSupport) { 1324 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1322 sc->sc_txaggr = 1; 1325 sc->sc_txaggr = 1;
1323 sc->sc_rxaggr = 1; 1326 sc->sc_rxaggr = 1;
1324 } 1327 }
1325 1328
1326 sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask; 1329 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1327 sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask; 1330 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1328 1331
1329 /* Configuration for rx chain detection */ 1332 /* Configuration for rx chain detection */
1330 sc->sc_rxchaindetect_ref = 0; 1333 sc->sc_rxchaindetect_ref = 0;
@@ -1333,11 +1336,11 @@ int ath_init(u16 devid, struct ath_softc *sc)
1333 sc->sc_rxchaindetect_delta5GHz = 30; 1336 sc->sc_rxchaindetect_delta5GHz = 30;
1334 sc->sc_rxchaindetect_delta2GHz = 30; 1337 sc->sc_rxchaindetect_delta2GHz = 30;
1335 1338
1336 ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, true, NULL); 1339 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1337 sc->sc_defant = ath9k_hw_getdefantenna(ah); 1340 sc->sc_defant = ath9k_hw_getdefantenna(ah);
1338 1341
1339 ath9k_hw_getmac(ah, sc->sc_myaddr); 1342 ath9k_hw_getmac(ah, sc->sc_myaddr);
1340 if (ah->ah_caps.halBssIdMaskSupport) { 1343 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1341 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask); 1344 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1342 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask); 1345 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1343 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); 1346 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
@@ -1555,7 +1558,7 @@ void ath_update_txpow(struct ath_softc *sc)
1555 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) { 1558 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
1556 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit); 1559 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
1557 /* read back in case value is clamped */ 1560 /* read back in case value is clamped */
1558 ath9k_hw_getcapability(ah, HAL_CAP_TXPOW, 1, &txpow); 1561 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
1559 sc->sc_curtxpow = txpow; 1562 sc->sc_curtxpow = txpow;
1560 } 1563 }
1561} 1564}
@@ -1757,7 +1760,7 @@ int ath_descdma_setup(struct ath_softc *sc,
1757 * descriptors that cross the 4K page boundary. Assume 1760 * descriptors that cross the 4K page boundary. Assume
1758 * one skipped descriptor per 4K page. 1761 * one skipped descriptor per 4K page.
1759 */ 1762 */
1760 if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) { 1763 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1761 u32 ndesc_skipped = 1764 u32 ndesc_skipped =
1762 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 1765 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1763 u32 dma_len; 1766 u32 dma_len;
@@ -1798,7 +1801,8 @@ int ath_descdma_setup(struct ath_softc *sc,
1798 bf->bf_desc = ds; 1801 bf->bf_desc = ds;
1799 bf->bf_daddr = DS2PHYS(dd, ds); 1802 bf->bf_daddr = DS2PHYS(dd, ds);
1800 1803
1801 if (!(sc->sc_ah->ah_caps.hal4kbSplitTransSupport)) { 1804 if (!(sc->sc_ah->ah_caps.hw_caps &
1805 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1802 /* 1806 /*
1803 * Skip descriptor addresses which can cause 4KB 1807 * Skip descriptor addresses which can cause 4KB
1804 * boundary crossing (addr + length) with a 32 dword 1808 * boundary crossing (addr + length) with a 32 dword
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 63d0ead1c412..0dd11ee3b314 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -335,40 +335,40 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah)
335{ 335{
336 int i; 336 int i;
337 337
338 ah->ah_config.ath_hal_dma_beacon_response_time = 2; 338 ah->ah_config.dma_beacon_response_time = 2;
339 ah->ah_config.ath_hal_sw_beacon_response_time = 10; 339 ah->ah_config.sw_beacon_response_time = 10;
340 ah->ah_config.ath_hal_additional_swba_backoff = 0; 340 ah->ah_config.additional_swba_backoff = 0;
341 ah->ah_config.ath_hal_6mb_ack = 0x0; 341 ah->ah_config.ack_6mb = 0x0;
342 ah->ah_config.ath_hal_cwmIgnoreExtCCA = 0; 342 ah->ah_config.cwm_ignore_extcca = 0;
343 ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 343 ah->ah_config.pcie_powersave_enable = 0;
344 ah->ah_config.ath_hal_pcieL1SKPEnable = 0; 344 ah->ah_config.pcie_l1skp_enable = 0;
345 ah->ah_config.ath_hal_pcieClockReq = 0; 345 ah->ah_config.pcie_clock_req = 0;
346 ah->ah_config.ath_hal_pciePowerReset = 0x100; 346 ah->ah_config.pcie_power_reset = 0x100;
347 ah->ah_config.ath_hal_pcieRestore = 0; 347 ah->ah_config.pcie_restore = 0;
348 ah->ah_config.ath_hal_pcieWaen = 0; 348 ah->ah_config.pcie_waen = 0;
349 ah->ah_config.ath_hal_analogShiftReg = 1; 349 ah->ah_config.analog_shiftreg = 1;
350 ah->ah_config.ath_hal_htEnable = 1; 350 ah->ah_config.ht_enable = 1;
351 ah->ah_config.ath_hal_ofdmTrigLow = 200; 351 ah->ah_config.ofdm_trig_low = 200;
352 ah->ah_config.ath_hal_ofdmTrigHigh = 500; 352 ah->ah_config.ofdm_trig_high = 500;
353 ah->ah_config.ath_hal_cckTrigHigh = 200; 353 ah->ah_config.cck_trig_high = 200;
354 ah->ah_config.ath_hal_cckTrigLow = 100; 354 ah->ah_config.cck_trig_low = 100;
355 ah->ah_config.ath_hal_enableANI = 0; 355 ah->ah_config.enable_ani = 0;
356 ah->ah_config.ath_hal_noiseImmunityLvl = 4; 356 ah->ah_config.noise_immunity_level = 4;
357 ah->ah_config.ath_hal_ofdmWeakSigDet = 1; 357 ah->ah_config.ofdm_weaksignal_det = 1;
358 ah->ah_config.ath_hal_cckWeakSigThr = 0; 358 ah->ah_config.cck_weaksignal_thr = 0;
359 ah->ah_config.ath_hal_spurImmunityLvl = 2; 359 ah->ah_config.spur_immunity_level = 2;
360 ah->ah_config.ath_hal_firStepLvl = 0; 360 ah->ah_config.firstep_level = 0;
361 ah->ah_config.ath_hal_rssiThrHigh = 40; 361 ah->ah_config.rssi_thr_high = 40;
362 ah->ah_config.ath_hal_rssiThrLow = 7; 362 ah->ah_config.rssi_thr_low = 7;
363 ah->ah_config.ath_hal_diversityControl = 0; 363 ah->ah_config.diversity_control = 0;
364 ah->ah_config.ath_hal_antennaSwitchSwap = 0; 364 ah->ah_config.antenna_switch_swap = 0;
365 365
366 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 366 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
367 ah->ah_config.ath_hal_spurChans[i][0] = AR_NO_SPUR; 367 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
368 ah->ah_config.ath_hal_spurChans[i][1] = AR_NO_SPUR; 368 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
369 } 369 }
370 370
371 ah->ah_config.ath_hal_intrMitigation = 0; 371 ah->ah_config.intr_mitigation = 0;
372} 372}
373 373
374static inline void ath9k_hw_override_ini(struct ath_hal *ah, 374static inline void ath9k_hw_override_ini(struct ath_hal *ah,
@@ -458,7 +458,7 @@ static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
458 458
459 REG_WRITE(ah, reg, regVal); 459 REG_WRITE(ah, reg, regVal);
460 460
461 if (ah->ah_config.ath_hal_analogShiftReg) 461 if (ah->ah_config.analog_shiftreg)
462 udelay(100); 462 udelay(100);
463 463
464 return; 464 return;
@@ -1001,7 +1001,7 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
1001} 1001}
1002 1002
1003bool ath9k_hw_setcapability(struct ath_hal *ah, 1003bool ath9k_hw_setcapability(struct ath_hal *ah,
1004 enum hal_capability_type type, 1004 enum ath9k_capability_type type,
1005 u32 capability, 1005 u32 capability,
1006 u32 setting, 1006 u32 setting,
1007 int *status) 1007 int *status)
@@ -1010,7 +1010,7 @@ bool ath9k_hw_setcapability(struct ath_hal *ah,
1010 u32 v; 1010 u32 v;
1011 1011
1012 switch (type) { 1012 switch (type) {
1013 case HAL_CAP_TKIP_MIC: 1013 case ATH9K_CAP_TKIP_MIC:
1014 if (setting) 1014 if (setting)
1015 ahp->ah_staId1Defaults |= 1015 ahp->ah_staId1Defaults |=
1016 AR_STA_ID1_CRPT_MIC_ENABLE; 1016 AR_STA_ID1_CRPT_MIC_ENABLE;
@@ -1018,7 +1018,7 @@ bool ath9k_hw_setcapability(struct ath_hal *ah,
1018 ahp->ah_staId1Defaults &= 1018 ahp->ah_staId1Defaults &=
1019 ~AR_STA_ID1_CRPT_MIC_ENABLE; 1019 ~AR_STA_ID1_CRPT_MIC_ENABLE;
1020 return true; 1020 return true;
1021 case HAL_CAP_DIVERSITY: 1021 case ATH9K_CAP_DIVERSITY:
1022 v = REG_READ(ah, AR_PHY_CCK_DETECT); 1022 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1023 if (setting) 1023 if (setting)
1024 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 1024 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
@@ -1026,13 +1026,13 @@ bool ath9k_hw_setcapability(struct ath_hal *ah,
1026 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 1026 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1027 REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 1027 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1028 return true; 1028 return true;
1029 case HAL_CAP_MCAST_KEYSRCH: 1029 case ATH9K_CAP_MCAST_KEYSRCH:
1030 if (setting) 1030 if (setting)
1031 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; 1031 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1032 else 1032 else
1033 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1033 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1034 return true; 1034 return true;
1035 case HAL_CAP_TSF_ADJUST: 1035 case ATH9K_CAP_TSF_ADJUST:
1036 if (setting) 1036 if (setting)
1037 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 1037 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1038 else 1038 else
@@ -1161,7 +1161,7 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1161 u32 macmode; 1161 u32 macmode;
1162 1162
1163 if (mode == ATH9K_HT_MACMODE_2040 && 1163 if (mode == ATH9K_HT_MACMODE_2040 &&
1164 !ah->ah_config.ath_hal_cwmIgnoreExtCCA) 1164 !ah->ah_config.cwm_ignore_extcca)
1165 macmode = AR_2040_JOINED_RX_CLEAR; 1165 macmode = AR_2040_JOINED_RX_CLEAR;
1166 else 1166 else
1167 macmode = 0; 1167 macmode = 0;
@@ -1214,9 +1214,9 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1214 ah->ah_tpScale = ATH9K_TP_SCALE_MAX; 1214 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1215 1215
1216 ahp->ah_atimWindow = 0; 1216 ahp->ah_atimWindow = 0;
1217 ahp->ah_diversityControl = ah->ah_config.ath_hal_diversityControl; 1217 ahp->ah_diversityControl = ah->ah_config.diversity_control;
1218 ahp->ah_antennaSwitchSwap = 1218 ahp->ah_antennaSwitchSwap =
1219 ah->ah_config.ath_hal_antennaSwitchSwap; 1219 ah->ah_config.antenna_switch_swap;
1220 1220
1221 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 1221 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1222 ahp->ah_beaconInterval = 100; 1222 ahp->ah_beaconInterval = 100;
@@ -1371,13 +1371,13 @@ static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1371 1371
1372 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1372 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1373 "Getting spur idx %d is2Ghz. %d val %x\n", 1373 "Getting spur idx %d is2Ghz. %d val %x\n",
1374 i, is2GHz, ah->ah_config.ath_hal_spurChans[i][is2GHz]); 1374 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1375 1375
1376 switch (ah->ah_config.ath_hal_spurMode) { 1376 switch (ah->ah_config.spurmode) {
1377 case SPUR_DISABLE: 1377 case SPUR_DISABLE:
1378 break; 1378 break;
1379 case SPUR_ENABLE_IOCTL: 1379 case SPUR_ENABLE_IOCTL:
1380 spur_val = ah->ah_config.ath_hal_spurChans[i][is2GHz]; 1380 spur_val = ah->ah_config.spurchans[i][is2GHz];
1381 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1381 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1382 "Getting spur val from new loc. %d\n", spur_val); 1382 "Getting spur val from new loc. %d\n", spur_val);
1383 break; 1383 break;
@@ -2094,7 +2094,7 @@ static void ath9k_hw_ani_attach(struct ath_hal *ah)
2094 ath9k_enable_mib_counters(ah); 2094 ath9k_enable_mib_counters(ah);
2095 } 2095 }
2096 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; 2096 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2097 if (ah->ah_config.ath_hal_enableANI) 2097 if (ah->ah_config.enable_ani)
2098 ahp->ah_procPhyErr |= HAL_PROCESS_ANI; 2098 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2099} 2099}
2100 2100
@@ -2504,13 +2504,13 @@ static void ath9k_ani_reset(struct ath_hal *ah)
2504 ATH9K_RX_FILTER_PHYERR); 2504 ATH9K_RX_FILTER_PHYERR);
2505 if (ah->ah_opmode == ATH9K_M_HOSTAP) { 2505 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2506 ahp->ah_curani->ofdmTrigHigh = 2506 ahp->ah_curani->ofdmTrigHigh =
2507 ah->ah_config.ath_hal_ofdmTrigHigh; 2507 ah->ah_config.ofdm_trig_high;
2508 ahp->ah_curani->ofdmTrigLow = 2508 ahp->ah_curani->ofdmTrigLow =
2509 ah->ah_config.ath_hal_ofdmTrigLow; 2509 ah->ah_config.ofdm_trig_low;
2510 ahp->ah_curani->cckTrigHigh = 2510 ahp->ah_curani->cckTrigHigh =
2511 ah->ah_config.ath_hal_cckTrigHigh; 2511 ah->ah_config.cck_trig_high;
2512 ahp->ah_curani->cckTrigLow = 2512 ahp->ah_curani->cckTrigLow =
2513 ah->ah_config.ath_hal_cckTrigLow; 2513 ah->ah_config.cck_trig_low;
2514 } 2514 }
2515 ath9k_ani_restart(ah); 2515 ath9k_ani_restart(ah);
2516 return; 2516 return;
@@ -2870,7 +2870,7 @@ static bool ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio,
2870 2870
2871static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) 2871static u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2872{ 2872{
2873 if (gpio >= ah->ah_caps.halNumGpioPins) 2873 if (gpio >= ah->ah_caps.num_gpio_pins)
2874 return 0xffffffff; 2874 return 0xffffffff;
2875 2875
2876 if (AR_SREV_9280_10_OR_LATER(ah)) { 2876 if (AR_SREV_9280_10_OR_LATER(ah)) {
@@ -2947,7 +2947,7 @@ static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2947static bool ath9k_hw_fill_cap_info(struct ath_hal *ah) 2947static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2948{ 2948{
2949 struct ath_hal_5416 *ahp = AH5416(ah); 2949 struct ath_hal_5416 *ahp = AH5416(ah);
2950 struct hal_capabilities *pCap = &ah->ah_caps; 2950 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2951 u16 capField = 0, eeval; 2951 u16 capField = 0, eeval;
2952 2952
2953 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0); 2953 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
@@ -2970,12 +2970,12 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2970 ah->ah_currentRD); 2970 ah->ah_currentRD);
2971 } 2971 }
2972 2972
2973 pCap->halWirelessModes = 0; 2973 pCap->wireless_modes = 0;
2974 eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE); 2974 eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2975 2975
2976 if (eeval & AR5416_OPFLAGS_11A) { 2976 if (eeval & AR5416_OPFLAGS_11A) {
2977 pCap->halWirelessModes |= ATH9K_MODE_SEL_11A | 2977 pCap->wireless_modes |= ATH9K_MODE_SEL_11A |
2978 ((!ah->ah_config.ath_hal_htEnable 2978 ((!ah->ah_config.ht_enable
2979 || (eeval & AR5416_OPFLAGS_N_5G_HT20)) ? 0 2979 || (eeval & AR5416_OPFLAGS_N_5G_HT20)) ? 0
2980 : (ATH9K_MODE_SEL_11NA_HT20 | 2980 : (ATH9K_MODE_SEL_11NA_HT20 |
2981 ((eeval & AR5416_OPFLAGS_N_5G_HT40) ? 0 2981 ((eeval & AR5416_OPFLAGS_N_5G_HT40) ? 0
@@ -2983,9 +2983,9 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2983 ATH9K_MODE_SEL_11NA_HT40MINUS)))); 2983 ATH9K_MODE_SEL_11NA_HT40MINUS))));
2984 } 2984 }
2985 if (eeval & AR5416_OPFLAGS_11G) { 2985 if (eeval & AR5416_OPFLAGS_11G) {
2986 pCap->halWirelessModes |= 2986 pCap->wireless_modes |=
2987 ATH9K_MODE_SEL_11B | ATH9K_MODE_SEL_11G | 2987 ATH9K_MODE_SEL_11B | ATH9K_MODE_SEL_11G |
2988 ((!ah->ah_config.ath_hal_htEnable 2988 ((!ah->ah_config.ht_enable
2989 || (eeval & AR5416_OPFLAGS_N_2G_HT20)) ? 0 2989 || (eeval & AR5416_OPFLAGS_N_2G_HT20)) ? 0
2990 : (ATH9K_MODE_SEL_11NG_HT20 | 2990 : (ATH9K_MODE_SEL_11NG_HT20 |
2991 ((eeval & AR5416_OPFLAGS_N_2G_HT40) ? 0 2991 ((eeval & AR5416_OPFLAGS_N_2G_HT40) ? 0
@@ -2993,79 +2993,82 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2993 ATH9K_MODE_SEL_11NG_HT40MINUS)))); 2993 ATH9K_MODE_SEL_11NG_HT40MINUS))));
2994 2994
2995 } 2995 }
2996 pCap->halTxChainMask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK); 2996 pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
2997 if ((ah->ah_isPciExpress) 2997 if ((ah->ah_isPciExpress)
2998 || (eeval & AR5416_OPFLAGS_11A)) { 2998 || (eeval & AR5416_OPFLAGS_11A)) {
2999 pCap->halRxChainMask = 2999 pCap->rx_chainmask =
3000 ath9k_hw_get_eeprom(ahp, EEP_RX_MASK); 3000 ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
3001 } else { 3001 } else {
3002 pCap->halRxChainMask = 3002 pCap->rx_chainmask =
3003 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; 3003 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3004 } 3004 }
3005 3005
3006 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0))) 3006 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3007 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; 3007 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3008 3008
3009 pCap->halLow2GhzChan = 2312; 3009 pCap->low_2ghz_chan = 2312;
3010 pCap->halHigh2GhzChan = 2732; 3010 pCap->high_2ghz_chan = 2732;
3011 3011
3012 pCap->halLow5GhzChan = 4920; 3012 pCap->low_5ghz_chan = 4920;
3013 pCap->halHigh5GhzChan = 6100; 3013 pCap->high_5ghz_chan = 6100;
3014 3014
3015 pCap->halCipherCkipSupport = false; 3015 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3016 pCap->halCipherTkipSupport = true; 3016 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3017 pCap->halCipherAesCcmSupport = true; 3017 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3018 3018
3019 pCap->halMicCkipSupport = false; 3019 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3020 pCap->halMicTkipSupport = true; 3020 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3021 pCap->halMicAesCcmSupport = true; 3021 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3022 3022
3023 pCap->halChanSpreadSupport = true; 3023 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3024 3024
3025 pCap->halHTSupport = 3025 if (ah->ah_config.ht_enable)
3026 ah->ah_config.ath_hal_htEnable ? true : false; 3026 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3027 pCap->halGTTSupport = true; 3027 else
3028 pCap->halVEOLSupport = true; 3028 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3029 pCap->halBssIdMaskSupport = true; 3029
3030 pCap->halMcastKeySrchSupport = false; 3030 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3031 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3032 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3033 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3031 3034
3032 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 3035 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3033 pCap->halTotalQueues = 3036 pCap->total_queues =
3034 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 3037 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3035 else 3038 else
3036 pCap->halTotalQueues = ATH9K_NUM_TX_QUEUES; 3039 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3037 3040
3038 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 3041 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3039 pCap->halKeyCacheSize = 3042 pCap->keycache_size =
3040 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 3043 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3041 else 3044 else
3042 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 3045 pCap->keycache_size = AR_KEYTABLE_SIZE;
3043 3046
3044 pCap->halFastCCSupport = true; 3047 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3045 pCap->halNumMRRetries = 4; 3048 pCap->num_mr_retries = 4;
3046 pCap->halTxTrigLevelMax = MAX_TX_FIFO_THRESHOLD; 3049 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3047 3050
3048 if (AR_SREV_9280_10_OR_LATER(ah)) 3051 if (AR_SREV_9280_10_OR_LATER(ah))
3049 pCap->halNumGpioPins = AR928X_NUM_GPIO; 3052 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3050 else 3053 else
3051 pCap->halNumGpioPins = AR_NUM_GPIO; 3054 pCap->num_gpio_pins = AR_NUM_GPIO;
3052 3055
3053 if (AR_SREV_9280_10_OR_LATER(ah)) { 3056 if (AR_SREV_9280_10_OR_LATER(ah)) {
3054 pCap->halWowSupport = true; 3057 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3055 pCap->halWowMatchPatternExact = true; 3058 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3056 } else { 3059 } else {
3057 pCap->halWowSupport = false; 3060 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3058 pCap->halWowMatchPatternExact = false; 3061 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3059 } 3062 }
3060 3063
3061 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 3064 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3062 pCap->halCSTSupport = true; 3065 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3063 pCap->halRtsAggrLimit = ATH_AMPDU_LIMIT_MAX; 3066 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3064 } else { 3067 } else {
3065 pCap->halRtsAggrLimit = (8 * 1024); 3068 pCap->rts_aggr_limit = (8 * 1024);
3066 } 3069 }
3067 3070
3068 pCap->halEnhancedPmSupport = true; 3071 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3069 3072
3070 ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT); 3073 ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3071 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { 3074 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
@@ -3074,9 +3077,9 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3074 ahp->ah_polarity = 3077 ahp->ah_polarity =
3075 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); 3078 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3076 3079
3077 ath9k_hw_setcapability(ah, HAL_CAP_RFSILENT, 1, true, 3080 ath9k_hw_setcapability(ah, ATH9K_CAP_RFSILENT, 1, true,
3078 NULL); 3081 NULL);
3079 pCap->halRfSilentSupport = true; 3082 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3080 } 3083 }
3081 3084
3082 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || 3085 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
@@ -3084,32 +3087,32 @@ static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3084 (ah->ah_macVersion == AR_SREV_VERSION_9160) || 3087 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3085 (ah->ah_macVersion == AR_SREV_VERSION_9100) || 3088 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3086 (ah->ah_macVersion == AR_SREV_VERSION_9280)) 3089 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3087 pCap->halAutoSleepSupport = false; 3090 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3088 else 3091 else
3089 pCap->halAutoSleepSupport = true; 3092 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3090 3093
3091 if (AR_SREV_9280(ah)) 3094 if (AR_SREV_9280(ah))
3092 pCap->hal4kbSplitTransSupport = false; 3095 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3093 else 3096 else
3094 pCap->hal4kbSplitTransSupport = true; 3097 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3095 3098
3096 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) { 3099 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3097 pCap->halRegCap = 3100 pCap->reg_cap =
3098 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3101 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3099 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 3102 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3100 AR_EEPROM_EEREGCAP_EN_KK_U2 | 3103 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3101 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 3104 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3102 } else { 3105 } else {
3103 pCap->halRegCap = 3106 pCap->reg_cap =
3104 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3107 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3105 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 3108 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3106 } 3109 }
3107 3110
3108 pCap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3111 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3109 3112
3110 pCap->halNumAntCfg5GHz = 3113 pCap->num_antcfg_5ghz =
3111 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 3114 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ);
3112 pCap->halNumAntCfg2GHz = 3115 pCap->num_antcfg_2ghz =
3113 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 3116 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ);
3114 3117
3115 return true; 3118 return true;
@@ -3151,9 +3154,9 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3151{ 3154{
3152 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 3155 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3153 if (setChip) { 3156 if (setChip) {
3154 struct hal_capabilities *pCap = &ah->ah_caps; 3157 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3155 3158
3156 if (!pCap->halAutoSleepSupport) { 3159 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3157 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 3160 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3158 AR_RTC_FORCE_WAKE_ON_INT); 3161 AR_RTC_FORCE_WAKE_ON_INT);
3159 } else { 3162 } else {
@@ -3262,7 +3265,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3262 3265
3263 ath9k_hw_set_defaults(ah); 3266 ath9k_hw_set_defaults(ah);
3264 3267
3265 if (ah->ah_config.ath_hal_intrMitigation != 0) 3268 if (ah->ah_config.intr_mitigation != 0)
3266 ahp->ah_intrMitigation = true; 3269 ahp->ah_intrMitigation = true;
3267 3270
3268 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 3271 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
@@ -3279,18 +3282,18 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3279 goto bad; 3282 goto bad;
3280 } 3283 }
3281 3284
3282 if (ah->ah_config.ath_hal_serializeRegMode == SER_REG_MODE_AUTO) { 3285 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
3283 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) { 3286 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3284 ah->ah_config.ath_hal_serializeRegMode = 3287 ah->ah_config.serialize_regmode =
3285 SER_REG_MODE_ON; 3288 SER_REG_MODE_ON;
3286 } else { 3289 } else {
3287 ah->ah_config.ath_hal_serializeRegMode = 3290 ah->ah_config.serialize_regmode =
3288 SER_REG_MODE_OFF; 3291 SER_REG_MODE_OFF;
3289 } 3292 }
3290 } 3293 }
3291 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 3294 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3292 "%s: ath_hal_serializeRegMode is %d\n", 3295 "%s: serialize_regmode is %d\n",
3293 __func__, ah->ah_config.ath_hal_serializeRegMode); 3296 __func__, ah->ah_config.serialize_regmode);
3294 3297
3295 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && 3298 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3296 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && 3299 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
@@ -3334,7 +3337,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3334 } 3337 }
3335 3338
3336 if (AR_SREV_9160(ah)) { 3339 if (AR_SREV_9160(ah)) {
3337 ah->ah_config.ath_hal_enableANI = 1; 3340 ah->ah_config.enable_ani = 1;
3338 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 3341 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
3339 ATH9K_ANI_FIRSTEP_LEVEL); 3342 ATH9K_ANI_FIRSTEP_LEVEL);
3340 } else { 3343 } else {
@@ -3355,7 +3358,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3355 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, 3358 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3356 ARRAY_SIZE(ar9280Common_9280_2), 2); 3359 ARRAY_SIZE(ar9280Common_9280_2), 2);
3357 3360
3358 if (ah->ah_config.ath_hal_pcieClockReq) { 3361 if (ah->ah_config.pcie_clock_req) {
3359 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 3362 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3360 ar9280PciePhy_clkreq_off_L1_9280, 3363 ar9280PciePhy_clkreq_off_L1_9280,
3361 ARRAY_SIZE 3364 ARRAY_SIZE
@@ -3528,16 +3531,16 @@ bool ath9k_get_channel_edges(struct ath_hal *ah,
3528 u16 flags, u16 *low, 3531 u16 flags, u16 *low,
3529 u16 *high) 3532 u16 *high)
3530{ 3533{
3531 struct hal_capabilities *pCap = &ah->ah_caps; 3534 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3532 3535
3533 if (flags & CHANNEL_5GHZ) { 3536 if (flags & CHANNEL_5GHZ) {
3534 *low = pCap->halLow5GhzChan; 3537 *low = pCap->low_5ghz_chan;
3535 *high = pCap->halHigh5GhzChan; 3538 *high = pCap->high_5ghz_chan;
3536 return true; 3539 return true;
3537 } 3540 }
3538 if ((flags & CHANNEL_2GHZ)) { 3541 if ((flags & CHANNEL_2GHZ)) {
3539 *low = pCap->halLow2GhzChan; 3542 *low = pCap->low_2ghz_chan;
3540 *high = pCap->halHigh2GhzChan; 3543 *high = pCap->high_2ghz_chan;
3541 3544
3542 return true; 3545 return true;
3543 } 3546 }
@@ -3908,7 +3911,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3908 if (ah->ah_isPciExpress != true) 3911 if (ah->ah_isPciExpress != true)
3909 return; 3912 return;
3910 3913
3911 if (ah->ah_config.ath_hal_pciePowerSaveEnable == 2) 3914 if (ah->ah_config.pcie_powersave_enable == 2)
3912 return; 3915 return;
3913 3916
3914 if (restore) 3917 if (restore)
@@ -3929,7 +3932,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3929 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 3932 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3930 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 3933 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3931 3934
3932 if (ah->ah_config.ath_hal_pcieClockReq) 3935 if (ah->ah_config.pcie_clock_req)
3933 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 3936 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3934 else 3937 else
3935 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); 3938 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
@@ -3956,8 +3959,8 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3956 3959
3957 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 3960 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3958 3961
3959 if (ah->ah_config.ath_hal_pcieWaen) { 3962 if (ah->ah_config.pcie_waen) {
3960 REG_WRITE(ah, AR_WA, ah->ah_config.ath_hal_pcieWaen); 3963 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3961 } else { 3964 } else {
3962 if (AR_SREV_9280(ah)) 3965 if (AR_SREV_9280(ah))
3963 REG_WRITE(ah, AR_WA, 0x0040073f); 3966 REG_WRITE(ah, AR_WA, 0x0040073f);
@@ -4690,7 +4693,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4690 ath9k_hw_get_channel_centers(ah, chan, &centers); 4693 ath9k_hw_get_channel_centers(ah, chan, &centers);
4691 freq = centers.synth_center; 4694 freq = centers.synth_center;
4692 4695
4693 ah->ah_config.ath_hal_spurMode = SPUR_ENABLE_EEPROM; 4696 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
4694 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 4697 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4695 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); 4698 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4696 4699
@@ -5404,7 +5407,7 @@ ath9k_hw_process_ini(struct ath_hal *ah,
5404 REG_WRITE(ah, reg, val); 5407 REG_WRITE(ah, reg, val);
5405 5408
5406 if (reg >= 0x7800 && reg < 0x78a0 5409 if (reg >= 0x7800 && reg < 0x78a0
5407 && ah->ah_config.ath_hal_analogShiftReg) { 5410 && ah->ah_config.analog_shiftreg) {
5408 udelay(100); 5411 udelay(100);
5409 } 5412 }
5410 5413
@@ -5418,7 +5421,7 @@ ath9k_hw_process_ini(struct ath_hal *ah,
5418 REG_WRITE(ah, reg, val); 5421 REG_WRITE(ah, reg, val);
5419 5422
5420 if (reg >= 0x7800 && reg < 0x78a0 5423 if (reg >= 0x7800 && reg < 0x78a0
5421 && ah->ah_config.ath_hal_analogShiftReg) { 5424 && ah->ah_config.analog_shiftreg) {
5422 udelay(100); 5425 udelay(100);
5423 } 5426 }
5424 5427
@@ -5921,7 +5924,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
5921 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 5924 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
5922 AR_GPIO_JTAG_DISABLE); 5925 AR_GPIO_JTAG_DISABLE);
5923 5926
5924 if (ah->ah_caps.halWirelessModes & ATH9K_MODE_SEL_11A) { 5927 if (ah->ah_caps.wireless_modes & ATH9K_MODE_SEL_11A) {
5925 if (IS_CHAN_5GHZ(chan)) 5928 if (IS_CHAN_5GHZ(chan))
5926 ath9k_hw_set_gpio(ah, 9, 0); 5929 ath9k_hw_set_gpio(ah, 9, 0);
5927 else 5930 else
@@ -5955,7 +5958,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
5955 | macStaId1 5958 | macStaId1
5956 | AR_STA_ID1_RTS_USE_DEF 5959 | AR_STA_ID1_RTS_USE_DEF
5957 | (ah->ah_config. 5960 | (ah->ah_config.
5958 ath_hal_6mb_ack ? AR_STA_ID1_ACKCTS_6MB : 0) 5961 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
5959 | ahp->ah_staId1Defaults); 5962 | ahp->ah_staId1Defaults);
5960 ath9k_hw_set_operating_mode(ah, opmode); 5963 ath9k_hw_set_operating_mode(ah, opmode);
5961 5964
@@ -5984,7 +5987,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
5984 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 5987 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
5985 5988
5986 ahp->ah_intrTxqs = 0; 5989 ahp->ah_intrTxqs = 0;
5987 for (i = 0; i < ah->ah_caps.halTotalQueues; i++) 5990 for (i = 0; i < ah->ah_caps.total_queues; i++)
5988 ath9k_hw_resettxqueue(ah, i); 5991 ath9k_hw_resettxqueue(ah, i);
5989 5992
5990 ath9k_hw_init_interrupt_masks(ah, opmode); 5993 ath9k_hw_init_interrupt_masks(ah, opmode);
@@ -6622,7 +6625,7 @@ ath9k_hw_setantennaswitch(struct ath_hal *ah,
6622 *antenna_cfgd = true; 6625 *antenna_cfgd = true;
6623 break; 6626 break;
6624 case ATH9K_ANT_FIXED_B: 6627 case ATH9K_ANT_FIXED_B:
6625 if (ah->ah_caps.halTxChainMask > 6628 if (ah->ah_caps.tx_chainmask >
6626 ATH9K_ANTENNA1_CHAINMASK) { 6629 ATH9K_ANTENNA1_CHAINMASK) {
6627 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; 6630 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6628 } 6631 }
@@ -6650,14 +6653,14 @@ void ath9k_hw_setopmode(struct ath_hal *ah)
6650} 6653}
6651 6654
6652bool 6655bool
6653ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type, 6656ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
6654 u32 capability, u32 *result) 6657 u32 capability, u32 *result)
6655{ 6658{
6656 struct ath_hal_5416 *ahp = AH5416(ah); 6659 struct ath_hal_5416 *ahp = AH5416(ah);
6657 const struct hal_capabilities *pCap = &ah->ah_caps; 6660 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6658 6661
6659 switch (type) { 6662 switch (type) {
6660 case HAL_CAP_CIPHER: 6663 case ATH9K_CAP_CIPHER:
6661 switch (capability) { 6664 switch (capability) {
6662 case ATH9K_CIPHER_AES_CCM: 6665 case ATH9K_CIPHER_AES_CCM:
6663 case ATH9K_CIPHER_AES_OCB: 6666 case ATH9K_CIPHER_AES_OCB:
@@ -6669,7 +6672,7 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
6669 default: 6672 default:
6670 return false; 6673 return false;
6671 } 6674 }
6672 case HAL_CAP_TKIP_MIC: 6675 case ATH9K_CAP_TKIP_MIC:
6673 switch (capability) { 6676 switch (capability) {
6674 case 0: 6677 case 0:
6675 return true; 6678 return true;
@@ -6678,20 +6681,20 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
6678 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 6681 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
6679 false; 6682 false;
6680 } 6683 }
6681 case HAL_CAP_TKIP_SPLIT: 6684 case ATH9K_CAP_TKIP_SPLIT:
6682 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? 6685 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6683 false : true; 6686 false : true;
6684 case HAL_CAP_WME_TKIPMIC: 6687 case ATH9K_CAP_WME_TKIPMIC:
6685 return 0; 6688 return 0;
6686 case HAL_CAP_PHYCOUNTERS: 6689 case ATH9K_CAP_PHYCOUNTERS:
6687 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; 6690 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
6688 case HAL_CAP_DIVERSITY: 6691 case ATH9K_CAP_DIVERSITY:
6689 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 6692 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6690 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 6693 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6691 true : false; 6694 true : false;
6692 case HAL_CAP_PHYDIAG: 6695 case ATH9K_CAP_PHYDIAG:
6693 return true; 6696 return true;
6694 case HAL_CAP_MCAST_KEYSRCH: 6697 case ATH9K_CAP_MCAST_KEYSRCH:
6695 switch (capability) { 6698 switch (capability) {
6696 case 0: 6699 case 0:
6697 return true; 6700 return true;
@@ -6705,19 +6708,19 @@ ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
6705 } 6708 }
6706 } 6709 }
6707 return false; 6710 return false;
6708 case HAL_CAP_TSF_ADJUST: 6711 case ATH9K_CAP_TSF_ADJUST:
6709 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? 6712 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6710 true : false; 6713 true : false;
6711 case HAL_CAP_RFSILENT: 6714 case ATH9K_CAP_RFSILENT:
6712 if (capability == 3) 6715 if (capability == 3)
6713 return false; 6716 return false;
6714 case HAL_CAP_ANT_CFG_2GHZ: 6717 case ATH9K_CAP_ANT_CFG_2GHZ:
6715 *result = pCap->halNumAntCfg2GHz; 6718 *result = pCap->num_antcfg_2ghz;
6716 return true; 6719 return true;
6717 case HAL_CAP_ANT_CFG_5GHZ: 6720 case ATH9K_CAP_ANT_CFG_5GHZ:
6718 *result = pCap->halNumAntCfg5GHz; 6721 *result = pCap->num_antcfg_5ghz;
6719 return true; 6722 return true;
6720 case HAL_CAP_TXPOW: 6723 case ATH9K_CAP_TXPOW:
6721 switch (capability) { 6724 switch (capability) {
6722 case 0: 6725 case 0:
6723 return 0; 6726 return 0;
@@ -6742,13 +6745,13 @@ ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
6742{ 6745{
6743 struct ath_hal_5416 *ahp = AH5416(ah); 6746 struct ath_hal_5416 *ahp = AH5416(ah);
6744 struct ath9k_channel *chan = ah->ah_curchan; 6747 struct ath9k_channel *chan = ah->ah_curchan;
6745 const struct hal_capabilities *pCap = &ah->ah_caps; 6748 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6746 u16 ant_config; 6749 u16 ant_config;
6747 u32 halNumAntConfig; 6750 u32 halNumAntConfig;
6748 6751
6749 halNumAntConfig = 6752 halNumAntConfig =
6750 IS_CHAN_2GHZ(chan) ? pCap->halNumAntCfg2GHz : pCap-> 6753 IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap->
6751 halNumAntCfg5GHz; 6754 num_antcfg_5ghz;
6752 6755
6753 if (cfg < halNumAntConfig) { 6756 if (cfg < halNumAntConfig) {
6754 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 6757 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan,
@@ -6784,7 +6787,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6784{ 6787{
6785 u32 isr = 0; 6788 u32 isr = 0;
6786 u32 mask2 = 0; 6789 u32 mask2 = 0;
6787 struct hal_capabilities *pCap = &ah->ah_caps; 6790 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6788 u32 sync_cause = 0; 6791 u32 sync_cause = 0;
6789 bool fatal_int = false; 6792 bool fatal_int = false;
6790 6793
@@ -6868,7 +6871,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6868 } 6871 }
6869 6872
6870 if (!AR_SREV_9100(ah)) { 6873 if (!AR_SREV_9100(ah)) {
6871 if (!pCap->halAutoSleepSupport) { 6874 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6872 u32 isr5 = REG_READ(ah, AR_ISR_S5_S); 6875 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
6873 if (isr5 & AR_ISR_S5_TIM_TIMER) 6876 if (isr5 & AR_ISR_S5_TIM_TIMER)
6874 *masked |= ATH9K_INT_TIM_TIMER; 6877 *masked |= ATH9K_INT_TIM_TIMER;
@@ -6927,7 +6930,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6927 struct ath_hal_5416 *ahp = AH5416(ah); 6930 struct ath_hal_5416 *ahp = AH5416(ah);
6928 u32 omask = ahp->ah_maskReg; 6931 u32 omask = ahp->ah_maskReg;
6929 u32 mask, mask2; 6932 u32 mask, mask2;
6930 struct hal_capabilities *pCap = &ah->ah_caps; 6933 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6931 6934
6932 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__, 6935 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
6933 omask, ints); 6936 omask, ints);
@@ -6965,7 +6968,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6965 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 6968 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
6966 else 6969 else
6967 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 6970 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
6968 if (!pCap->halAutoSleepSupport) 6971 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
6969 mask |= AR_IMR_GENTMR; 6972 mask |= AR_IMR_GENTMR;
6970 } 6973 }
6971 6974
@@ -7002,7 +7005,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
7002 REG_WRITE(ah, AR_IMR_S2, mask | mask2); 7005 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
7003 ahp->ah_maskReg = ints; 7006 ahp->ah_maskReg = ints;
7004 7007
7005 if (!pCap->halAutoSleepSupport) { 7008 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
7006 if (ints & ATH9K_INT_TIM_TIMER) 7009 if (ints & ATH9K_INT_TIM_TIMER)
7007 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 7010 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7008 else 7011 else
@@ -7061,11 +7064,11 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
7061 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 7064 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7062 TU_TO_USEC(next_beacon - 7065 TU_TO_USEC(next_beacon -
7063 ah->ah_config. 7066 ah->ah_config.
7064 ath_hal_dma_beacon_response_time)); 7067 dma_beacon_response_time));
7065 REG_WRITE(ah, AR_NEXT_SWBA, 7068 REG_WRITE(ah, AR_NEXT_SWBA,
7066 TU_TO_USEC(next_beacon - 7069 TU_TO_USEC(next_beacon -
7067 ah->ah_config. 7070 ah->ah_config.
7068 ath_hal_sw_beacon_response_time)); 7071 sw_beacon_response_time));
7069 flags |= 7072 flags |=
7070 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 7073 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7071 break; 7074 break;
@@ -7090,7 +7093,7 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7090 const struct ath9k_beacon_state *bs) 7093 const struct ath9k_beacon_state *bs)
7091{ 7094{
7092 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 7095 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
7093 struct hal_capabilities *pCap = &ah->ah_caps; 7096 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7094 7097
7095 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 7098 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
7096 7099
@@ -7133,7 +7136,7 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7133 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 7136 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
7134 | AR_SLEEP1_ASSUME_DTIM); 7137 | AR_SLEEP1_ASSUME_DTIM);
7135 7138
7136 if (pCap->halAutoSleepSupport) 7139 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
7137 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 7140 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
7138 else 7141 else
7139 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 7142 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
@@ -7152,7 +7155,7 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7152 7155
7153bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) 7156bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
7154{ 7157{
7155 if (entry < ah->ah_caps.halKeyCacheSize) { 7158 if (entry < ah->ah_caps.keycache_size) {
7156 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 7159 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7157 if (val & AR_KEYTABLE_VALID) 7160 if (val & AR_KEYTABLE_VALID)
7158 return true; 7161 return true;
@@ -7164,7 +7167,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
7164{ 7167{
7165 u32 keyType; 7168 u32 keyType;
7166 7169
7167 if (entry >= ah->ah_caps.halKeyCacheSize) { 7170 if (entry >= ah->ah_caps.keycache_size) {
7168 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 7171 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7169 "%s: entry %u out of range\n", __func__, entry); 7172 "%s: entry %u out of range\n", __func__, entry);
7170 return false; 7173 return false;
@@ -7202,7 +7205,7 @@ ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
7202{ 7205{
7203 u32 macHi, macLo; 7206 u32 macHi, macLo;
7204 7207
7205 if (entry >= ah->ah_caps.halKeyCacheSize) { 7208 if (entry >= ah->ah_caps.keycache_size) {
7206 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 7209 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7207 "%s: entry %u out of range\n", __func__, entry); 7210 "%s: entry %u out of range\n", __func__, entry);
7208 return false; 7211 return false;
@@ -7229,7 +7232,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7229 const struct ath9k_keyval *k, 7232 const struct ath9k_keyval *k,
7230 const u8 *mac, int xorKey) 7233 const u8 *mac, int xorKey)
7231{ 7234{
7232 const struct hal_capabilities *pCap = &ah->ah_caps; 7235 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7233 u32 key0, key1, key2, key3, key4; 7236 u32 key0, key1, key2, key3, key4;
7234 u32 keyType; 7237 u32 keyType;
7235 u32 xorMask = xorKey ? 7238 u32 xorMask = xorKey ?
@@ -7237,7 +7240,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7237 | ATH9K_KEY_XOR) : 0; 7240 | ATH9K_KEY_XOR) : 0;
7238 struct ath_hal_5416 *ahp = AH5416(ah); 7241 struct ath_hal_5416 *ahp = AH5416(ah);
7239 7242
7240 if (entry >= pCap->halKeyCacheSize) { 7243 if (entry >= pCap->keycache_size) {
7241 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 7244 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7242 "%s: entry %u out of range\n", __func__, entry); 7245 "%s: entry %u out of range\n", __func__, entry);
7243 return false; 7246 return false;
@@ -7247,7 +7250,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7247 keyType = AR_KEYTABLE_TYPE_AES; 7250 keyType = AR_KEYTABLE_TYPE_AES;
7248 break; 7251 break;
7249 case ATH9K_CIPHER_AES_CCM: 7252 case ATH9K_CIPHER_AES_CCM:
7250 if (!pCap->halCipherAesCcmSupport) { 7253 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
7251 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 7254 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7252 "%s: AES-CCM not supported by " 7255 "%s: AES-CCM not supported by "
7253 "mac rev 0x%x\n", __func__, 7256 "mac rev 0x%x\n", __func__,
@@ -7259,7 +7262,7 @@ ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
7259 case ATH9K_CIPHER_TKIP: 7262 case ATH9K_CIPHER_TKIP:
7260 keyType = AR_KEYTABLE_TYPE_TKIP; 7263 keyType = AR_KEYTABLE_TYPE_TKIP;
7261 if (ATH9K_IS_MIC_ENABLED(ah) 7264 if (ATH9K_IS_MIC_ENABLED(ah)
7262 && entry + 64 >= pCap->halKeyCacheSize) { 7265 && entry + 64 >= pCap->keycache_size) {
7263 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 7266 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7264 "%s: entry %u inappropriate for TKIP\n", 7267 "%s: entry %u inappropriate for TKIP\n",
7265 __func__, entry); 7268 __func__, entry);
@@ -7456,9 +7459,9 @@ bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
7456 const struct ath9k_txq_info *qInfo) 7459 const struct ath9k_txq_info *qInfo)
7457{ 7460{
7458 struct ath_hal_5416 *ahp = AH5416(ah); 7461 struct ath_hal_5416 *ahp = AH5416(ah);
7459 struct hal_capabilities *pCap = &ah->ah_caps; 7462 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7460 7463
7461 if (q >= pCap->halTotalQueues) { 7464 if (q >= pCap->total_queues) {
7462 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 7465 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7463 __func__, q); 7466 __func__, q);
7464 return false; 7467 return false;
@@ -7499,9 +7502,9 @@ ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
7499 struct ath9k_txq_info *qInfo) 7502 struct ath9k_txq_info *qInfo)
7500{ 7503{
7501 struct ath_hal_5416 *ahp = AH5416(ah); 7504 struct ath_hal_5416 *ahp = AH5416(ah);
7502 struct hal_capabilities *pCap = &ah->ah_caps; 7505 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7503 7506
7504 if (q >= pCap->halTotalQueues) { 7507 if (q >= pCap->total_queues) {
7505 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 7508 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7506 __func__, q); 7509 __func__, q);
7507 return false; 7510 return false;
@@ -7515,28 +7518,28 @@ ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
7515{ 7518{
7516 struct ath_hal_5416 *ahp = AH5416(ah); 7519 struct ath_hal_5416 *ahp = AH5416(ah);
7517 struct ath9k_tx_queue_info *qi; 7520 struct ath9k_tx_queue_info *qi;
7518 struct hal_capabilities *pCap = &ah->ah_caps; 7521 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7519 int q; 7522 int q;
7520 7523
7521 switch (type) { 7524 switch (type) {
7522 case ATH9K_TX_QUEUE_BEACON: 7525 case ATH9K_TX_QUEUE_BEACON:
7523 q = pCap->halTotalQueues - 1; 7526 q = pCap->total_queues - 1;
7524 break; 7527 break;
7525 case ATH9K_TX_QUEUE_CAB: 7528 case ATH9K_TX_QUEUE_CAB:
7526 q = pCap->halTotalQueues - 2; 7529 q = pCap->total_queues - 2;
7527 break; 7530 break;
7528 case ATH9K_TX_QUEUE_PSPOLL: 7531 case ATH9K_TX_QUEUE_PSPOLL:
7529 q = 1; 7532 q = 1;
7530 break; 7533 break;
7531 case ATH9K_TX_QUEUE_UAPSD: 7534 case ATH9K_TX_QUEUE_UAPSD:
7532 q = pCap->halTotalQueues - 3; 7535 q = pCap->total_queues - 3;
7533 break; 7536 break;
7534 case ATH9K_TX_QUEUE_DATA: 7537 case ATH9K_TX_QUEUE_DATA:
7535 for (q = 0; q < pCap->halTotalQueues; q++) 7538 for (q = 0; q < pCap->total_queues; q++)
7536 if (ahp->ah_txq[q].tqi_type == 7539 if (ahp->ah_txq[q].tqi_type ==
7537 ATH9K_TX_QUEUE_INACTIVE) 7540 ATH9K_TX_QUEUE_INACTIVE)
7538 break; 7541 break;
7539 if (q == pCap->halTotalQueues) { 7542 if (q == pCap->total_queues) {
7540 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 7543 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7541 "%s: no available tx queue\n", __func__); 7544 "%s: no available tx queue\n", __func__);
7542 return -1; 7545 return -1;
@@ -7602,10 +7605,10 @@ ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
7602bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) 7605bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
7603{ 7606{
7604 struct ath_hal_5416 *ahp = AH5416(ah); 7607 struct ath_hal_5416 *ahp = AH5416(ah);
7605 struct hal_capabilities *pCap = &ah->ah_caps; 7608 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7606 struct ath9k_tx_queue_info *qi; 7609 struct ath9k_tx_queue_info *qi;
7607 7610
7608 if (q >= pCap->halTotalQueues) { 7611 if (q >= pCap->total_queues) {
7609 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 7612 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7610 __func__, q); 7613 __func__, q);
7611 return false; 7614 return false;
@@ -7634,12 +7637,12 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
7634bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) 7637bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
7635{ 7638{
7636 struct ath_hal_5416 *ahp = AH5416(ah); 7639 struct ath_hal_5416 *ahp = AH5416(ah);
7637 struct hal_capabilities *pCap = &ah->ah_caps; 7640 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7638 struct ath9k_channel *chan = ah->ah_curchan; 7641 struct ath9k_channel *chan = ah->ah_curchan;
7639 struct ath9k_tx_queue_info *qi; 7642 struct ath9k_tx_queue_info *qi;
7640 u32 cwMin, chanCwMin, value; 7643 u32 cwMin, chanCwMin, value;
7641 7644
7642 if (q >= pCap->halTotalQueues) { 7645 if (q >= pCap->total_queues) {
7643 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 7646 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7644 __func__, q); 7647 __func__, q);
7645 return false; 7648 return false;
@@ -7739,10 +7742,10 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
7739 | AR_Q_MISC_CBR_INCR_DIS1 7742 | AR_Q_MISC_CBR_INCR_DIS1
7740 | AR_Q_MISC_CBR_INCR_DIS0); 7743 | AR_Q_MISC_CBR_INCR_DIS0);
7741 value = (qi->tqi_readyTime 7744 value = (qi->tqi_readyTime
7742 - (ah->ah_config.ath_hal_sw_beacon_response_time - 7745 - (ah->ah_config.sw_beacon_response_time -
7743 ah->ah_config.ath_hal_dma_beacon_response_time) 7746 ah->ah_config.dma_beacon_response_time)
7744 - 7747 -
7745 ah->ah_config.ath_hal_additional_swba_backoff) * 7748 ah->ah_config.additional_swba_backoff) *
7746 1024; 7749 1024;
7747 REG_WRITE(ah, AR_QRDYTIMECFG(q), 7750 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7748 value | AR_Q_RDYTIMECFG_EN); 7751 value | AR_Q_RDYTIMECFG_EN);
@@ -8131,14 +8134,14 @@ ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8131 u32 size, u32 flags) 8134 u32 size, u32 flags)
8132{ 8135{
8133 struct ar5416_desc *ads = AR5416DESC(ds); 8136 struct ar5416_desc *ads = AR5416DESC(ds);
8134 struct hal_capabilities *pCap = &ah->ah_caps; 8137 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
8135 8138
8136 ads->ds_ctl1 = size & AR_BufLen; 8139 ads->ds_ctl1 = size & AR_BufLen;
8137 if (flags & ATH9K_RXDESC_INTREQ) 8140 if (flags & ATH9K_RXDESC_INTREQ)
8138 ads->ds_ctl1 |= AR_RxIntrReq; 8141 ads->ds_ctl1 |= AR_RxIntrReq;
8139 8142
8140 ads->ds_rxstatus8 &= ~AR_RxDone; 8143 ads->ds_rxstatus8 &= ~AR_RxDone;
8141 if (!pCap->halAutoSleepSupport) 8144 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
8142 memset(&(ads->u), 0, sizeof(ads->u)); 8145 memset(&(ads->u), 0, sizeof(ads->u));
8143 return true; 8146 return true;
8144} 8147}
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index 9549524630f7..01bee5ec7233 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -1268,14 +1268,14 @@ static int ath_attach(u16 devid,
1268 sc->rates[IEEE80211_BAND_2GHZ]; 1268 sc->rates[IEEE80211_BAND_2GHZ];
1269 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 1269 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1270 1270
1271 if (sc->sc_ah->ah_caps.halHTSupport) 1271 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1272 /* Setup HT capabilities for 2.4Ghz*/ 1272 /* Setup HT capabilities for 2.4Ghz*/
1273 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info); 1273 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
1274 1274
1275 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 1275 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1276 &sc->sbands[IEEE80211_BAND_2GHZ]; 1276 &sc->sbands[IEEE80211_BAND_2GHZ];
1277 1277
1278 if (sc->sc_ah->ah_caps.halWirelessModes & ATH9K_MODE_SEL_11A) { 1278 if (sc->sc_ah->ah_caps.wireless_modes & ATH9K_MODE_SEL_11A) {
1279 sc->sbands[IEEE80211_BAND_5GHZ].channels = 1279 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1280 sc->channels[IEEE80211_BAND_5GHZ]; 1280 sc->channels[IEEE80211_BAND_5GHZ];
1281 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 1281 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
@@ -1283,7 +1283,7 @@ static int ath_attach(u16 devid,
1283 sc->sbands[IEEE80211_BAND_5GHZ].band = 1283 sc->sbands[IEEE80211_BAND_5GHZ].band =
1284 IEEE80211_BAND_5GHZ; 1284 IEEE80211_BAND_5GHZ;
1285 1285
1286 if (sc->sc_ah->ah_caps.halHTSupport) 1286 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1287 /* Setup HT capabilities for 5Ghz*/ 1287 /* Setup HT capabilities for 5Ghz*/
1288 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info); 1288 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
1289 1289
diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c
index e0797afee52b..d3132009d94d 100644
--- a/drivers/net/wireless/ath9k/rc.c
+++ b/drivers/net/wireless/ath9k/rc.c
@@ -780,7 +780,7 @@ struct ath_rate_softc *ath_rate_attach(struct ath_hal *ah)
780 ar5416_attach_ratetables(asc); 780 ar5416_attach_ratetables(asc);
781 781
782 /* Save Maximum TX Trigger Level (used for 11n) */ 782 /* Save Maximum TX Trigger Level (used for 11n) */
783 tx_triglevel_max = ah->ah_caps.halTxTrigLevelMax; 783 tx_triglevel_max = ah->ah_caps.tx_triglevel_max;
784 /* return alias for ath_rate_softc * */ 784 /* return alias for ath_rate_softc * */
785 return asc; 785 return asc;
786} 786}
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c
index 8e14e643e994..2fe806175c01 100644
--- a/drivers/net/wireless/ath9k/recv.c
+++ b/drivers/net/wireless/ath9k/recv.c
@@ -478,7 +478,7 @@ static void ath_opmode_init(struct ath_softc *sc)
478 ath9k_hw_setrxfilter(ah, rfilt); 478 ath9k_hw_setrxfilter(ah, rfilt);
479 479
480 /* configure bssid mask */ 480 /* configure bssid mask */
481 if (ah->ah_caps.halBssIdMaskSupport) 481 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
482 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); 482 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
483 483
484 /* configure operational mode */ 484 /* configure operational mode */
@@ -1018,7 +1018,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
1018 PCI_DMA_FROMDEVICE); 1018 PCI_DMA_FROMDEVICE);
1019 1019
1020 /* XXX: Ah! make me more readable, use a helper */ 1020 /* XXX: Ah! make me more readable, use a helper */
1021 if (ah->ah_caps.halHTSupport) { 1021 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1022 if (ds->ds_rxstat.rs_moreaggr == 0) { 1022 if (ds->ds_rxstat.rs_moreaggr == 0) {
1023 rx_status.rssictl[0] = 1023 rx_status.rssictl[0] =
1024 ds->ds_rxstat.rs_rssi_ctl0; 1024 ds->ds_rxstat.rs_rssi_ctl0;
diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c
index 7b0176e3eb40..05e10c485fa4 100644
--- a/drivers/net/wireless/ath9k/regd.c
+++ b/drivers/net/wireless/ath9k/regd.c
@@ -87,7 +87,7 @@ static bool ath9k_regd_is_fcc_midband_supported(struct ath_hal *ah)
87{ 87{
88 u32 regcap; 88 u32 regcap;
89 89
90 regcap = ah->ah_caps.halRegCap; 90 regcap = ah->ah_caps.reg_cap;
91 91
92 if (regcap & AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND) 92 if (regcap & AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND)
93 return true; 93 return true;
@@ -138,7 +138,7 @@ ath9k_regd_get_wmodes_nreg(struct ath_hal *ah,
138{ 138{
139 u32 modesAvail; 139 u32 modesAvail;
140 140
141 modesAvail = ah->ah_caps.halWirelessModes; 141 modesAvail = ah->ah_caps.wireless_modes;
142 142
143 if ((modesAvail & ATH9K_MODE_SEL_11G) && (!country->allow11g)) 143 if ((modesAvail & ATH9K_MODE_SEL_11G) && (!country->allow11g))
144 modesAvail &= ~ATH9K_MODE_SEL_11G; 144 modesAvail &= ~ATH9K_MODE_SEL_11G;
@@ -436,7 +436,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
436 return false; 436 return false;
437 } 437 }
438 if ((fband->channelBW == CHANNEL_HALF_BW) && 438 if ((fband->channelBW == CHANNEL_HALF_BW) &&
439 !ah->ah_caps.halChanHalfRate) { 439 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) {
440 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 440 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
441 "%s: Skipping %u half rate channel\n", 441 "%s: Skipping %u half rate channel\n",
442 __func__, c); 442 __func__, c);
@@ -444,7 +444,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
444 } 444 }
445 445
446 if ((fband->channelBW == CHANNEL_QUARTER_BW) && 446 if ((fband->channelBW == CHANNEL_QUARTER_BW) &&
447 !ah->ah_caps.halChanQuarterRate) { 447 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) {
448 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 448 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
449 "%s: Skipping %u quarter rate channel\n", 449 "%s: Skipping %u quarter rate channel\n",
450 __func__, c); 450 __func__, c);
@@ -529,7 +529,7 @@ ath9k_regd_add_channel(struct ath_hal *ah,
529 if ((c < 2412) || (c > 2462)) { 529 if ((c < 2412) || (c > 2462)) {
530 if (rd5GHz.regDmnEnum == MKK1 || 530 if (rd5GHz.regDmnEnum == MKK1 ||
531 rd5GHz.regDmnEnum == MKK2) { 531 rd5GHz.regDmnEnum == MKK2) {
532 u32 regcap = ah->ah_caps.halRegCap; 532 u32 regcap = ah->ah_caps.reg_cap;
533 if (!(regcap & 533 if (!(regcap &
534 (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 534 (AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
535 AR_EEPROM_EEREGCAP_EN_KK_U2 | 535 AR_EEPROM_EEREGCAP_EN_KK_U2 |
@@ -594,7 +594,7 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
594 594
595 for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) { 595 for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) {
596 if (j_bandcheck[i].freqbandbit == b) { 596 if (j_bandcheck[i].freqbandbit == b) {
597 regcap = ah->ah_caps.halRegCap; 597 regcap = ah->ah_caps.reg_cap;
598 if ((j_bandcheck[i].eepromflagtocheck & regcap) == 0) { 598 if ((j_bandcheck[i].eepromflagtocheck & regcap) == 0) {
599 skipband = true; 599 skipband = true;
600 } else if ((regcap & AR_EEPROM_EEREGCAP_EN_KK_U2) || 600 } else if ((regcap & AR_EEPROM_EEREGCAP_EN_KK_U2) ||
@@ -726,7 +726,7 @@ ath9k_regd_init_channels(struct ath_hal *ah,
726 } 726 }
727 727
728 if (country == NULL) { 728 if (country == NULL) {
729 modesAvail = ah->ah_caps.halWirelessModes; 729 modesAvail = ah->ah_caps.wireless_modes;
730 } else { 730 } else {
731 modesAvail = ath9k_regd_get_wmodes_nreg(ah, country, &rd5GHz); 731 modesAvail = ath9k_regd_get_wmodes_nreg(ah, country, &rd5GHz);
732 if (!enableOutdoor) 732 if (!enableOutdoor)
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c
index f0297ee5d053..92bb3c22e7c2 100644
--- a/drivers/net/wireless/ath9k/xmit.c
+++ b/drivers/net/wireless/ath9k/xmit.c
@@ -781,7 +781,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
781 * let rate series flags determine which rates will actually 781 * let rate series flags determine which rates will actually
782 * use RTS. 782 * use RTS.
783 */ 783 */
784 if (ah->ah_caps.halHTSupport && bf->bf_isdata) { 784 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf->bf_isdata) {
785 BUG_ON(!an); 785 BUG_ON(!an);
786 /* 786 /*
787 * 802.11g protection not needed, use our default behavior 787 * 802.11g protection not needed, use our default behavior
@@ -897,7 +897,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
897 * For non-HT devices, calculate RTS/CTS duration in software 897 * For non-HT devices, calculate RTS/CTS duration in software
898 * and disable multi-rate retry. 898 * and disable multi-rate retry.
899 */ 899 */
900 if (flags && !ah->ah_caps.halHTSupport) { 900 if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
901 /* 901 /*
902 * Compute the transmit duration based on the frame 902 * Compute the transmit duration based on the frame
903 * size and the size of an ACK frame. We call into the 903 * size and the size of an ACK frame. We call into the
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 15:47:18 -0500